2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39 #include <linux/slab.h>
44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
46 return ctrl->pcie->port;
49 /* Power Control Command */
51 #define POWER_OFF PCI_EXP_SLTCTL_PCC
53 static irqreturn_t pcie_isr(int irq, void *dev_id);
54 static void start_int_poll_timer(struct controller *ctrl, int sec);
56 /* This is the interrupt polling timeout function. */
57 static void int_poll_timeout(unsigned long data)
59 struct controller *ctrl = (struct controller *)data;
61 /* Poll for interrupt events. regs == NULL => polling */
64 init_timer(&ctrl->poll_timer);
65 if (!pciehp_poll_time)
66 pciehp_poll_time = 2; /* default polling interval is 2 sec */
68 start_int_poll_timer(ctrl, pciehp_poll_time);
71 /* This function starts the interrupt polling timer. */
72 static void start_int_poll_timer(struct controller *ctrl, int sec)
74 /* Clamp to sane value */
75 if ((sec <= 0) || (sec > 60))
78 ctrl->poll_timer.function = &int_poll_timeout;
79 ctrl->poll_timer.data = (unsigned long)ctrl;
80 ctrl->poll_timer.expires = jiffies + sec * HZ;
81 add_timer(&ctrl->poll_timer);
84 static inline int pciehp_request_irq(struct controller *ctrl)
86 int retval, irq = ctrl->pcie->irq;
88 /* Install interrupt polling timer. Start with 10 sec delay */
89 if (pciehp_poll_mode) {
90 init_timer(&ctrl->poll_timer);
91 start_int_poll_timer(ctrl, 10);
95 /* Installs the interrupt handler */
96 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
98 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
103 static inline void pciehp_free_irq(struct controller *ctrl)
105 if (pciehp_poll_mode)
106 del_timer_sync(&ctrl->poll_timer);
108 free_irq(ctrl->pcie->irq, ctrl);
111 static int pcie_poll_cmd(struct controller *ctrl)
113 struct pci_dev *pdev = ctrl_dev(ctrl);
117 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
118 if (slot_status & PCI_EXP_SLTSTA_CC) {
119 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
123 while (timeout > 0) {
126 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
127 if (slot_status & PCI_EXP_SLTSTA_CC) {
128 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
133 return 0; /* timeout */
136 static void pcie_wait_cmd(struct controller *ctrl, int poll)
138 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
139 unsigned long timeout = msecs_to_jiffies(msecs);
143 rc = pcie_poll_cmd(ctrl);
145 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
147 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
151 * pcie_write_cmd - Issue controller command
152 * @ctrl: controller to which the command is issued
153 * @cmd: command value written to slot control register
154 * @mask: bitmask of slot control register to be modified
156 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
158 struct pci_dev *pdev = ctrl_dev(ctrl);
162 mutex_lock(&ctrl->ctrl_lock);
164 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
165 if (slot_status & PCI_EXP_SLTSTA_CC) {
166 if (!ctrl->no_cmd_complete) {
168 * After 1 sec and CMD_COMPLETED still not set, just
169 * proceed forward to issue the next command according
170 * to spec. Just print out the error message.
172 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
173 } else if (!NO_CMD_CMPL(ctrl)) {
175 * This controller seems to notify of command completed
176 * event even though it supports none of power
177 * controller, attention led, power led and EMI.
179 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
180 "wait for command completed event.\n");
181 ctrl->no_cmd_complete = 0;
183 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
184 "the controller is broken.\n");
188 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
190 slot_ctrl |= (cmd & mask);
193 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
196 * Wait for command completion.
198 if (!ctrl->no_cmd_complete) {
201 * if hotplug interrupt is not enabled or command
202 * completed interrupt is not enabled, we need to poll
203 * command completed event.
205 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
206 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
208 pcie_wait_cmd(ctrl, poll);
210 mutex_unlock(&ctrl->ctrl_lock);
214 static bool check_link_active(struct controller *ctrl)
216 struct pci_dev *pdev = ctrl_dev(ctrl);
220 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
221 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
224 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
229 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
233 if (check_link_active(ctrl) == active)
235 while (timeout > 0) {
238 if (check_link_active(ctrl) == active)
241 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
242 active ? "set" : "cleared");
245 static void pcie_wait_link_active(struct controller *ctrl)
247 __pcie_wait_link_active(ctrl, true);
250 static void pcie_wait_link_not_active(struct controller *ctrl)
252 __pcie_wait_link_active(ctrl, false);
255 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
259 int delay = 1000, step = 20;
263 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
273 if (count > 1 && pciehp_debug)
274 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
275 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
276 PCI_FUNC(devfn), count, step, l);
281 int pciehp_check_link_status(struct controller *ctrl)
283 struct pci_dev *pdev = ctrl_dev(ctrl);
288 * Data Link Layer Link Active Reporting must be capable for
289 * hot-plug capable downstream port. But old controller might
290 * not implement it. In this case, we wait for 1000 ms.
292 if (ctrl->link_active_reporting)
293 pcie_wait_link_active(ctrl);
297 /* wait 100ms before read pci conf, and try in 1s */
299 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
302 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
303 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
304 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
305 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
306 ctrl_err(ctrl, "Link Training Error occurs \n");
310 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
318 static int __pciehp_link_set(struct controller *ctrl, bool enable)
320 struct pci_dev *pdev = ctrl_dev(ctrl);
323 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
326 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
328 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
330 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
331 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
335 static int pciehp_link_enable(struct controller *ctrl)
337 return __pciehp_link_set(ctrl, true);
340 static int pciehp_link_disable(struct controller *ctrl)
342 return __pciehp_link_set(ctrl, false);
345 int pciehp_get_attention_status(struct slot *slot, u8 *status)
347 struct controller *ctrl = slot->ctrl;
348 struct pci_dev *pdev = ctrl_dev(ctrl);
352 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
353 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
354 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
356 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
358 switch (atten_led_state) {
360 *status = 0xFF; /* Reserved */
363 *status = 1; /* On */
366 *status = 2; /* Blink */
369 *status = 0; /* Off */
379 int pciehp_get_power_status(struct slot *slot, u8 *status)
381 struct controller *ctrl = slot->ctrl;
382 struct pci_dev *pdev = ctrl_dev(ctrl);
386 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
387 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
388 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
390 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
407 int pciehp_get_latch_status(struct slot *slot, u8 *status)
409 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
412 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
413 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
417 int pciehp_get_adapter_status(struct slot *slot, u8 *status)
419 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
422 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
423 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
427 int pciehp_query_power_fault(struct slot *slot)
429 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
432 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
433 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
436 int pciehp_set_attention_status(struct slot *slot, u8 value)
438 struct controller *ctrl = slot->ctrl;
442 cmd_mask = PCI_EXP_SLTCTL_AIC;
444 case 0 : /* turn off */
447 case 1: /* turn on */
450 case 2: /* turn blink */
456 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
457 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
458 return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
461 void pciehp_green_led_on(struct slot *slot)
463 struct controller *ctrl = slot->ctrl;
468 cmd_mask = PCI_EXP_SLTCTL_PIC;
469 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
470 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
471 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
474 void pciehp_green_led_off(struct slot *slot)
476 struct controller *ctrl = slot->ctrl;
481 cmd_mask = PCI_EXP_SLTCTL_PIC;
482 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
483 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
484 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
487 void pciehp_green_led_blink(struct slot *slot)
489 struct controller *ctrl = slot->ctrl;
494 cmd_mask = PCI_EXP_SLTCTL_PIC;
495 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
496 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
497 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
500 int pciehp_power_on_slot(struct slot * slot)
502 struct controller *ctrl = slot->ctrl;
503 struct pci_dev *pdev = ctrl_dev(ctrl);
509 /* Clear sticky power-fault bit from previous power failures */
510 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
511 slot_status &= PCI_EXP_SLTSTA_PFD;
513 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, slot_status);
514 ctrl->power_fault_detected = 0;
517 cmd_mask = PCI_EXP_SLTCTL_PCC;
518 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
520 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
523 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
524 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
526 retval = pciehp_link_enable(ctrl);
528 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
533 int pciehp_power_off_slot(struct slot * slot)
535 struct controller *ctrl = slot->ctrl;
540 /* Disable the link at first */
541 pciehp_link_disable(ctrl);
542 /* wait the link is down */
543 if (ctrl->link_active_reporting)
544 pcie_wait_link_not_active(ctrl);
548 slot_cmd = POWER_OFF;
549 cmd_mask = PCI_EXP_SLTCTL_PCC;
550 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
552 ctrl_err(ctrl, "Write command failed!\n");
555 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
556 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
560 static irqreturn_t pcie_isr(int irq, void *dev_id)
562 struct controller *ctrl = (struct controller *)dev_id;
563 struct pci_dev *pdev = ctrl_dev(ctrl);
564 struct slot *slot = ctrl->slot;
565 u16 detected, intr_loc;
568 * In order to guarantee that all interrupt events are
569 * serviced, we need to re-inspect Slot Status register after
570 * clearing what is presumed to be the last pending interrupt.
574 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
576 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
577 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
579 detected &= ~intr_loc;
580 intr_loc |= detected;
584 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
588 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
590 /* Check Command Complete Interrupt Pending */
591 if (intr_loc & PCI_EXP_SLTSTA_CC) {
594 wake_up(&ctrl->queue);
597 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
600 /* Check MRL Sensor Changed */
601 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
602 pciehp_handle_switch_change(slot);
604 /* Check Attention Button Pressed */
605 if (intr_loc & PCI_EXP_SLTSTA_ABP)
606 pciehp_handle_attention_button(slot);
608 /* Check Presence Detect Changed */
609 if (intr_loc & PCI_EXP_SLTSTA_PDC)
610 pciehp_handle_presence_change(slot);
612 /* Check Power Fault Detected */
613 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
614 ctrl->power_fault_detected = 1;
615 pciehp_handle_power_fault(slot);
620 int pcie_enable_notification(struct controller *ctrl)
625 * TBD: Power fault detected software notification support.
627 * Power fault detected software notification is not enabled
628 * now, because it caused power fault detected interrupt storm
629 * on some machines. On those machines, power fault detected
630 * bit in the slot status register was set again immediately
631 * when it is cleared in the interrupt service routine, and
632 * next power fault detected interrupt was notified again.
634 cmd = PCI_EXP_SLTCTL_PDCE;
635 if (ATTN_BUTTN(ctrl))
636 cmd |= PCI_EXP_SLTCTL_ABPE;
638 cmd |= PCI_EXP_SLTCTL_MRLSCE;
639 if (!pciehp_poll_mode)
640 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
642 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
643 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
644 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
646 if (pcie_write_cmd(ctrl, cmd, mask)) {
647 ctrl_err(ctrl, "Cannot enable software notification\n");
653 static void pcie_disable_notification(struct controller *ctrl)
656 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
657 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
658 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
659 PCI_EXP_SLTCTL_DLLSCE);
660 if (pcie_write_cmd(ctrl, 0, mask))
661 ctrl_warn(ctrl, "Cannot disable software notification\n");
665 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
666 * bus reset of the bridge, but if the slot supports surprise removal we need
667 * to disable presence detection around the bus reset and clear any spurious
670 int pciehp_reset_slot(struct slot *slot, int probe)
672 struct controller *ctrl = slot->ctrl;
673 struct pci_dev *pdev = ctrl_dev(ctrl);
678 if (HP_SUPR_RM(ctrl)) {
679 pcie_write_cmd(ctrl, 0, PCI_EXP_SLTCTL_PDCE);
680 if (pciehp_poll_mode)
681 del_timer_sync(&ctrl->poll_timer);
684 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
686 if (HP_SUPR_RM(ctrl)) {
687 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
689 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE);
690 if (pciehp_poll_mode)
691 int_poll_timeout(ctrl->poll_timer.data);
697 int pcie_init_notification(struct controller *ctrl)
699 if (pciehp_request_irq(ctrl))
701 if (pcie_enable_notification(ctrl)) {
702 pciehp_free_irq(ctrl);
705 ctrl->notification_enabled = 1;
709 static void pcie_shutdown_notification(struct controller *ctrl)
711 if (ctrl->notification_enabled) {
712 pcie_disable_notification(ctrl);
713 pciehp_free_irq(ctrl);
714 ctrl->notification_enabled = 0;
718 static int pcie_init_slot(struct controller *ctrl)
722 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
726 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
731 mutex_init(&slot->lock);
732 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
740 static void pcie_cleanup_slot(struct controller *ctrl)
742 struct slot *slot = ctrl->slot;
743 cancel_delayed_work(&slot->work);
744 destroy_workqueue(slot->wq);
748 static inline void dbg_ctrl(struct controller *ctrl)
752 struct pci_dev *pdev = ctrl->pcie->port;
757 ctrl_info(ctrl, "Hotplug Controller:\n");
758 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
759 pci_name(pdev), pdev->irq);
760 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
761 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
762 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
763 pdev->subsystem_device);
764 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
765 pdev->subsystem_vendor);
766 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
768 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
769 if (!pci_resource_len(pdev, i))
771 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
772 i, &pdev->resource[i]);
774 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
775 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
776 ctrl_info(ctrl, " Attention Button : %3s\n",
777 ATTN_BUTTN(ctrl) ? "yes" : "no");
778 ctrl_info(ctrl, " Power Controller : %3s\n",
779 POWER_CTRL(ctrl) ? "yes" : "no");
780 ctrl_info(ctrl, " MRL Sensor : %3s\n",
781 MRL_SENS(ctrl) ? "yes" : "no");
782 ctrl_info(ctrl, " Attention Indicator : %3s\n",
783 ATTN_LED(ctrl) ? "yes" : "no");
784 ctrl_info(ctrl, " Power Indicator : %3s\n",
785 PWR_LED(ctrl) ? "yes" : "no");
786 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
787 HP_SUPR_RM(ctrl) ? "yes" : "no");
788 ctrl_info(ctrl, " EMI Present : %3s\n",
789 EMI(ctrl) ? "yes" : "no");
790 ctrl_info(ctrl, " Command Completed : %3s\n",
791 NO_CMD_CMPL(ctrl) ? "no" : "yes");
792 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
793 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
794 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
795 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
798 struct controller *pcie_init(struct pcie_device *dev)
800 struct controller *ctrl;
801 u32 slot_cap, link_cap;
802 struct pci_dev *pdev = dev->port;
804 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
806 dev_err(&dev->device, "%s: Out of memory\n", __func__);
810 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
811 ctrl->slot_cap = slot_cap;
812 mutex_init(&ctrl->ctrl_lock);
813 init_waitqueue_head(&ctrl->queue);
816 * Controller doesn't notify of command completion if the "No
817 * Command Completed Support" bit is set in Slot Capability
818 * register or the controller supports none of power
819 * controller, attention led, power led and EMI.
821 if (NO_CMD_CMPL(ctrl) ||
822 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
823 ctrl->no_cmd_complete = 1;
825 /* Check if Data Link Layer Link Active Reporting is implemented */
826 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
827 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
828 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
829 ctrl->link_active_reporting = 1;
832 /* Clear all remaining event bits in Slot Status register */
833 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 0x1f);
835 /* Disable software notification */
836 pcie_disable_notification(ctrl);
838 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
839 pdev->vendor, pdev->device, pdev->subsystem_vendor,
840 pdev->subsystem_device);
842 if (pcie_init_slot(ctrl))
853 void pciehp_release_ctrl(struct controller *ctrl)
855 pcie_shutdown_notification(ctrl);
856 pcie_cleanup_slot(ctrl);