2 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
3 * Copyright (C) 2015 Broadcom Corporatcommon ion
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/msi.h>
18 #include <linux/clk.h>
19 #include <linux/module.h>
20 #include <linux/mbus.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_platform.h>
29 #include <linux/phy/phy.h>
31 #include "pcie-iproc.h"
33 #define CLK_CONTROL_OFFSET 0x000
34 #define EP_MODE_SURVIVE_PERST_SHIFT 1
35 #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
36 #define RC_PCIE_RST_OUTPUT_SHIFT 0
37 #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
39 #define CFG_IND_ADDR_OFFSET 0x120
40 #define CFG_IND_ADDR_MASK 0x00001ffc
42 #define CFG_IND_DATA_OFFSET 0x124
44 #define CFG_ADDR_OFFSET 0x1f8
45 #define CFG_ADDR_BUS_NUM_SHIFT 20
46 #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
47 #define CFG_ADDR_DEV_NUM_SHIFT 15
48 #define CFG_ADDR_DEV_NUM_MASK 0x000f8000
49 #define CFG_ADDR_FUNC_NUM_SHIFT 12
50 #define CFG_ADDR_FUNC_NUM_MASK 0x00007000
51 #define CFG_ADDR_REG_NUM_SHIFT 2
52 #define CFG_ADDR_REG_NUM_MASK 0x00000ffc
53 #define CFG_ADDR_CFG_TYPE_SHIFT 0
54 #define CFG_ADDR_CFG_TYPE_MASK 0x00000003
56 #define CFG_DATA_OFFSET 0x1fc
58 #define SYS_RC_INTX_EN 0x330
59 #define SYS_RC_INTX_MASK 0xf
61 static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
63 struct iproc_pcie *pcie;
65 struct pci_sys_data *sys = bus->sysdata;
67 pcie = sys->private_data;
75 * Note access to the configuration registers are protected at the higher layer
76 * by 'pci_lock' in drivers/pci/access.c
78 static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
82 struct iproc_pcie *pcie = iproc_data(bus);
83 unsigned slot = PCI_SLOT(devfn);
84 unsigned fn = PCI_FUNC(devfn);
85 unsigned busno = bus->number;
88 /* root complex access */
92 writel(where & CFG_IND_ADDR_MASK,
93 pcie->base + CFG_IND_ADDR_OFFSET);
94 return (pcie->base + CFG_IND_DATA_OFFSET);
100 /* EP device access */
101 val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
102 (slot << CFG_ADDR_DEV_NUM_SHIFT) |
103 (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
104 (where & CFG_ADDR_REG_NUM_MASK) |
105 (1 & CFG_ADDR_CFG_TYPE_MASK);
106 writel(val, pcie->base + CFG_ADDR_OFFSET);
108 return (pcie->base + CFG_DATA_OFFSET);
111 static struct pci_ops iproc_pcie_ops = {
112 .map_bus = iproc_pcie_map_cfg_bus,
113 .read = pci_generic_config_read32,
114 .write = pci_generic_config_write32,
117 static void iproc_pcie_reset(struct iproc_pcie *pcie)
122 * Configure the PCIe controller as root complex and send a downstream
125 val = EP_MODE_SURVIVE_PERST | RC_PCIE_RST_OUTPUT;
126 writel(val, pcie->base + CLK_CONTROL_OFFSET);
128 val &= ~EP_MODE_SURVIVE_PERST;
129 writel(val, pcie->base + CLK_CONTROL_OFFSET);
133 static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
137 u16 pos, link_status;
138 int link_is_active = 0;
140 /* make sure we are not in EP mode */
141 pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
142 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
143 dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
147 /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
148 pci_bus_write_config_word(bus, 0, PCI_CLASS_DEVICE,
149 PCI_CLASS_BRIDGE_PCI);
151 /* check link status to see if link is active */
152 pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
153 pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
154 if (link_status & PCI_EXP_LNKSTA_NLW)
157 if (!link_is_active) {
158 /* try GEN 1 link speed */
159 #define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
160 #define PCI_TARGET_LINK_SPEED_MASK 0xf
161 #define PCI_TARGET_LINK_SPEED_GEN2 0x2
162 #define PCI_TARGET_LINK_SPEED_GEN1 0x1
163 pci_bus_read_config_dword(bus, 0,
164 PCI_LINK_STATUS_CTRL_2_OFFSET,
166 if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
167 PCI_TARGET_LINK_SPEED_GEN2) {
168 link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
169 link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
170 pci_bus_write_config_dword(bus, 0,
171 PCI_LINK_STATUS_CTRL_2_OFFSET,
175 pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
176 pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
178 if (link_status & PCI_EXP_LNKSTA_NLW)
183 dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
185 return link_is_active ? 0 : -ENODEV;
188 static void iproc_pcie_enable(struct iproc_pcie *pcie)
190 writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
193 int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
199 if (!pcie || !pcie->dev || !pcie->base)
203 ret = phy_init(pcie->phy);
205 dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
209 ret = phy_power_on(pcie->phy);
211 dev_err(pcie->dev, "unable to power on PCIe PHY\n");
217 iproc_pcie_reset(pcie);
220 pcie->sysdata.private_data = pcie;
221 sysdata = &pcie->sysdata;
225 bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, sysdata, res);
227 dev_err(pcie->dev, "unable to create PCI root bus\n");
229 goto err_power_off_phy;
231 pcie->root_bus = bus;
233 ret = iproc_pcie_check_link(pcie, bus);
235 dev_err(pcie->dev, "no PCIe EP device detected\n");
236 goto err_rm_root_bus;
239 iproc_pcie_enable(pcie);
241 pci_scan_child_bus(bus);
242 pci_assign_unassigned_bus_resources(bus);
244 pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
246 pci_bus_add_devices(bus);
251 pci_stop_root_bus(bus);
252 pci_remove_root_bus(bus);
256 phy_power_off(pcie->phy);
263 EXPORT_SYMBOL(iproc_pcie_setup);
265 int iproc_pcie_remove(struct iproc_pcie *pcie)
267 pci_stop_root_bus(pcie->root_bus);
268 pci_remove_root_bus(pcie->root_bus);
271 phy_power_off(pcie->phy);
277 EXPORT_SYMBOL(iproc_pcie_remove);
279 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
280 MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
281 MODULE_LICENSE("GPL v2");