2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/module.h>
15 #include <linux/mbus.h>
16 #include <linux/msi.h>
17 #include <linux/slab.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_pci.h>
23 #include <linux/of_platform.h>
26 * PCIe unit register offsets.
28 #define PCIE_DEV_ID_OFF 0x0000
29 #define PCIE_CMD_OFF 0x0004
30 #define PCIE_DEV_REV_OFF 0x0008
31 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
32 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
33 #define PCIE_HEADER_LOG_4_OFF 0x0128
34 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
35 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
36 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
37 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
38 #define PCIE_WIN5_CTRL_OFF 0x1880
39 #define PCIE_WIN5_BASE_OFF 0x1884
40 #define PCIE_WIN5_REMAP_OFF 0x188c
41 #define PCIE_CONF_ADDR_OFF 0x18f8
42 #define PCIE_CONF_ADDR_EN 0x80000000
43 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
44 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
45 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
46 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
47 #define PCIE_CONF_ADDR(bus, devfn, where) \
48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
51 #define PCIE_CONF_DATA_OFF 0x18fc
52 #define PCIE_MASK_OFF 0x1910
53 #define PCIE_MASK_ENABLE_INTS 0x0f000000
54 #define PCIE_CTRL_OFF 0x1a00
55 #define PCIE_CTRL_X1_MODE 0x0001
56 #define PCIE_STAT_OFF 0x1a04
57 #define PCIE_STAT_BUS 0xff00
58 #define PCIE_STAT_DEV 0x1f0000
59 #define PCIE_STAT_LINK_DOWN BIT(0)
60 #define PCIE_DEBUG_CTRL 0x1a60
61 #define PCIE_DEBUG_SOFT_RESET BIT(20)
63 /* PCI configuration space of a PCI-to-PCI bridge */
64 struct mvebu_sw_pci_bridge {
79 u8 secondary_latency_timer;
96 struct mvebu_pcie_port;
98 /* Structure representing all PCIe interfaces */
100 struct platform_device *pdev;
101 struct mvebu_pcie_port *ports;
102 struct msi_chip *msi;
104 struct resource realio;
106 struct resource busn;
110 /* Structure representing one PCIe interface */
111 struct mvebu_pcie_port {
114 spinlock_t conf_lock;
118 unsigned int mem_target;
119 unsigned int mem_attr;
120 unsigned int io_target;
121 unsigned int io_attr;
124 int reset_active_low;
126 struct mvebu_sw_pci_bridge bridge;
127 struct device_node *dn;
128 struct mvebu_pcie *pcie;
129 phys_addr_t memwin_base;
131 phys_addr_t iowin_base;
135 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
137 writel(val, port->base + reg);
140 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
142 return readl(port->base + reg);
145 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
147 return port->io_target != -1 && port->io_attr != -1;
150 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
152 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
155 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
159 stat = mvebu_readl(port, PCIE_STAT_OFF);
160 stat &= ~PCIE_STAT_BUS;
162 mvebu_writel(port, stat, PCIE_STAT_OFF);
165 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
169 stat = mvebu_readl(port, PCIE_STAT_OFF);
170 stat &= ~PCIE_STAT_DEV;
172 mvebu_writel(port, stat, PCIE_STAT_OFF);
176 * Setup PCIE BARs and Address Decode Wins:
177 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
178 * WIN[0-3] -> DRAM bank[0-3]
180 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
182 const struct mbus_dram_target_info *dram;
186 dram = mv_mbus_dram_info();
188 /* First, disable and clear BARs and windows. */
189 for (i = 1; i < 3; i++) {
190 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
191 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
192 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
195 for (i = 0; i < 5; i++) {
196 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
197 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
198 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
201 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
202 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
203 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
205 /* Setup windows for DDR banks. Count total DDR size on the fly. */
207 for (i = 0; i < dram->num_cs; i++) {
208 const struct mbus_dram_window *cs = dram->cs + i;
210 mvebu_writel(port, cs->base & 0xffff0000,
211 PCIE_WIN04_BASE_OFF(i));
212 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
214 ((cs->size - 1) & 0xffff0000) |
215 (cs->mbus_attr << 8) |
216 (dram->mbus_dram_target_id << 4) | 1,
217 PCIE_WIN04_CTRL_OFF(i));
222 /* Round up 'size' to the nearest power of two. */
223 if ((size & (size - 1)) != 0)
224 size = 1 << fls(size);
226 /* Setup BAR[1] to all DRAM banks. */
227 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
228 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
229 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
230 PCIE_BAR_CTRL_OFF(1));
233 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
237 /* Point PCIe unit MBUS decode windows to DRAM space. */
238 mvebu_pcie_setup_wins(port);
240 /* Master + slave enable. */
241 cmd = mvebu_readl(port, PCIE_CMD_OFF);
242 cmd |= PCI_COMMAND_IO;
243 cmd |= PCI_COMMAND_MEMORY;
244 cmd |= PCI_COMMAND_MASTER;
245 mvebu_writel(port, cmd, PCIE_CMD_OFF);
247 /* Enable interrupt lines A-D. */
248 mask = mvebu_readl(port, PCIE_MASK_OFF);
249 mask |= PCIE_MASK_ENABLE_INTS;
250 mvebu_writel(port, mask, PCIE_MASK_OFF);
253 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
255 u32 devfn, int where, int size, u32 *val)
257 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
260 *val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
263 *val = (*val >> (8 * (where & 3))) & 0xff;
265 *val = (*val >> (8 * (where & 3))) & 0xffff;
267 return PCIBIOS_SUCCESSFUL;
270 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
272 u32 devfn, int where, int size, u32 val)
274 u32 _val, shift = 8 * (where & 3);
276 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
278 _val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
283 _val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift);
285 _val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift);
287 return PCIBIOS_BAD_REGISTER_NUMBER;
289 mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);
291 return PCIBIOS_SUCCESSFUL;
294 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
298 /* Are the new iobase/iolimit values invalid? */
299 if (port->bridge.iolimit < port->bridge.iobase ||
300 port->bridge.iolimitupper < port->bridge.iobaseupper ||
301 !(port->bridge.command & PCI_COMMAND_IO)) {
303 /* If a window was configured, remove it */
304 if (port->iowin_base) {
305 mvebu_mbus_del_window(port->iowin_base,
307 port->iowin_base = 0;
308 port->iowin_size = 0;
314 if (!mvebu_has_ioport(port)) {
315 dev_WARN(&port->pcie->pdev->dev,
316 "Attempt to set IO when IO is disabled\n");
321 * We read the PCI-to-PCI bridge emulated registers, and
322 * calculate the base address and size of the address decoding
323 * window to setup, according to the PCI-to-PCI bridge
324 * specifications. iobase is the bus address, port->iowin_base
325 * is the CPU address.
327 iobase = ((port->bridge.iobase & 0xF0) << 8) |
328 (port->bridge.iobaseupper << 16);
329 port->iowin_base = port->pcie->io.start + iobase;
330 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
331 (port->bridge.iolimitupper << 16)) -
334 mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
335 port->iowin_base, port->iowin_size,
339 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
341 /* Are the new membase/memlimit values invalid? */
342 if (port->bridge.memlimit < port->bridge.membase ||
343 !(port->bridge.command & PCI_COMMAND_MEMORY)) {
345 /* If a window was configured, remove it */
346 if (port->memwin_base) {
347 mvebu_mbus_del_window(port->memwin_base,
349 port->memwin_base = 0;
350 port->memwin_size = 0;
357 * We read the PCI-to-PCI bridge emulated registers, and
358 * calculate the base address and size of the address decoding
359 * window to setup, according to the PCI-to-PCI bridge
362 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
364 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
367 mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
368 port->memwin_base, port->memwin_size);
372 * Initialize the configuration space of the PCI-to-PCI bridge
373 * associated with the given PCIe interface.
375 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
377 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
379 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
381 bridge->class = PCI_CLASS_BRIDGE_PCI;
382 bridge->vendor = PCI_VENDOR_ID_MARVELL;
383 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
384 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
385 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
386 bridge->cache_line_size = 0x10;
388 /* We support 32 bits I/O addressing */
389 bridge->iobase = PCI_IO_RANGE_TYPE_32;
390 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
394 * Read the configuration space of the PCI-to-PCI bridge associated to
395 * the given PCIe interface.
397 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
398 unsigned int where, int size, u32 *value)
400 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
402 switch (where & ~3) {
404 *value = bridge->device << 16 | bridge->vendor;
408 *value = bridge->command;
411 case PCI_CLASS_REVISION:
412 *value = bridge->class << 16 | bridge->interface << 8 |
416 case PCI_CACHE_LINE_SIZE:
417 *value = bridge->bist << 24 | bridge->header_type << 16 |
418 bridge->latency_timer << 8 | bridge->cache_line_size;
421 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
422 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
425 case PCI_PRIMARY_BUS:
426 *value = (bridge->secondary_latency_timer << 24 |
427 bridge->subordinate_bus << 16 |
428 bridge->secondary_bus << 8 |
429 bridge->primary_bus);
433 if (!mvebu_has_ioport(port))
434 *value = bridge->secondary_status << 16;
436 *value = (bridge->secondary_status << 16 |
437 bridge->iolimit << 8 |
441 case PCI_MEMORY_BASE:
442 *value = (bridge->memlimit << 16 | bridge->membase);
445 case PCI_PREF_MEMORY_BASE:
449 case PCI_IO_BASE_UPPER16:
450 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
453 case PCI_ROM_ADDRESS1:
457 case PCI_INTERRUPT_LINE:
458 /* LINE PIN MIN_GNT MAX_LAT */
464 return PCIBIOS_BAD_REGISTER_NUMBER;
468 *value = (*value >> (8 * (where & 3))) & 0xffff;
470 *value = (*value >> (8 * (where & 3))) & 0xff;
472 return PCIBIOS_SUCCESSFUL;
475 /* Write to the PCI-to-PCI bridge configuration space */
476 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
477 unsigned int where, int size, u32 value)
479 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
486 mask = ~(0xffff << ((where & 3) * 8));
488 mask = ~(0xff << ((where & 3) * 8));
490 return PCIBIOS_BAD_REGISTER_NUMBER;
492 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
496 value = (reg & mask) | value << ((where & 3) * 8);
498 switch (where & ~3) {
501 u32 old = bridge->command;
503 if (!mvebu_has_ioport(port))
504 value &= ~PCI_COMMAND_IO;
506 bridge->command = value & 0xffff;
507 if ((old ^ bridge->command) & PCI_COMMAND_IO)
508 mvebu_pcie_handle_iobase_change(port);
509 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
510 mvebu_pcie_handle_membase_change(port);
514 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
515 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
520 * We also keep bit 1 set, it is a read-only bit that
521 * indicates we support 32 bits addressing for the
524 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
525 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
526 mvebu_pcie_handle_iobase_change(port);
529 case PCI_MEMORY_BASE:
530 bridge->membase = value & 0xffff;
531 bridge->memlimit = value >> 16;
532 mvebu_pcie_handle_membase_change(port);
535 case PCI_IO_BASE_UPPER16:
536 bridge->iobaseupper = value & 0xffff;
537 bridge->iolimitupper = value >> 16;
538 mvebu_pcie_handle_iobase_change(port);
541 case PCI_PRIMARY_BUS:
542 bridge->primary_bus = value & 0xff;
543 bridge->secondary_bus = (value >> 8) & 0xff;
544 bridge->subordinate_bus = (value >> 16) & 0xff;
545 bridge->secondary_latency_timer = (value >> 24) & 0xff;
546 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
553 return PCIBIOS_SUCCESSFUL;
556 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
558 return sys->private_data;
561 static struct mvebu_pcie_port *
562 mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
567 for (i = 0; i < pcie->nports; i++) {
568 struct mvebu_pcie_port *port = &pcie->ports[i];
569 if (bus->number == 0 && port->devfn == devfn)
571 if (bus->number != 0 &&
572 bus->number >= port->bridge.secondary_bus &&
573 bus->number <= port->bridge.subordinate_bus)
580 /* PCI configuration space write function */
581 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
582 int where, int size, u32 val)
584 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
585 struct mvebu_pcie_port *port;
589 port = mvebu_pcie_find_port(pcie, bus, devfn);
591 return PCIBIOS_DEVICE_NOT_FOUND;
593 /* Access the emulated PCI-to-PCI bridge */
594 if (bus->number == 0)
595 return mvebu_sw_pci_bridge_write(port, where, size, val);
597 if (!mvebu_pcie_link_up(port))
598 return PCIBIOS_DEVICE_NOT_FOUND;
601 * On the secondary bus, we don't want to expose any other
602 * device than the device physically connected in the PCIe
603 * slot, visible in slot 0. In slot 1, there's a special
604 * Marvell device that only makes sense when the Armada is
605 * used as a PCIe endpoint.
607 if (bus->number == port->bridge.secondary_bus &&
608 PCI_SLOT(devfn) != 0)
609 return PCIBIOS_DEVICE_NOT_FOUND;
611 /* Access the real PCIe interface */
612 spin_lock_irqsave(&port->conf_lock, flags);
613 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
615 spin_unlock_irqrestore(&port->conf_lock, flags);
620 /* PCI configuration space read function */
621 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
624 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
625 struct mvebu_pcie_port *port;
629 port = mvebu_pcie_find_port(pcie, bus, devfn);
632 return PCIBIOS_DEVICE_NOT_FOUND;
635 /* Access the emulated PCI-to-PCI bridge */
636 if (bus->number == 0)
637 return mvebu_sw_pci_bridge_read(port, where, size, val);
639 if (!mvebu_pcie_link_up(port)) {
641 return PCIBIOS_DEVICE_NOT_FOUND;
645 * On the secondary bus, we don't want to expose any other
646 * device than the device physically connected in the PCIe
647 * slot, visible in slot 0. In slot 1, there's a special
648 * Marvell device that only makes sense when the Armada is
649 * used as a PCIe endpoint.
651 if (bus->number == port->bridge.secondary_bus &&
652 PCI_SLOT(devfn) != 0) {
654 return PCIBIOS_DEVICE_NOT_FOUND;
657 /* Access the real PCIe interface */
658 spin_lock_irqsave(&port->conf_lock, flags);
659 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
661 spin_unlock_irqrestore(&port->conf_lock, flags);
666 static struct pci_ops mvebu_pcie_ops = {
667 .read = mvebu_pcie_rd_conf,
668 .write = mvebu_pcie_wr_conf,
671 static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
673 struct mvebu_pcie *pcie = sys_to_pcie(sys);
676 if (resource_size(&pcie->realio) != 0)
677 pci_add_resource_offset(&sys->resources, &pcie->realio,
679 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
680 pci_add_resource(&sys->resources, &pcie->busn);
682 for (i = 0; i < pcie->nports; i++) {
683 struct mvebu_pcie_port *port = &pcie->ports[i];
686 mvebu_pcie_setup_hw(port);
692 static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
694 struct mvebu_pcie *pcie = sys_to_pcie(sys);
697 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
698 &mvebu_pcie_ops, sys, &sys->resources);
702 pci_scan_child_bus(bus);
707 static void mvebu_pcie_add_bus(struct pci_bus *bus)
709 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
710 bus->msi = pcie->msi;
713 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
714 const struct resource *res,
715 resource_size_t start,
716 resource_size_t size,
717 resource_size_t align)
719 if (dev->bus->number != 0)
723 * On the PCI-to-PCI bridge side, the I/O windows must have at
724 * least a 64 KB size and be aligned on their size, and the
725 * memory windows must have at least a 1 MB size and be
726 * aligned on their size
728 if (res->flags & IORESOURCE_IO)
729 return round_up(start, max_t(resource_size_t, SZ_64K, size));
730 else if (res->flags & IORESOURCE_MEM)
731 return round_up(start, max_t(resource_size_t, SZ_1M, size));
736 static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
740 memset(&hw, 0, sizeof(hw));
742 hw.nr_controllers = 1;
743 hw.private_data = (void **)&pcie;
744 hw.setup = mvebu_pcie_setup;
745 hw.scan = mvebu_pcie_scan_bus;
746 hw.map_irq = of_irq_parse_and_map_pci;
747 hw.ops = &mvebu_pcie_ops;
748 hw.align_resource = mvebu_pcie_align_resource;
749 hw.add_bus = mvebu_pcie_add_bus;
751 pci_common_init(&hw);
755 * Looks up the list of register addresses encoded into the reg =
756 * <...> property for one that matches the given port/lane. Once
759 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
760 struct device_node *np, struct mvebu_pcie_port *port)
762 struct resource regs;
765 ret = of_address_to_resource(np, 0, ®s);
769 return devm_ioremap_resource(&pdev->dev, ®s);
772 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
773 #define DT_TYPE_IO 0x1
774 #define DT_TYPE_MEM32 0x2
775 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
776 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
778 static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
783 const int na = 3, ns = 2;
785 int rlen, nranges, rangesz, pna, i;
790 range = of_get_property(np, "ranges", &rlen);
794 pna = of_n_addr_cells(np);
795 rangesz = pna + na + ns;
796 nranges = rlen / sizeof(__be32) / rangesz;
798 for (i = 0; i < nranges; i++) {
799 u32 flags = of_read_number(range, 1);
800 u32 slot = of_read_number(range, 2);
801 u64 cpuaddr = of_read_number(range + na, pna);
804 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
805 rtype = IORESOURCE_IO;
806 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
807 rtype = IORESOURCE_MEM;
809 if (slot == PCI_SLOT(devfn) && type == rtype) {
810 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
811 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
821 static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
823 struct device_node *msi_node;
825 msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
830 pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
833 pcie->msi->dev = &pcie->pdev->dev;
836 static int mvebu_pcie_probe(struct platform_device *pdev)
838 struct mvebu_pcie *pcie;
839 struct device_node *np = pdev->dev.of_node;
840 struct device_node *child;
843 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
849 platform_set_drvdata(pdev, pcie);
851 /* Get the PCIe memory and I/O aperture */
852 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
853 if (resource_size(&pcie->mem) == 0) {
854 dev_err(&pdev->dev, "invalid memory aperture size\n");
858 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
860 if (resource_size(&pcie->io) != 0) {
861 pcie->realio.flags = pcie->io.flags;
862 pcie->realio.start = PCIBIOS_MIN_IO;
863 pcie->realio.end = min_t(resource_size_t,
865 resource_size(&pcie->io));
867 pcie->realio = pcie->io;
869 /* Get the bus range */
870 ret = of_pci_parse_bus_range(np, &pcie->busn);
872 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
878 for_each_child_of_node(pdev->dev.of_node, child) {
879 if (!of_device_is_available(child))
884 pcie->ports = devm_kzalloc(&pdev->dev, i *
885 sizeof(struct mvebu_pcie_port),
891 for_each_child_of_node(pdev->dev.of_node, child) {
892 struct mvebu_pcie_port *port = &pcie->ports[i];
893 enum of_gpio_flags flags;
895 if (!of_device_is_available(child))
900 if (of_property_read_u32(child, "marvell,pcie-port",
903 "ignoring PCIe DT node, missing pcie-port property\n");
907 if (of_property_read_u32(child, "marvell,pcie-lane",
911 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
912 port->port, port->lane);
914 port->devfn = of_pci_get_devfn(child);
918 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
919 &port->mem_target, &port->mem_attr);
921 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
922 port->port, port->lane);
926 if (resource_size(&pcie->io) != 0)
927 mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
928 &port->io_target, &port->io_attr);
930 port->io_target = -1;
934 port->reset_gpio = of_get_named_gpio_flags(child,
935 "reset-gpios", 0, &flags);
936 if (gpio_is_valid(port->reset_gpio)) {
937 u32 reset_udelay = 20000;
939 port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
940 port->reset_name = kasprintf(GFP_KERNEL,
941 "pcie%d.%d-reset", port->port, port->lane);
942 of_property_read_u32(child, "reset-delay-us",
945 ret = devm_gpio_request_one(&pdev->dev,
946 port->reset_gpio, GPIOF_DIR_OUT, port->reset_name);
948 if (ret == -EPROBE_DEFER)
953 gpio_set_value(port->reset_gpio,
954 (port->reset_active_low) ? 1 : 0);
955 msleep(reset_udelay/1000);
958 port->clk = of_clk_get_by_name(child, NULL);
959 if (IS_ERR(port->clk)) {
960 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
961 port->port, port->lane);
965 ret = clk_prepare_enable(port->clk);
969 port->base = mvebu_pcie_map_registers(pdev, child, port);
970 if (IS_ERR(port->base)) {
971 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
972 port->port, port->lane);
974 clk_disable_unprepare(port->clk);
978 mvebu_pcie_set_local_dev_nr(port, 1);
981 spin_lock_init(&port->conf_lock);
982 mvebu_sw_pci_bridge_init(port);
988 for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K)
989 pci_ioremap_io(i, pcie->io.start + i);
991 mvebu_pcie_msi_enable(pcie);
992 mvebu_pcie_enable(pcie);
997 static const struct of_device_id mvebu_pcie_of_match_table[] = {
998 { .compatible = "marvell,armada-xp-pcie", },
999 { .compatible = "marvell,armada-370-pcie", },
1000 { .compatible = "marvell,dove-pcie", },
1001 { .compatible = "marvell,kirkwood-pcie", },
1004 MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
1006 static struct platform_driver mvebu_pcie_driver = {
1008 .owner = THIS_MODULE,
1009 .name = "mvebu-pcie",
1010 .of_match_table = mvebu_pcie_of_match_table,
1011 /* driver unloading/unbinding currently not supported */
1012 .suppress_bind_attrs = true,
1014 .probe = mvebu_pcie_probe,
1016 module_platform_driver(mvebu_pcie_driver);
1018 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1019 MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1020 MODULE_LICENSE("GPLv2");