1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/msi.h>
16 #include <linux/of_address.h>
17 #include <linux/of_pci.h>
18 #include <linux/of_platform.h>
19 #include <linux/of_irq.h>
20 #include <linux/pci.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqchip/chained_irq.h>
26 /* Bridge core config registers */
27 #define BRCFG_PCIE_RX0 0x00000000
28 #define BRCFG_INTERRUPT 0x00000010
29 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
31 /* Egress - Bridge translation registers */
32 #define E_BREG_CAPABILITIES 0x00000200
33 #define E_BREG_CONTROL 0x00000208
34 #define E_BREG_BASE_LO 0x00000210
35 #define E_BREG_BASE_HI 0x00000214
36 #define E_ECAM_CAPABILITIES 0x00000220
37 #define E_ECAM_CONTROL 0x00000228
38 #define E_ECAM_BASE_LO 0x00000230
39 #define E_ECAM_BASE_HI 0x00000234
41 /* Ingress - address translations */
42 #define I_MSII_CAPABILITIES 0x00000300
43 #define I_MSII_CONTROL 0x00000308
44 #define I_MSII_BASE_LO 0x00000310
45 #define I_MSII_BASE_HI 0x00000314
47 #define I_ISUB_CONTROL 0x000003E8
48 #define SET_ISUB_CONTROL BIT(0)
49 /* Rxed msg fifo - Interrupt status registers */
50 #define MSGF_MISC_STATUS 0x00000400
51 #define MSGF_MISC_MASK 0x00000404
52 #define MSGF_LEG_STATUS 0x00000420
53 #define MSGF_LEG_MASK 0x00000424
54 #define MSGF_MSI_STATUS_LO 0x00000440
55 #define MSGF_MSI_STATUS_HI 0x00000444
56 #define MSGF_MSI_MASK_LO 0x00000448
57 #define MSGF_MSI_MASK_HI 0x0000044C
59 /* Msg filter mask bits */
60 #define CFG_ENABLE_PM_MSG_FWD BIT(1)
61 #define CFG_ENABLE_INT_MSG_FWD BIT(2)
62 #define CFG_ENABLE_ERR_MSG_FWD BIT(3)
63 #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
64 CFG_ENABLE_INT_MSG_FWD | \
65 CFG_ENABLE_ERR_MSG_FWD)
67 /* Misc interrupt status mask bits */
68 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
69 #define MSGF_MISC_SR_RXMSG_OVER BIT(1)
70 #define MSGF_MISC_SR_SLAVE_ERR BIT(4)
71 #define MSGF_MISC_SR_MASTER_ERR BIT(5)
72 #define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
73 #define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
74 #define MSGF_MISC_SR_FATAL_AER BIT(16)
75 #define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
76 #define MSGF_MISC_SR_CORR_AER BIT(18)
77 #define MSGF_MISC_SR_UR_DETECT BIT(20)
78 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
79 #define MSGF_MISC_SR_FATAL_DEV BIT(23)
80 #define MSGF_MISC_SR_LINK_DOWN BIT(24)
81 #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
82 #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
84 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
85 MSGF_MISC_SR_RXMSG_OVER | \
86 MSGF_MISC_SR_SLAVE_ERR | \
87 MSGF_MISC_SR_MASTER_ERR | \
88 MSGF_MISC_SR_I_ADDR_ERR | \
89 MSGF_MISC_SR_E_ADDR_ERR | \
90 MSGF_MISC_SR_FATAL_AER | \
91 MSGF_MISC_SR_NON_FATAL_AER | \
92 MSGF_MISC_SR_CORR_AER | \
93 MSGF_MISC_SR_UR_DETECT | \
94 MSGF_MISC_SR_NON_FATAL_DEV | \
95 MSGF_MISC_SR_FATAL_DEV | \
96 MSGF_MISC_SR_LINK_DOWN | \
97 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
98 MSGF_MSIC_SR_LINK_BWIDTH)
100 /* Legacy interrupt status mask bits */
101 #define MSGF_LEG_SR_INTA BIT(0)
102 #define MSGF_LEG_SR_INTB BIT(1)
103 #define MSGF_LEG_SR_INTC BIT(2)
104 #define MSGF_LEG_SR_INTD BIT(3)
105 #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
106 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
108 /* MSI interrupt status mask bits */
109 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
110 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
112 #define MSII_PRESENT BIT(0)
113 #define MSII_ENABLE BIT(0)
114 #define MSII_STATUS_ENABLE BIT(15)
116 /* Bridge config interrupt mask */
117 #define BRCFG_INTERRUPT_MASK BIT(0)
118 #define BREG_PRESENT BIT(0)
119 #define BREG_ENABLE BIT(0)
120 #define BREG_ENABLE_FORCE BIT(1)
122 /* E_ECAM status mask bits */
123 #define E_ECAM_PRESENT BIT(0)
124 #define E_ECAM_CR_ENABLE BIT(0)
125 #define E_ECAM_SIZE_LOC GENMASK(20, 16)
126 #define E_ECAM_SIZE_SHIFT 16
127 #define ECAM_BUS_LOC_SHIFT 20
128 #define ECAM_DEV_LOC_SHIFT 12
129 #define NWL_ECAM_VALUE_DEFAULT 12
131 #define CFG_DMA_REG_BAR GENMASK(2, 0)
133 #define INT_PCI_MSI_NR (2 * 32)
135 /* Readin the PS_LINKUP */
136 #define PS_LINKUP_OFFSET 0x00000238
137 #define PCIE_PHY_LINKUP_BIT BIT(0)
138 #define PHY_RDY_LINKUP_BIT BIT(1)
140 /* Parameters for the waiting for link up routine */
141 #define LINK_WAIT_MAX_RETRIES 10
142 #define LINK_WAIT_USLEEP_MIN 90000
143 #define LINK_WAIT_USLEEP_MAX 100000
145 struct nwl_msi { /* MSI information */
146 struct irq_domain *msi_domain;
147 unsigned long *bitmap;
148 struct irq_domain *dev_domain;
149 struct mutex lock; /* protect bitmap variable */
156 void __iomem *breg_base;
157 void __iomem *pcireg_base;
158 void __iomem *ecam_base;
159 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
160 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
161 phys_addr_t phys_ecam_base; /* Physical Configuration Base */
170 struct irq_domain *legacy_irq_domain;
171 raw_spinlock_t leg_mask_lock;
174 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
176 return readl(pcie->breg_base + off);
179 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
181 writel(val, pcie->breg_base + off);
184 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
186 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
191 static bool nwl_phy_link_up(struct nwl_pcie *pcie)
193 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
198 static int nwl_wait_for_link(struct nwl_pcie *pcie)
200 struct device *dev = pcie->dev;
203 /* check if the link is up or not */
204 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
205 if (nwl_phy_link_up(pcie))
207 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
210 dev_err(dev, "PHY link never came up\n");
214 static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
216 struct nwl_pcie *pcie = bus->sysdata;
218 /* Check link before accessing downstream ports */
219 if (!pci_is_root_bus(bus)) {
220 if (!nwl_pcie_link_up(pcie))
222 } else if (devfn > 0)
223 /* Only one device down on each root port */
230 * nwl_pcie_map_bus - Get configuration base
232 * @bus: Bus structure of current bus
233 * @devfn: Device/function
234 * @where: Offset from base
236 * Return: Base address of the configuration space needed to be
239 static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
242 struct nwl_pcie *pcie = bus->sysdata;
245 if (!nwl_pcie_valid_device(bus, devfn))
248 relbus = (bus->number << ECAM_BUS_LOC_SHIFT) |
249 (devfn << ECAM_DEV_LOC_SHIFT);
251 return pcie->ecam_base + relbus + where;
254 /* PCIe operations */
255 static struct pci_ops nwl_pcie_ops = {
256 .map_bus = nwl_pcie_map_bus,
257 .read = pci_generic_config_read,
258 .write = pci_generic_config_write,
261 static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
263 struct nwl_pcie *pcie = data;
264 struct device *dev = pcie->dev;
267 /* Checking for misc interrupts */
268 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
269 MSGF_MISC_SR_MASKALL;
273 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
274 dev_err(dev, "Received Message FIFO Overflow\n");
276 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
277 dev_err(dev, "Slave error\n");
279 if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
280 dev_err(dev, "Master error\n");
282 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
283 dev_err(dev, "In Misc Ingress address translation error\n");
285 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
286 dev_err(dev, "In Misc Egress address translation error\n");
288 if (misc_stat & MSGF_MISC_SR_FATAL_AER)
289 dev_err(dev, "Fatal Error in AER Capability\n");
291 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
292 dev_err(dev, "Non-Fatal Error in AER Capability\n");
294 if (misc_stat & MSGF_MISC_SR_CORR_AER)
295 dev_err(dev, "Correctable Error in AER Capability\n");
297 if (misc_stat & MSGF_MISC_SR_UR_DETECT)
298 dev_err(dev, "Unsupported request Detected\n");
300 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
301 dev_err(dev, "Non-Fatal Error Detected\n");
303 if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
304 dev_err(dev, "Fatal Error Detected\n");
306 if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
307 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
309 if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
310 dev_info(dev, "Link Bandwidth Management Status bit set\n");
312 /* Clear misc interrupt status */
313 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
318 static void nwl_pcie_leg_handler(struct irq_desc *desc)
320 struct irq_chip *chip = irq_desc_get_chip(desc);
321 struct nwl_pcie *pcie;
322 unsigned long status;
326 chained_irq_enter(chip, desc);
327 pcie = irq_desc_get_handler_data(desc);
329 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
330 MSGF_LEG_SR_MASKALL) != 0) {
331 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
332 virq = irq_find_mapping(pcie->legacy_irq_domain, bit);
334 generic_handle_irq(virq);
338 chained_irq_exit(chip, desc);
341 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
344 unsigned long status;
350 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
351 for_each_set_bit(bit, &status, 32) {
352 nwl_bridge_writel(pcie, 1 << bit, status_reg);
353 virq = irq_find_mapping(msi->dev_domain, bit);
355 generic_handle_irq(virq);
360 static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
362 struct irq_chip *chip = irq_desc_get_chip(desc);
363 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
365 chained_irq_enter(chip, desc);
366 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
367 chained_irq_exit(chip, desc);
370 static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
372 struct irq_chip *chip = irq_desc_get_chip(desc);
373 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
375 chained_irq_enter(chip, desc);
376 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
377 chained_irq_exit(chip, desc);
380 static void nwl_mask_leg_irq(struct irq_data *data)
382 struct irq_desc *desc = irq_to_desc(data->irq);
383 struct nwl_pcie *pcie;
388 pcie = irq_desc_get_chip_data(desc);
389 mask = 1 << (data->hwirq - 1);
390 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
391 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
392 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
393 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
396 static void nwl_unmask_leg_irq(struct irq_data *data)
398 struct irq_desc *desc = irq_to_desc(data->irq);
399 struct nwl_pcie *pcie;
404 pcie = irq_desc_get_chip_data(desc);
405 mask = 1 << (data->hwirq - 1);
406 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
407 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
408 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
409 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
412 static struct irq_chip nwl_leg_irq_chip = {
413 .name = "nwl_pcie:legacy",
414 .irq_enable = nwl_unmask_leg_irq,
415 .irq_disable = nwl_mask_leg_irq,
416 .irq_mask = nwl_mask_leg_irq,
417 .irq_unmask = nwl_unmask_leg_irq,
420 static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
421 irq_hw_number_t hwirq)
423 irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
424 irq_set_chip_data(irq, domain->host_data);
425 irq_set_status_flags(irq, IRQ_LEVEL);
430 static const struct irq_domain_ops legacy_domain_ops = {
431 .map = nwl_legacy_map,
432 .xlate = pci_irqd_intx_xlate,
435 #ifdef CONFIG_PCI_MSI
436 static struct irq_chip nwl_msi_irq_chip = {
437 .name = "nwl_pcie:msi",
438 .irq_enable = pci_msi_unmask_irq,
439 .irq_disable = pci_msi_mask_irq,
440 .irq_mask = pci_msi_mask_irq,
441 .irq_unmask = pci_msi_unmask_irq,
444 static struct msi_domain_info nwl_msi_domain_info = {
445 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
446 MSI_FLAG_MULTI_PCI_MSI),
447 .chip = &nwl_msi_irq_chip,
451 static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
453 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
454 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
456 msg->address_lo = lower_32_bits(msi_addr);
457 msg->address_hi = upper_32_bits(msi_addr);
458 msg->data = data->hwirq;
461 static int nwl_msi_set_affinity(struct irq_data *irq_data,
462 const struct cpumask *mask, bool force)
467 static struct irq_chip nwl_irq_chip = {
468 .name = "Xilinx MSI",
469 .irq_compose_msi_msg = nwl_compose_msi_msg,
470 .irq_set_affinity = nwl_msi_set_affinity,
473 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
474 unsigned int nr_irqs, void *args)
476 struct nwl_pcie *pcie = domain->host_data;
477 struct nwl_msi *msi = &pcie->msi;
481 mutex_lock(&msi->lock);
482 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR,
483 get_count_order(nr_irqs));
485 mutex_unlock(&msi->lock);
489 for (i = 0; i < nr_irqs; i++) {
490 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
491 domain->host_data, handle_simple_irq,
494 mutex_unlock(&msi->lock);
498 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
499 unsigned int nr_irqs)
501 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
502 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
503 struct nwl_msi *msi = &pcie->msi;
505 mutex_lock(&msi->lock);
506 bitmap_release_region(msi->bitmap, data->hwirq,
507 get_count_order(nr_irqs));
508 mutex_unlock(&msi->lock);
511 static const struct irq_domain_ops dev_msi_domain_ops = {
512 .alloc = nwl_irq_domain_alloc,
513 .free = nwl_irq_domain_free,
516 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
518 #ifdef CONFIG_PCI_MSI
519 struct device *dev = pcie->dev;
520 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
521 struct nwl_msi *msi = &pcie->msi;
523 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
524 &dev_msi_domain_ops, pcie);
525 if (!msi->dev_domain) {
526 dev_err(dev, "failed to create dev IRQ domain\n");
529 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
530 &nwl_msi_domain_info,
532 if (!msi->msi_domain) {
533 dev_err(dev, "failed to create msi IRQ domain\n");
534 irq_domain_remove(msi->dev_domain);
541 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
543 struct device *dev = pcie->dev;
544 struct device_node *node = dev->of_node;
545 struct device_node *legacy_intc_node;
547 legacy_intc_node = of_get_next_child(node, NULL);
548 if (!legacy_intc_node) {
549 dev_err(dev, "No legacy intc node found\n");
553 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
557 of_node_put(legacy_intc_node);
558 if (!pcie->legacy_irq_domain) {
559 dev_err(dev, "failed to create IRQ domain\n");
563 raw_spin_lock_init(&pcie->leg_mask_lock);
564 nwl_pcie_init_msi_irq_domain(pcie);
568 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
570 struct device *dev = pcie->dev;
571 struct platform_device *pdev = to_platform_device(dev);
572 struct nwl_msi *msi = &pcie->msi;
575 int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long);
577 mutex_init(&msi->lock);
579 msi->bitmap = kzalloc(size, GFP_KERNEL);
583 /* Get msi_1 IRQ number */
584 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
585 if (msi->irq_msi1 < 0) {
590 irq_set_chained_handler_and_data(msi->irq_msi1,
591 nwl_pcie_msi_handler_high, pcie);
593 /* Get msi_0 IRQ number */
594 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
595 if (msi->irq_msi0 < 0) {
600 irq_set_chained_handler_and_data(msi->irq_msi0,
601 nwl_pcie_msi_handler_low, pcie);
603 /* Check for msii_present bit */
604 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
606 dev_err(dev, "MSI not present\n");
612 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
613 MSII_ENABLE, I_MSII_CONTROL);
615 /* Enable MSII status */
616 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
617 MSII_STATUS_ENABLE, I_MSII_CONTROL);
619 /* setup AFI/FPCI range */
620 base = pcie->phys_pcie_reg_base;
621 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
622 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
625 * For high range MSI interrupts: disable, clear any pending,
628 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
630 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
631 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
633 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
636 * For low range MSI interrupts: disable, clear any pending,
639 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
641 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
642 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
644 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
653 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
655 struct device *dev = pcie->dev;
656 struct platform_device *pdev = to_platform_device(dev);
657 u32 breg_val, ecam_val, first_busno = 0;
660 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
662 dev_err(dev, "BREG is not present\n");
666 /* Write bridge_off to breg base */
667 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
669 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
673 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
676 /* Disable DMA channel registers */
677 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
678 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
680 /* Enable Ingress subtractive decode translation */
681 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
683 /* Enable msg filtering details */
684 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
685 BRCFG_PCIE_RX_MSG_FILTER);
687 err = nwl_wait_for_link(pcie);
691 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
693 dev_err(dev, "ECAM is not present\n");
698 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
699 E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
701 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
702 (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
705 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
707 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
711 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
712 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
713 /* Write primary, secondary and subordinate bus numbers */
714 ecam_val = first_busno;
715 ecam_val |= (first_busno + 1) << 8;
716 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
717 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
719 if (nwl_pcie_link_up(pcie))
720 dev_info(dev, "Link is UP\n");
722 dev_info(dev, "Link is DOWN\n");
724 /* Get misc IRQ number */
725 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
726 if (pcie->irq_misc < 0)
729 err = devm_request_irq(dev, pcie->irq_misc,
730 nwl_pcie_misc_handler, IRQF_SHARED,
731 "nwl_pcie:misc", pcie);
733 dev_err(dev, "fail to register misc IRQ#%d\n",
738 /* Disable all misc interrupts */
739 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
741 /* Clear pending misc interrupts */
742 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
743 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
745 /* Enable all misc interrupts */
746 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
749 /* Disable all legacy interrupts */
750 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
752 /* Clear pending legacy interrupts */
753 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
754 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
756 /* Enable all legacy interrupts */
757 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
759 /* Enable the bridge config interrupt */
760 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
761 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
766 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
767 struct platform_device *pdev)
769 struct device *dev = pcie->dev;
770 struct resource *res;
772 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
773 pcie->breg_base = devm_ioremap_resource(dev, res);
774 if (IS_ERR(pcie->breg_base))
775 return PTR_ERR(pcie->breg_base);
776 pcie->phys_breg_base = res->start;
778 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
779 pcie->pcireg_base = devm_ioremap_resource(dev, res);
780 if (IS_ERR(pcie->pcireg_base))
781 return PTR_ERR(pcie->pcireg_base);
782 pcie->phys_pcie_reg_base = res->start;
784 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
785 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
786 if (IS_ERR(pcie->ecam_base))
787 return PTR_ERR(pcie->ecam_base);
788 pcie->phys_ecam_base = res->start;
790 /* Get intx IRQ number */
791 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
792 if (pcie->irq_intx < 0)
793 return pcie->irq_intx;
795 irq_set_chained_handler_and_data(pcie->irq_intx,
796 nwl_pcie_leg_handler, pcie);
801 static const struct of_device_id nwl_pcie_of_match[] = {
802 { .compatible = "xlnx,nwl-pcie-2.11", },
806 static int nwl_pcie_probe(struct platform_device *pdev)
808 struct device *dev = &pdev->dev;
809 struct nwl_pcie *pcie;
810 struct pci_host_bridge *bridge;
813 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
817 pcie = pci_host_bridge_priv(bridge);
820 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
822 err = nwl_pcie_parse_dt(pcie, pdev);
824 dev_err(dev, "Parsing DT failed\n");
828 err = nwl_pcie_bridge_init(pcie);
830 dev_err(dev, "HW Initialization failed\n");
834 err = nwl_pcie_init_irq_domain(pcie);
836 dev_err(dev, "Failed creating IRQ Domain\n");
840 bridge->sysdata = pcie;
841 bridge->ops = &nwl_pcie_ops;
843 if (IS_ENABLED(CONFIG_PCI_MSI)) {
844 err = nwl_pcie_enable_msi(pcie);
846 dev_err(dev, "failed to enable MSI support: %d\n", err);
851 return pci_host_probe(bridge);
854 static struct platform_driver nwl_pcie_driver = {
857 .suppress_bind_attrs = true,
858 .of_match_table = nwl_pcie_of_match,
860 .probe = nwl_pcie_probe,
862 builtin_platform_driver(nwl_pcie_driver);