1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
4 #include <linux/bitfield.h>
5 #include <linux/bitops.h>
7 #include <linux/compiler.h>
8 #include <linux/delay.h>
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
12 #include <linux/ioport.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/log2.h>
18 #include <linux/module.h>
19 #include <linux/msi.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_pci.h>
23 #include <linux/of_platform.h>
24 #include <linux/pci.h>
25 #include <linux/pci-ecam.h>
26 #include <linux/printk.h>
27 #include <linux/reset.h>
28 #include <linux/sizes.h>
29 #include <linux/slab.h>
30 #include <linux/string.h>
31 #include <linux/types.h>
35 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
36 #define BRCM_PCIE_CAP_REGS 0x00ac
38 /* Broadcom STB PCIe Register Offsets */
39 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
40 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
41 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
43 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
44 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
46 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
47 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
49 #define PCIE_RC_DL_MDIO_ADDR 0x1100
50 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
51 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
53 #define PCIE_MISC_MISC_CTRL 0x4008
54 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
55 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
56 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
58 #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
59 #define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
60 #define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
61 #define SCB_SIZE_MASK(x) PCIE_MISC_MISC_CTRL_SCB ## x ## _SIZE_MASK
63 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
64 #define PCIE_MEM_WIN0_LO(win) \
65 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
67 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
68 #define PCIE_MEM_WIN0_HI(win) \
69 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
71 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
72 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
74 #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
75 #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
76 #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
78 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
79 #define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
81 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
82 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
84 #define PCIE_MISC_MSI_DATA_CONFIG 0x404c
85 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
86 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
88 #define PCIE_MISC_PCIE_CTRL 0x4064
89 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
90 #define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
92 #define PCIE_MISC_PCIE_STATUS 0x4068
93 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
94 #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
95 #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
96 #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
98 #define PCIE_MISC_REVISION 0x406c
99 #define BRCM_PCIE_HW_REV_33 0x0303
100 #define BRCM_PCIE_HW_REV_3_20 0x0320
102 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
103 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
104 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
105 #define PCIE_MEM_WIN0_BASE_LIMIT(win) \
106 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
108 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
109 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
110 #define PCIE_MEM_WIN0_BASE_HI(win) \
111 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
113 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
114 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
115 #define PCIE_MEM_WIN0_LIMIT_HI(win) \
116 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
118 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
119 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
120 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
123 #define PCIE_INTR2_CPU_BASE 0x4300
124 #define PCIE_MSI_INTR2_BASE 0x4500
125 /* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */
126 #define MSI_INT_STATUS 0x0
127 #define MSI_INT_CLR 0x8
128 #define MSI_INT_MASK_SET 0x10
129 #define MSI_INT_MASK_CLR 0x14
131 #define PCIE_EXT_CFG_DATA 0x8000
132 #define PCIE_EXT_CFG_INDEX 0x9000
134 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
135 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
137 #define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
138 #define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
139 #define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
140 #define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
142 /* PCIe parameters */
143 #define BRCM_NUM_PCIE_OUT_WINS 0x4
144 #define BRCM_INT_PCI_MSI_NR 32
145 #define BRCM_INT_PCI_MSI_LEGACY_NR 8
146 #define BRCM_INT_PCI_MSI_SHIFT 0
148 /* MSI target adresses */
149 #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
150 #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
153 #define MDIO_PORT0 0x0
154 #define MDIO_DATA_MASK 0x7fffffff
155 #define MDIO_PORT_MASK 0xf0000
156 #define MDIO_REGAD_MASK 0xffff
157 #define MDIO_CMD_MASK 0xfff00000
158 #define MDIO_CMD_READ 0x1
159 #define MDIO_CMD_WRITE 0x0
160 #define MDIO_DATA_DONE_MASK 0x80000000
161 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
162 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
163 #define SSC_REGS_ADDR 0x1100
164 #define SET_ADDR_OFFSET 0x1f
165 #define SSC_CNTL_OFFSET 0x2
166 #define SSC_CNTL_OVRD_EN_MASK 0x8000
167 #define SSC_CNTL_OVRD_VAL_MASK 0x4000
168 #define SSC_STATUS_OFFSET 0x1
169 #define SSC_STATUS_SSC_MASK 0x400
170 #define SSC_STATUS_PLL_LOCK_MASK 0x800
171 #define PCIE_BRCM_MAX_MEMC 3
173 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
174 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
175 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
177 /* Rescal registers */
178 #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
179 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
180 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
181 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
182 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
183 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
184 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
185 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
187 /* Forward declarations */
189 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
190 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
191 static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val);
192 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
193 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
202 RGR1_SW_INIT_1_INIT_MASK,
203 RGR1_SW_INIT_1_INIT_SHIFT,
213 struct pcie_cfg_data {
215 const enum pcie_type type;
216 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
217 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
220 static const int pcie_offsets[] = {
221 [RGR1_SW_INIT_1] = 0x9210,
222 [EXT_CFG_INDEX] = 0x9000,
223 [EXT_CFG_DATA] = 0x9004,
226 static const struct pcie_cfg_data generic_cfg = {
227 .offsets = pcie_offsets,
229 .perst_set = brcm_pcie_perst_set_generic,
230 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
233 static const struct pcie_cfg_data bcm4908_cfg = {
234 .offsets = pcie_offsets,
236 .perst_set = brcm_pcie_perst_set_4908,
237 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
240 static const int pcie_offset_bcm7278[] = {
241 [RGR1_SW_INIT_1] = 0xc010,
242 [EXT_CFG_INDEX] = 0x9000,
243 [EXT_CFG_DATA] = 0x9004,
246 static const struct pcie_cfg_data bcm7278_cfg = {
247 .offsets = pcie_offset_bcm7278,
249 .perst_set = brcm_pcie_perst_set_7278,
250 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
253 static const struct pcie_cfg_data bcm2711_cfg = {
254 .offsets = pcie_offsets,
256 .perst_set = brcm_pcie_perst_set_generic,
257 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
263 struct device_node *np;
264 struct irq_domain *msi_domain;
265 struct irq_domain *inner_domain;
266 struct mutex lock; /* guards the alloc/free operations */
269 /* used indicates which MSI interrupts have been alloc'd */
272 /* Some chips have MSIs in bits [31..24] of a shared register. */
274 int nr; /* No. of MSI available, depends on chip */
275 /* This is the base pointer for interrupt status/set/clr regs */
276 void __iomem *intr_base;
279 /* Internal PCIe Host Controller Information.*/
284 struct device_node *np;
288 struct brcm_msi *msi;
289 const int *reg_offsets;
291 struct reset_control *rescal;
292 struct reset_control *perst_reset;
294 u64 memc_size[PCIE_BRCM_MAX_MEMC];
296 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
297 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
301 * This is to convert the size of the inbound "BAR" region to the
302 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
304 static int brcm_pcie_encode_ibar_size(u64 size)
306 int log2_in = ilog2(size);
308 if (log2_in >= 12 && log2_in <= 15)
309 /* Covers 4KB to 32KB (inclusive) */
310 return (log2_in - 12) + 0x1c;
311 else if (log2_in >= 16 && log2_in <= 35)
312 /* Covers 64KB to 32GB, (inclusive) */
314 /* Something is awry so disable */
318 static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd)
322 pkt |= FIELD_PREP(MDIO_PORT_MASK, port);
323 pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad);
324 pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd);
329 /* negative return value indicates error */
330 static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val)
335 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ),
336 base + PCIE_RC_DL_MDIO_ADDR);
337 readl(base + PCIE_RC_DL_MDIO_ADDR);
339 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
340 for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
342 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
345 *val = FIELD_GET(MDIO_DATA_MASK, data);
346 return MDIO_RD_DONE(data) ? 0 : -EIO;
349 /* negative return value indicates error */
350 static int brcm_pcie_mdio_write(void __iomem *base, u8 port,
351 u8 regad, u16 wrdata)
356 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
357 base + PCIE_RC_DL_MDIO_ADDR);
358 readl(base + PCIE_RC_DL_MDIO_ADDR);
359 writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
361 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
362 for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
364 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
367 return MDIO_WT_DONE(data) ? 0 : -EIO;
371 * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
372 * return value indicates error.
374 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie)
380 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
385 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
386 SSC_CNTL_OFFSET, &tmp);
390 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK);
391 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK);
392 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0,
393 SSC_CNTL_OFFSET, tmp);
397 usleep_range(1000, 2000);
398 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
399 SSC_STATUS_OFFSET, &tmp);
403 ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp);
404 pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp);
406 return ssc && pll ? 0 : -EIO;
409 /* Limits operation to a specific generation (1, 2, or 3) */
410 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
412 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
413 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
415 lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
416 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
418 lnkctl2 = (lnkctl2 & ~0xf) | gen;
419 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
422 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
423 unsigned int win, u64 cpu_addr,
424 u64 pcie_addr, u64 size)
426 u32 cpu_addr_mb_high, limit_addr_mb_high;
427 phys_addr_t cpu_addr_mb, limit_addr_mb;
431 /* Set the base of the pcie_addr window */
432 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win));
433 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win));
435 /* Write the addr base & limit lower bits (in MBs) */
436 cpu_addr_mb = cpu_addr / SZ_1M;
437 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M;
439 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
440 u32p_replace_bits(&tmp, cpu_addr_mb,
441 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
442 u32p_replace_bits(&tmp, limit_addr_mb,
443 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
444 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
446 /* Write the cpu & limit addr upper bits */
448 HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
450 cpu_addr_mb_high = cpu_addr_mb >> high_addr_shift;
451 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
452 u32p_replace_bits(&tmp, cpu_addr_mb_high,
453 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK);
454 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
456 limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
457 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
458 u32p_replace_bits(&tmp, limit_addr_mb_high,
459 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
460 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
463 static struct irq_chip brcm_msi_irq_chip = {
464 .name = "BRCM STB PCIe MSI",
465 .irq_ack = irq_chip_ack_parent,
466 .irq_mask = pci_msi_mask_irq,
467 .irq_unmask = pci_msi_unmask_irq,
470 static struct msi_domain_info brcm_msi_domain_info = {
471 /* Multi MSI is supported by the controller, but not by this driver */
472 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
473 .chip = &brcm_msi_irq_chip,
476 static void brcm_pcie_msi_isr(struct irq_desc *desc)
478 struct irq_chip *chip = irq_desc_get_chip(desc);
479 unsigned long status, virq;
480 struct brcm_msi *msi;
484 chained_irq_enter(chip, desc);
485 msi = irq_desc_get_handler_data(desc);
488 status = readl(msi->intr_base + MSI_INT_STATUS);
489 status >>= msi->legacy_shift;
491 for_each_set_bit(bit, &status, msi->nr) {
492 virq = irq_find_mapping(msi->inner_domain, bit);
494 generic_handle_irq(virq);
496 dev_dbg(dev, "unexpected MSI\n");
499 chained_irq_exit(chip, desc);
502 static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
504 struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
506 msg->address_lo = lower_32_bits(msi->target_addr);
507 msg->address_hi = upper_32_bits(msi->target_addr);
508 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq;
511 static int brcm_msi_set_affinity(struct irq_data *irq_data,
512 const struct cpumask *mask, bool force)
517 static void brcm_msi_ack_irq(struct irq_data *data)
519 struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
520 const int shift_amt = data->hwirq + msi->legacy_shift;
522 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR);
526 static struct irq_chip brcm_msi_bottom_irq_chip = {
527 .name = "BRCM STB MSI",
528 .irq_compose_msi_msg = brcm_msi_compose_msi_msg,
529 .irq_set_affinity = brcm_msi_set_affinity,
530 .irq_ack = brcm_msi_ack_irq,
533 static int brcm_msi_alloc(struct brcm_msi *msi)
537 mutex_lock(&msi->lock);
538 hwirq = bitmap_find_free_region(&msi->used, msi->nr, 0);
539 mutex_unlock(&msi->lock);
544 static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
546 mutex_lock(&msi->lock);
547 bitmap_release_region(&msi->used, hwirq, 0);
548 mutex_unlock(&msi->lock);
551 static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
552 unsigned int nr_irqs, void *args)
554 struct brcm_msi *msi = domain->host_data;
557 hwirq = brcm_msi_alloc(msi);
562 irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
563 &brcm_msi_bottom_irq_chip, domain->host_data,
564 handle_edge_irq, NULL, NULL);
568 static void brcm_irq_domain_free(struct irq_domain *domain,
569 unsigned int virq, unsigned int nr_irqs)
571 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
572 struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
574 brcm_msi_free(msi, d->hwirq);
577 static const struct irq_domain_ops msi_domain_ops = {
578 .alloc = brcm_irq_domain_alloc,
579 .free = brcm_irq_domain_free,
582 static int brcm_allocate_domains(struct brcm_msi *msi)
584 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np);
585 struct device *dev = msi->dev;
587 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi);
588 if (!msi->inner_domain) {
589 dev_err(dev, "failed to create IRQ domain\n");
593 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
594 &brcm_msi_domain_info,
596 if (!msi->msi_domain) {
597 dev_err(dev, "failed to create MSI domain\n");
598 irq_domain_remove(msi->inner_domain);
605 static void brcm_free_domains(struct brcm_msi *msi)
607 irq_domain_remove(msi->msi_domain);
608 irq_domain_remove(msi->inner_domain);
611 static void brcm_msi_remove(struct brcm_pcie *pcie)
613 struct brcm_msi *msi = pcie->msi;
617 irq_set_chained_handler_and_data(msi->irq, NULL, NULL);
618 brcm_free_domains(msi);
621 static void brcm_msi_set_regs(struct brcm_msi *msi)
623 u32 val = __GENMASK(31, msi->legacy_shift);
625 writel(val, msi->intr_base + MSI_INT_MASK_CLR);
626 writel(val, msi->intr_base + MSI_INT_CLR);
629 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
630 * enable, which we set to 1.
632 writel(lower_32_bits(msi->target_addr) | 0x1,
633 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
634 writel(upper_32_bits(msi->target_addr),
635 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
637 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32;
638 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
641 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
643 struct brcm_msi *msi;
645 struct device *dev = pcie->dev;
647 irq = irq_of_parse_and_map(dev->of_node, 1);
649 dev_err(dev, "cannot map MSI interrupt\n");
653 msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL);
657 mutex_init(&msi->lock);
659 msi->base = pcie->base;
661 msi->target_addr = pcie->msi_target_addr;
663 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33;
666 msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
667 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR;
668 msi->legacy_shift = 24;
670 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
671 msi->nr = BRCM_INT_PCI_MSI_NR;
672 msi->legacy_shift = 0;
675 ret = brcm_allocate_domains(msi);
679 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
681 brcm_msi_set_regs(msi);
687 /* The controller is capable of serving in both RC and EP roles */
688 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
690 void __iomem *base = pcie->base;
691 u32 val = readl(base + PCIE_MISC_PCIE_STATUS);
693 return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val);
696 static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
698 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
699 u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val);
700 u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val);
705 static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
708 struct brcm_pcie *pcie = bus->sysdata;
709 void __iomem *base = pcie->base;
712 /* Accesses to the RC go right to the RC registers if slot==0 */
713 if (pci_is_root_bus(bus))
714 return PCI_SLOT(devfn) ? NULL : base + where;
716 /* For devices, write to the config space index register */
717 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
718 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
719 return base + PCIE_EXT_CFG_DATA + where;
722 static struct pci_ops brcm_pcie_ops = {
723 .map_bus = brcm_pcie_map_conf,
724 .read = pci_generic_config_read,
725 .write = pci_generic_config_write,
728 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
730 u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
731 u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
733 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
734 tmp = (tmp & ~mask) | ((val << shift) & mask);
735 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
738 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
740 u32 tmp, mask = RGR1_SW_INIT_1_INIT_7278_MASK;
741 u32 shift = RGR1_SW_INIT_1_INIT_7278_SHIFT;
743 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
744 tmp = (tmp & ~mask) | ((val << shift) & mask);
745 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
748 static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
750 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n"))
754 reset_control_assert(pcie->perst_reset);
756 reset_control_deassert(pcie->perst_reset);
759 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
763 /* Perst bit has moved and assert value is 0 */
764 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
765 u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK);
766 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
769 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
773 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
774 u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK);
775 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
778 static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
782 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
783 struct resource_entry *entry;
784 struct device *dev = pcie->dev;
785 u64 lowest_pcie_addr = ~(u64)0;
789 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
790 u64 pcie_beg = entry->res->start - entry->offset;
792 size += entry->res->end - entry->res->start + 1;
793 if (pcie_beg < lowest_pcie_addr)
794 lowest_pcie_addr = pcie_beg;
797 if (lowest_pcie_addr == ~(u64)0) {
798 dev_err(dev, "DT node has no dma-ranges\n");
802 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1,
806 /* Make an educated guess */
808 pcie->memc_size[0] = 1ULL << fls64(size - 1);
810 pcie->num_memc = ret;
813 /* Each memc is viewed through a "port" that is a power of 2 */
814 for (i = 0, size = 0; i < pcie->num_memc; i++)
815 size += pcie->memc_size[i];
817 /* System memory starts at this address in PCIe-space */
818 *rc_bar2_offset = lowest_pcie_addr;
819 /* The sum of all memc views must also be a power of 2 */
820 *rc_bar2_size = 1ULL << fls64(size - 1);
823 * We validate the inbound memory view even though we should trust
824 * whatever the device-tree provides. This is because of an HW issue on
825 * early Raspberry Pi 4's revisions (bcm2711). It turns out its
826 * firmware has to dynamically edit dma-ranges due to a bug on the
827 * PCIe controller integration, which prohibits any access above the
828 * lower 3GB of memory. Given this, we decided to keep the dma-ranges
829 * in check, avoiding hard to debug device-tree related issues in the
832 * The PCIe host controller by design must set the inbound viewport to
833 * be a contiguous arrangement of all of the system's memory. In
834 * addition, its size mut be a power of two. To further complicate
835 * matters, the viewport must start on a pcie-address that is aligned
836 * on a multiple of its size. If a portion of the viewport does not
837 * represent system memory -- e.g. 3GB of memory requires a 4GB
838 * viewport -- we can map the outbound memory in or after 3GB and even
839 * though the viewport will overlap the outbound memory the controller
840 * will know to send outbound memory downstream and everything else
845 * - The best-case scenario, memory up to 3GB, is to place the inbound
846 * region in the first 4GB of pcie-space, as some legacy devices can
847 * only address 32bits. We would also like to put the MSI under 4GB
848 * as well, since some devices require a 32bit MSI target address.
850 * - If the system memory is 4GB or larger we cannot start the inbound
851 * region at location 0 (since we have to allow some space for
852 * outbound memory @ 3GB). So instead it will start at the 1x
853 * multiple of its size
855 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) ||
856 (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
857 dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
858 *rc_bar2_size, *rc_bar2_offset);
865 static int brcm_pcie_setup(struct brcm_pcie *pcie)
867 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
868 u64 rc_bar2_offset, rc_bar2_size;
869 void __iomem *base = pcie->base;
870 struct device *dev = pcie->dev;
871 struct resource_entry *entry;
872 bool ssc_good = false;
873 struct resource *res;
874 int num_out_wins = 0;
875 u16 nlw, cls, lnksta;
877 u32 tmp, burst, aspm_support;
879 /* Reset the bridge */
880 pcie->bridge_sw_init_set(pcie, 1);
881 usleep_range(100, 200);
883 /* Take the bridge out of reset */
884 pcie->bridge_sw_init_set(pcie, 0);
886 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
887 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
888 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
889 /* Wait for SerDes to be stable */
890 usleep_range(100, 200);
893 * SCB_MAX_BURST_SIZE is a two bit field. For GENERIC chips it
894 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it
895 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512.
897 if (pcie->type == BCM2711)
898 burst = 0x0; /* 128B */
899 else if (pcie->type == BCM7278)
900 burst = 0x3; /* 512 bytes */
902 burst = 0x2; /* 512 bytes */
904 /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
905 tmp = readl(base + PCIE_MISC_MISC_CTRL);
906 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);
907 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);
908 u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);
909 writel(tmp, base + PCIE_MISC_MISC_CTRL);
911 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
916 tmp = lower_32_bits(rc_bar2_offset);
917 u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
918 PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK);
919 writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
920 writel(upper_32_bits(rc_bar2_offset),
921 base + PCIE_MISC_RC_BAR2_CONFIG_HI);
923 tmp = readl(base + PCIE_MISC_MISC_CTRL);
924 for (memc = 0; memc < pcie->num_memc; memc++) {
925 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15;
928 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0));
930 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(1));
932 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(2));
934 writel(tmp, base + PCIE_MISC_MISC_CTRL);
937 * We ideally want the MSI target address to be located in the 32bit
938 * addressable memory area. Some devices might depend on it. This is
939 * possible either when the inbound window is located above the lower
940 * 4GB or when the inbound area is smaller than 4GB (taking into
941 * account the rounding-up we're forced to perform).
943 if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G)
944 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
946 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
948 /* disable the PCIe->GISB memory window (RC_BAR1) */
949 tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO);
950 tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK;
951 writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO);
953 /* disable the PCIe->SCB memory window (RC_BAR3) */
954 tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO);
955 tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK;
956 writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO);
959 brcm_pcie_set_gen(pcie, pcie->gen);
961 /* Unassert the fundamental reset */
962 pcie->perst_set(pcie, 0);
965 * Give the RC/EP time to wake up, before trying to configure RC.
966 * Intermittently check status for link-up, up to a total of 100ms.
968 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
971 if (!brcm_pcie_link_up(pcie)) {
972 dev_err(dev, "link down\n");
976 if (!brcm_pcie_rc_mode(pcie)) {
977 dev_err(dev, "PCIe misconfigured; is in EP mode\n");
981 resource_list_for_each_entry(entry, &bridge->windows) {
984 if (resource_type(res) != IORESOURCE_MEM)
987 if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
988 dev_err(pcie->dev, "too many outbound wins\n");
992 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
993 res->start - entry->offset,
998 /* Don't advertise L0s capability if 'aspm-no-l0s' */
999 aspm_support = PCIE_LINK_STATE_L1;
1000 if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
1001 aspm_support |= PCIE_LINK_STATE_L0S;
1002 tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
1003 u32p_replace_bits(&tmp, aspm_support,
1004 PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
1005 writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
1008 * For config space accesses on the RC, show the right class for
1009 * a PCIe-PCIe bridge (the default setting is to be EP mode).
1011 tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
1012 u32p_replace_bits(&tmp, 0x060400,
1013 PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
1014 writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
1017 ret = brcm_pcie_set_ssc(pcie);
1021 dev_err(dev, "failed attempt to enter ssc mode\n");
1024 lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
1025 cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);
1026 nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
1027 dev_info(dev, "link up, %s x%u %s\n",
1028 pci_speed_string(pcie_link_speed[cls]), nlw,
1029 ssc_good ? "(SSC)" : "(!SSC)");
1031 /* PCIe->SCB endian mode for BAR */
1032 tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1033 u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
1034 PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
1035 writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1038 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
1039 * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
1041 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1042 tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
1043 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1048 /* L23 is a low-power PCIe link state */
1049 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
1051 void __iomem *base = pcie->base;
1055 /* Assert request for L23 */
1056 tmp = readl(base + PCIE_MISC_PCIE_CTRL);
1057 u32p_replace_bits(&tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
1058 writel(tmp, base + PCIE_MISC_PCIE_CTRL);
1060 /* Wait up to 36 msec for L23 */
1061 tmp = readl(base + PCIE_MISC_PCIE_STATUS);
1062 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, tmp);
1063 for (i = 0; i < 15 && !l23; i++) {
1064 usleep_range(2000, 2400);
1065 tmp = readl(base + PCIE_MISC_PCIE_STATUS);
1066 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK,
1071 dev_err(pcie->dev, "failed to enter low-power link state\n");
1074 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start)
1076 static const u32 shifts[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
1077 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT,
1078 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT,
1079 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT,};
1080 static const u32 masks[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
1081 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK,
1082 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK,
1083 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK,};
1084 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1;
1085 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1;
1086 u32 tmp, combined_mask = 0;
1088 void __iomem *base = pcie->base;
1091 for (i = beg; i != end; start ? i++ : i--) {
1092 val = start ? BIT_MASK(shifts[i]) : 0;
1093 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1094 tmp = (tmp & ~masks[i]) | (val & masks[i]);
1095 writel(tmp, base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1096 usleep_range(50, 200);
1097 combined_mask |= masks[i];
1100 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1101 val = start ? combined_mask : 0;
1103 ret = (tmp & combined_mask) == val ? 0 : -EIO;
1105 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop"));
1110 static inline int brcm_phy_start(struct brcm_pcie *pcie)
1112 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0;
1115 static inline int brcm_phy_stop(struct brcm_pcie *pcie)
1117 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0;
1120 static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
1122 void __iomem *base = pcie->base;
1125 if (brcm_pcie_link_up(pcie))
1126 brcm_pcie_enter_l23(pcie);
1127 /* Assert fundamental reset */
1128 pcie->perst_set(pcie, 1);
1130 /* Deassert request for L23 in case it was asserted */
1131 tmp = readl(base + PCIE_MISC_PCIE_CTRL);
1132 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
1133 writel(tmp, base + PCIE_MISC_PCIE_CTRL);
1135 /* Turn off SerDes */
1136 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1137 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
1138 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1140 /* Shutdown PCIe bridge */
1141 pcie->bridge_sw_init_set(pcie, 1);
1144 static int brcm_pcie_suspend(struct device *dev)
1146 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1149 brcm_pcie_turn_off(pcie);
1150 ret = brcm_phy_stop(pcie);
1151 clk_disable_unprepare(pcie->clk);
1156 static int brcm_pcie_resume(struct device *dev)
1158 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1164 clk_prepare_enable(pcie->clk);
1166 ret = brcm_phy_start(pcie);
1170 /* Take bridge out of reset so we can access the SERDES reg */
1171 pcie->bridge_sw_init_set(pcie, 0);
1173 /* SERDES_IDDQ = 0 */
1174 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1175 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
1176 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1178 /* wait for serdes to be stable */
1181 ret = brcm_pcie_setup(pcie);
1186 brcm_msi_set_regs(pcie->msi);
1191 clk_disable_unprepare(pcie->clk);
1195 static void __brcm_pcie_remove(struct brcm_pcie *pcie)
1197 brcm_msi_remove(pcie);
1198 brcm_pcie_turn_off(pcie);
1199 brcm_phy_stop(pcie);
1200 reset_control_assert(pcie->rescal);
1201 clk_disable_unprepare(pcie->clk);
1204 static int brcm_pcie_remove(struct platform_device *pdev)
1206 struct brcm_pcie *pcie = platform_get_drvdata(pdev);
1207 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1209 pci_stop_root_bus(bridge->bus);
1210 pci_remove_root_bus(bridge->bus);
1211 __brcm_pcie_remove(pcie);
1216 static const struct of_device_id brcm_pcie_match[] = {
1217 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1218 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1219 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1220 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1221 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1222 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1226 static int brcm_pcie_probe(struct platform_device *pdev)
1228 struct device_node *np = pdev->dev.of_node, *msi_np;
1229 struct pci_host_bridge *bridge;
1230 const struct pcie_cfg_data *data;
1231 struct brcm_pcie *pcie;
1234 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
1238 data = of_device_get_match_data(&pdev->dev);
1240 pr_err("failed to look up compatible string\n");
1244 pcie = pci_host_bridge_priv(bridge);
1245 pcie->dev = &pdev->dev;
1247 pcie->reg_offsets = data->offsets;
1248 pcie->type = data->type;
1249 pcie->perst_set = data->perst_set;
1250 pcie->bridge_sw_init_set = data->bridge_sw_init_set;
1252 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1253 if (IS_ERR(pcie->base))
1254 return PTR_ERR(pcie->base);
1256 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie");
1257 if (IS_ERR(pcie->clk))
1258 return PTR_ERR(pcie->clk);
1260 ret = of_pci_get_max_link_speed(np);
1261 pcie->gen = (ret < 0) ? 0 : ret;
1263 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
1265 ret = clk_prepare_enable(pcie->clk);
1267 dev_err(&pdev->dev, "could not enable clock\n");
1270 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal");
1271 if (IS_ERR(pcie->rescal)) {
1272 clk_disable_unprepare(pcie->clk);
1273 return PTR_ERR(pcie->rescal);
1275 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst");
1276 if (IS_ERR(pcie->perst_reset)) {
1277 clk_disable_unprepare(pcie->clk);
1278 return PTR_ERR(pcie->perst_reset);
1281 ret = reset_control_deassert(pcie->rescal);
1283 dev_err(&pdev->dev, "failed to deassert 'rescal'\n");
1285 ret = brcm_phy_start(pcie);
1287 reset_control_assert(pcie->rescal);
1288 clk_disable_unprepare(pcie->clk);
1292 ret = brcm_pcie_setup(pcie);
1296 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
1297 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
1298 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
1302 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
1303 if (pci_msi_enabled() && msi_np == pcie->np) {
1304 ret = brcm_pcie_enable_msi(pcie);
1306 dev_err(pcie->dev, "probe of internal MSI failed");
1311 bridge->ops = &brcm_pcie_ops;
1312 bridge->sysdata = pcie;
1314 platform_set_drvdata(pdev, pcie);
1316 return pci_host_probe(bridge);
1318 __brcm_pcie_remove(pcie);
1322 MODULE_DEVICE_TABLE(of, brcm_pcie_match);
1324 static const struct dev_pm_ops brcm_pcie_pm_ops = {
1325 .suspend = brcm_pcie_suspend,
1326 .resume = brcm_pcie_resume,
1329 static struct platform_driver brcm_pcie_driver = {
1330 .probe = brcm_pcie_probe,
1331 .remove = brcm_pcie_remove,
1333 .name = "brcm-pcie",
1334 .of_match_table = brcm_pcie_match,
1335 .pm = &brcm_pcie_pm_ops,
1338 module_platform_driver(brcm_pcie_driver);
1340 MODULE_LICENSE("GPL");
1341 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
1342 MODULE_AUTHOR("Broadcom");