1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Faraday Technology FTPC100 PCI Controller
5 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
7 * Based on the out-of-tree OpenWRT patch for Cortina Gemini:
8 * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
9 * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
10 * Based on SL2312 PCI controller code
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_pci.h>
22 #include <linux/pci.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/irqdomain.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/bitops.h>
28 #include <linux/irq.h>
29 #include <linux/clk.h>
34 * Special configuration registers directly in the first few words
37 #define PCI_IOSIZE 0x00
38 #define PCI_PROT 0x04 /* AHB protection */
39 #define PCI_CTRL 0x08 /* PCI control signal */
40 #define PCI_SOFTRST 0x10 /* Soft reset counter and response error enable */
41 #define PCI_CONFIG 0x28 /* PCI configuration command register */
44 #define FARADAY_PCI_STATUS_CMD 0x04 /* Status and command */
45 #define FARADAY_PCI_PMC 0x40 /* Power management control */
46 #define FARADAY_PCI_PMCSR 0x44 /* Power management status */
47 #define FARADAY_PCI_CTRL1 0x48 /* Control register 1 */
48 #define FARADAY_PCI_CTRL2 0x4C /* Control register 2 */
49 #define FARADAY_PCI_MEM1_BASE_SIZE 0x50 /* Memory base and size #1 */
50 #define FARADAY_PCI_MEM2_BASE_SIZE 0x54 /* Memory base and size #2 */
51 #define FARADAY_PCI_MEM3_BASE_SIZE 0x58 /* Memory base and size #3 */
53 #define PCI_STATUS_66MHZ_CAPABLE BIT(21)
55 /* Bits 31..28 gives INTD..INTA status */
56 #define PCI_CTRL2_INTSTS_SHIFT 28
57 #define PCI_CTRL2_INTMASK_CMDERR BIT(27)
58 #define PCI_CTRL2_INTMASK_PARERR BIT(26)
59 /* Bits 25..22 masks INTD..INTA */
60 #define PCI_CTRL2_INTMASK_SHIFT 22
61 #define PCI_CTRL2_INTMASK_MABRT_RX BIT(21)
62 #define PCI_CTRL2_INTMASK_TABRT_RX BIT(20)
63 #define PCI_CTRL2_INTMASK_TABRT_TX BIT(19)
64 #define PCI_CTRL2_INTMASK_RETRY4 BIT(18)
65 #define PCI_CTRL2_INTMASK_SERR_RX BIT(17)
66 #define PCI_CTRL2_INTMASK_PERR_RX BIT(16)
68 #define PCI_CTRL2_MSTPRI_REQ6 BIT(14)
69 #define PCI_CTRL2_MSTPRI_REQ5 BIT(13)
70 #define PCI_CTRL2_MSTPRI_REQ4 BIT(12)
71 #define PCI_CTRL2_MSTPRI_REQ3 BIT(11)
72 #define PCI_CTRL2_MSTPRI_REQ2 BIT(10)
73 #define PCI_CTRL2_MSTPRI_REQ1 BIT(9)
74 #define PCI_CTRL2_MSTPRI_REQ0 BIT(8)
75 /* Bits 7..4 reserved */
80 * Bit 31..20 defines the PCI side memory base
81 * Bit 19..16 (4 bits) defines the size per below
83 #define FARADAY_PCI_MEMBASE_MASK 0xfff00000
84 #define FARADAY_PCI_MEMSIZE_1MB 0x0
85 #define FARADAY_PCI_MEMSIZE_2MB 0x1
86 #define FARADAY_PCI_MEMSIZE_4MB 0x2
87 #define FARADAY_PCI_MEMSIZE_8MB 0x3
88 #define FARADAY_PCI_MEMSIZE_16MB 0x4
89 #define FARADAY_PCI_MEMSIZE_32MB 0x5
90 #define FARADAY_PCI_MEMSIZE_64MB 0x6
91 #define FARADAY_PCI_MEMSIZE_128MB 0x7
92 #define FARADAY_PCI_MEMSIZE_256MB 0x8
93 #define FARADAY_PCI_MEMSIZE_512MB 0x9
94 #define FARADAY_PCI_MEMSIZE_1GB 0xa
95 #define FARADAY_PCI_MEMSIZE_2GB 0xb
96 #define FARADAY_PCI_MEMSIZE_SHIFT 16
99 * The DMA base is set to 0x0 for all memory segments, it reflects the
100 * fact that the memory of the host system starts at 0x0.
102 #define FARADAY_PCI_DMA_MEM1_BASE 0x00000000
103 #define FARADAY_PCI_DMA_MEM2_BASE 0x00000000
104 #define FARADAY_PCI_DMA_MEM3_BASE 0x00000000
106 /* Defines for PCI configuration command register */
107 #define PCI_CONF_ENABLE BIT(31)
108 #define PCI_CONF_WHERE(r) ((r) & 0xFC)
109 #define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
110 #define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
111 #define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
114 * struct faraday_pci_variant - encodes IP block differences
115 * @cascaded_irq: this host has cascaded IRQs from an interrupt controller
116 * embedded in the host bridge.
118 struct faraday_pci_variant {
125 struct irq_domain *irqdomain;
130 static int faraday_res_to_memcfg(resource_size_t mem_base,
131 resource_size_t mem_size, u32 *val)
137 outval = FARADAY_PCI_MEMSIZE_1MB;
140 outval = FARADAY_PCI_MEMSIZE_2MB;
143 outval = FARADAY_PCI_MEMSIZE_4MB;
146 outval = FARADAY_PCI_MEMSIZE_8MB;
149 outval = FARADAY_PCI_MEMSIZE_16MB;
152 outval = FARADAY_PCI_MEMSIZE_32MB;
155 outval = FARADAY_PCI_MEMSIZE_64MB;
158 outval = FARADAY_PCI_MEMSIZE_128MB;
161 outval = FARADAY_PCI_MEMSIZE_256MB;
164 outval = FARADAY_PCI_MEMSIZE_512MB;
167 outval = FARADAY_PCI_MEMSIZE_1GB;
170 outval = FARADAY_PCI_MEMSIZE_2GB;
175 outval <<= FARADAY_PCI_MEMSIZE_SHIFT;
177 /* This is probably not good */
178 if (mem_base & ~(FARADAY_PCI_MEMBASE_MASK))
179 pr_warn("truncated PCI memory base\n");
180 /* Translate to bridge side address space */
181 outval |= (mem_base & FARADAY_PCI_MEMBASE_MASK);
182 pr_debug("Translated pci base @%pap, size %pap to config %08x\n",
183 &mem_base, &mem_size, outval);
189 static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number,
190 unsigned int fn, int config, int size,
193 writel(PCI_CONF_BUS(bus_number) |
194 PCI_CONF_DEVICE(PCI_SLOT(fn)) |
195 PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
196 PCI_CONF_WHERE(config) |
198 p->base + PCI_CONFIG);
200 *value = readl(p->base + PCI_DATA);
203 *value = (*value >> (8 * (config & 3))) & 0xFF;
205 *value = (*value >> (8 * (config & 3))) & 0xFFFF;
207 return PCIBIOS_SUCCESSFUL;
210 static int faraday_pci_read_config(struct pci_bus *bus, unsigned int fn,
211 int config, int size, u32 *value)
213 struct faraday_pci *p = bus->sysdata;
216 "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
217 PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
219 return faraday_raw_pci_read_config(p, bus->number, fn, config, size, value);
222 static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number,
223 unsigned int fn, int config, int size,
226 int ret = PCIBIOS_SUCCESSFUL;
228 writel(PCI_CONF_BUS(bus_number) |
229 PCI_CONF_DEVICE(PCI_SLOT(fn)) |
230 PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
231 PCI_CONF_WHERE(config) |
233 p->base + PCI_CONFIG);
237 writel(value, p->base + PCI_DATA);
240 writew(value, p->base + PCI_DATA + (config & 3));
243 writeb(value, p->base + PCI_DATA + (config & 3));
246 ret = PCIBIOS_BAD_REGISTER_NUMBER;
252 static int faraday_pci_write_config(struct pci_bus *bus, unsigned int fn,
253 int config, int size, u32 value)
255 struct faraday_pci *p = bus->sysdata;
258 "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
259 PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
261 return faraday_raw_pci_write_config(p, bus->number, fn, config, size,
265 static struct pci_ops faraday_pci_ops = {
266 .read = faraday_pci_read_config,
267 .write = faraday_pci_write_config,
270 static void faraday_pci_ack_irq(struct irq_data *d)
272 struct faraday_pci *p = irq_data_get_irq_chip_data(d);
275 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
276 reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
277 reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT);
278 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
281 static void faraday_pci_mask_irq(struct irq_data *d)
283 struct faraday_pci *p = irq_data_get_irq_chip_data(d);
286 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
287 reg &= ~((0xF << PCI_CTRL2_INTSTS_SHIFT)
288 | BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT));
289 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
292 static void faraday_pci_unmask_irq(struct irq_data *d)
294 struct faraday_pci *p = irq_data_get_irq_chip_data(d);
297 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
298 reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
299 reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT);
300 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
303 static void faraday_pci_irq_handler(struct irq_desc *desc)
305 struct faraday_pci *p = irq_desc_get_handler_data(desc);
306 struct irq_chip *irqchip = irq_desc_get_chip(desc);
307 unsigned int irq_stat, reg, i;
309 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
310 irq_stat = reg >> PCI_CTRL2_INTSTS_SHIFT;
312 chained_irq_enter(irqchip, desc);
314 for (i = 0; i < 4; i++) {
315 if ((irq_stat & BIT(i)) == 0)
317 generic_handle_irq(irq_find_mapping(p->irqdomain, i));
320 chained_irq_exit(irqchip, desc);
323 static struct irq_chip faraday_pci_irq_chip = {
325 .irq_ack = faraday_pci_ack_irq,
326 .irq_mask = faraday_pci_mask_irq,
327 .irq_unmask = faraday_pci_unmask_irq,
330 static int faraday_pci_irq_map(struct irq_domain *domain, unsigned int irq,
331 irq_hw_number_t hwirq)
333 irq_set_chip_and_handler(irq, &faraday_pci_irq_chip, handle_level_irq);
334 irq_set_chip_data(irq, domain->host_data);
339 static const struct irq_domain_ops faraday_pci_irqdomain_ops = {
340 .map = faraday_pci_irq_map,
343 static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p)
345 struct device_node *intc = of_get_next_child(p->dev->of_node, NULL);
350 dev_err(p->dev, "missing child interrupt-controller node\n");
354 /* All PCI IRQs cascade off this one */
355 irq = of_irq_get(intc, 0);
357 dev_err(p->dev, "failed to get parent IRQ\n");
359 return irq ?: -EINVAL;
362 p->irqdomain = irq_domain_add_linear(intc, PCI_NUM_INTX,
363 &faraday_pci_irqdomain_ops, p);
366 dev_err(p->dev, "failed to create Gemini PCI IRQ domain\n");
370 irq_set_chained_handler_and_data(irq, faraday_pci_irq_handler, p);
372 for (i = 0; i < 4; i++)
373 irq_create_mapping(p->irqdomain, i);
378 static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p,
379 struct device_node *np)
381 struct of_pci_range range;
382 struct of_pci_range_parser parser;
383 struct device *dev = p->dev;
385 FARADAY_PCI_MEM1_BASE_SIZE,
386 FARADAY_PCI_MEM2_BASE_SIZE,
387 FARADAY_PCI_MEM3_BASE_SIZE,
392 if (of_pci_dma_range_parser_init(&parser, np)) {
393 dev_err(dev, "missing dma-ranges property\n");
398 * Get the dma-ranges from the device tree
400 for_each_of_pci_range(&parser, &range) {
401 u64 end = range.pci_addr + range.size - 1;
404 ret = faraday_res_to_memcfg(range.pci_addr, range.size, &val);
407 "DMA range %d: illegal MEM resource size\n", i);
411 dev_info(dev, "DMA MEM%d BASE: 0x%016llx -> 0x%016llx config %08x\n",
412 i + 1, range.pci_addr, end, val);
414 faraday_raw_pci_write_config(p, 0, 0, confreg[i],
417 dev_err(dev, "ignore extraneous dma-range %d\n", i);
427 static int faraday_pci_probe(struct platform_device *pdev)
429 struct device *dev = &pdev->dev;
430 const struct faraday_pci_variant *variant =
431 of_device_get_match_data(dev);
432 struct resource *regs;
433 struct resource_entry *win;
434 struct faraday_pci *p;
436 struct pci_host_bridge *host;
438 unsigned char max_bus_speed = PCI_SPEED_33MHz;
439 unsigned char cur_bus_speed = PCI_SPEED_33MHz;
443 host = devm_pci_alloc_host_bridge(dev, sizeof(*p));
447 host->dev.parent = dev;
448 host->ops = &faraday_pci_ops;
451 host->map_irq = of_irq_parse_and_map_pci;
452 host->swizzle_irq = pci_common_swizzle;
453 p = pci_host_bridge_priv(host);
457 /* Retrieve and enable optional clocks */
458 clk = devm_clk_get(dev, "PCLK");
461 ret = clk_prepare_enable(clk);
463 dev_err(dev, "could not prepare PCLK\n");
466 p->bus_clk = devm_clk_get(dev, "PCICLK");
467 if (IS_ERR(p->bus_clk))
468 return PTR_ERR(p->bus_clk);
469 ret = clk_prepare_enable(p->bus_clk);
471 dev_err(dev, "could not prepare PCICLK\n");
475 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
476 p->base = devm_ioremap_resource(dev, regs);
478 return PTR_ERR(p->base);
480 ret = pci_parse_request_of_pci_ranges(dev, &host->windows,
481 &host->dma_ranges, NULL);
485 win = resource_list_first_type(&host->windows, IORESOURCE_IO);
488 if (!faraday_res_to_memcfg(io->start - win->offset,
489 resource_size(io), &val)) {
490 /* setup I/O space size */
491 writel(val, p->base + PCI_IOSIZE);
493 dev_err(dev, "illegal IO mem size\n");
498 /* Setup hostbridge */
499 val = readl(p->base + PCI_CTRL);
500 val |= PCI_COMMAND_IO;
501 val |= PCI_COMMAND_MEMORY;
502 val |= PCI_COMMAND_MASTER;
503 writel(val, p->base + PCI_CTRL);
504 /* Mask and clear all interrupts */
505 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000);
506 if (variant->cascaded_irq) {
507 ret = faraday_pci_setup_cascaded_irq(p);
509 dev_err(dev, "failed to setup cascaded IRQ\n");
514 /* Check bus clock if we can gear up to 66 MHz */
515 if (!IS_ERR(p->bus_clk)) {
519 faraday_raw_pci_read_config(p, 0, 0,
520 FARADAY_PCI_STATUS_CMD, 4, &val);
521 rate = clk_get_rate(p->bus_clk);
523 if ((rate == 33000000) && (val & PCI_STATUS_66MHZ_CAPABLE)) {
524 dev_info(dev, "33MHz bus is 66MHz capable\n");
525 max_bus_speed = PCI_SPEED_66MHz;
526 ret = clk_set_rate(p->bus_clk, 66000000);
528 dev_err(dev, "failed to set bus clock\n");
530 dev_info(dev, "33MHz only bus\n");
531 max_bus_speed = PCI_SPEED_33MHz;
534 /* Bumping the clock may fail so read back the rate */
535 rate = clk_get_rate(p->bus_clk);
536 if (rate == 33000000)
537 cur_bus_speed = PCI_SPEED_33MHz;
538 if (rate == 66000000)
539 cur_bus_speed = PCI_SPEED_66MHz;
542 ret = faraday_pci_parse_map_dma_ranges(p, dev->of_node);
546 ret = pci_scan_root_bus_bridge(host);
548 dev_err(dev, "failed to scan host: %d\n", ret);
552 p->bus->max_bus_speed = max_bus_speed;
553 p->bus->cur_bus_speed = cur_bus_speed;
555 pci_bus_assign_resources(p->bus);
556 pci_bus_add_devices(p->bus);
562 * We encode bridge variants here, we have at least two so it doesn't
563 * hurt to have infrastructure to encompass future variants as well.
565 static const struct faraday_pci_variant faraday_regular = {
566 .cascaded_irq = true,
569 static const struct faraday_pci_variant faraday_dual = {
570 .cascaded_irq = false,
573 static const struct of_device_id faraday_pci_of_match[] = {
575 .compatible = "faraday,ftpci100",
576 .data = &faraday_regular,
579 .compatible = "faraday,ftpci100-dual",
580 .data = &faraday_dual,
585 static struct platform_driver faraday_pci_driver = {
588 .of_match_table = of_match_ptr(faraday_pci_of_match),
589 .suppress_bind_attrs = true,
591 .probe = faraday_pci_probe,
593 builtin_platform_driver(faraday_pci_driver);