1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for UniPhier SoCs
4 * Copyright 2018 Socionext Inc.
5 * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
8 #include <linux/bitops.h>
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/module.h>
17 #include <linux/of_irq.h>
18 #include <linux/pci.h>
19 #include <linux/phy/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/reset.h>
23 #include "pcie-designware.h"
25 #define PCL_PINCTRL0 0x002c
26 #define PCL_PERST_PLDN_REGEN BIT(12)
27 #define PCL_PERST_NOE_REGEN BIT(11)
28 #define PCL_PERST_OUT_REGEN BIT(8)
29 #define PCL_PERST_PLDN_REGVAL BIT(4)
30 #define PCL_PERST_NOE_REGVAL BIT(3)
31 #define PCL_PERST_OUT_REGVAL BIT(0)
33 #define PCL_PIPEMON 0x0044
34 #define PCL_PCLK_ALIVE BIT(15)
36 #define PCL_MODE 0x8000
37 #define PCL_MODE_REGEN BIT(8)
38 #define PCL_MODE_REGVAL BIT(0)
40 #define PCL_APP_READY_CTRL 0x8008
41 #define PCL_APP_LTSSM_ENABLE BIT(0)
43 #define PCL_APP_PM0 0x8078
44 #define PCL_SYS_AUX_PWR_DET BIT(8)
46 #define PCL_RCV_INT 0x8108
47 #define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17)
48 #define PCL_CFG_BW_MGT_STATUS BIT(4)
49 #define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3)
50 #define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2)
51 #define PCL_CFG_PME_MSI_STATUS BIT(1)
53 #define PCL_RCV_INTX 0x810c
54 #define PCL_RCV_INTX_ALL_ENABLE GENMASK(19, 16)
55 #define PCL_RCV_INTX_ALL_MASK GENMASK(11, 8)
56 #define PCL_RCV_INTX_MASK_SHIFT 8
57 #define PCL_RCV_INTX_ALL_STATUS GENMASK(3, 0)
58 #define PCL_RCV_INTX_STATUS_SHIFT 0
60 #define PCL_STATUS_LINK 0x8140
61 #define PCL_RDLH_LINK_UP BIT(1)
62 #define PCL_XMLH_LINK_UP BIT(0)
64 struct uniphier_pcie_priv {
68 struct reset_control *rst;
70 struct irq_domain *legacy_irq_domain;
73 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv,
80 val = readl(priv->base + PCL_APP_READY_CTRL);
82 val |= PCL_APP_LTSSM_ENABLE;
84 val &= ~PCL_APP_LTSSM_ENABLE;
85 writel(val, priv->base + PCL_APP_READY_CTRL);
88 static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
93 val = readl(priv->base + PCL_MODE);
94 val |= PCL_MODE_REGEN;
95 val &= ~PCL_MODE_REGVAL;
96 writel(val, priv->base + PCL_MODE);
98 /* use auxiliary power detection */
99 val = readl(priv->base + PCL_APP_PM0);
100 val |= PCL_SYS_AUX_PWR_DET;
101 writel(val, priv->base + PCL_APP_PM0);
104 val = readl(priv->base + PCL_PINCTRL0);
105 val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
106 | PCL_PERST_PLDN_REGVAL);
107 val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
108 | PCL_PERST_PLDN_REGEN;
109 writel(val, priv->base + PCL_PINCTRL0);
111 uniphier_pcie_ltssm_enable(priv, false);
113 usleep_range(100000, 200000);
115 /* deassert PERST# */
116 val = readl(priv->base + PCL_PINCTRL0);
117 val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
118 writel(val, priv->base + PCL_PINCTRL0);
121 static int uniphier_pcie_wait_rc(struct uniphier_pcie_priv *priv)
126 /* wait PIPE clock */
127 ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
128 status & PCL_PCLK_ALIVE, 100000, 1000000);
130 dev_err(priv->pci.dev,
131 "Failed to initialize controller in RC mode\n");
138 static int uniphier_pcie_link_up(struct dw_pcie *pci)
140 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
143 val = readl(priv->base + PCL_STATUS_LINK);
144 mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP;
146 return (val & mask) == mask;
149 static int uniphier_pcie_establish_link(struct dw_pcie *pci)
151 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
153 if (dw_pcie_link_up(pci))
156 uniphier_pcie_ltssm_enable(priv, true);
158 return dw_pcie_wait_for_link(pci);
161 static void uniphier_pcie_stop_link(struct dw_pcie *pci)
163 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
165 uniphier_pcie_ltssm_enable(priv, false);
168 static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv)
170 writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT);
171 writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX);
174 static void uniphier_pcie_irq_disable(struct uniphier_pcie_priv *priv)
176 writel(0, priv->base + PCL_RCV_INT);
177 writel(0, priv->base + PCL_RCV_INTX);
180 static void uniphier_pcie_irq_ack(struct irq_data *d)
182 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
183 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
184 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
187 val = readl(priv->base + PCL_RCV_INTX);
188 val &= ~PCL_RCV_INTX_ALL_STATUS;
189 val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT);
190 writel(val, priv->base + PCL_RCV_INTX);
193 static void uniphier_pcie_irq_mask(struct irq_data *d)
195 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
196 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
197 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
200 val = readl(priv->base + PCL_RCV_INTX);
201 val &= ~PCL_RCV_INTX_ALL_MASK;
202 val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
203 writel(val, priv->base + PCL_RCV_INTX);
206 static void uniphier_pcie_irq_unmask(struct irq_data *d)
208 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
209 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
210 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
213 val = readl(priv->base + PCL_RCV_INTX);
214 val &= ~PCL_RCV_INTX_ALL_MASK;
215 val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
216 writel(val, priv->base + PCL_RCV_INTX);
219 static struct irq_chip uniphier_pcie_irq_chip = {
221 .irq_ack = uniphier_pcie_irq_ack,
222 .irq_mask = uniphier_pcie_irq_mask,
223 .irq_unmask = uniphier_pcie_irq_unmask,
226 static int uniphier_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
227 irq_hw_number_t hwirq)
229 irq_set_chip_and_handler(irq, &uniphier_pcie_irq_chip,
231 irq_set_chip_data(irq, domain->host_data);
236 static const struct irq_domain_ops uniphier_intx_domain_ops = {
237 .map = uniphier_pcie_intx_map,
240 static void uniphier_pcie_irq_handler(struct irq_desc *desc)
242 struct pcie_port *pp = irq_desc_get_handler_data(desc);
243 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
244 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
245 struct irq_chip *chip = irq_desc_get_chip(desc);
250 val = readl(priv->base + PCL_RCV_INT);
252 if (val & PCL_CFG_BW_MGT_STATUS)
253 dev_dbg(pci->dev, "Link Bandwidth Management Event\n");
254 if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
255 dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n");
256 if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
257 dev_dbg(pci->dev, "Root Error\n");
258 if (val & PCL_CFG_PME_MSI_STATUS)
259 dev_dbg(pci->dev, "PME Interrupt\n");
261 writel(val, priv->base + PCL_RCV_INT);
264 chained_irq_enter(chip, desc);
266 val = readl(priv->base + PCL_RCV_INTX);
267 reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
269 for_each_set_bit(bit, ®, PCI_NUM_INTX) {
270 virq = irq_linear_revmap(priv->legacy_irq_domain, bit);
271 generic_handle_irq(virq);
274 chained_irq_exit(chip, desc);
277 static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
279 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
280 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
281 struct device_node *np = pci->dev->of_node;
282 struct device_node *np_intc;
285 np_intc = of_get_child_by_name(np, "legacy-interrupt-controller");
287 dev_err(pci->dev, "Failed to get legacy-interrupt-controller node\n");
291 pp->irq = irq_of_parse_and_map(np_intc, 0);
293 dev_err(pci->dev, "Failed to get an IRQ entry in legacy-interrupt-controller\n");
298 priv->legacy_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
299 &uniphier_intx_domain_ops, pp);
300 if (!priv->legacy_irq_domain) {
301 dev_err(pci->dev, "Failed to get INTx domain\n");
306 irq_set_chained_handler_and_data(pp->irq, uniphier_pcie_irq_handler,
310 of_node_put(np_intc);
314 static int uniphier_pcie_host_init(struct pcie_port *pp)
316 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
317 struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
320 ret = uniphier_pcie_config_legacy_irq(pp);
324 uniphier_pcie_irq_enable(priv);
326 dw_pcie_setup_rc(pp);
327 ret = uniphier_pcie_establish_link(pci);
331 if (IS_ENABLED(CONFIG_PCI_MSI))
332 dw_pcie_msi_init(pp);
337 static const struct dw_pcie_host_ops uniphier_pcie_host_ops = {
338 .host_init = uniphier_pcie_host_init,
341 static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv,
342 struct platform_device *pdev)
344 struct dw_pcie *pci = &priv->pci;
345 struct pcie_port *pp = &pci->pp;
346 struct device *dev = &pdev->dev;
349 pp->ops = &uniphier_pcie_host_ops;
351 if (IS_ENABLED(CONFIG_PCI_MSI)) {
352 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
357 ret = dw_pcie_host_init(pp);
359 dev_err(dev, "Failed to initialize host (%d)\n", ret);
366 static int uniphier_pcie_host_enable(struct uniphier_pcie_priv *priv)
370 ret = clk_prepare_enable(priv->clk);
374 ret = reset_control_deassert(priv->rst);
376 goto out_clk_disable;
378 uniphier_pcie_init_rc(priv);
380 ret = phy_init(priv->phy);
384 ret = uniphier_pcie_wait_rc(priv);
393 reset_control_assert(priv->rst);
395 clk_disable_unprepare(priv->clk);
400 static void uniphier_pcie_host_disable(struct uniphier_pcie_priv *priv)
402 uniphier_pcie_irq_disable(priv);
404 reset_control_assert(priv->rst);
405 clk_disable_unprepare(priv->clk);
408 static const struct dw_pcie_ops dw_pcie_ops = {
409 .start_link = uniphier_pcie_establish_link,
410 .stop_link = uniphier_pcie_stop_link,
411 .link_up = uniphier_pcie_link_up,
414 static int uniphier_pcie_probe(struct platform_device *pdev)
416 struct device *dev = &pdev->dev;
417 struct uniphier_pcie_priv *priv;
418 struct resource *res;
421 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
426 priv->pci.ops = &dw_pcie_ops;
428 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
429 priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res);
430 if (IS_ERR(priv->pci.dbi_base))
431 return PTR_ERR(priv->pci.dbi_base);
433 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "link");
434 priv->base = devm_ioremap_resource(dev, res);
435 if (IS_ERR(priv->base))
436 return PTR_ERR(priv->base);
438 priv->clk = devm_clk_get(dev, NULL);
439 if (IS_ERR(priv->clk))
440 return PTR_ERR(priv->clk);
442 priv->rst = devm_reset_control_get_shared(dev, NULL);
443 if (IS_ERR(priv->rst))
444 return PTR_ERR(priv->rst);
446 priv->phy = devm_phy_optional_get(dev, "pcie-phy");
447 if (IS_ERR(priv->phy))
448 return PTR_ERR(priv->phy);
450 platform_set_drvdata(pdev, priv);
452 ret = uniphier_pcie_host_enable(priv);
456 return uniphier_add_pcie_port(priv, pdev);
459 static int uniphier_pcie_remove(struct platform_device *pdev)
461 struct uniphier_pcie_priv *priv = platform_get_drvdata(pdev);
463 uniphier_pcie_host_disable(priv);
468 static const struct of_device_id uniphier_pcie_match[] = {
469 { .compatible = "socionext,uniphier-pcie", },
472 MODULE_DEVICE_TABLE(of, uniphier_pcie_match);
474 static struct platform_driver uniphier_pcie_driver = {
475 .probe = uniphier_pcie_probe,
476 .remove = uniphier_pcie_remove,
478 .name = "uniphier-pcie",
479 .of_match_table = uniphier_pcie_match,
482 builtin_platform_driver(uniphier_pcie_driver);
484 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
485 MODULE_DESCRIPTION("UniPhier PCIe host controller driver");
486 MODULE_LICENSE("GPL v2");