1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra194 SoC
5 * Copyright (C) 2019 NVIDIA Corporation.
7 * Author: Vidya Sagar <vidyas@nvidia.com>
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/interrupt.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_pci.h>
24 #include <linux/pci.h>
25 #include <linux/phy/phy.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/random.h>
30 #include <linux/reset.h>
31 #include <linux/resource.h>
32 #include <linux/types.h>
33 #include "pcie-designware.h"
34 #include <soc/tegra/bpmp.h>
35 #include <soc/tegra/bpmp-abi.h>
36 #include "../../pci.h"
38 #define APPL_PINMUX 0x0
39 #define APPL_PINMUX_PEX_RST BIT(0)
40 #define APPL_PINMUX_CLKREQ_OVERRIDE_EN BIT(2)
41 #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3)
42 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4)
43 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5)
46 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6)
47 #define APPL_CTRL_LTSSM_EN BIT(7)
48 #define APPL_CTRL_HW_HOT_RST_EN BIT(20)
49 #define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0)
50 #define APPL_CTRL_HW_HOT_RST_MODE_SHIFT 22
51 #define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST 0x1
53 #define APPL_INTR_EN_L0_0 0x8
54 #define APPL_INTR_EN_L0_0_LINK_STATE_INT_EN BIT(0)
55 #define APPL_INTR_EN_L0_0_MSI_RCV_INT_EN BIT(4)
56 #define APPL_INTR_EN_L0_0_INT_INT_EN BIT(8)
57 #define APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN BIT(15)
58 #define APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN BIT(19)
59 #define APPL_INTR_EN_L0_0_SYS_INTR_EN BIT(30)
60 #define APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN BIT(31)
62 #define APPL_INTR_STATUS_L0 0xC
63 #define APPL_INTR_STATUS_L0_LINK_STATE_INT BIT(0)
64 #define APPL_INTR_STATUS_L0_INT_INT BIT(8)
65 #define APPL_INTR_STATUS_L0_PCI_CMD_EN_INT BIT(15)
66 #define APPL_INTR_STATUS_L0_PEX_RST_INT BIT(16)
67 #define APPL_INTR_STATUS_L0_CDM_REG_CHK_INT BIT(18)
69 #define APPL_INTR_EN_L1_0_0 0x1C
70 #define APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN BIT(1)
71 #define APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN BIT(3)
72 #define APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN BIT(30)
74 #define APPL_INTR_STATUS_L1_0_0 0x20
75 #define APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED BIT(1)
76 #define APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED BIT(3)
77 #define APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE BIT(30)
79 #define APPL_INTR_STATUS_L1_1 0x2C
80 #define APPL_INTR_STATUS_L1_2 0x30
81 #define APPL_INTR_STATUS_L1_3 0x34
82 #define APPL_INTR_STATUS_L1_6 0x3C
83 #define APPL_INTR_STATUS_L1_7 0x40
84 #define APPL_INTR_STATUS_L1_15_CFG_BME_CHGED BIT(1)
86 #define APPL_INTR_EN_L1_8_0 0x44
87 #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2)
88 #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3)
89 #define APPL_INTR_EN_L1_8_INTX_EN BIT(11)
90 #define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15)
92 #define APPL_INTR_STATUS_L1_8_0 0x4C
93 #define APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK GENMASK(11, 6)
94 #define APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS BIT(2)
95 #define APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS BIT(3)
97 #define APPL_INTR_STATUS_L1_9 0x54
98 #define APPL_INTR_STATUS_L1_10 0x58
99 #define APPL_INTR_STATUS_L1_11 0x64
100 #define APPL_INTR_STATUS_L1_13 0x74
101 #define APPL_INTR_STATUS_L1_14 0x78
102 #define APPL_INTR_STATUS_L1_15 0x7C
103 #define APPL_INTR_STATUS_L1_17 0x88
105 #define APPL_INTR_EN_L1_18 0x90
106 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMPLT BIT(2)
107 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR BIT(1)
108 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0)
110 #define APPL_INTR_STATUS_L1_18 0x94
111 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT BIT(2)
112 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR BIT(1)
113 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0)
115 #define APPL_MSI_CTRL_1 0xAC
117 #define APPL_MSI_CTRL_2 0xB0
119 #define APPL_LEGACY_INTX 0xB8
121 #define APPL_LTR_MSG_1 0xC4
122 #define LTR_MSG_REQ BIT(15)
123 #define LTR_MST_NO_SNOOP_SHIFT 16
125 #define APPL_LTR_MSG_2 0xC8
126 #define APPL_LTR_MSG_2_LTR_MSG_REQ_STATE BIT(3)
128 #define APPL_LINK_STATUS 0xCC
129 #define APPL_LINK_STATUS_RDLH_LINK_UP BIT(0)
131 #define APPL_DEBUG 0xD0
132 #define APPL_DEBUG_PM_LINKST_IN_L2_LAT BIT(21)
133 #define APPL_DEBUG_PM_LINKST_IN_L0 0x11
134 #define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3)
135 #define APPL_DEBUG_LTSSM_STATE_SHIFT 3
136 #define LTSSM_STATE_PRE_DETECT 5
138 #define APPL_RADM_STATUS 0xE4
139 #define APPL_PM_XMT_TURNOFF_STATE BIT(0)
141 #define APPL_DM_TYPE 0x100
142 #define APPL_DM_TYPE_MASK GENMASK(3, 0)
143 #define APPL_DM_TYPE_RP 0x4
144 #define APPL_DM_TYPE_EP 0x0
146 #define APPL_CFG_BASE_ADDR 0x104
147 #define APPL_CFG_BASE_ADDR_MASK GENMASK(31, 12)
149 #define APPL_CFG_IATU_DMA_BASE_ADDR 0x108
150 #define APPL_CFG_IATU_DMA_BASE_ADDR_MASK GENMASK(31, 18)
152 #define APPL_CFG_MISC 0x110
153 #define APPL_CFG_MISC_SLV_EP_MODE BIT(14)
154 #define APPL_CFG_MISC_ARCACHE_MASK GENMASK(13, 10)
155 #define APPL_CFG_MISC_ARCACHE_SHIFT 10
156 #define APPL_CFG_MISC_ARCACHE_VAL 3
158 #define APPL_CFG_SLCG_OVERRIDE 0x114
159 #define APPL_CFG_SLCG_OVERRIDE_SLCG_EN_MASTER BIT(0)
161 #define APPL_CAR_RESET_OVRD 0x12C
162 #define APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N BIT(0)
164 #define IO_BASE_IO_DECODE BIT(0)
165 #define IO_BASE_IO_DECODE_BIT8 BIT(8)
167 #define CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE BIT(0)
168 #define CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE BIT(16)
170 #define CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x718
171 #define CFG_TIMER_CTRL_ACK_NAK_SHIFT (19)
173 #define EVENT_COUNTER_ALL_CLEAR 0x3
174 #define EVENT_COUNTER_ENABLE_ALL 0x7
175 #define EVENT_COUNTER_ENABLE_SHIFT 2
176 #define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0)
177 #define EVENT_COUNTER_EVENT_SEL_SHIFT 16
178 #define EVENT_COUNTER_EVENT_Tx_L0S 0x2
179 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3
180 #define EVENT_COUNTER_EVENT_L1 0x5
181 #define EVENT_COUNTER_EVENT_L1_1 0x7
182 #define EVENT_COUNTER_EVENT_L1_2 0x8
183 #define EVENT_COUNTER_GROUP_SEL_SHIFT 24
184 #define EVENT_COUNTER_GROUP_5 0x5
189 #define GEN3_EQ_CONTROL_OFF 0x8a8
190 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT 8
191 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
192 #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
194 #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
195 #define AMBA_ERROR_RESPONSE_CRS_SHIFT 3
196 #define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0)
197 #define AMBA_ERROR_RESPONSE_CRS_OKAY 0
198 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF 1
199 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 2
201 #define MSIX_ADDR_MATCH_LOW_OFF 0x940
202 #define MSIX_ADDR_MATCH_LOW_OFF_EN BIT(0)
203 #define MSIX_ADDR_MATCH_LOW_OFF_MASK GENMASK(31, 2)
205 #define MSIX_ADDR_MATCH_HIGH_OFF 0x944
206 #define MSIX_ADDR_MATCH_HIGH_OFF_MASK GENMASK(31, 0)
208 #define PORT_LOGIC_MSIX_DOORBELL 0x948
210 #define CAP_SPCIE_CAP_OFF 0x154
211 #define CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK GENMASK(3, 0)
212 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8)
213 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8
215 #define PME_ACK_TIMEOUT 10000
217 #define LTSSM_TIMEOUT 50000 /* 50ms */
219 #define GEN3_GEN4_EQ_PRESET_INIT 5
221 #define GEN1_CORE_CLK_FREQ 62500000
222 #define GEN2_CORE_CLK_FREQ 125000000
223 #define GEN3_CORE_CLK_FREQ 250000000
224 #define GEN4_CORE_CLK_FREQ 500000000
226 #define LTR_MSG_TIMEOUT (100 * 1000)
228 #define PERST_DEBOUNCE_TIME (5 * 1000)
230 #define EP_STATE_DISABLED 0
231 #define EP_STATE_ENABLED 1
233 static const unsigned int pcie_gen_freq[] = {
240 struct tegra194_pcie {
242 struct resource *appl_res;
243 struct resource *dbi_res;
244 struct resource *atu_dma_res;
245 void __iomem *appl_base;
246 struct clk *core_clk;
247 struct reset_control *core_apb_rst;
248 struct reset_control *core_rst;
250 struct tegra_bpmp *bpmp;
252 enum dw_pcie_device_mode mode;
254 bool supports_clkreq;
255 bool enable_cdm_check;
257 bool update_fc_fixup;
262 u32 cfg_link_cap_l1sub;
266 u32 aspm_l0s_enter_lat;
268 struct regulator *pex_ctl_supply;
269 struct regulator *slot_ctl_3v3;
270 struct regulator *slot_ctl_12v;
272 unsigned int phy_count;
275 struct dentry *debugfs;
277 /* Endpoint mode specific */
278 struct gpio_desc *pex_rst_gpiod;
279 struct gpio_desc *pex_refclk_sel_gpiod;
280 unsigned int pex_rst_irq;
284 struct tegra194_pcie_of_data {
285 enum dw_pcie_device_mode mode;
288 static inline struct tegra194_pcie *to_tegra_pcie(struct dw_pcie *pci)
290 return container_of(pci, struct tegra194_pcie, pci);
293 static inline void appl_writel(struct tegra194_pcie *pcie, const u32 value,
296 writel_relaxed(value, pcie->appl_base + reg);
299 static inline u32 appl_readl(struct tegra194_pcie *pcie, const u32 reg)
301 return readl_relaxed(pcie->appl_base + reg);
304 struct tegra_pcie_soc {
305 enum dw_pcie_device_mode mode;
308 static void apply_bad_link_workaround(struct dw_pcie_rp *pp)
310 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
311 struct tegra194_pcie *pcie = to_tegra_pcie(pci);
312 u32 current_link_width;
316 * NOTE:- Since this scenario is uncommon and link as such is not
317 * stable anyway, not waiting to confirm if link is really
318 * transitioning to Gen-2 speed
320 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
321 if (val & PCI_EXP_LNKSTA_LBMS) {
322 current_link_width = (val & PCI_EXP_LNKSTA_NLW) >>
323 PCI_EXP_LNKSTA_NLW_SHIFT;
324 if (pcie->init_link_width > current_link_width) {
325 dev_warn(pci->dev, "PCIe link is bad, width reduced\n");
326 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
328 val &= ~PCI_EXP_LNKCTL2_TLS;
329 val |= PCI_EXP_LNKCTL2_TLS_2_5GT;
330 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
331 PCI_EXP_LNKCTL2, val);
333 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
335 val |= PCI_EXP_LNKCTL_RL;
336 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
337 PCI_EXP_LNKCTL, val);
342 static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
344 struct tegra194_pcie *pcie = arg;
345 struct dw_pcie *pci = &pcie->pci;
346 struct dw_pcie_rp *pp = &pci->pp;
350 val = appl_readl(pcie, APPL_INTR_STATUS_L0);
351 if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
352 val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
353 if (val & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) {
354 appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0);
356 /* SBR & Surprise Link Down WAR */
357 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
358 val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
359 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
361 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
362 val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
363 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
365 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
366 val |= PORT_LOGIC_SPEED_CHANGE;
367 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
371 if (val & APPL_INTR_STATUS_L0_INT_INT) {
372 val = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
373 if (val & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) {
375 APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS,
376 APPL_INTR_STATUS_L1_8_0);
377 apply_bad_link_workaround(pp);
379 if (val & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) {
381 APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS,
382 APPL_INTR_STATUS_L1_8_0);
384 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
386 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w &
391 val = appl_readl(pcie, APPL_INTR_STATUS_L0);
392 if (val & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) {
393 val = appl_readl(pcie, APPL_INTR_STATUS_L1_18);
394 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
395 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) {
396 dev_info(pci->dev, "CDM check complete\n");
397 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE;
399 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) {
400 dev_err(pci->dev, "CDM comparison mismatch\n");
401 tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR;
403 if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) {
404 dev_err(pci->dev, "CDM Logic error\n");
405 tmp |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR;
407 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, tmp);
408 tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR);
409 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", tmp);
415 static void pex_ep_event_hot_rst_done(struct tegra194_pcie *pcie)
419 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
420 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
421 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
422 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
423 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
424 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
425 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
426 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
427 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
428 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
429 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
430 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
431 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
432 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
433 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
434 appl_writel(pcie, 0xFFFFFFFF, APPL_MSI_CTRL_2);
436 val = appl_readl(pcie, APPL_CTRL);
437 val |= APPL_CTRL_LTSSM_EN;
438 appl_writel(pcie, val, APPL_CTRL);
441 static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
443 struct tegra194_pcie *pcie = arg;
444 struct dw_pcie *pci = &pcie->pci;
447 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
449 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
451 /* If EP doesn't advertise L1SS, just return */
452 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
453 if (!(val & (PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2)))
456 /* Check if BME is set to '1' */
457 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
458 if (val & PCI_COMMAND_MASTER) {
461 /* 110us for both snoop and no-snoop */
462 val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ;
463 val |= (val << LTR_MST_NO_SNOOP_SHIFT);
464 appl_writel(pcie, val, APPL_LTR_MSG_1);
466 /* Send LTR upstream */
467 val = appl_readl(pcie, APPL_LTR_MSG_2);
468 val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE;
469 appl_writel(pcie, val, APPL_LTR_MSG_2);
471 timeout = ktime_add_us(ktime_get(), LTR_MSG_TIMEOUT);
473 val = appl_readl(pcie, APPL_LTR_MSG_2);
474 if (!(val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE))
476 if (ktime_after(ktime_get(), timeout))
478 usleep_range(1000, 1100);
480 if (val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE)
481 dev_err(pcie->dev, "Failed to send LTR message\n");
487 static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
489 struct tegra194_pcie *pcie = arg;
490 struct dw_pcie_ep *ep = &pcie->pci.ep;
492 u32 status_l0, status_l1, link_status;
494 status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
495 if (status_l0 & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
496 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
497 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
499 if (status_l1 & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE)
500 pex_ep_event_hot_rst_done(pcie);
502 if (status_l1 & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) {
503 link_status = appl_readl(pcie, APPL_LINK_STATUS);
504 if (link_status & APPL_LINK_STATUS_RDLH_LINK_UP) {
505 dev_dbg(pcie->dev, "Link is up with Host\n");
506 dw_pcie_ep_linkup(ep);
513 if (status_l0 & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) {
514 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_15);
515 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_15);
517 if (status_l1 & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED)
518 return IRQ_WAKE_THREAD;
524 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
526 appl_writel(pcie, status_l0, APPL_INTR_STATUS_L0);
532 static int tegra194_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn, int where,
536 * This is an endpoint mode specific register happen to appear even
537 * when controller is operating in root port mode and system hangs
538 * when it is accessed with link being in ASPM-L1 state.
539 * So skip accessing it altogether
541 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) {
543 return PCIBIOS_SUCCESSFUL;
546 return pci_generic_config_read(bus, devfn, where, size, val);
549 static int tegra194_pcie_wr_own_conf(struct pci_bus *bus, u32 devfn, int where,
553 * This is an endpoint mode specific register happen to appear even
554 * when controller is operating in root port mode and system hangs
555 * when it is accessed with link being in ASPM-L1 state.
556 * So skip accessing it altogether
558 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL)
559 return PCIBIOS_SUCCESSFUL;
561 return pci_generic_config_write(bus, devfn, where, size, val);
564 static struct pci_ops tegra_pci_ops = {
565 .map_bus = dw_pcie_own_conf_map_bus,
566 .read = tegra194_pcie_rd_own_conf,
567 .write = tegra194_pcie_wr_own_conf,
570 #if defined(CONFIG_PCIEASPM)
571 static const u32 event_cntr_ctrl_offset[] = {
580 static const u32 event_cntr_data_offset[] = {
589 static void disable_aspm_l11(struct tegra194_pcie *pcie)
593 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
594 val &= ~PCI_L1SS_CAP_ASPM_L1_1;
595 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
598 static void disable_aspm_l12(struct tegra194_pcie *pcie)
602 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
603 val &= ~PCI_L1SS_CAP_ASPM_L1_2;
604 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
607 static inline u32 event_counter_prog(struct tegra194_pcie *pcie, u32 event)
611 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]);
612 val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
613 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
614 val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
615 val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
616 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
617 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]);
622 static int aspm_state_cnt(struct seq_file *s, void *data)
624 struct tegra194_pcie *pcie = (struct tegra194_pcie *)
625 dev_get_drvdata(s->private);
628 seq_printf(s, "Tx L0s entry count : %u\n",
629 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Tx_L0S));
631 seq_printf(s, "Rx L0s entry count : %u\n",
632 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Rx_L0S));
634 seq_printf(s, "Link L1 entry count : %u\n",
635 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1));
637 seq_printf(s, "Link L1.1 entry count : %u\n",
638 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_1));
640 seq_printf(s, "Link L1.2 entry count : %u\n",
641 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2));
643 /* Clear all counters */
644 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid],
645 EVENT_COUNTER_ALL_CLEAR);
647 /* Re-enable counting */
648 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
649 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
650 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
655 static void init_host_aspm(struct tegra194_pcie *pcie)
657 struct dw_pcie *pci = &pcie->pci;
660 val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);
661 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP;
663 /* Enable ASPM counters */
664 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
665 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
666 dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val);
668 /* Program T_cmrt and T_pwr_on values */
669 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
670 val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE);
671 val |= (pcie->aspm_cmrt << 8);
672 val |= (pcie->aspm_pwr_on_t << 19);
673 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
675 /* Program L0s and L1 entrance latencies */
676 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
677 val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
678 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
679 val |= PORT_AFR_ENTER_ASPM;
680 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
683 static void init_debugfs(struct tegra194_pcie *pcie)
685 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs,
689 static inline void disable_aspm_l12(struct tegra194_pcie *pcie) { return; }
690 static inline void disable_aspm_l11(struct tegra194_pcie *pcie) { return; }
691 static inline void init_host_aspm(struct tegra194_pcie *pcie) { return; }
692 static inline void init_debugfs(struct tegra194_pcie *pcie) { return; }
695 static void tegra_pcie_enable_system_interrupts(struct dw_pcie_rp *pp)
697 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
698 struct tegra194_pcie *pcie = to_tegra_pcie(pci);
702 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
703 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
704 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
706 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
707 val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN;
708 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
710 if (pcie->enable_cdm_check) {
711 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
712 val |= APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN;
713 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
715 val = appl_readl(pcie, APPL_INTR_EN_L1_18);
716 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR;
717 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR;
718 appl_writel(pcie, val, APPL_INTR_EN_L1_18);
721 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
723 pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >>
724 PCI_EXP_LNKSTA_NLW_SHIFT;
726 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
728 val_w |= PCI_EXP_LNKCTL_LBMIE;
729 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL,
733 static void tegra_pcie_enable_legacy_interrupts(struct dw_pcie_rp *pp)
735 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
736 struct tegra194_pcie *pcie = to_tegra_pcie(pci);
739 /* Enable legacy interrupt generation */
740 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
741 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
742 val |= APPL_INTR_EN_L0_0_INT_INT_EN;
743 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
745 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
746 val |= APPL_INTR_EN_L1_8_INTX_EN;
747 val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;
748 val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;
749 if (IS_ENABLED(CONFIG_PCIEAER))
750 val |= APPL_INTR_EN_L1_8_AER_INT_EN;
751 appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
754 static void tegra_pcie_enable_msi_interrupts(struct dw_pcie_rp *pp)
756 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
757 struct tegra194_pcie *pcie = to_tegra_pcie(pci);
760 /* Enable MSI interrupt generation */
761 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
762 val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN;
763 val |= APPL_INTR_EN_L0_0_MSI_RCV_INT_EN;
764 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
767 static void tegra_pcie_enable_interrupts(struct dw_pcie_rp *pp)
769 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
770 struct tegra194_pcie *pcie = to_tegra_pcie(pci);
772 /* Clear interrupt statuses before enabling interrupts */
773 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
774 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
775 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
776 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
777 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
778 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
779 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
780 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
781 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
782 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
783 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
784 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
785 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
786 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
787 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
789 tegra_pcie_enable_system_interrupts(pp);
790 tegra_pcie_enable_legacy_interrupts(pp);
791 if (IS_ENABLED(CONFIG_PCI_MSI))
792 tegra_pcie_enable_msi_interrupts(pp);
795 static void config_gen3_gen4_eq_presets(struct tegra194_pcie *pcie)
797 struct dw_pcie *pci = &pcie->pci;
800 /* Program init preset */
801 for (i = 0; i < pcie->num_lanes; i++) {
802 val = dw_pcie_readw_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2));
803 val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK;
804 val |= GEN3_GEN4_EQ_PRESET_INIT;
805 val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK;
806 val |= (GEN3_GEN4_EQ_PRESET_INIT <<
807 CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT);
808 dw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val);
810 offset = dw_pcie_find_ext_capability(pci,
811 PCI_EXT_CAP_ID_PL_16GT) +
813 val = dw_pcie_readb_dbi(pci, offset + i);
814 val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK;
815 val |= GEN3_GEN4_EQ_PRESET_INIT;
816 val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK;
817 val |= (GEN3_GEN4_EQ_PRESET_INIT <<
818 PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT);
819 dw_pcie_writeb_dbi(pci, offset + i, val);
822 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
823 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
824 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
826 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
827 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
828 val |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
829 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
830 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
832 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
833 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
834 val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT);
835 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
837 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
838 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
839 val |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
840 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
841 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
843 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
844 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
845 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
848 static int tegra194_pcie_host_init(struct dw_pcie_rp *pp)
850 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
851 struct tegra194_pcie *pcie = to_tegra_pcie(pci);
854 pp->bridge->ops = &tegra_pci_ops;
856 if (!pcie->pcie_cap_base)
857 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
860 val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
861 val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
862 dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
864 val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE);
865 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE;
866 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE;
867 dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val);
869 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
871 /* Enable as 0xFFFF0001 response for CRS */
872 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT);
873 val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT);
874 val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 <<
875 AMBA_ERROR_RESPONSE_CRS_SHIFT);
876 dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
878 /* Configure Max lane width from DT */
879 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
880 val &= ~PCI_EXP_LNKCAP_MLW;
881 val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
882 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
884 config_gen3_gen4_eq_presets(pcie);
886 init_host_aspm(pcie);
888 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */
889 if (!pcie->supports_clkreq) {
890 disable_aspm_l11(pcie);
891 disable_aspm_l12(pcie);
894 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
895 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
896 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
898 if (pcie->update_fc_fixup) {
899 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
900 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
901 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
904 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
909 static int tegra194_pcie_start_link(struct dw_pcie *pci)
911 u32 val, offset, speed, tmp;
912 struct tegra194_pcie *pcie = to_tegra_pcie(pci);
913 struct dw_pcie_rp *pp = &pci->pp;
916 if (pcie->mode == DW_PCIE_EP_TYPE) {
917 enable_irq(pcie->pex_rst_irq);
923 val = appl_readl(pcie, APPL_PINMUX);
924 val &= ~APPL_PINMUX_PEX_RST;
925 appl_writel(pcie, val, APPL_PINMUX);
927 usleep_range(100, 200);
930 val = appl_readl(pcie, APPL_CTRL);
931 val |= APPL_CTRL_LTSSM_EN;
932 appl_writel(pcie, val, APPL_CTRL);
935 val = appl_readl(pcie, APPL_PINMUX);
936 val |= APPL_PINMUX_PEX_RST;
937 appl_writel(pcie, val, APPL_PINMUX);
941 if (dw_pcie_wait_for_link(pci)) {
945 * There are some endpoints which can't get the link up if
946 * root port has Data Link Feature (DLF) enabled.
947 * Refer Spec rev 4.0 ver 1.0 sec 3.4.2 & 7.7.4 for more info
948 * on Scaled Flow Control and DLF.
949 * So, need to confirm that is indeed the case here and attempt
950 * link up once again with DLF disabled.
952 val = appl_readl(pcie, APPL_DEBUG);
953 val &= APPL_DEBUG_LTSSM_STATE_MASK;
954 val >>= APPL_DEBUG_LTSSM_STATE_SHIFT;
955 tmp = appl_readl(pcie, APPL_LINK_STATUS);
956 tmp &= APPL_LINK_STATUS_RDLH_LINK_UP;
957 if (!(val == 0x11 && !tmp)) {
958 /* Link is down for all good reasons */
962 dev_info(pci->dev, "Link is down in DLL");
963 dev_info(pci->dev, "Trying again with DLFE disabled\n");
965 val = appl_readl(pcie, APPL_CTRL);
966 val &= ~APPL_CTRL_LTSSM_EN;
967 appl_writel(pcie, val, APPL_CTRL);
969 reset_control_assert(pcie->core_rst);
970 reset_control_deassert(pcie->core_rst);
972 offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF);
973 val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP);
974 val &= ~PCI_DLF_EXCHANGE_ENABLE;
975 dw_pcie_writel_dbi(pci, offset, val);
977 tegra194_pcie_host_init(pp);
978 dw_pcie_setup_rc(pp);
984 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
986 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
988 tegra_pcie_enable_interrupts(pp);
993 static int tegra194_pcie_link_up(struct dw_pcie *pci)
995 struct tegra194_pcie *pcie = to_tegra_pcie(pci);
996 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
998 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1001 static void tegra194_pcie_stop_link(struct dw_pcie *pci)
1003 struct tegra194_pcie *pcie = to_tegra_pcie(pci);
1005 disable_irq(pcie->pex_rst_irq);
1008 static const struct dw_pcie_ops tegra_dw_pcie_ops = {
1009 .link_up = tegra194_pcie_link_up,
1010 .start_link = tegra194_pcie_start_link,
1011 .stop_link = tegra194_pcie_stop_link,
1014 static const struct dw_pcie_host_ops tegra194_pcie_host_ops = {
1015 .host_init = tegra194_pcie_host_init,
1018 static void tegra_pcie_disable_phy(struct tegra194_pcie *pcie)
1020 unsigned int phy_count = pcie->phy_count;
1022 while (phy_count--) {
1023 phy_power_off(pcie->phys[phy_count]);
1024 phy_exit(pcie->phys[phy_count]);
1028 static int tegra_pcie_enable_phy(struct tegra194_pcie *pcie)
1033 for (i = 0; i < pcie->phy_count; i++) {
1034 ret = phy_init(pcie->phys[i]);
1038 ret = phy_power_on(pcie->phys[i]);
1047 phy_power_off(pcie->phys[i]);
1049 phy_exit(pcie->phys[i]);
1055 static int tegra194_pcie_parse_dt(struct tegra194_pcie *pcie)
1057 struct platform_device *pdev = to_platform_device(pcie->dev);
1058 struct device_node *np = pcie->dev->of_node;
1061 pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1062 if (!pcie->dbi_res) {
1063 dev_err(pcie->dev, "Failed to find \"dbi\" region\n");
1067 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt);
1069 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret);
1073 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us",
1074 &pcie->aspm_pwr_on_t);
1076 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n",
1079 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us",
1080 &pcie->aspm_l0s_enter_lat);
1083 "Failed to read ASPM L0s Entrance latency: %d\n", ret);
1085 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
1087 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
1091 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid);
1093 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret);
1097 ret = of_property_count_strings(np, "phy-names");
1099 dev_err(pcie->dev, "Failed to find PHY entries: %d\n",
1103 pcie->phy_count = ret;
1105 if (of_property_read_bool(np, "nvidia,update-fc-fixup"))
1106 pcie->update_fc_fixup = true;
1108 pcie->supports_clkreq =
1109 of_property_read_bool(pcie->dev->of_node, "supports-clkreq");
1111 pcie->enable_cdm_check =
1112 of_property_read_bool(np, "snps,enable-cdm-check");
1114 if (pcie->mode == DW_PCIE_RC_TYPE)
1117 /* Endpoint mode specific DT entries */
1118 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN);
1119 if (IS_ERR(pcie->pex_rst_gpiod)) {
1120 int err = PTR_ERR(pcie->pex_rst_gpiod);
1121 const char *level = KERN_ERR;
1123 if (err == -EPROBE_DEFER)
1126 dev_printk(level, pcie->dev,
1127 dev_fmt("Failed to get PERST GPIO: %d\n"),
1132 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev,
1133 "nvidia,refclk-select",
1135 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) {
1136 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod);
1137 const char *level = KERN_ERR;
1139 if (err == -EPROBE_DEFER)
1142 dev_printk(level, pcie->dev,
1143 dev_fmt("Failed to get REFCLK select GPIOs: %d\n"),
1145 pcie->pex_refclk_sel_gpiod = NULL;
1151 static int tegra_pcie_bpmp_set_ctrl_state(struct tegra194_pcie *pcie,
1154 struct mrq_uphy_response resp;
1155 struct tegra_bpmp_message msg;
1156 struct mrq_uphy_request req;
1158 /* Controller-5 doesn't need to have its state set by BPMP-FW */
1162 memset(&req, 0, sizeof(req));
1163 memset(&resp, 0, sizeof(resp));
1165 req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE;
1166 req.controller_state.pcie_controller = pcie->cid;
1167 req.controller_state.enable = enable;
1169 memset(&msg, 0, sizeof(msg));
1172 msg.tx.size = sizeof(req);
1173 msg.rx.data = &resp;
1174 msg.rx.size = sizeof(resp);
1176 return tegra_bpmp_transfer(pcie->bpmp, &msg);
1179 static int tegra_pcie_bpmp_set_pll_state(struct tegra194_pcie *pcie,
1182 struct mrq_uphy_response resp;
1183 struct tegra_bpmp_message msg;
1184 struct mrq_uphy_request req;
1186 memset(&req, 0, sizeof(req));
1187 memset(&resp, 0, sizeof(resp));
1190 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT;
1191 req.ep_ctrlr_pll_init.ep_controller = pcie->cid;
1193 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF;
1194 req.ep_ctrlr_pll_off.ep_controller = pcie->cid;
1197 memset(&msg, 0, sizeof(msg));
1200 msg.tx.size = sizeof(req);
1201 msg.rx.data = &resp;
1202 msg.rx.size = sizeof(resp);
1204 return tegra_bpmp_transfer(pcie->bpmp, &msg);
1207 static void tegra_pcie_downstream_dev_to_D0(struct tegra194_pcie *pcie)
1209 struct dw_pcie_rp *pp = &pcie->pci.pp;
1210 struct pci_bus *child, *root_bus = NULL;
1211 struct pci_dev *pdev;
1214 * link doesn't go into L2 state with some of the endpoints with Tegra
1215 * if they are not in D0 state. So, need to make sure that immediate
1216 * downstream devices are in D0 state before sending PME_TurnOff to put
1217 * link into L2 state.
1218 * This is as per PCI Express Base r4.0 v1.0 September 27-2017,
1219 * 5.2 Link State Power Management (Page #428).
1222 list_for_each_entry(child, &pp->bridge->bus->children, node) {
1223 /* Bring downstream devices to D0 if they are not already in */
1224 if (child->parent == pp->bridge->bus) {
1231 dev_err(pcie->dev, "Failed to find downstream devices\n");
1235 list_for_each_entry(pdev, &root_bus->devices, bus_list) {
1236 if (PCI_SLOT(pdev->devfn) == 0) {
1237 if (pci_set_power_state(pdev, PCI_D0))
1239 "Failed to transition %s to D0 state\n",
1240 dev_name(&pdev->dev));
1245 static int tegra_pcie_get_slot_regulators(struct tegra194_pcie *pcie)
1247 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
1248 if (IS_ERR(pcie->slot_ctl_3v3)) {
1249 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV)
1250 return PTR_ERR(pcie->slot_ctl_3v3);
1252 pcie->slot_ctl_3v3 = NULL;
1255 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v");
1256 if (IS_ERR(pcie->slot_ctl_12v)) {
1257 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV)
1258 return PTR_ERR(pcie->slot_ctl_12v);
1260 pcie->slot_ctl_12v = NULL;
1266 static int tegra_pcie_enable_slot_regulators(struct tegra194_pcie *pcie)
1270 if (pcie->slot_ctl_3v3) {
1271 ret = regulator_enable(pcie->slot_ctl_3v3);
1274 "Failed to enable 3.3V slot supply: %d\n", ret);
1279 if (pcie->slot_ctl_12v) {
1280 ret = regulator_enable(pcie->slot_ctl_12v);
1283 "Failed to enable 12V slot supply: %d\n", ret);
1284 goto fail_12v_enable;
1289 * According to PCI Express Card Electromechanical Specification
1290 * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive)
1291 * should be a minimum of 100ms.
1293 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v)
1299 if (pcie->slot_ctl_3v3)
1300 regulator_disable(pcie->slot_ctl_3v3);
1304 static void tegra_pcie_disable_slot_regulators(struct tegra194_pcie *pcie)
1306 if (pcie->slot_ctl_12v)
1307 regulator_disable(pcie->slot_ctl_12v);
1308 if (pcie->slot_ctl_3v3)
1309 regulator_disable(pcie->slot_ctl_3v3);
1312 static int tegra_pcie_config_controller(struct tegra194_pcie *pcie,
1318 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
1321 "Failed to enable controller %u: %d\n", pcie->cid, ret);
1325 ret = tegra_pcie_enable_slot_regulators(pcie);
1327 goto fail_slot_reg_en;
1329 ret = regulator_enable(pcie->pex_ctl_supply);
1331 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
1335 ret = clk_prepare_enable(pcie->core_clk);
1337 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret);
1341 ret = reset_control_deassert(pcie->core_apb_rst);
1343 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n",
1345 goto fail_core_apb_rst;
1348 if (en_hw_hot_rst) {
1349 /* Enable HW_HOT_RST mode */
1350 val = appl_readl(pcie, APPL_CTRL);
1351 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
1352 APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
1353 val |= APPL_CTRL_HW_HOT_RST_EN;
1354 appl_writel(pcie, val, APPL_CTRL);
1357 ret = tegra_pcie_enable_phy(pcie);
1359 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret);
1363 /* Update CFG base address */
1364 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
1365 APPL_CFG_BASE_ADDR);
1367 /* Configure this core for RP mode operation */
1368 appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE);
1370 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
1372 val = appl_readl(pcie, APPL_CTRL);
1373 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);
1375 val = appl_readl(pcie, APPL_CFG_MISC);
1376 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
1377 appl_writel(pcie, val, APPL_CFG_MISC);
1379 if (!pcie->supports_clkreq) {
1380 val = appl_readl(pcie, APPL_PINMUX);
1381 val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
1382 val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
1383 appl_writel(pcie, val, APPL_PINMUX);
1386 /* Update iATU_DMA base address */
1388 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK,
1389 APPL_CFG_IATU_DMA_BASE_ADDR);
1391 reset_control_deassert(pcie->core_rst);
1396 reset_control_assert(pcie->core_apb_rst);
1398 clk_disable_unprepare(pcie->core_clk);
1400 regulator_disable(pcie->pex_ctl_supply);
1402 tegra_pcie_disable_slot_regulators(pcie);
1404 tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1409 static void tegra_pcie_unconfig_controller(struct tegra194_pcie *pcie)
1413 ret = reset_control_assert(pcie->core_rst);
1415 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret);
1417 tegra_pcie_disable_phy(pcie);
1419 ret = reset_control_assert(pcie->core_apb_rst);
1421 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret);
1423 clk_disable_unprepare(pcie->core_clk);
1425 ret = regulator_disable(pcie->pex_ctl_supply);
1427 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret);
1429 tegra_pcie_disable_slot_regulators(pcie);
1431 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1433 dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
1437 static int tegra_pcie_init_controller(struct tegra194_pcie *pcie)
1439 struct dw_pcie *pci = &pcie->pci;
1440 struct dw_pcie_rp *pp = &pci->pp;
1443 ret = tegra_pcie_config_controller(pcie, false);
1447 pp->ops = &tegra194_pcie_host_ops;
1449 ret = dw_pcie_host_init(pp);
1451 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret);
1452 goto fail_host_init;
1458 tegra_pcie_unconfig_controller(pcie);
1462 static int tegra_pcie_try_link_l2(struct tegra194_pcie *pcie)
1466 if (!tegra194_pcie_link_up(&pcie->pci))
1469 val = appl_readl(pcie, APPL_RADM_STATUS);
1470 val |= APPL_PM_XMT_TURNOFF_STATE;
1471 appl_writel(pcie, val, APPL_RADM_STATUS);
1473 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,
1474 val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,
1475 1, PME_ACK_TIMEOUT);
1478 static void tegra194_pcie_pme_turnoff(struct tegra194_pcie *pcie)
1483 if (!tegra194_pcie_link_up(&pcie->pci)) {
1484 dev_dbg(pcie->dev, "PCIe link is not up...!\n");
1489 * PCIe controller exits from L2 only if reset is applied, so
1490 * controller doesn't handle interrupts. But in cases where
1491 * L2 entry fails, PERST# is asserted which can trigger surprise
1492 * link down AER. However this function call happens in
1493 * suspend_noirq(), so AER interrupt will not be processed.
1494 * Disable all interrupts to avoid such a scenario.
1496 appl_writel(pcie, 0x0, APPL_INTR_EN_L0_0);
1498 if (tegra_pcie_try_link_l2(pcie)) {
1499 dev_info(pcie->dev, "Link didn't transition to L2 state\n");
1501 * TX lane clock freq will reset to Gen1 only if link is in L2
1503 * So apply pex_rst to end point to force RP to go into detect
1506 data = appl_readl(pcie, APPL_PINMUX);
1507 data &= ~APPL_PINMUX_PEX_RST;
1508 appl_writel(pcie, data, APPL_PINMUX);
1511 * Some cards do not go to detect state even after de-asserting
1512 * PERST#. So, de-assert LTSSM to bring link to detect state.
1514 data = readl(pcie->appl_base + APPL_CTRL);
1515 data &= ~APPL_CTRL_LTSSM_EN;
1516 writel(data, pcie->appl_base + APPL_CTRL);
1518 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
1521 APPL_DEBUG_LTSSM_STATE_MASK) >>
1522 APPL_DEBUG_LTSSM_STATE_SHIFT) ==
1523 LTSSM_STATE_PRE_DETECT,
1526 dev_info(pcie->dev, "Link didn't go to detect state\n");
1529 * DBI registers may not be accessible after this as PLL-E would be
1530 * down depending on how CLKREQ is pulled by end point
1532 data = appl_readl(pcie, APPL_PINMUX);
1533 data |= (APPL_PINMUX_CLKREQ_OVERRIDE_EN | APPL_PINMUX_CLKREQ_OVERRIDE);
1534 /* Cut REFCLK to slot */
1535 data |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN;
1536 data &= ~APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE;
1537 appl_writel(pcie, data, APPL_PINMUX);
1540 static void tegra_pcie_deinit_controller(struct tegra194_pcie *pcie)
1542 tegra_pcie_downstream_dev_to_D0(pcie);
1543 dw_pcie_host_deinit(&pcie->pci.pp);
1544 tegra194_pcie_pme_turnoff(pcie);
1545 tegra_pcie_unconfig_controller(pcie);
1548 static int tegra_pcie_config_rp(struct tegra194_pcie *pcie)
1550 struct device *dev = pcie->dev;
1554 pm_runtime_enable(dev);
1556 ret = pm_runtime_get_sync(dev);
1558 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
1560 goto fail_pm_get_sync;
1563 ret = pinctrl_pm_select_default_state(dev);
1565 dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
1566 goto fail_pm_get_sync;
1569 ret = tegra_pcie_init_controller(pcie);
1571 dev_err(dev, "Failed to initialize controller: %d\n", ret);
1572 goto fail_pm_get_sync;
1575 pcie->link_state = tegra194_pcie_link_up(&pcie->pci);
1576 if (!pcie->link_state) {
1578 goto fail_host_init;
1581 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
1584 goto fail_host_init;
1587 pcie->debugfs = debugfs_create_dir(name, NULL);
1593 tegra_pcie_deinit_controller(pcie);
1595 pm_runtime_put_sync(dev);
1596 pm_runtime_disable(dev);
1600 static void pex_ep_event_pex_rst_assert(struct tegra194_pcie *pcie)
1605 if (pcie->ep_state == EP_STATE_DISABLED)
1609 val = appl_readl(pcie, APPL_CTRL);
1610 val &= ~APPL_CTRL_LTSSM_EN;
1611 appl_writel(pcie, val, APPL_CTRL);
1613 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
1614 ((val & APPL_DEBUG_LTSSM_STATE_MASK) >>
1615 APPL_DEBUG_LTSSM_STATE_SHIFT) ==
1616 LTSSM_STATE_PRE_DETECT,
1619 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
1621 reset_control_assert(pcie->core_rst);
1623 tegra_pcie_disable_phy(pcie);
1625 reset_control_assert(pcie->core_apb_rst);
1627 clk_disable_unprepare(pcie->core_clk);
1629 pm_runtime_put_sync(pcie->dev);
1631 ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
1633 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret);
1635 pcie->ep_state = EP_STATE_DISABLED;
1636 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n");
1639 static void pex_ep_event_pex_rst_deassert(struct tegra194_pcie *pcie)
1641 struct dw_pcie *pci = &pcie->pci;
1642 struct dw_pcie_ep *ep = &pci->ep;
1643 struct device *dev = pcie->dev;
1647 if (pcie->ep_state == EP_STATE_ENABLED)
1650 ret = pm_runtime_resume_and_get(dev);
1652 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
1657 ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
1659 dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n", ret);
1663 ret = clk_prepare_enable(pcie->core_clk);
1665 dev_err(dev, "Failed to enable core clock: %d\n", ret);
1666 goto fail_core_clk_enable;
1669 ret = reset_control_deassert(pcie->core_apb_rst);
1671 dev_err(dev, "Failed to deassert core APB reset: %d\n", ret);
1672 goto fail_core_apb_rst;
1675 ret = tegra_pcie_enable_phy(pcie);
1677 dev_err(dev, "Failed to enable PHY: %d\n", ret);
1681 /* Clear any stale interrupt statuses */
1682 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
1683 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
1684 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
1685 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
1686 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
1687 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
1688 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
1689 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
1690 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
1691 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
1692 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
1693 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
1694 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
1695 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
1696 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
1698 /* configure this core for EP mode operation */
1699 val = appl_readl(pcie, APPL_DM_TYPE);
1700 val &= ~APPL_DM_TYPE_MASK;
1701 val |= APPL_DM_TYPE_EP;
1702 appl_writel(pcie, val, APPL_DM_TYPE);
1704 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
1706 val = appl_readl(pcie, APPL_CTRL);
1707 val |= APPL_CTRL_SYS_PRE_DET_STATE;
1708 val |= APPL_CTRL_HW_HOT_RST_EN;
1709 appl_writel(pcie, val, APPL_CTRL);
1711 val = appl_readl(pcie, APPL_CFG_MISC);
1712 val |= APPL_CFG_MISC_SLV_EP_MODE;
1713 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
1714 appl_writel(pcie, val, APPL_CFG_MISC);
1716 val = appl_readl(pcie, APPL_PINMUX);
1717 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN;
1718 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE;
1719 appl_writel(pcie, val, APPL_PINMUX);
1721 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
1722 APPL_CFG_BASE_ADDR);
1724 appl_writel(pcie, pcie->atu_dma_res->start &
1725 APPL_CFG_IATU_DMA_BASE_ADDR_MASK,
1726 APPL_CFG_IATU_DMA_BASE_ADDR);
1728 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
1729 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
1730 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
1731 val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN;
1732 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
1734 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
1735 val |= APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN;
1736 val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
1737 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
1739 reset_control_deassert(pcie->core_rst);
1741 if (pcie->update_fc_fixup) {
1742 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
1743 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
1744 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
1747 config_gen3_gen4_eq_presets(pcie);
1749 init_host_aspm(pcie);
1751 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */
1752 if (!pcie->supports_clkreq) {
1753 disable_aspm_l11(pcie);
1754 disable_aspm_l12(pcie);
1757 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
1758 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
1759 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
1761 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
1763 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
1765 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
1766 val |= MSIX_ADDR_MATCH_LOW_OFF_EN;
1767 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val);
1768 val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
1769 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val);
1771 ret = dw_pcie_ep_init_complete(ep);
1773 dev_err(dev, "Failed to complete initialization: %d\n", ret);
1774 goto fail_init_complete;
1777 dw_pcie_ep_init_notify(ep);
1780 val = appl_readl(pcie, APPL_CTRL);
1781 val |= APPL_CTRL_LTSSM_EN;
1782 appl_writel(pcie, val, APPL_CTRL);
1784 pcie->ep_state = EP_STATE_ENABLED;
1785 dev_dbg(dev, "Initialization of endpoint is completed\n");
1790 reset_control_assert(pcie->core_rst);
1791 tegra_pcie_disable_phy(pcie);
1793 reset_control_assert(pcie->core_apb_rst);
1795 clk_disable_unprepare(pcie->core_clk);
1796 fail_core_clk_enable:
1797 tegra_pcie_bpmp_set_pll_state(pcie, false);
1799 pm_runtime_put_sync(dev);
1802 static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)
1804 struct tegra194_pcie *pcie = arg;
1806 if (gpiod_get_value(pcie->pex_rst_gpiod))
1807 pex_ep_event_pex_rst_assert(pcie);
1809 pex_ep_event_pex_rst_deassert(pcie);
1814 static int tegra_pcie_ep_raise_legacy_irq(struct tegra194_pcie *pcie, u16 irq)
1816 /* Tegra194 supports only INTA */
1820 appl_writel(pcie, 1, APPL_LEGACY_INTX);
1821 usleep_range(1000, 2000);
1822 appl_writel(pcie, 0, APPL_LEGACY_INTX);
1826 static int tegra_pcie_ep_raise_msi_irq(struct tegra194_pcie *pcie, u16 irq)
1828 if (unlikely(irq > 31))
1831 appl_writel(pcie, BIT(irq), APPL_MSI_CTRL_1);
1836 static int tegra_pcie_ep_raise_msix_irq(struct tegra194_pcie *pcie, u16 irq)
1838 struct dw_pcie_ep *ep = &pcie->pci.ep;
1840 writel(irq, ep->msi_mem);
1845 static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
1846 enum pci_epc_irq_type type,
1849 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1850 struct tegra194_pcie *pcie = to_tegra_pcie(pci);
1853 case PCI_EPC_IRQ_LEGACY:
1854 return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
1856 case PCI_EPC_IRQ_MSI:
1857 return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num);
1859 case PCI_EPC_IRQ_MSIX:
1860 return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num);
1863 dev_err(pci->dev, "Unknown IRQ type\n");
1870 static const struct pci_epc_features tegra_pcie_epc_features = {
1871 .linkup_notifier = true,
1872 .core_init_notifier = true,
1873 .msi_capable = false,
1874 .msix_capable = false,
1875 .reserved_bar = 1 << BAR_2 | 1 << BAR_3 | 1 << BAR_4 | 1 << BAR_5,
1876 .bar_fixed_64bit = 1 << BAR_0,
1877 .bar_fixed_size[0] = SZ_1M,
1880 static const struct pci_epc_features*
1881 tegra_pcie_ep_get_features(struct dw_pcie_ep *ep)
1883 return &tegra_pcie_epc_features;
1886 static const struct dw_pcie_ep_ops pcie_ep_ops = {
1887 .raise_irq = tegra_pcie_ep_raise_irq,
1888 .get_features = tegra_pcie_ep_get_features,
1891 static int tegra_pcie_config_ep(struct tegra194_pcie *pcie,
1892 struct platform_device *pdev)
1894 struct dw_pcie *pci = &pcie->pci;
1895 struct device *dev = pcie->dev;
1896 struct dw_pcie_ep *ep;
1901 ep->ops = &pcie_ep_ops;
1903 ep->page_size = SZ_64K;
1905 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME);
1907 dev_err(dev, "Failed to set PERST GPIO debounce time: %d\n",
1912 ret = gpiod_to_irq(pcie->pex_rst_gpiod);
1914 dev_err(dev, "Failed to get IRQ for PERST GPIO: %d\n", ret);
1917 pcie->pex_rst_irq = (unsigned int)ret;
1919 name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_pex_rst_irq",
1922 dev_err(dev, "Failed to create PERST IRQ string\n");
1926 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN);
1928 pcie->ep_state = EP_STATE_DISABLED;
1930 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL,
1931 tegra_pcie_ep_pex_rst_irq,
1932 IRQF_TRIGGER_RISING |
1933 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1934 name, (void *)pcie);
1936 dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret);
1940 pm_runtime_enable(dev);
1942 ret = dw_pcie_ep_init(ep);
1944 dev_err(dev, "Failed to initialize DWC Endpoint subsystem: %d\n",
1952 static int tegra194_pcie_probe(struct platform_device *pdev)
1954 const struct tegra194_pcie_of_data *data;
1955 struct device *dev = &pdev->dev;
1956 struct resource *atu_dma_res;
1957 struct tegra194_pcie *pcie;
1958 struct dw_pcie_rp *pp;
1959 struct dw_pcie *pci;
1965 data = of_device_get_match_data(dev);
1967 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1972 pci->dev = &pdev->dev;
1973 pci->ops = &tegra_dw_pcie_ops;
1974 pci->n_fts[0] = N_FTS_VAL;
1975 pci->n_fts[1] = FTS_VAL;
1978 pp->num_vectors = MAX_MSI_IRQS;
1979 pcie->dev = &pdev->dev;
1980 pcie->mode = (enum dw_pcie_device_mode)data->mode;
1982 ret = tegra194_pcie_parse_dt(pcie);
1984 const char *level = KERN_ERR;
1986 if (ret == -EPROBE_DEFER)
1989 dev_printk(level, dev,
1990 dev_fmt("Failed to parse device tree: %d\n"),
1995 ret = tegra_pcie_get_slot_regulators(pcie);
1997 const char *level = KERN_ERR;
1999 if (ret == -EPROBE_DEFER)
2002 dev_printk(level, dev,
2003 dev_fmt("Failed to get slot regulators: %d\n"),
2008 if (pcie->pex_refclk_sel_gpiod)
2009 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1);
2011 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
2012 if (IS_ERR(pcie->pex_ctl_supply)) {
2013 ret = PTR_ERR(pcie->pex_ctl_supply);
2014 if (ret != -EPROBE_DEFER)
2015 dev_err(dev, "Failed to get regulator: %ld\n",
2016 PTR_ERR(pcie->pex_ctl_supply));
2020 pcie->core_clk = devm_clk_get(dev, "core");
2021 if (IS_ERR(pcie->core_clk)) {
2022 dev_err(dev, "Failed to get core clock: %ld\n",
2023 PTR_ERR(pcie->core_clk));
2024 return PTR_ERR(pcie->core_clk);
2027 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2029 if (!pcie->appl_res) {
2030 dev_err(dev, "Failed to find \"appl\" region\n");
2034 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
2035 if (IS_ERR(pcie->appl_base))
2036 return PTR_ERR(pcie->appl_base);
2038 pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
2039 if (IS_ERR(pcie->core_apb_rst)) {
2040 dev_err(dev, "Failed to get APB reset: %ld\n",
2041 PTR_ERR(pcie->core_apb_rst));
2042 return PTR_ERR(pcie->core_apb_rst);
2045 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
2049 for (i = 0; i < pcie->phy_count; i++) {
2050 name = kasprintf(GFP_KERNEL, "p2u-%u", i);
2052 dev_err(dev, "Failed to create P2U string\n");
2055 phys[i] = devm_phy_get(dev, name);
2057 if (IS_ERR(phys[i])) {
2058 ret = PTR_ERR(phys[i]);
2059 if (ret != -EPROBE_DEFER)
2060 dev_err(dev, "Failed to get PHY: %d\n", ret);
2067 atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2070 dev_err(dev, "Failed to find \"atu_dma\" region\n");
2073 pcie->atu_dma_res = atu_dma_res;
2075 pci->atu_size = resource_size(atu_dma_res);
2076 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res);
2077 if (IS_ERR(pci->atu_base))
2078 return PTR_ERR(pci->atu_base);
2080 pcie->core_rst = devm_reset_control_get(dev, "core");
2081 if (IS_ERR(pcie->core_rst)) {
2082 dev_err(dev, "Failed to get core reset: %ld\n",
2083 PTR_ERR(pcie->core_rst));
2084 return PTR_ERR(pcie->core_rst);
2087 pp->irq = platform_get_irq_byname(pdev, "intr");
2091 pcie->bpmp = tegra_bpmp_get(dev);
2092 if (IS_ERR(pcie->bpmp))
2093 return PTR_ERR(pcie->bpmp);
2095 platform_set_drvdata(pdev, pcie);
2097 switch (pcie->mode) {
2098 case DW_PCIE_RC_TYPE:
2099 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler,
2100 IRQF_SHARED, "tegra-pcie-intr", pcie);
2102 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
2107 ret = tegra_pcie_config_rp(pcie);
2108 if (ret && ret != -ENOMEDIUM)
2114 case DW_PCIE_EP_TYPE:
2115 ret = devm_request_threaded_irq(dev, pp->irq,
2116 tegra_pcie_ep_hard_irq,
2117 tegra_pcie_ep_irq_thread,
2118 IRQF_SHARED | IRQF_ONESHOT,
2119 "tegra-pcie-ep-intr", pcie);
2121 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
2126 ret = tegra_pcie_config_ep(pcie, pdev);
2132 dev_err(dev, "Invalid PCIe device type %d\n", pcie->mode);
2136 tegra_bpmp_put(pcie->bpmp);
2140 static int tegra194_pcie_remove(struct platform_device *pdev)
2142 struct tegra194_pcie *pcie = platform_get_drvdata(pdev);
2144 if (!pcie->link_state)
2147 debugfs_remove_recursive(pcie->debugfs);
2148 tegra_pcie_deinit_controller(pcie);
2149 pm_runtime_put_sync(pcie->dev);
2150 pm_runtime_disable(pcie->dev);
2151 tegra_bpmp_put(pcie->bpmp);
2152 if (pcie->pex_refclk_sel_gpiod)
2153 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0);
2158 static int tegra194_pcie_suspend_late(struct device *dev)
2160 struct tegra194_pcie *pcie = dev_get_drvdata(dev);
2163 if (!pcie->link_state)
2166 /* Enable HW_HOT_RST mode */
2167 val = appl_readl(pcie, APPL_CTRL);
2168 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
2169 APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
2170 val |= APPL_CTRL_HW_HOT_RST_EN;
2171 appl_writel(pcie, val, APPL_CTRL);
2176 static int tegra194_pcie_suspend_noirq(struct device *dev)
2178 struct tegra194_pcie *pcie = dev_get_drvdata(dev);
2180 if (!pcie->link_state)
2183 tegra_pcie_downstream_dev_to_D0(pcie);
2184 tegra194_pcie_pme_turnoff(pcie);
2185 tegra_pcie_unconfig_controller(pcie);
2190 static int tegra194_pcie_resume_noirq(struct device *dev)
2192 struct tegra194_pcie *pcie = dev_get_drvdata(dev);
2195 if (!pcie->link_state)
2198 ret = tegra_pcie_config_controller(pcie, true);
2202 ret = tegra194_pcie_host_init(&pcie->pci.pp);
2204 dev_err(dev, "Failed to init host: %d\n", ret);
2205 goto fail_host_init;
2208 dw_pcie_setup_rc(&pcie->pci.pp);
2210 ret = tegra194_pcie_start_link(&pcie->pci);
2212 goto fail_host_init;
2217 tegra_pcie_unconfig_controller(pcie);
2221 static int tegra194_pcie_resume_early(struct device *dev)
2223 struct tegra194_pcie *pcie = dev_get_drvdata(dev);
2226 if (pcie->mode == DW_PCIE_EP_TYPE) {
2227 dev_err(dev, "Suspend is not supported in EP mode");
2231 if (!pcie->link_state)
2234 /* Disable HW_HOT_RST mode */
2235 val = appl_readl(pcie, APPL_CTRL);
2236 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
2237 APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
2238 val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST <<
2239 APPL_CTRL_HW_HOT_RST_MODE_SHIFT;
2240 val &= ~APPL_CTRL_HW_HOT_RST_EN;
2241 appl_writel(pcie, val, APPL_CTRL);
2246 static void tegra194_pcie_shutdown(struct platform_device *pdev)
2248 struct tegra194_pcie *pcie = platform_get_drvdata(pdev);
2250 if (!pcie->link_state)
2253 debugfs_remove_recursive(pcie->debugfs);
2254 tegra_pcie_downstream_dev_to_D0(pcie);
2256 disable_irq(pcie->pci.pp.irq);
2257 if (IS_ENABLED(CONFIG_PCI_MSI))
2258 disable_irq(pcie->pci.pp.msi_irq[0]);
2260 tegra194_pcie_pme_turnoff(pcie);
2261 tegra_pcie_unconfig_controller(pcie);
2264 static const struct tegra194_pcie_of_data tegra194_pcie_rc_of_data = {
2265 .mode = DW_PCIE_RC_TYPE,
2268 static const struct tegra194_pcie_of_data tegra194_pcie_ep_of_data = {
2269 .mode = DW_PCIE_EP_TYPE,
2272 static const struct of_device_id tegra194_pcie_of_match[] = {
2274 .compatible = "nvidia,tegra194-pcie",
2275 .data = &tegra194_pcie_rc_of_data,
2278 .compatible = "nvidia,tegra194-pcie-ep",
2279 .data = &tegra194_pcie_ep_of_data,
2284 static const struct dev_pm_ops tegra194_pcie_pm_ops = {
2285 .suspend_late = tegra194_pcie_suspend_late,
2286 .suspend_noirq = tegra194_pcie_suspend_noirq,
2287 .resume_noirq = tegra194_pcie_resume_noirq,
2288 .resume_early = tegra194_pcie_resume_early,
2291 static struct platform_driver tegra194_pcie_driver = {
2292 .probe = tegra194_pcie_probe,
2293 .remove = tegra194_pcie_remove,
2294 .shutdown = tegra194_pcie_shutdown,
2296 .name = "tegra194-pcie",
2297 .pm = &tegra194_pcie_pm_ops,
2298 .of_match_table = tegra194_pcie_of_match,
2301 module_platform_driver(tegra194_pcie_driver);
2303 MODULE_DEVICE_TABLE(of, tegra194_pcie_of_match);
2305 MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
2306 MODULE_DESCRIPTION("NVIDIA PCIe host controller driver");
2307 MODULE_LICENSE("GPL v2");