1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
11 #include <linux/clk.h>
12 #include <linux/crc8.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/interrupt.h>
17 #include <linux/iopoll.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/pci.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/platform_device.h>
25 #include <linux/phy/phy.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/reset.h>
28 #include <linux/slab.h>
29 #include <linux/types.h>
31 #include "../../pci.h"
32 #include "pcie-designware.h"
34 #define PCIE20_PARF_SYS_CTRL 0x00
35 #define MST_WAKEUP_EN BIT(13)
36 #define SLV_WAKEUP_EN BIT(12)
37 #define MSTR_ACLK_CGC_DIS BIT(10)
38 #define SLV_ACLK_CGC_DIS BIT(9)
39 #define CORE_CLK_CGC_DIS BIT(6)
40 #define AUX_PWR_DET BIT(4)
41 #define L23_CLK_RMV_DIS BIT(2)
42 #define L1_CLK_RMV_DIS BIT(1)
44 #define PCIE20_PARF_PHY_CTRL 0x40
45 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
46 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
48 #define PCIE20_PARF_PHY_REFCLK 0x4C
49 #define PHY_REFCLK_SSP_EN BIT(16)
50 #define PHY_REFCLK_USE_PAD BIT(12)
52 #define PCIE20_PARF_DBI_BASE_ADDR 0x168
53 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
54 #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
55 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
56 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
57 #define PCIE20_PARF_LTSSM 0x1B0
58 #define PCIE20_PARF_SID_OFFSET 0x234
59 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
60 #define PCIE20_PARF_DEVICE_TYPE 0x1000
61 #define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000
63 #define PCIE20_ELBI_SYS_CTRL 0x04
64 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
66 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
67 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
68 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
69 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
70 #define CFG_BRIDGE_SB_INIT BIT(0)
72 #define PCIE_CAP_LINK1_VAL 0x2FD7F
74 #define PCIE20_PARF_Q2A_FLUSH 0x1AC
76 #define PCIE20_MISC_CONTROL_1_REG 0x8BC
77 #define DBI_RO_WR_EN 1
79 #define PERST_DELAY_US 1000
81 #define PCIE20_PARF_PCS_DEEMPH 0x34
82 #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
83 #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
84 #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
86 #define PCIE20_PARF_PCS_SWING 0x38
87 #define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
88 #define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
90 #define PCIE20_PARF_CONFIG_BITS 0x50
91 #define PHY_RX0_EQ(x) ((x) << 24)
93 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
94 #define SLV_ADDR_SPACE_SZ 0x10000000
96 #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
98 #define DEVICE_TYPE_RC 0x4
100 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
101 #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
103 #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
105 struct qcom_pcie_resources_2_1_0 {
106 struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
107 struct reset_control *pci_reset;
108 struct reset_control *axi_reset;
109 struct reset_control *ahb_reset;
110 struct reset_control *por_reset;
111 struct reset_control *phy_reset;
112 struct reset_control *ext_reset;
113 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
116 struct qcom_pcie_resources_1_0_0 {
119 struct clk *master_bus;
120 struct clk *slave_bus;
121 struct reset_control *core;
122 struct regulator *vdda;
125 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
126 struct qcom_pcie_resources_2_3_2 {
128 struct clk *master_clk;
129 struct clk *slave_clk;
131 struct clk *pipe_clk;
132 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
135 #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4
136 struct qcom_pcie_resources_2_4_0 {
137 struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS];
139 struct reset_control *axi_m_reset;
140 struct reset_control *axi_s_reset;
141 struct reset_control *pipe_reset;
142 struct reset_control *axi_m_vmid_reset;
143 struct reset_control *axi_s_xpu_reset;
144 struct reset_control *parf_reset;
145 struct reset_control *phy_reset;
146 struct reset_control *axi_m_sticky_reset;
147 struct reset_control *pipe_sticky_reset;
148 struct reset_control *pwr_reset;
149 struct reset_control *ahb_reset;
150 struct reset_control *phy_ahb_reset;
153 struct qcom_pcie_resources_2_3_3 {
155 struct clk *axi_m_clk;
156 struct clk *axi_s_clk;
159 struct reset_control *rst[7];
162 /* 6 clocks typically, 7 for sm8250 */
163 struct qcom_pcie_resources_2_7_0 {
164 struct clk_bulk_data clks[7];
166 struct regulator_bulk_data supplies[2];
167 struct reset_control *pci_reset;
168 struct clk *pipe_clk;
171 union qcom_pcie_resources {
172 struct qcom_pcie_resources_1_0_0 v1_0_0;
173 struct qcom_pcie_resources_2_1_0 v2_1_0;
174 struct qcom_pcie_resources_2_3_2 v2_3_2;
175 struct qcom_pcie_resources_2_3_3 v2_3_3;
176 struct qcom_pcie_resources_2_4_0 v2_4_0;
177 struct qcom_pcie_resources_2_7_0 v2_7_0;
182 struct qcom_pcie_ops {
183 int (*get_resources)(struct qcom_pcie *pcie);
184 int (*init)(struct qcom_pcie *pcie);
185 int (*post_init)(struct qcom_pcie *pcie);
186 void (*deinit)(struct qcom_pcie *pcie);
187 void (*post_deinit)(struct qcom_pcie *pcie);
188 void (*ltssm_enable)(struct qcom_pcie *pcie);
189 int (*config_sid)(struct qcom_pcie *pcie);
194 void __iomem *parf; /* DT parf */
195 void __iomem *elbi; /* DT elbi */
196 union qcom_pcie_resources res;
198 struct gpio_desc *reset;
199 const struct qcom_pcie_ops *ops;
202 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
204 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
206 gpiod_set_value_cansleep(pcie->reset, 1);
207 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
210 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
212 /* Ensure that PERST has been asserted for at least 100 ms */
214 gpiod_set_value_cansleep(pcie->reset, 0);
215 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
218 static int qcom_pcie_start_link(struct dw_pcie *pci)
220 struct qcom_pcie *pcie = to_qcom_pcie(pci);
222 /* Enable Link Training state machine */
223 if (pcie->ops->ltssm_enable)
224 pcie->ops->ltssm_enable(pcie);
229 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
233 /* enable link training */
234 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
235 val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
236 writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
239 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
241 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
242 struct dw_pcie *pci = pcie->pci;
243 struct device *dev = pci->dev;
246 res->supplies[0].supply = "vdda";
247 res->supplies[1].supply = "vdda_phy";
248 res->supplies[2].supply = "vdda_refclk";
249 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
254 res->clks[0].id = "iface";
255 res->clks[1].id = "core";
256 res->clks[2].id = "phy";
257 res->clks[3].id = "aux";
258 res->clks[4].id = "ref";
260 /* iface, core, phy are required */
261 ret = devm_clk_bulk_get(dev, 3, res->clks);
265 /* aux, ref are optional */
266 ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
270 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
271 if (IS_ERR(res->pci_reset))
272 return PTR_ERR(res->pci_reset);
274 res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");
275 if (IS_ERR(res->axi_reset))
276 return PTR_ERR(res->axi_reset);
278 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
279 if (IS_ERR(res->ahb_reset))
280 return PTR_ERR(res->ahb_reset);
282 res->por_reset = devm_reset_control_get_exclusive(dev, "por");
283 if (IS_ERR(res->por_reset))
284 return PTR_ERR(res->por_reset);
286 res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
287 if (IS_ERR(res->ext_reset))
288 return PTR_ERR(res->ext_reset);
290 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
291 return PTR_ERR_OR_ZERO(res->phy_reset);
294 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
296 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
298 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
299 reset_control_assert(res->pci_reset);
300 reset_control_assert(res->axi_reset);
301 reset_control_assert(res->ahb_reset);
302 reset_control_assert(res->por_reset);
303 reset_control_assert(res->ext_reset);
304 reset_control_assert(res->phy_reset);
306 writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
308 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
311 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
313 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
314 struct dw_pcie *pci = pcie->pci;
315 struct device *dev = pci->dev;
316 struct device_node *node = dev->of_node;
320 /* reset the PCIe interface as uboot can leave it undefined state */
321 reset_control_assert(res->pci_reset);
322 reset_control_assert(res->axi_reset);
323 reset_control_assert(res->ahb_reset);
324 reset_control_assert(res->por_reset);
325 reset_control_assert(res->ext_reset);
326 reset_control_assert(res->phy_reset);
328 writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
330 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
332 dev_err(dev, "cannot enable regulators\n");
336 ret = reset_control_deassert(res->ahb_reset);
338 dev_err(dev, "cannot deassert ahb reset\n");
339 goto err_deassert_ahb;
342 ret = reset_control_deassert(res->ext_reset);
344 dev_err(dev, "cannot deassert ext reset\n");
345 goto err_deassert_ext;
348 ret = reset_control_deassert(res->phy_reset);
350 dev_err(dev, "cannot deassert phy reset\n");
351 goto err_deassert_phy;
354 ret = reset_control_deassert(res->pci_reset);
356 dev_err(dev, "cannot deassert pci reset\n");
357 goto err_deassert_pci;
360 ret = reset_control_deassert(res->por_reset);
362 dev_err(dev, "cannot deassert por reset\n");
363 goto err_deassert_por;
366 ret = reset_control_deassert(res->axi_reset);
368 dev_err(dev, "cannot deassert axi reset\n");
369 goto err_deassert_axi;
372 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
376 /* enable PCIe clocks and resets */
377 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
379 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
381 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
382 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
383 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
384 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
385 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
386 pcie->parf + PCIE20_PARF_PCS_DEEMPH);
387 writel(PCS_SWING_TX_SWING_FULL(120) |
388 PCS_SWING_TX_SWING_LOW(120),
389 pcie->parf + PCIE20_PARF_PCS_SWING);
390 writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
393 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
394 /* set TX termination offset */
395 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
396 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
397 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
398 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
401 /* enable external reference clock */
402 val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
403 /* USE_PAD is required only for ipq806x */
404 if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
405 val &= ~PHY_REFCLK_USE_PAD;
406 val |= PHY_REFCLK_SSP_EN;
407 writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
409 /* wait for clock acquisition */
410 usleep_range(1000, 1500);
412 /* Set the Max TLP size to 2K, instead of using default of 4K */
413 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
414 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
415 writel(CFG_BRIDGE_SB_INIT,
416 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
421 reset_control_assert(res->axi_reset);
423 reset_control_assert(res->por_reset);
425 reset_control_assert(res->pci_reset);
427 reset_control_assert(res->phy_reset);
429 reset_control_assert(res->ext_reset);
431 reset_control_assert(res->ahb_reset);
433 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
438 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
440 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
441 struct dw_pcie *pci = pcie->pci;
442 struct device *dev = pci->dev;
444 res->vdda = devm_regulator_get(dev, "vdda");
445 if (IS_ERR(res->vdda))
446 return PTR_ERR(res->vdda);
448 res->iface = devm_clk_get(dev, "iface");
449 if (IS_ERR(res->iface))
450 return PTR_ERR(res->iface);
452 res->aux = devm_clk_get(dev, "aux");
453 if (IS_ERR(res->aux))
454 return PTR_ERR(res->aux);
456 res->master_bus = devm_clk_get(dev, "master_bus");
457 if (IS_ERR(res->master_bus))
458 return PTR_ERR(res->master_bus);
460 res->slave_bus = devm_clk_get(dev, "slave_bus");
461 if (IS_ERR(res->slave_bus))
462 return PTR_ERR(res->slave_bus);
464 res->core = devm_reset_control_get_exclusive(dev, "core");
465 return PTR_ERR_OR_ZERO(res->core);
468 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
470 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
472 reset_control_assert(res->core);
473 clk_disable_unprepare(res->slave_bus);
474 clk_disable_unprepare(res->master_bus);
475 clk_disable_unprepare(res->iface);
476 clk_disable_unprepare(res->aux);
477 regulator_disable(res->vdda);
480 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
482 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
483 struct dw_pcie *pci = pcie->pci;
484 struct device *dev = pci->dev;
487 ret = reset_control_deassert(res->core);
489 dev_err(dev, "cannot deassert core reset\n");
493 ret = clk_prepare_enable(res->aux);
495 dev_err(dev, "cannot prepare/enable aux clock\n");
499 ret = clk_prepare_enable(res->iface);
501 dev_err(dev, "cannot prepare/enable iface clock\n");
505 ret = clk_prepare_enable(res->master_bus);
507 dev_err(dev, "cannot prepare/enable master_bus clock\n");
511 ret = clk_prepare_enable(res->slave_bus);
513 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
517 ret = regulator_enable(res->vdda);
519 dev_err(dev, "cannot enable vdda regulator\n");
523 /* change DBI base address */
524 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
526 if (IS_ENABLED(CONFIG_PCI_MSI)) {
527 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
530 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
535 clk_disable_unprepare(res->slave_bus);
537 clk_disable_unprepare(res->master_bus);
539 clk_disable_unprepare(res->iface);
541 clk_disable_unprepare(res->aux);
543 reset_control_assert(res->core);
548 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
552 /* enable link training */
553 val = readl(pcie->parf + PCIE20_PARF_LTSSM);
555 writel(val, pcie->parf + PCIE20_PARF_LTSSM);
558 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
560 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
561 struct dw_pcie *pci = pcie->pci;
562 struct device *dev = pci->dev;
565 res->supplies[0].supply = "vdda";
566 res->supplies[1].supply = "vddpe-3v3";
567 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
572 res->aux_clk = devm_clk_get(dev, "aux");
573 if (IS_ERR(res->aux_clk))
574 return PTR_ERR(res->aux_clk);
576 res->cfg_clk = devm_clk_get(dev, "cfg");
577 if (IS_ERR(res->cfg_clk))
578 return PTR_ERR(res->cfg_clk);
580 res->master_clk = devm_clk_get(dev, "bus_master");
581 if (IS_ERR(res->master_clk))
582 return PTR_ERR(res->master_clk);
584 res->slave_clk = devm_clk_get(dev, "bus_slave");
585 if (IS_ERR(res->slave_clk))
586 return PTR_ERR(res->slave_clk);
588 res->pipe_clk = devm_clk_get(dev, "pipe");
589 return PTR_ERR_OR_ZERO(res->pipe_clk);
592 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
594 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
596 clk_disable_unprepare(res->slave_clk);
597 clk_disable_unprepare(res->master_clk);
598 clk_disable_unprepare(res->cfg_clk);
599 clk_disable_unprepare(res->aux_clk);
601 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
604 static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
606 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
608 clk_disable_unprepare(res->pipe_clk);
611 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
613 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
614 struct dw_pcie *pci = pcie->pci;
615 struct device *dev = pci->dev;
619 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
621 dev_err(dev, "cannot enable regulators\n");
625 ret = clk_prepare_enable(res->aux_clk);
627 dev_err(dev, "cannot prepare/enable aux clock\n");
631 ret = clk_prepare_enable(res->cfg_clk);
633 dev_err(dev, "cannot prepare/enable cfg clock\n");
637 ret = clk_prepare_enable(res->master_clk);
639 dev_err(dev, "cannot prepare/enable master clock\n");
643 ret = clk_prepare_enable(res->slave_clk);
645 dev_err(dev, "cannot prepare/enable slave clock\n");
649 /* enable PCIe clocks and resets */
650 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
652 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
654 /* change DBI base address */
655 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
657 /* MAC PHY_POWERDOWN MUX DISABLE */
658 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
660 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
662 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
664 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
666 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
668 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
673 clk_disable_unprepare(res->master_clk);
675 clk_disable_unprepare(res->cfg_clk);
677 clk_disable_unprepare(res->aux_clk);
680 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
685 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
687 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
688 struct dw_pcie *pci = pcie->pci;
689 struct device *dev = pci->dev;
692 ret = clk_prepare_enable(res->pipe_clk);
694 dev_err(dev, "cannot prepare/enable pipe clock\n");
701 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
703 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
704 struct dw_pcie *pci = pcie->pci;
705 struct device *dev = pci->dev;
706 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
709 res->clks[0].id = "aux";
710 res->clks[1].id = "master_bus";
711 res->clks[2].id = "slave_bus";
712 res->clks[3].id = "iface";
714 /* qcom,pcie-ipq4019 is defined without "iface" */
715 res->num_clks = is_ipq ? 3 : 4;
717 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
721 res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
722 if (IS_ERR(res->axi_m_reset))
723 return PTR_ERR(res->axi_m_reset);
725 res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");
726 if (IS_ERR(res->axi_s_reset))
727 return PTR_ERR(res->axi_s_reset);
731 * These resources relates to the PHY or are secure clocks, but
732 * are controlled here for IPQ4019
734 res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
735 if (IS_ERR(res->pipe_reset))
736 return PTR_ERR(res->pipe_reset);
738 res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
740 if (IS_ERR(res->axi_m_vmid_reset))
741 return PTR_ERR(res->axi_m_vmid_reset);
743 res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
745 if (IS_ERR(res->axi_s_xpu_reset))
746 return PTR_ERR(res->axi_s_xpu_reset);
748 res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
749 if (IS_ERR(res->parf_reset))
750 return PTR_ERR(res->parf_reset);
752 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
753 if (IS_ERR(res->phy_reset))
754 return PTR_ERR(res->phy_reset);
757 res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
759 if (IS_ERR(res->axi_m_sticky_reset))
760 return PTR_ERR(res->axi_m_sticky_reset);
762 res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,
764 if (IS_ERR(res->pipe_sticky_reset))
765 return PTR_ERR(res->pipe_sticky_reset);
767 res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");
768 if (IS_ERR(res->pwr_reset))
769 return PTR_ERR(res->pwr_reset);
771 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
772 if (IS_ERR(res->ahb_reset))
773 return PTR_ERR(res->ahb_reset);
776 res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
777 if (IS_ERR(res->phy_ahb_reset))
778 return PTR_ERR(res->phy_ahb_reset);
784 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
786 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
788 reset_control_assert(res->axi_m_reset);
789 reset_control_assert(res->axi_s_reset);
790 reset_control_assert(res->pipe_reset);
791 reset_control_assert(res->pipe_sticky_reset);
792 reset_control_assert(res->phy_reset);
793 reset_control_assert(res->phy_ahb_reset);
794 reset_control_assert(res->axi_m_sticky_reset);
795 reset_control_assert(res->pwr_reset);
796 reset_control_assert(res->ahb_reset);
797 clk_bulk_disable_unprepare(res->num_clks, res->clks);
800 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
802 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
803 struct dw_pcie *pci = pcie->pci;
804 struct device *dev = pci->dev;
808 ret = reset_control_assert(res->axi_m_reset);
810 dev_err(dev, "cannot assert axi master reset\n");
814 ret = reset_control_assert(res->axi_s_reset);
816 dev_err(dev, "cannot assert axi slave reset\n");
820 usleep_range(10000, 12000);
822 ret = reset_control_assert(res->pipe_reset);
824 dev_err(dev, "cannot assert pipe reset\n");
828 ret = reset_control_assert(res->pipe_sticky_reset);
830 dev_err(dev, "cannot assert pipe sticky reset\n");
834 ret = reset_control_assert(res->phy_reset);
836 dev_err(dev, "cannot assert phy reset\n");
840 ret = reset_control_assert(res->phy_ahb_reset);
842 dev_err(dev, "cannot assert phy ahb reset\n");
846 usleep_range(10000, 12000);
848 ret = reset_control_assert(res->axi_m_sticky_reset);
850 dev_err(dev, "cannot assert axi master sticky reset\n");
854 ret = reset_control_assert(res->pwr_reset);
856 dev_err(dev, "cannot assert power reset\n");
860 ret = reset_control_assert(res->ahb_reset);
862 dev_err(dev, "cannot assert ahb reset\n");
866 usleep_range(10000, 12000);
868 ret = reset_control_deassert(res->phy_ahb_reset);
870 dev_err(dev, "cannot deassert phy ahb reset\n");
874 ret = reset_control_deassert(res->phy_reset);
876 dev_err(dev, "cannot deassert phy reset\n");
880 ret = reset_control_deassert(res->pipe_reset);
882 dev_err(dev, "cannot deassert pipe reset\n");
886 ret = reset_control_deassert(res->pipe_sticky_reset);
888 dev_err(dev, "cannot deassert pipe sticky reset\n");
889 goto err_rst_pipe_sticky;
892 usleep_range(10000, 12000);
894 ret = reset_control_deassert(res->axi_m_reset);
896 dev_err(dev, "cannot deassert axi master reset\n");
900 ret = reset_control_deassert(res->axi_m_sticky_reset);
902 dev_err(dev, "cannot deassert axi master sticky reset\n");
903 goto err_rst_axi_m_sticky;
906 ret = reset_control_deassert(res->axi_s_reset);
908 dev_err(dev, "cannot deassert axi slave reset\n");
912 ret = reset_control_deassert(res->pwr_reset);
914 dev_err(dev, "cannot deassert power reset\n");
918 ret = reset_control_deassert(res->ahb_reset);
920 dev_err(dev, "cannot deassert ahb reset\n");
924 usleep_range(10000, 12000);
926 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
930 /* enable PCIe clocks and resets */
931 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
933 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
935 /* change DBI base address */
936 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
938 /* MAC PHY_POWERDOWN MUX DISABLE */
939 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
941 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
943 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
945 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
947 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
949 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
954 reset_control_assert(res->ahb_reset);
956 reset_control_assert(res->pwr_reset);
958 reset_control_assert(res->axi_s_reset);
960 reset_control_assert(res->axi_m_sticky_reset);
961 err_rst_axi_m_sticky:
962 reset_control_assert(res->axi_m_reset);
964 reset_control_assert(res->pipe_sticky_reset);
966 reset_control_assert(res->pipe_reset);
968 reset_control_assert(res->phy_reset);
970 reset_control_assert(res->phy_ahb_reset);
974 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
976 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
977 struct dw_pcie *pci = pcie->pci;
978 struct device *dev = pci->dev;
980 const char *rst_names[] = { "axi_m", "axi_s", "pipe",
981 "axi_m_sticky", "sticky",
984 res->iface = devm_clk_get(dev, "iface");
985 if (IS_ERR(res->iface))
986 return PTR_ERR(res->iface);
988 res->axi_m_clk = devm_clk_get(dev, "axi_m");
989 if (IS_ERR(res->axi_m_clk))
990 return PTR_ERR(res->axi_m_clk);
992 res->axi_s_clk = devm_clk_get(dev, "axi_s");
993 if (IS_ERR(res->axi_s_clk))
994 return PTR_ERR(res->axi_s_clk);
996 res->ahb_clk = devm_clk_get(dev, "ahb");
997 if (IS_ERR(res->ahb_clk))
998 return PTR_ERR(res->ahb_clk);
1000 res->aux_clk = devm_clk_get(dev, "aux");
1001 if (IS_ERR(res->aux_clk))
1002 return PTR_ERR(res->aux_clk);
1004 for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
1005 res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
1006 if (IS_ERR(res->rst[i]))
1007 return PTR_ERR(res->rst[i]);
1013 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
1015 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1017 clk_disable_unprepare(res->iface);
1018 clk_disable_unprepare(res->axi_m_clk);
1019 clk_disable_unprepare(res->axi_s_clk);
1020 clk_disable_unprepare(res->ahb_clk);
1021 clk_disable_unprepare(res->aux_clk);
1024 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
1026 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1027 struct dw_pcie *pci = pcie->pci;
1028 struct device *dev = pci->dev;
1029 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1033 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1034 ret = reset_control_assert(res->rst[i]);
1036 dev_err(dev, "reset #%d assert failed (%d)\n", i, ret);
1041 usleep_range(2000, 2500);
1043 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1044 ret = reset_control_deassert(res->rst[i]);
1046 dev_err(dev, "reset #%d deassert failed (%d)\n", i,
1053 * Don't have a way to see if the reset has completed.
1054 * Wait for some time.
1056 usleep_range(2000, 2500);
1058 ret = clk_prepare_enable(res->iface);
1060 dev_err(dev, "cannot prepare/enable core clock\n");
1064 ret = clk_prepare_enable(res->axi_m_clk);
1066 dev_err(dev, "cannot prepare/enable core clock\n");
1070 ret = clk_prepare_enable(res->axi_s_clk);
1072 dev_err(dev, "cannot prepare/enable axi slave clock\n");
1076 ret = clk_prepare_enable(res->ahb_clk);
1078 dev_err(dev, "cannot prepare/enable ahb clock\n");
1082 ret = clk_prepare_enable(res->aux_clk);
1084 dev_err(dev, "cannot prepare/enable aux clock\n");
1088 writel(SLV_ADDR_SPACE_SZ,
1089 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1091 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1093 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1095 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1097 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
1098 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1099 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1100 pcie->parf + PCIE20_PARF_SYS_CTRL);
1101 writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1103 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
1104 writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
1105 writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
1107 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
1108 val &= ~PCI_EXP_LNKCAP_ASPMS;
1109 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
1111 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
1117 clk_disable_unprepare(res->ahb_clk);
1119 clk_disable_unprepare(res->axi_s_clk);
1121 clk_disable_unprepare(res->axi_m_clk);
1123 clk_disable_unprepare(res->iface);
1126 * Not checking for failure, will anyway return
1127 * the original failure in 'ret'.
1129 for (i = 0; i < ARRAY_SIZE(res->rst); i++)
1130 reset_control_assert(res->rst[i]);
1135 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
1137 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1138 struct dw_pcie *pci = pcie->pci;
1139 struct device *dev = pci->dev;
1142 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
1143 if (IS_ERR(res->pci_reset))
1144 return PTR_ERR(res->pci_reset);
1146 res->supplies[0].supply = "vdda";
1147 res->supplies[1].supply = "vddpe-3v3";
1148 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
1153 res->clks[0].id = "aux";
1154 res->clks[1].id = "cfg";
1155 res->clks[2].id = "bus_master";
1156 res->clks[3].id = "bus_slave";
1157 res->clks[4].id = "slave_q2a";
1158 res->clks[5].id = "tbu";
1159 if (of_device_is_compatible(dev->of_node, "qcom,pcie-sm8250")) {
1160 res->clks[6].id = "ddrss_sf_tbu";
1166 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
1170 res->pipe_clk = devm_clk_get(dev, "pipe");
1171 return PTR_ERR_OR_ZERO(res->pipe_clk);
1174 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
1176 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1177 struct dw_pcie *pci = pcie->pci;
1178 struct device *dev = pci->dev;
1182 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
1184 dev_err(dev, "cannot enable regulators\n");
1188 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
1190 goto err_disable_regulators;
1192 ret = reset_control_assert(res->pci_reset);
1194 dev_err(dev, "cannot deassert pci reset\n");
1195 goto err_disable_clocks;
1198 usleep_range(1000, 1500);
1200 ret = reset_control_deassert(res->pci_reset);
1202 dev_err(dev, "cannot deassert pci reset\n");
1203 goto err_disable_clocks;
1206 ret = clk_prepare_enable(res->pipe_clk);
1208 dev_err(dev, "cannot prepare/enable pipe clock\n");
1209 goto err_disable_clocks;
1212 /* configure PCIe to RC mode */
1213 writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
1215 /* enable PCIe clocks and resets */
1216 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1218 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1220 /* change DBI base address */
1221 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1223 /* MAC PHY_POWERDOWN MUX DISABLE */
1224 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
1226 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
1228 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1230 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1232 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1233 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
1235 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
1240 clk_bulk_disable_unprepare(res->num_clks, res->clks);
1241 err_disable_regulators:
1242 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1247 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
1249 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1251 clk_bulk_disable_unprepare(res->num_clks, res->clks);
1252 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1255 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
1257 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1259 return clk_prepare_enable(res->pipe_clk);
1262 static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)
1264 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1266 clk_disable_unprepare(res->pipe_clk);
1269 static int qcom_pcie_link_up(struct dw_pcie *pci)
1271 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1272 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1274 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1277 static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie)
1279 /* iommu map structure */
1286 void __iomem *bdf_to_sid_base = pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N;
1287 struct device *dev = pcie->pci->dev;
1288 u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE];
1289 int i, nr_map, size = 0;
1292 of_get_property(dev->of_node, "iommu-map", &size);
1296 map = kzalloc(size, GFP_KERNEL);
1300 of_property_read_u32_array(dev->of_node,
1301 "iommu-map", (u32 *)map, size / sizeof(u32));
1303 nr_map = size / (sizeof(*map));
1305 crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL);
1307 /* Registers need to be zero out first */
1308 memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));
1310 /* Extract the SMMU SID base from the first entry of iommu-map */
1311 smmu_sid_base = map[0].smmu_sid;
1313 /* Look for an available entry to hold the mapping */
1314 for (i = 0; i < nr_map; i++) {
1315 u16 bdf_be = cpu_to_be16(map[i].bdf);
1319 hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be),
1322 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1324 /* If the register is already populated, look for next available entry */
1326 u8 current_hash = hash++;
1327 u8 next_mask = 0xff;
1329 /* If NEXT field is NULL then update it with next hash */
1330 if (!(val & next_mask)) {
1332 writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
1335 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1338 /* BDF [31:16] | SID [15:8] | NEXT [7:0] */
1339 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0;
1340 writel(val, bdf_to_sid_base + hash * sizeof(u32));
1348 static int qcom_pcie_host_init(struct pcie_port *pp)
1350 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1351 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1354 qcom_ep_reset_assert(pcie);
1356 ret = pcie->ops->init(pcie);
1360 ret = phy_power_on(pcie->phy);
1364 if (pcie->ops->post_init) {
1365 ret = pcie->ops->post_init(pcie);
1367 goto err_disable_phy;
1370 qcom_ep_reset_deassert(pcie);
1372 if (pcie->ops->config_sid) {
1373 ret = pcie->ops->config_sid(pcie);
1381 qcom_ep_reset_assert(pcie);
1382 if (pcie->ops->post_deinit)
1383 pcie->ops->post_deinit(pcie);
1385 phy_power_off(pcie->phy);
1387 pcie->ops->deinit(pcie);
1392 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1393 .host_init = qcom_pcie_host_init,
1396 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1397 static const struct qcom_pcie_ops ops_2_1_0 = {
1398 .get_resources = qcom_pcie_get_resources_2_1_0,
1399 .init = qcom_pcie_init_2_1_0,
1400 .deinit = qcom_pcie_deinit_2_1_0,
1401 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1404 /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1405 static const struct qcom_pcie_ops ops_1_0_0 = {
1406 .get_resources = qcom_pcie_get_resources_1_0_0,
1407 .init = qcom_pcie_init_1_0_0,
1408 .deinit = qcom_pcie_deinit_1_0_0,
1409 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1412 /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1413 static const struct qcom_pcie_ops ops_2_3_2 = {
1414 .get_resources = qcom_pcie_get_resources_2_3_2,
1415 .init = qcom_pcie_init_2_3_2,
1416 .post_init = qcom_pcie_post_init_2_3_2,
1417 .deinit = qcom_pcie_deinit_2_3_2,
1418 .post_deinit = qcom_pcie_post_deinit_2_3_2,
1419 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1422 /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1423 static const struct qcom_pcie_ops ops_2_4_0 = {
1424 .get_resources = qcom_pcie_get_resources_2_4_0,
1425 .init = qcom_pcie_init_2_4_0,
1426 .deinit = qcom_pcie_deinit_2_4_0,
1427 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1430 /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1431 static const struct qcom_pcie_ops ops_2_3_3 = {
1432 .get_resources = qcom_pcie_get_resources_2_3_3,
1433 .init = qcom_pcie_init_2_3_3,
1434 .deinit = qcom_pcie_deinit_2_3_3,
1435 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1438 /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */
1439 static const struct qcom_pcie_ops ops_2_7_0 = {
1440 .get_resources = qcom_pcie_get_resources_2_7_0,
1441 .init = qcom_pcie_init_2_7_0,
1442 .deinit = qcom_pcie_deinit_2_7_0,
1443 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1444 .post_init = qcom_pcie_post_init_2_7_0,
1445 .post_deinit = qcom_pcie_post_deinit_2_7_0,
1448 /* Qcom IP rev.: 1.9.0 */
1449 static const struct qcom_pcie_ops ops_1_9_0 = {
1450 .get_resources = qcom_pcie_get_resources_2_7_0,
1451 .init = qcom_pcie_init_2_7_0,
1452 .deinit = qcom_pcie_deinit_2_7_0,
1453 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1454 .post_init = qcom_pcie_post_init_2_7_0,
1455 .post_deinit = qcom_pcie_post_deinit_2_7_0,
1456 .config_sid = qcom_pcie_config_sid_sm8250,
1459 static const struct dw_pcie_ops dw_pcie_ops = {
1460 .link_up = qcom_pcie_link_up,
1461 .start_link = qcom_pcie_start_link,
1464 static int qcom_pcie_probe(struct platform_device *pdev)
1466 struct device *dev = &pdev->dev;
1467 struct pcie_port *pp;
1468 struct dw_pcie *pci;
1469 struct qcom_pcie *pcie;
1472 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1476 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1480 pm_runtime_enable(dev);
1481 ret = pm_runtime_get_sync(dev);
1483 goto err_pm_runtime_put;
1486 pci->ops = &dw_pcie_ops;
1491 pcie->ops = of_device_get_match_data(dev);
1493 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1494 if (IS_ERR(pcie->reset)) {
1495 ret = PTR_ERR(pcie->reset);
1496 goto err_pm_runtime_put;
1499 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1500 if (IS_ERR(pcie->parf)) {
1501 ret = PTR_ERR(pcie->parf);
1502 goto err_pm_runtime_put;
1505 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
1506 if (IS_ERR(pcie->elbi)) {
1507 ret = PTR_ERR(pcie->elbi);
1508 goto err_pm_runtime_put;
1511 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1512 if (IS_ERR(pcie->phy)) {
1513 ret = PTR_ERR(pcie->phy);
1514 goto err_pm_runtime_put;
1517 ret = pcie->ops->get_resources(pcie);
1519 goto err_pm_runtime_put;
1521 pp->ops = &qcom_pcie_dw_ops;
1523 ret = phy_init(pcie->phy);
1525 pm_runtime_disable(&pdev->dev);
1526 goto err_pm_runtime_put;
1529 platform_set_drvdata(pdev, pcie);
1531 ret = dw_pcie_host_init(pp);
1533 dev_err(dev, "cannot initialize host\n");
1534 pm_runtime_disable(&pdev->dev);
1535 goto err_pm_runtime_put;
1541 pm_runtime_put(dev);
1542 pm_runtime_disable(dev);
1547 static const struct of_device_id qcom_pcie_match[] = {
1548 { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
1549 { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
1550 { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
1551 { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
1552 { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
1553 { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
1554 { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
1555 { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
1556 { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
1557 { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 },
1561 static void qcom_fixup_class(struct pci_dev *dev)
1563 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
1565 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class);
1566 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class);
1567 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class);
1568 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class);
1569 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class);
1570 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class);
1571 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class);
1573 static struct platform_driver qcom_pcie_driver = {
1574 .probe = qcom_pcie_probe,
1576 .name = "qcom-pcie",
1577 .suppress_bind_attrs = true,
1578 .of_match_table = qcom_pcie_match,
1581 builtin_platform_driver(qcom_pcie_driver);