1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for HiSilicon SoCs
5 * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
7 * Authors: Zhou Wang <wangzhou1@hisilicon.com>
8 * Dacai Zhu <zhudacai@hisilicon.com>
9 * Gabriele Paoloni <gabriele.paoloni@huawei.com>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/of_address.h>
15 #include <linux/of_pci.h>
16 #include <linux/platform_device.h>
17 #include <linux/of_device.h>
18 #include <linux/pci.h>
19 #include <linux/pci-acpi.h>
20 #include <linux/pci-ecam.h>
21 #include <linux/regmap.h>
22 #include "../../pci.h"
24 #if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
26 static int hisi_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
29 struct pci_config_window *cfg = bus->sysdata;
30 int dev = PCI_SLOT(devfn);
32 if (bus->number == cfg->busr.start) {
33 /* access only one slot on each root port */
35 return PCIBIOS_DEVICE_NOT_FOUND;
37 return pci_generic_config_read32(bus, devfn, where,
41 return pci_generic_config_read(bus, devfn, where, size, val);
44 static int hisi_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
45 int where, int size, u32 val)
47 struct pci_config_window *cfg = bus->sysdata;
48 int dev = PCI_SLOT(devfn);
50 if (bus->number == cfg->busr.start) {
51 /* access only one slot on each root port */
53 return PCIBIOS_DEVICE_NOT_FOUND;
55 return pci_generic_config_write32(bus, devfn, where,
59 return pci_generic_config_write(bus, devfn, where, size, val);
62 static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
65 struct pci_config_window *cfg = bus->sysdata;
66 void __iomem *reg_base = cfg->priv;
68 if (bus->number == cfg->busr.start)
69 return reg_base + where;
71 return pci_ecam_map_bus(bus, devfn, where);
74 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
76 static int hisi_pcie_init(struct pci_config_window *cfg)
78 struct device *dev = cfg->parent;
79 struct acpi_device *adev = to_acpi_device(dev);
80 struct acpi_pci_root *root = acpi_driver_data(adev);
82 void __iomem *reg_base;
86 * Retrieve RC base and size from a HISI0081 device with _UID
87 * matching our segment.
89 res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
93 ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
95 dev_err(dev, "can't get rc base address\n");
99 reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
103 cfg->priv = reg_base;
107 const struct pci_ecam_ops hisi_pcie_ops = {
109 .init = hisi_pcie_init,
111 .map_bus = hisi_pcie_map_bus,
112 .read = hisi_pcie_rd_conf,
113 .write = hisi_pcie_wr_conf,
119 #ifdef CONFIG_PCI_HISI
121 #include "pcie-designware.h"
123 #define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
124 #define PCIE_HIP06_CTRL_OFF 0x1000
125 #define PCIE_SYS_STATE4 (PCIE_HIP06_CTRL_OFF + 0x31c)
126 #define PCIE_LTSSM_LINKUP_STATE 0x11
127 #define PCIE_LTSSM_STATE_MASK 0x3F
129 #define to_hisi_pcie(x) dev_get_drvdata((x)->dev)
133 struct pcie_soc_ops {
134 int (*hisi_pcie_link_up)(struct hisi_pcie *hisi_pcie);
139 struct regmap *subctrl;
141 const struct pcie_soc_ops *soc_ops;
144 /* HipXX PCIe host only supports 32-bit config access */
145 static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
150 void *walker = ®_val;
151 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
153 walker += (where & 0x3);
155 reg_val = dw_pcie_readl_dbi(pci, reg);
158 *val = *(u8 __force *) walker;
160 *val = *(u16 __force *) walker;
164 return PCIBIOS_BAD_REGISTER_NUMBER;
166 return PCIBIOS_SUCCESSFUL;
169 /* HipXX PCIe host only supports 32-bit config access */
170 static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
175 void *walker = ®_val;
176 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
178 walker += (where & 0x3);
181 dw_pcie_writel_dbi(pci, reg, val);
182 else if (size == 2) {
183 reg_val = dw_pcie_readl_dbi(pci, reg);
184 *(u16 __force *) walker = val;
185 dw_pcie_writel_dbi(pci, reg, reg_val);
186 } else if (size == 1) {
187 reg_val = dw_pcie_readl_dbi(pci, reg);
188 *(u8 __force *) walker = val;
189 dw_pcie_writel_dbi(pci, reg, reg_val);
191 return PCIBIOS_BAD_REGISTER_NUMBER;
193 return PCIBIOS_SUCCESSFUL;
196 static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
200 regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
201 0x100 * hisi_pcie->port_id, &val);
203 return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
206 static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
208 struct dw_pcie *pci = hisi_pcie->pci;
211 val = dw_pcie_readl_dbi(pci, PCIE_SYS_STATE4);
213 return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
216 static int hisi_pcie_link_up(struct dw_pcie *pci)
218 struct hisi_pcie *hisi_pcie = to_hisi_pcie(pci);
220 return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie);
223 static const struct dw_pcie_host_ops hisi_pcie_host_ops = {
224 .rd_own_conf = hisi_pcie_cfg_read,
225 .wr_own_conf = hisi_pcie_cfg_write,
228 static int hisi_add_pcie_port(struct hisi_pcie *hisi_pcie,
229 struct platform_device *pdev)
231 struct dw_pcie *pci = hisi_pcie->pci;
232 struct pcie_port *pp = &pci->pp;
233 struct device *dev = &pdev->dev;
237 if (of_property_read_u32(dev->of_node, "port-id", &port_id)) {
238 dev_err(dev, "failed to read port-id\n");
242 dev_err(dev, "Invalid port-id: %d\n", port_id);
245 hisi_pcie->port_id = port_id;
247 pp->ops = &hisi_pcie_host_ops;
249 ret = dw_pcie_host_init(pp);
251 dev_err(dev, "failed to initialize host\n");
258 static const struct dw_pcie_ops dw_pcie_ops = {
259 .link_up = hisi_pcie_link_up,
262 static int hisi_pcie_probe(struct platform_device *pdev)
264 struct device *dev = &pdev->dev;
266 struct hisi_pcie *hisi_pcie;
267 struct resource *reg;
270 hisi_pcie = devm_kzalloc(dev, sizeof(*hisi_pcie), GFP_KERNEL);
274 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
279 pci->ops = &dw_pcie_ops;
281 hisi_pcie->pci = pci;
283 hisi_pcie->soc_ops = of_device_get_match_data(dev);
286 syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
287 if (IS_ERR(hisi_pcie->subctrl)) {
288 dev_err(dev, "cannot get subctrl base\n");
289 return PTR_ERR(hisi_pcie->subctrl);
292 reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
293 pci->dbi_base = devm_pci_remap_cfg_resource(dev, reg);
294 if (IS_ERR(pci->dbi_base))
295 return PTR_ERR(pci->dbi_base);
296 platform_set_drvdata(pdev, hisi_pcie);
298 ret = hisi_add_pcie_port(hisi_pcie, pdev);
305 static struct pcie_soc_ops hip05_ops = {
306 &hisi_pcie_link_up_hip05
309 static struct pcie_soc_ops hip06_ops = {
310 &hisi_pcie_link_up_hip06
313 static const struct of_device_id hisi_pcie_of_match[] = {
315 .compatible = "hisilicon,hip05-pcie",
316 .data = (void *) &hip05_ops,
319 .compatible = "hisilicon,hip06-pcie",
320 .data = (void *) &hip06_ops,
325 static struct platform_driver hisi_pcie_driver = {
326 .probe = hisi_pcie_probe,
329 .of_match_table = hisi_pcie_of_match,
330 .suppress_bind_attrs = true,
333 builtin_platform_driver(hisi_pcie_driver);
335 static int hisi_pcie_platform_init(struct pci_config_window *cfg)
337 struct device *dev = cfg->parent;
338 struct platform_device *pdev = to_platform_device(dev);
339 struct resource *res;
340 void __iomem *reg_base;
342 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
344 dev_err(dev, "missing \"reg[1]\"property\n");
348 reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
352 cfg->priv = reg_base;
356 static const struct pci_ecam_ops hisi_pcie_platform_ops = {
358 .init = hisi_pcie_platform_init,
360 .map_bus = hisi_pcie_map_bus,
361 .read = hisi_pcie_rd_conf,
362 .write = hisi_pcie_wr_conf,
366 static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = {
368 .compatible = "hisilicon,hip06-pcie-ecam",
369 .data = &hisi_pcie_platform_ops,
372 .compatible = "hisilicon,hip07-pcie-ecam",
373 .data = &hisi_pcie_platform_ops,
378 static struct platform_driver hisi_pcie_almost_ecam_driver = {
379 .probe = pci_host_common_probe,
381 .name = "hisi-pcie-almost-ecam",
382 .of_match_table = hisi_pcie_almost_ecam_of_match,
383 .suppress_bind_attrs = true,
386 builtin_platform_driver(hisi_pcie_almost_ecam_driver);