1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
9 #include <linux/delay.h>
10 #include <linux/gpio/consumer.h>
12 #include <linux/irqchip/chained_irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/mfd/syscon.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/pci.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
22 #include "../../pci.h"
23 #include "pcie-cadence.h"
25 #define ENABLE_REG_SYS_2 0x108
26 #define STATUS_REG_SYS_2 0x508
27 #define STATUS_CLR_REG_SYS_2 0x708
28 #define LINK_DOWN BIT(1)
30 #define J721E_PCIE_USER_CMD_STATUS 0x4
31 #define LINK_TRAINING_ENABLE BIT(0)
33 #define J721E_PCIE_USER_LINKSTATUS 0x14
34 #define LINK_STATUS GENMASK(1, 0)
37 NO_RECEIVERS_DETECTED,
38 LINK_TRAINING_IN_PROGRESS,
39 LINK_UP_DL_IN_PROGRESS,
43 #define J721E_MODE_RC BIT(7)
44 #define LANE_COUNT_MASK BIT(8)
45 #define LANE_COUNT(n) ((n) << 8)
47 #define GENERATION_SEL_MASK GENMASK(1, 0)
55 struct cdns_pcie *cdns_pcie;
56 void __iomem *user_cfg_base;
57 void __iomem *intd_cfg_base;
60 enum j721e_pcie_mode {
65 struct j721e_pcie_data {
66 enum j721e_pcie_mode mode;
69 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
71 return readl(pcie->user_cfg_base + offset);
74 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset,
77 writel(value, pcie->user_cfg_base + offset);
80 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset)
82 return readl(pcie->intd_cfg_base + offset);
85 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset,
88 writel(value, pcie->intd_cfg_base + offset);
91 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
93 struct j721e_pcie *pcie = priv;
94 struct device *dev = pcie->dev;
97 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2);
98 if (!(reg & LINK_DOWN))
101 dev_err(dev, "LINK DOWN!\n");
103 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, LINK_DOWN);
107 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
111 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2);
113 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg);
116 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie)
118 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
121 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
122 reg |= LINK_TRAINING_ENABLE;
123 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
128 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie)
130 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
133 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
134 reg &= ~LINK_TRAINING_ENABLE;
135 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
138 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)
140 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
143 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);
145 if (reg == LINK_UP_DL_COMPLETED)
151 static const struct cdns_pcie_ops j721e_pcie_ops = {
152 .start_link = j721e_pcie_start_link,
153 .stop_link = j721e_pcie_stop_link,
154 .link_up = j721e_pcie_link_up,
157 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,
160 struct device *dev = pcie->dev;
161 u32 mask = J721E_MODE_RC;
162 u32 mode = pcie->mode;
166 if (mode == PCI_MODE_RC)
169 ret = regmap_update_bits(syscon, offset, mask, val);
171 dev_err(dev, "failed to set pcie mode\n");
176 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
177 struct regmap *syscon, unsigned int offset)
179 struct device *dev = pcie->dev;
180 struct device_node *np = dev->of_node;
185 link_speed = of_pci_get_max_link_speed(np);
189 val = link_speed - 1;
190 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);
192 dev_err(dev, "failed to set link speed\n");
197 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
198 struct regmap *syscon, unsigned int offset)
200 struct device *dev = pcie->dev;
201 u32 lanes = pcie->num_lanes;
205 val = LANE_COUNT(lanes - 1);
206 ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
208 dev_err(dev, "failed to set link count\n");
213 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
215 struct device *dev = pcie->dev;
216 struct device_node *node = dev->of_node;
217 struct of_phandle_args args;
218 unsigned int offset = 0;
219 struct regmap *syscon;
222 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl");
223 if (IS_ERR(syscon)) {
224 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n");
225 return PTR_ERR(syscon);
228 /* Do not error out to maintain old DT compatibility */
229 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1,
232 offset = args.args[0];
234 ret = j721e_pcie_set_mode(pcie, syscon, offset);
236 dev_err(dev, "Failed to set pci mode\n");
240 ret = j721e_pcie_set_link_speed(pcie, syscon, offset);
242 dev_err(dev, "Failed to set link speed\n");
246 ret = j721e_pcie_set_lane_count(pcie, syscon, offset);
248 dev_err(dev, "Failed to set num-lanes\n");
255 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
256 int where, int size, u32 *value)
258 if (pci_is_root_bus(bus))
259 return pci_generic_config_read32(bus, devfn, where, size,
262 return pci_generic_config_read(bus, devfn, where, size, value);
265 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
266 int where, int size, u32 value)
268 if (pci_is_root_bus(bus))
269 return pci_generic_config_write32(bus, devfn, where, size,
272 return pci_generic_config_write(bus, devfn, where, size, value);
275 static struct pci_ops cdns_ti_pcie_host_ops = {
276 .map_bus = cdns_pci_map_bus,
277 .read = cdns_ti_pcie_config_read,
278 .write = cdns_ti_pcie_config_write,
281 static const struct j721e_pcie_data j721e_pcie_rc_data = {
285 static const struct j721e_pcie_data j721e_pcie_ep_data = {
289 static const struct of_device_id of_j721e_pcie_match[] = {
291 .compatible = "ti,j721e-pcie-host",
292 .data = &j721e_pcie_rc_data,
295 .compatible = "ti,j721e-pcie-ep",
296 .data = &j721e_pcie_ep_data,
301 static int j721e_pcie_probe(struct platform_device *pdev)
303 struct device *dev = &pdev->dev;
304 struct device_node *node = dev->of_node;
305 struct pci_host_bridge *bridge;
306 struct j721e_pcie_data *data;
307 struct cdns_pcie *cdns_pcie;
308 struct j721e_pcie *pcie;
309 struct cdns_pcie_rc *rc;
310 struct cdns_pcie_ep *ep;
311 struct gpio_desc *gpiod;
318 data = (struct j721e_pcie_data *)of_device_get_match_data(dev);
322 mode = (u32)data->mode;
324 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
331 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg");
333 return PTR_ERR(base);
334 pcie->intd_cfg_base = base;
336 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg");
338 return PTR_ERR(base);
339 pcie->user_cfg_base = base;
341 ret = of_property_read_u32(node, "num-lanes", &num_lanes);
342 if (ret || num_lanes > MAX_LANES)
344 pcie->num_lanes = num_lanes;
346 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
349 irq = platform_get_irq_byname(pdev, "link_state");
353 dev_set_drvdata(dev, pcie);
354 pm_runtime_enable(dev);
355 ret = pm_runtime_get_sync(dev);
357 dev_err(dev, "pm_runtime_get_sync failed\n");
361 ret = j721e_pcie_ctrl_init(pcie);
363 dev_err(dev, "pm_runtime_get_sync failed\n");
367 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0,
368 "j721e-pcie-link-down-irq", pcie);
370 dev_err(dev, "failed to request link state IRQ %d\n", irq);
374 j721e_pcie_config_link_irq(pcie);
378 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) {
383 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
389 bridge->ops = &cdns_ti_pcie_host_ops;
390 rc = pci_host_bridge_priv(bridge);
392 cdns_pcie = &rc->pcie;
393 cdns_pcie->dev = dev;
394 cdns_pcie->ops = &j721e_pcie_ops;
395 pcie->cdns_pcie = cdns_pcie;
397 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
399 ret = PTR_ERR(gpiod);
400 if (ret != -EPROBE_DEFER)
401 dev_err(dev, "Failed to get reset GPIO\n");
405 ret = cdns_pcie_init_phy(dev, cdns_pcie);
407 dev_err(dev, "Failed to init phy\n");
412 * "Power Sequencing and Reset Signal Timings" table in
413 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
414 * indicates PERST# should be deasserted after minimum of 100us
415 * once REFCLK is stable. The REFCLK to the connector in RC
416 * mode is selected while enabling the PHY. So deassert PERST#
420 usleep_range(100, 200);
421 gpiod_set_value_cansleep(gpiod, 1);
424 ret = cdns_pcie_host_setup(rc);
430 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) {
435 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
441 cdns_pcie = &ep->pcie;
442 cdns_pcie->dev = dev;
443 cdns_pcie->ops = &j721e_pcie_ops;
444 pcie->cdns_pcie = cdns_pcie;
446 ret = cdns_pcie_init_phy(dev, cdns_pcie);
448 dev_err(dev, "Failed to init phy\n");
452 ret = cdns_pcie_ep_setup(ep);
458 dev_err(dev, "INVALID device type %d\n", mode);
464 cdns_pcie_disable_phy(cdns_pcie);
468 pm_runtime_disable(dev);
473 static int j721e_pcie_remove(struct platform_device *pdev)
475 struct j721e_pcie *pcie = platform_get_drvdata(pdev);
476 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
477 struct device *dev = &pdev->dev;
479 cdns_pcie_disable_phy(cdns_pcie);
481 pm_runtime_disable(dev);
486 static struct platform_driver j721e_pcie_driver = {
487 .probe = j721e_pcie_probe,
488 .remove = j721e_pcie_remove,
490 .name = "j721e-pcie",
491 .of_match_table = of_j721e_pcie_match,
492 .suppress_bind_attrs = true,
495 builtin_platform_driver(j721e_pcie_driver);