1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/mfd/syscon.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pci.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
23 #include "../../pci.h"
24 #include "pcie-cadence.h"
26 #define ENABLE_REG_SYS_2 0x108
27 #define STATUS_REG_SYS_2 0x508
28 #define STATUS_CLR_REG_SYS_2 0x708
29 #define LINK_DOWN BIT(1)
30 #define J7200_LINK_DOWN BIT(10)
32 #define J721E_PCIE_USER_CMD_STATUS 0x4
33 #define LINK_TRAINING_ENABLE BIT(0)
35 #define J721E_PCIE_USER_LINKSTATUS 0x14
36 #define LINK_STATUS GENMASK(1, 0)
39 NO_RECEIVERS_DETECTED,
40 LINK_TRAINING_IN_PROGRESS,
41 LINK_UP_DL_IN_PROGRESS,
45 #define J721E_MODE_RC BIT(7)
46 #define LANE_COUNT_MASK BIT(8)
47 #define LANE_COUNT(n) ((n) << 8)
49 #define GENERATION_SEL_MASK GENMASK(1, 0)
54 struct cdns_pcie *cdns_pcie;
58 void __iomem *user_cfg_base;
59 void __iomem *intd_cfg_base;
60 u32 linkdown_irq_regfield;
63 enum j721e_pcie_mode {
68 struct j721e_pcie_data {
69 enum j721e_pcie_mode mode;
70 unsigned int quirk_retrain_flag:1;
71 unsigned int quirk_detect_quiet_flag:1;
72 u32 linkdown_irq_regfield;
73 unsigned int byte_access_allowed:1;
76 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
78 return readl(pcie->user_cfg_base + offset);
81 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset,
84 writel(value, pcie->user_cfg_base + offset);
87 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset)
89 return readl(pcie->intd_cfg_base + offset);
92 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset,
95 writel(value, pcie->intd_cfg_base + offset);
98 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
100 struct j721e_pcie *pcie = priv;
101 struct device *dev = pcie->cdns_pcie->dev;
104 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2);
105 if (!(reg & pcie->linkdown_irq_regfield))
108 dev_err(dev, "LINK DOWN!\n");
110 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield);
114 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
118 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2);
119 reg |= pcie->linkdown_irq_regfield;
120 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg);
123 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie)
125 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
128 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
129 reg |= LINK_TRAINING_ENABLE;
130 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
135 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie)
137 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
140 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
141 reg &= ~LINK_TRAINING_ENABLE;
142 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
145 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)
147 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
150 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);
152 if (reg == LINK_UP_DL_COMPLETED)
158 static const struct cdns_pcie_ops j721e_pcie_ops = {
159 .start_link = j721e_pcie_start_link,
160 .stop_link = j721e_pcie_stop_link,
161 .link_up = j721e_pcie_link_up,
164 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,
167 struct device *dev = pcie->cdns_pcie->dev;
168 u32 mask = J721E_MODE_RC;
169 u32 mode = pcie->mode;
173 if (mode == PCI_MODE_RC)
176 ret = regmap_update_bits(syscon, offset, mask, val);
178 dev_err(dev, "failed to set pcie mode\n");
183 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
184 struct regmap *syscon, unsigned int offset)
186 struct device *dev = pcie->cdns_pcie->dev;
187 struct device_node *np = dev->of_node;
192 link_speed = of_pci_get_max_link_speed(np);
196 val = link_speed - 1;
197 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);
199 dev_err(dev, "failed to set link speed\n");
204 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
205 struct regmap *syscon, unsigned int offset)
207 struct device *dev = pcie->cdns_pcie->dev;
208 u32 lanes = pcie->num_lanes;
212 val = LANE_COUNT(lanes - 1);
213 ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
215 dev_err(dev, "failed to set link count\n");
220 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
222 struct device *dev = pcie->cdns_pcie->dev;
223 struct device_node *node = dev->of_node;
224 struct of_phandle_args args;
225 unsigned int offset = 0;
226 struct regmap *syscon;
229 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl");
230 if (IS_ERR(syscon)) {
231 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n");
232 return PTR_ERR(syscon);
235 /* Do not error out to maintain old DT compatibility */
236 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1,
239 offset = args.args[0];
241 ret = j721e_pcie_set_mode(pcie, syscon, offset);
243 dev_err(dev, "Failed to set pci mode\n");
247 ret = j721e_pcie_set_link_speed(pcie, syscon, offset);
249 dev_err(dev, "Failed to set link speed\n");
253 ret = j721e_pcie_set_lane_count(pcie, syscon, offset);
255 dev_err(dev, "Failed to set num-lanes\n");
262 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
263 int where, int size, u32 *value)
265 if (pci_is_root_bus(bus))
266 return pci_generic_config_read32(bus, devfn, where, size,
269 return pci_generic_config_read(bus, devfn, where, size, value);
272 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
273 int where, int size, u32 value)
275 if (pci_is_root_bus(bus))
276 return pci_generic_config_write32(bus, devfn, where, size,
279 return pci_generic_config_write(bus, devfn, where, size, value);
282 static struct pci_ops cdns_ti_pcie_host_ops = {
283 .map_bus = cdns_pci_map_bus,
284 .read = cdns_ti_pcie_config_read,
285 .write = cdns_ti_pcie_config_write,
288 static const struct j721e_pcie_data j721e_pcie_rc_data = {
290 .quirk_retrain_flag = true,
291 .byte_access_allowed = false,
292 .linkdown_irq_regfield = LINK_DOWN,
295 static const struct j721e_pcie_data j721e_pcie_ep_data = {
297 .linkdown_irq_regfield = LINK_DOWN,
300 static const struct j721e_pcie_data j7200_pcie_rc_data = {
302 .quirk_detect_quiet_flag = true,
303 .linkdown_irq_regfield = J7200_LINK_DOWN,
304 .byte_access_allowed = true,
307 static const struct j721e_pcie_data j7200_pcie_ep_data = {
309 .quirk_detect_quiet_flag = true,
312 static const struct j721e_pcie_data am64_pcie_rc_data = {
314 .linkdown_irq_regfield = J7200_LINK_DOWN,
315 .byte_access_allowed = true,
318 static const struct j721e_pcie_data am64_pcie_ep_data = {
320 .linkdown_irq_regfield = J7200_LINK_DOWN,
323 static const struct of_device_id of_j721e_pcie_match[] = {
325 .compatible = "ti,j721e-pcie-host",
326 .data = &j721e_pcie_rc_data,
329 .compatible = "ti,j721e-pcie-ep",
330 .data = &j721e_pcie_ep_data,
333 .compatible = "ti,j7200-pcie-host",
334 .data = &j7200_pcie_rc_data,
337 .compatible = "ti,j7200-pcie-ep",
338 .data = &j7200_pcie_ep_data,
341 .compatible = "ti,am64-pcie-host",
342 .data = &am64_pcie_rc_data,
345 .compatible = "ti,am64-pcie-ep",
346 .data = &am64_pcie_ep_data,
351 static int j721e_pcie_probe(struct platform_device *pdev)
353 struct device *dev = &pdev->dev;
354 struct device_node *node = dev->of_node;
355 struct pci_host_bridge *bridge;
356 const struct j721e_pcie_data *data;
357 struct cdns_pcie *cdns_pcie;
358 struct j721e_pcie *pcie;
359 struct cdns_pcie_rc *rc = NULL;
360 struct cdns_pcie_ep *ep = NULL;
361 struct gpio_desc *gpiod;
369 data = of_device_get_match_data(dev);
373 mode = (u32)data->mode;
375 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
381 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST))
384 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
388 if (!data->byte_access_allowed)
389 bridge->ops = &cdns_ti_pcie_host_ops;
390 rc = pci_host_bridge_priv(bridge);
391 rc->quirk_retrain_flag = data->quirk_retrain_flag;
392 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
394 cdns_pcie = &rc->pcie;
395 cdns_pcie->dev = dev;
396 cdns_pcie->ops = &j721e_pcie_ops;
397 pcie->cdns_pcie = cdns_pcie;
400 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP))
403 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
407 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
409 cdns_pcie = &ep->pcie;
410 cdns_pcie->dev = dev;
411 cdns_pcie->ops = &j721e_pcie_ops;
412 pcie->cdns_pcie = cdns_pcie;
415 dev_err(dev, "INVALID device type %d\n", mode);
420 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield;
422 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg");
424 return PTR_ERR(base);
425 pcie->intd_cfg_base = base;
427 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg");
429 return PTR_ERR(base);
430 pcie->user_cfg_base = base;
432 ret = of_property_read_u32(node, "num-lanes", &num_lanes);
433 if (ret || num_lanes > MAX_LANES)
435 pcie->num_lanes = num_lanes;
437 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
440 irq = platform_get_irq_byname(pdev, "link_state");
444 dev_set_drvdata(dev, pcie);
445 pm_runtime_enable(dev);
446 ret = pm_runtime_get_sync(dev);
448 dev_err(dev, "pm_runtime_get_sync failed\n");
452 ret = j721e_pcie_ctrl_init(pcie);
454 dev_err(dev, "pm_runtime_get_sync failed\n");
458 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0,
459 "j721e-pcie-link-down-irq", pcie);
461 dev_err(dev, "failed to request link state IRQ %d\n", irq);
465 j721e_pcie_config_link_irq(pcie);
469 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
471 ret = PTR_ERR(gpiod);
472 if (ret != -EPROBE_DEFER)
473 dev_err(dev, "Failed to get reset GPIO\n");
477 ret = cdns_pcie_init_phy(dev, cdns_pcie);
479 dev_err(dev, "Failed to init phy\n");
483 clk = devm_clk_get_optional(dev, "pcie_refclk");
486 dev_err(dev, "failed to get pcie_refclk\n");
490 ret = clk_prepare_enable(clk);
492 dev_err(dev, "failed to enable pcie_refclk\n");
498 * "Power Sequencing and Reset Signal Timings" table in
499 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
500 * indicates PERST# should be deasserted after minimum of 100us
501 * once REFCLK is stable. The REFCLK to the connector in RC
502 * mode is selected while enabling the PHY. So deassert PERST#
506 usleep_range(100, 200);
507 gpiod_set_value_cansleep(gpiod, 1);
510 ret = cdns_pcie_host_setup(rc);
512 clk_disable_unprepare(pcie->refclk);
518 ret = cdns_pcie_init_phy(dev, cdns_pcie);
520 dev_err(dev, "Failed to init phy\n");
524 ret = cdns_pcie_ep_setup(ep);
534 cdns_pcie_disable_phy(cdns_pcie);
538 pm_runtime_disable(dev);
543 static int j721e_pcie_remove(struct platform_device *pdev)
545 struct j721e_pcie *pcie = platform_get_drvdata(pdev);
546 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
547 struct device *dev = &pdev->dev;
549 clk_disable_unprepare(pcie->refclk);
550 cdns_pcie_disable_phy(cdns_pcie);
552 pm_runtime_disable(dev);
557 static struct platform_driver j721e_pcie_driver = {
558 .probe = j721e_pcie_probe,
559 .remove = j721e_pcie_remove,
561 .name = "j721e-pcie",
562 .of_match_table = of_j721e_pcie_match,
563 .suppress_bind_attrs = true,
566 builtin_platform_driver(j721e_pcie_driver);