1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/module.h>
4 #include <linux/slab.h>
5 #include <linux/ioport.h>
6 #include <linux/wait.h>
11 * This interrupt-safe spinlock protects all accesses to PCI
12 * configuration space.
15 DEFINE_RAW_SPINLOCK(pci_lock);
18 * Wrappers for all PCI configuration access functions. They just check
19 * alignment, do locking and call the low-level functions pointed to
23 #define PCI_byte_BAD 0
24 #define PCI_word_BAD (pos & 1)
25 #define PCI_dword_BAD (pos & 3)
27 #ifdef CONFIG_PCI_LOCKLESS_CONFIG
28 # define pci_lock_config(f) do { (void)(f); } while (0)
29 # define pci_unlock_config(f) do { (void)(f); } while (0)
31 # define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f)
32 # define pci_unlock_config(f) raw_spin_unlock_irqrestore(&pci_lock, f)
35 #define PCI_OP_READ(size, type, len) \
36 int noinline pci_bus_read_config_##size \
37 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
40 unsigned long flags; \
42 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
43 pci_lock_config(flags); \
44 res = bus->ops->read(bus, devfn, pos, len, &data); \
46 PCI_SET_ERROR_RESPONSE(value); \
48 *value = (type)data; \
49 pci_unlock_config(flags); \
53 #define PCI_OP_WRITE(size, type, len) \
54 int noinline pci_bus_write_config_##size \
55 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
58 unsigned long flags; \
59 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
60 pci_lock_config(flags); \
61 res = bus->ops->write(bus, devfn, pos, len, value); \
62 pci_unlock_config(flags); \
66 PCI_OP_READ(byte, u8, 1)
67 PCI_OP_READ(word, u16, 2)
68 PCI_OP_READ(dword, u32, 4)
69 PCI_OP_WRITE(byte, u8, 1)
70 PCI_OP_WRITE(word, u16, 2)
71 PCI_OP_WRITE(dword, u32, 4)
73 EXPORT_SYMBOL(pci_bus_read_config_byte);
74 EXPORT_SYMBOL(pci_bus_read_config_word);
75 EXPORT_SYMBOL(pci_bus_read_config_dword);
76 EXPORT_SYMBOL(pci_bus_write_config_byte);
77 EXPORT_SYMBOL(pci_bus_write_config_word);
78 EXPORT_SYMBOL(pci_bus_write_config_dword);
80 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
81 int where, int size, u32 *val)
85 addr = bus->ops->map_bus(bus, devfn, where);
87 return PCIBIOS_DEVICE_NOT_FOUND;
96 return PCIBIOS_SUCCESSFUL;
98 EXPORT_SYMBOL_GPL(pci_generic_config_read);
100 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
101 int where, int size, u32 val)
105 addr = bus->ops->map_bus(bus, devfn, where);
107 return PCIBIOS_DEVICE_NOT_FOUND;
116 return PCIBIOS_SUCCESSFUL;
118 EXPORT_SYMBOL_GPL(pci_generic_config_write);
120 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
121 int where, int size, u32 *val)
125 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
127 return PCIBIOS_DEVICE_NOT_FOUND;
132 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
134 return PCIBIOS_SUCCESSFUL;
136 EXPORT_SYMBOL_GPL(pci_generic_config_read32);
138 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
139 int where, int size, u32 val)
144 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
146 return PCIBIOS_DEVICE_NOT_FOUND;
150 return PCIBIOS_SUCCESSFUL;
154 * In general, hardware that supports only 32-bit writes on PCI is
155 * not spec-compliant. For example, software may perform a 16-bit
156 * write. If the hardware only supports 32-bit accesses, we must
157 * do a 32-bit read, merge in the 16 bits we intend to write,
158 * followed by a 32-bit write. If the 16 bits we *don't* intend to
159 * write happen to have any RW1C (write-one-to-clear) bits set, we
160 * just inadvertently cleared something we shouldn't have.
162 dev_warn_ratelimited(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
163 size, pci_domain_nr(bus), bus->number,
164 PCI_SLOT(devfn), PCI_FUNC(devfn), where);
166 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
167 tmp = readl(addr) & mask;
168 tmp |= val << ((where & 0x3) * 8);
171 return PCIBIOS_SUCCESSFUL;
173 EXPORT_SYMBOL_GPL(pci_generic_config_write32);
176 * pci_bus_set_ops - Set raw operations of pci bus
177 * @bus: pci bus struct
178 * @ops: new raw operations
180 * Return previous raw operations
182 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
184 struct pci_ops *old_ops;
187 raw_spin_lock_irqsave(&pci_lock, flags);
190 raw_spin_unlock_irqrestore(&pci_lock, flags);
193 EXPORT_SYMBOL(pci_bus_set_ops);
196 * The following routines are to prevent the user from accessing PCI config
197 * space when it's unsafe to do so. Some devices require this during BIST and
198 * we're required to prevent it during D-state transitions.
200 * We have a bit per device to indicate it's blocked and a global wait queue
201 * for callers to sleep on until devices are unblocked.
203 static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
205 static noinline void pci_wait_cfg(struct pci_dev *dev)
206 __must_hold(&pci_lock)
209 raw_spin_unlock_irq(&pci_lock);
210 wait_event(pci_cfg_wait, !dev->block_cfg_access);
211 raw_spin_lock_irq(&pci_lock);
212 } while (dev->block_cfg_access);
215 /* Returns 0 on success, negative values indicate error. */
216 #define PCI_USER_READ_CONFIG(size, type) \
217 int pci_user_read_config_##size \
218 (struct pci_dev *dev, int pos, type *val) \
220 int ret = PCIBIOS_SUCCESSFUL; \
222 if (PCI_##size##_BAD) \
224 raw_spin_lock_irq(&pci_lock); \
225 if (unlikely(dev->block_cfg_access)) \
227 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
228 pos, sizeof(type), &data); \
229 raw_spin_unlock_irq(&pci_lock); \
231 PCI_SET_ERROR_RESPONSE(val); \
234 return pcibios_err_to_errno(ret); \
236 EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
238 /* Returns 0 on success, negative values indicate error. */
239 #define PCI_USER_WRITE_CONFIG(size, type) \
240 int pci_user_write_config_##size \
241 (struct pci_dev *dev, int pos, type val) \
243 int ret = PCIBIOS_SUCCESSFUL; \
244 if (PCI_##size##_BAD) \
246 raw_spin_lock_irq(&pci_lock); \
247 if (unlikely(dev->block_cfg_access)) \
249 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
250 pos, sizeof(type), val); \
251 raw_spin_unlock_irq(&pci_lock); \
252 return pcibios_err_to_errno(ret); \
254 EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
256 PCI_USER_READ_CONFIG(byte, u8)
257 PCI_USER_READ_CONFIG(word, u16)
258 PCI_USER_READ_CONFIG(dword, u32)
259 PCI_USER_WRITE_CONFIG(byte, u8)
260 PCI_USER_WRITE_CONFIG(word, u16)
261 PCI_USER_WRITE_CONFIG(dword, u32)
264 * pci_cfg_access_lock - Lock PCI config reads/writes
265 * @dev: pci device struct
267 * When access is locked, any userspace reads or writes to config
268 * space and concurrent lock requests will sleep until access is
269 * allowed via pci_cfg_access_unlock() again.
271 void pci_cfg_access_lock(struct pci_dev *dev)
275 raw_spin_lock_irq(&pci_lock);
276 if (dev->block_cfg_access)
278 dev->block_cfg_access = 1;
279 raw_spin_unlock_irq(&pci_lock);
281 EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
284 * pci_cfg_access_trylock - try to lock PCI config reads/writes
285 * @dev: pci device struct
287 * Same as pci_cfg_access_lock, but will return 0 if access is
288 * already locked, 1 otherwise. This function can be used from
291 bool pci_cfg_access_trylock(struct pci_dev *dev)
296 raw_spin_lock_irqsave(&pci_lock, flags);
297 if (dev->block_cfg_access)
300 dev->block_cfg_access = 1;
301 raw_spin_unlock_irqrestore(&pci_lock, flags);
305 EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
308 * pci_cfg_access_unlock - Unlock PCI config reads/writes
309 * @dev: pci device struct
311 * This function allows PCI config accesses to resume.
313 void pci_cfg_access_unlock(struct pci_dev *dev)
317 raw_spin_lock_irqsave(&pci_lock, flags);
320 * This indicates a problem in the caller, but we don't need
321 * to kill them, unlike a double-block above.
323 WARN_ON(!dev->block_cfg_access);
325 dev->block_cfg_access = 0;
326 raw_spin_unlock_irqrestore(&pci_lock, flags);
328 wake_up_all(&pci_cfg_wait);
330 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
332 static inline int pcie_cap_version(const struct pci_dev *dev)
334 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
337 bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
339 int type = pci_pcie_type(dev);
341 return type == PCI_EXP_TYPE_ENDPOINT ||
342 type == PCI_EXP_TYPE_LEG_END ||
343 type == PCI_EXP_TYPE_ROOT_PORT ||
344 type == PCI_EXP_TYPE_UPSTREAM ||
345 type == PCI_EXP_TYPE_DOWNSTREAM ||
346 type == PCI_EXP_TYPE_PCI_BRIDGE ||
347 type == PCI_EXP_TYPE_PCIE_BRIDGE;
350 static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
352 return pcie_downstream_port(dev) &&
353 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
356 bool pcie_cap_has_rtctl(const struct pci_dev *dev)
358 int type = pci_pcie_type(dev);
360 return type == PCI_EXP_TYPE_ROOT_PORT ||
361 type == PCI_EXP_TYPE_RC_EC;
364 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
366 if (!pci_is_pcie(dev))
379 return pcie_cap_has_lnkctl(dev);
383 return pcie_cap_has_sltctl(dev);
387 return pcie_cap_has_rtctl(dev);
388 case PCI_EXP_DEVCAP2:
389 case PCI_EXP_DEVCTL2:
390 case PCI_EXP_LNKCAP2:
391 case PCI_EXP_LNKCTL2:
392 case PCI_EXP_LNKSTA2:
393 return pcie_cap_version(dev) > 1;
400 * Note that these accessor functions are only for the "PCI Express
401 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
402 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
404 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
410 return PCIBIOS_BAD_REGISTER_NUMBER;
412 if (pcie_capability_reg_implemented(dev, pos)) {
413 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
415 * Reset *val to 0 if pci_read_config_word() fails; it may
416 * have been written as 0xFFFF (PCI_ERROR_RESPONSE) if the
417 * config read failed on PCI.
425 * For Functions that do not implement the Slot Capabilities,
426 * Slot Status, and Slot Control registers, these spaces must
427 * be hardwired to 0b, with the exception of the Presence Detect
428 * State bit in the Slot Status register of Downstream Ports,
429 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
431 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
432 pos == PCI_EXP_SLTSTA)
433 *val = PCI_EXP_SLTSTA_PDS;
437 EXPORT_SYMBOL(pcie_capability_read_word);
439 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
445 return PCIBIOS_BAD_REGISTER_NUMBER;
447 if (pcie_capability_reg_implemented(dev, pos)) {
448 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
450 * Reset *val to 0 if pci_read_config_dword() fails; it may
451 * have been written as 0xFFFFFFFF (PCI_ERROR_RESPONSE) if
452 * the config read failed on PCI.
459 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
460 pos == PCI_EXP_SLTSTA)
461 *val = PCI_EXP_SLTSTA_PDS;
465 EXPORT_SYMBOL(pcie_capability_read_dword);
467 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
470 return PCIBIOS_BAD_REGISTER_NUMBER;
472 if (!pcie_capability_reg_implemented(dev, pos))
475 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
477 EXPORT_SYMBOL(pcie_capability_write_word);
479 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
482 return PCIBIOS_BAD_REGISTER_NUMBER;
484 if (!pcie_capability_reg_implemented(dev, pos))
487 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
489 EXPORT_SYMBOL(pcie_capability_write_dword);
491 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
497 ret = pcie_capability_read_word(dev, pos, &val);
501 ret = pcie_capability_write_word(dev, pos, val);
506 EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
508 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
514 ret = pcie_capability_read_dword(dev, pos, &val);
518 ret = pcie_capability_write_dword(dev, pos, val);
523 EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
525 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
527 if (pci_dev_is_disconnected(dev)) {
528 PCI_SET_ERROR_RESPONSE(val);
529 return PCIBIOS_DEVICE_NOT_FOUND;
531 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
533 EXPORT_SYMBOL(pci_read_config_byte);
535 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
537 if (pci_dev_is_disconnected(dev)) {
538 PCI_SET_ERROR_RESPONSE(val);
539 return PCIBIOS_DEVICE_NOT_FOUND;
541 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
543 EXPORT_SYMBOL(pci_read_config_word);
545 int pci_read_config_dword(const struct pci_dev *dev, int where,
548 if (pci_dev_is_disconnected(dev)) {
549 PCI_SET_ERROR_RESPONSE(val);
550 return PCIBIOS_DEVICE_NOT_FOUND;
552 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
554 EXPORT_SYMBOL(pci_read_config_dword);
556 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
558 if (pci_dev_is_disconnected(dev))
559 return PCIBIOS_DEVICE_NOT_FOUND;
560 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
562 EXPORT_SYMBOL(pci_write_config_byte);
564 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
566 if (pci_dev_is_disconnected(dev))
567 return PCIBIOS_DEVICE_NOT_FOUND;
568 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
570 EXPORT_SYMBOL(pci_write_config_word);
572 int pci_write_config_dword(const struct pci_dev *dev, int where,
575 if (pci_dev_is_disconnected(dev))
576 return PCIBIOS_DEVICE_NOT_FOUND;
577 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
579 EXPORT_SYMBOL(pci_write_config_dword);