2 * Rockchip eFuse Driver
4 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
5 * Author: Caesar Wang <wxt@rock-chips.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/nvmem-provider.h>
23 #include <linux/slab.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
28 #define RK3288_A_SHIFT 6
29 #define RK3288_A_MASK 0x3ff
30 #define RK3288_PGENB BIT(3)
31 #define RK3288_LOAD BIT(2)
32 #define RK3288_STROBE BIT(1)
33 #define RK3288_CSB BIT(0)
35 #define RK3328_SECURE_SIZES 96
36 #define RK3328_INT_STATUS 0x0018
37 #define RK3328_DOUT 0x0020
38 #define RK3328_AUTO_CTRL 0x0024
39 #define RK3328_INT_FINISH BIT(0)
40 #define RK3328_AUTO_ENB BIT(0)
41 #define RK3328_AUTO_RD BIT(1)
43 #define RK3399_A_SHIFT 16
44 #define RK3399_A_MASK 0x3ff
45 #define RK3399_NBYTES 4
46 #define RK3399_STROBSFTSEL BIT(9)
47 #define RK3399_RSB BIT(7)
48 #define RK3399_PD BIT(5)
49 #define RK3399_PGENB BIT(3)
50 #define RK3399_LOAD BIT(2)
51 #define RK3399_STROBE BIT(1)
52 #define RK3399_CSB BIT(0)
54 #define REG_EFUSE_CTRL 0x0000
55 #define REG_EFUSE_DOUT 0x0004
57 struct rockchip_efuse_chip {
63 static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,
64 void *val, size_t bytes)
66 struct rockchip_efuse_chip *efuse = context;
70 ret = clk_prepare_enable(efuse->clk);
72 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
76 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);
79 writel(readl(efuse->base + REG_EFUSE_CTRL) &
80 (~(RK3288_A_MASK << RK3288_A_SHIFT)),
81 efuse->base + REG_EFUSE_CTRL);
82 writel(readl(efuse->base + REG_EFUSE_CTRL) |
83 ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
84 efuse->base + REG_EFUSE_CTRL);
86 writel(readl(efuse->base + REG_EFUSE_CTRL) |
87 RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);
89 *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
90 writel(readl(efuse->base + REG_EFUSE_CTRL) &
91 (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);
95 /* Switch to standby mode */
96 writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);
98 clk_disable_unprepare(efuse->clk);
103 static int rockchip_rk3328_efuse_read(void *context, unsigned int offset,
104 void *val, size_t bytes)
106 struct rockchip_efuse_chip *efuse = context;
107 unsigned int addr_start, addr_end, addr_offset, addr_len;
108 u32 out_value, status;
112 ret = clk_prepare_enable(efuse->clk);
114 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
118 /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */
119 offset += RK3328_SECURE_SIZES;
120 addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
121 addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
122 addr_offset = offset % RK3399_NBYTES;
123 addr_len = addr_end - addr_start;
125 buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)),
133 writel(RK3328_AUTO_RD | RK3328_AUTO_ENB |
134 ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
135 efuse->base + RK3328_AUTO_CTRL);
137 status = readl(efuse->base + RK3328_INT_STATUS);
138 if (!(status & RK3328_INT_FINISH)) {
142 out_value = readl(efuse->base + RK3328_DOUT);
143 writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS);
145 memcpy(&buf[i], &out_value, RK3399_NBYTES);
149 memcpy(val, buf + addr_offset, bytes);
153 clk_disable_unprepare(efuse->clk);
158 static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,
159 void *val, size_t bytes)
161 struct rockchip_efuse_chip *efuse = context;
162 unsigned int addr_start, addr_end, addr_offset, addr_len;
167 ret = clk_prepare_enable(efuse->clk);
169 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
173 addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
174 addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
175 addr_offset = offset % RK3399_NBYTES;
176 addr_len = addr_end - addr_start;
178 buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)),
181 clk_disable_unprepare(efuse->clk);
185 writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
186 efuse->base + REG_EFUSE_CTRL);
189 writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE |
190 ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
191 efuse->base + REG_EFUSE_CTRL);
193 out_value = readl(efuse->base + REG_EFUSE_DOUT);
194 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE),
195 efuse->base + REG_EFUSE_CTRL);
198 memcpy(&buf[i], &out_value, RK3399_NBYTES);
202 /* Switch to standby mode */
203 writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL);
205 memcpy(val, buf + addr_offset, bytes);
209 clk_disable_unprepare(efuse->clk);
214 static struct nvmem_config econfig = {
215 .name = "rockchip-efuse",
221 static const struct of_device_id rockchip_efuse_match[] = {
222 /* deprecated but kept around for dts binding compatibility */
224 .compatible = "rockchip,rockchip-efuse",
225 .data = (void *)&rockchip_rk3288_efuse_read,
228 .compatible = "rockchip,rk3066a-efuse",
229 .data = (void *)&rockchip_rk3288_efuse_read,
232 .compatible = "rockchip,rk3188-efuse",
233 .data = (void *)&rockchip_rk3288_efuse_read,
236 .compatible = "rockchip,rk3228-efuse",
237 .data = (void *)&rockchip_rk3288_efuse_read,
240 .compatible = "rockchip,rk3288-efuse",
241 .data = (void *)&rockchip_rk3288_efuse_read,
244 .compatible = "rockchip,rk3368-efuse",
245 .data = (void *)&rockchip_rk3288_efuse_read,
248 .compatible = "rockchip,rk3328-efuse",
249 .data = (void *)&rockchip_rk3328_efuse_read,
252 .compatible = "rockchip,rk3399-efuse",
253 .data = (void *)&rockchip_rk3399_efuse_read,
257 MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
259 static int rockchip_efuse_probe(struct platform_device *pdev)
261 struct resource *res;
262 struct nvmem_device *nvmem;
263 struct rockchip_efuse_chip *efuse;
265 struct device *dev = &pdev->dev;
267 data = of_device_get_match_data(dev);
269 dev_err(dev, "failed to get match data\n");
273 efuse = devm_kzalloc(dev, sizeof(struct rockchip_efuse_chip),
278 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
279 efuse->base = devm_ioremap_resource(dev, res);
280 if (IS_ERR(efuse->base))
281 return PTR_ERR(efuse->base);
283 efuse->clk = devm_clk_get(dev, "pclk_efuse");
284 if (IS_ERR(efuse->clk))
285 return PTR_ERR(efuse->clk);
288 if (of_property_read_u32(dev->of_node, "rockchip,efuse-size",
290 econfig.size = resource_size(res);
291 econfig.reg_read = data;
292 econfig.priv = efuse;
293 econfig.dev = efuse->dev;
294 nvmem = devm_nvmem_register(dev, &econfig);
296 return PTR_ERR_OR_ZERO(nvmem);
299 static struct platform_driver rockchip_efuse_driver = {
300 .probe = rockchip_efuse_probe,
302 .name = "rockchip-efuse",
303 .of_match_table = rockchip_efuse_match,
307 module_platform_driver(rockchip_efuse_driver);
308 MODULE_DESCRIPTION("rockchip_efuse driver");
309 MODULE_LICENSE("GPL v2");