drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/aer.h>
   9 #include <linux/async.h>
  10 #include <linux/blkdev.h>
  11 #include <linux/blk-mq.h>
  12 #include <linux/blk-mq-pci.h>
  13 #include <linux/dmi.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/once.h>
  21 #include <linux/pci.h>
  22 #include <linux/suspend.h>
  23 #include <linux/t10-pi.h>
  24 #include <linux/types.h>
  25 #include <linux/io-64-nonatomic-lo-hi.h>
  26 #include <linux/io-64-nonatomic-hi-lo.h>
  27 #include <linux/sed-opal.h>
  28 #include <linux/pci-p2pdma.h>
  29
  30 #include "trace.h"
  31 #include "nvme.h"
  32
  33 #define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  34 #define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  35
  36 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  37
  38 /*
  39  * These can be higher, but we need to ensure that any command doesn't
  40  * require an sg allocation that needs more than a page of data.
  41  */
  42 #define NVME_MAX_KB_SZ  4096
  43 #define NVME_MAX_SEGS   127
  44
  45 static int use_threaded_interrupts;
  46 module_param(use_threaded_interrupts, int, 0);
  47
  48 static bool use_cmb_sqes = true;
  49 module_param(use_cmb_sqes, bool, 0444);
  50 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  51
  52 static unsigned int max_host_mem_size_mb = 128;
  53 module_param(max_host_mem_size_mb, uint, 0444);
  54 MODULE_PARM_DESC(max_host_mem_size_mb,
  55         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  56
  57 static unsigned int sgl_threshold = SZ_32K;
  58 module_param(sgl_threshold, uint, 0644);
  59 MODULE_PARM_DESC(sgl_threshold,
  60                 "Use SGLs when average request segment size is larger or equal to "
  61                 "this size. Use 0 to disable SGLs.");
  62
  63 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  64 static const struct kernel_param_ops io_queue_depth_ops = {
  65         .set = io_queue_depth_set,
  66         .get = param_get_uint,
  67 };
  68
  69 static unsigned int io_queue_depth = 1024;
  70 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  71 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
  72
  73 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  74 {
  75         unsigned int n;
  76         int ret;
  77
  78         ret = kstrtouint(val, 10, &n);
  79         if (ret != 0 || n > num_possible_cpus())
  80                 return -EINVAL;
  81         return param_set_uint(val, kp);
  82 }
  83
  84 static const struct kernel_param_ops io_queue_count_ops = {
  85         .set = io_queue_count_set,
  86         .get = param_get_uint,
  87 };
  88
  89 static unsigned int write_queues;
  90 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  91 MODULE_PARM_DESC(write_queues,
  92         "Number of queues to use for writes. If not set, reads and writes "
  93         "will share a queue set.");
  94
  95 static unsigned int poll_queues;
  96 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
  97 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
  98
  99 static bool noacpi;
 100 module_param(noacpi, bool, 0444);
 101 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 102
 103 struct nvme_dev;
 104 struct nvme_queue;
 105
 106 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 107 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
 108
 109 /*
 110  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 111  */
 112 struct nvme_dev {
 113         struct nvme_queue *queues;
 114         struct blk_mq_tag_set tagset;
 115         struct blk_mq_tag_set admin_tagset;
 116         u32 __iomem *dbs;
 117         struct device *dev;
 118         struct dma_pool *prp_page_pool;
 119         struct dma_pool *prp_small_pool;
 120         unsigned online_queues;
 121         unsigned max_qid;
 122         unsigned io_queues[HCTX_MAX_TYPES];
 123         unsigned int num_vecs;
 124         u32 q_depth;
 125         int io_sqes;
 126         u32 db_stride;
 127         void __iomem *bar;
 128         unsigned long bar_mapped_size;
 129         struct work_struct remove_work;
 130         struct mutex shutdown_lock;
 131         bool subsystem;
 132         u64 cmb_size;
 133         bool cmb_use_sqes;
 134         u32 cmbsz;
 135         u32 cmbloc;
 136         struct nvme_ctrl ctrl;
 137         u32 last_ps;
 138
 139         mempool_t *iod_mempool;
 140
 141         /* shadow doorbell buffer support: */
 142         u32 *dbbuf_dbs;
 143         dma_addr_t dbbuf_dbs_dma_addr;
 144         u32 *dbbuf_eis;
 145         dma_addr_t dbbuf_eis_dma_addr;
 146
 147         /* host memory buffer support: */
 148         u64 host_mem_size;
 149         u32 nr_host_mem_descs;
 150         dma_addr_t host_mem_descs_dma;
 151         struct nvme_host_mem_buf_desc *host_mem_descs;
 152         void **host_mem_desc_bufs;
 153         unsigned int nr_allocated_queues;
 154         unsigned int nr_write_queues;
 155         unsigned int nr_poll_queues;
 156 };
 157
 158 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 159 {
 160         int ret;
 161         u32 n;
 162
 163         ret = kstrtou32(val, 10, &n);
 164         if (ret != 0 || n < 2)
 165                 return -EINVAL;
 166
 167         return param_set_uint(val, kp);
 168 }
 169
 170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 171 {
 172         return qid * 2 * stride;
 173 }
 174
 175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 176 {
 177         return (qid * 2 + 1) * stride;
 178 }
 179
 180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 181 {
 182         return container_of(ctrl, struct nvme_dev, ctrl);
 183 }
 184
 185 /*
 186  * An NVM Express queue.  Each device has at least two (one for admin
 187  * commands and one for I/O commands).
 188  */
 189 struct nvme_queue {
 190         struct nvme_dev *dev;
 191         spinlock_t sq_lock;
 192         void *sq_cmds;
 193          /* only used for poll queues: */
 194         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 195         struct nvme_completion *cqes;
 196         dma_addr_t sq_dma_addr;
 197         dma_addr_t cq_dma_addr;
 198         u32 __iomem *q_db;
 199         u32 q_depth;
 200         u16 cq_vector;
 201         u16 sq_tail;
 202         u16 last_sq_tail;
 203         u16 cq_head;
 204         u16 qid;
 205         u8 cq_phase;
 206         u8 sqes;
 207         unsigned long flags;
 208 #define NVMEQ_ENABLED           0
 209 #define NVMEQ_SQ_CMB            1
 210 #define NVMEQ_DELETE_ERROR      2
 211 #define NVMEQ_POLLED            3
 212         u32 *dbbuf_sq_db;
 213         u32 *dbbuf_cq_db;
 214         u32 *dbbuf_sq_ei;
 215         u32 *dbbuf_cq_ei;
 216         struct completion delete_done;
 217 };
 218
 219 /*
 220  * The nvme_iod describes the data in an I/O.
 221  *
 222  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 223  * to the actual struct scatterlist.
 224  */
 225 struct nvme_iod {
 226         struct nvme_request req;
 227         struct nvme_command cmd;
 228         struct nvme_queue *nvmeq;
 229         bool use_sgl;
 230         int aborted;
 231         int npages;             /* In the PRP list. 0 means small pool in use */
 232         int nents;              /* Used in scatterlist */
 233         dma_addr_t first_dma;
 234         unsigned int dma_len;   /* length of single DMA segment mapping */
 235         dma_addr_t meta_dma;
 236         struct scatterlist *sg;
 237 };
 238
 239 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 240 {
 241         return dev->nr_allocated_queues * 8 * dev->db_stride;
 242 }
 243
 244 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 245 {
 246         unsigned int mem_size = nvme_dbbuf_size(dev);
 247
 248         if (dev->dbbuf_dbs)
 249                 return 0;
 250
 251         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 252                                             &dev->dbbuf_dbs_dma_addr,
 253                                             GFP_KERNEL);
 254         if (!dev->dbbuf_dbs)
 255                 return -ENOMEM;
 256         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 257                                             &dev->dbbuf_eis_dma_addr,
 258                                             GFP_KERNEL);
 259         if (!dev->dbbuf_eis) {
 260                 dma_free_coherent(dev->dev, mem_size,
 261                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 262                 dev->dbbuf_dbs = NULL;
 263                 return -ENOMEM;
 264         }
 265
 266         return 0;
 267 }
 268
 269 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 270 {
 271         unsigned int mem_size = nvme_dbbuf_size(dev);
 272
 273         if (dev->dbbuf_dbs) {
 274                 dma_free_coherent(dev->dev, mem_size,
 275                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 276                 dev->dbbuf_dbs = NULL;
 277         }
 278         if (dev->dbbuf_eis) {
 279                 dma_free_coherent(dev->dev, mem_size,
 280                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 281                 dev->dbbuf_eis = NULL;
 282         }
 283 }
 284
 285 static void nvme_dbbuf_init(struct nvme_dev *dev,
 286                             struct nvme_queue *nvmeq, int qid)
 287 {
 288         if (!dev->dbbuf_dbs || !qid)
 289                 return;
 290
 291         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 292         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 293         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 294         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 295 }
 296
 297 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 298 {
 299         if (!nvmeq->qid)
 300                 return;
 301
 302         nvmeq->dbbuf_sq_db = NULL;
 303         nvmeq->dbbuf_cq_db = NULL;
 304         nvmeq->dbbuf_sq_ei = NULL;
 305         nvmeq->dbbuf_cq_ei = NULL;
 306 }
 307
 308 static void nvme_dbbuf_set(struct nvme_dev *dev)
 309 {
 310         struct nvme_command c;
 311         unsigned int i;
 312
 313         if (!dev->dbbuf_dbs)
 314                 return;
 315
 316         memset(&c, 0, sizeof(c));
 317         c.dbbuf.opcode = nvme_admin_dbbuf;
 318         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 319         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 320
 321         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 322                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 323                 /* Free memory and continue on */
 324                 nvme_dbbuf_dma_free(dev);
 325
 326                 for (i = 1; i <= dev->online_queues; i++)
 327                         nvme_dbbuf_free(&dev->queues[i]);
 328         }
 329 }
 330
 331 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 332 {
 333         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 334 }
 335
 336 /* Update dbbuf and return true if an MMIO is required */
 337 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 338                                               volatile u32 *dbbuf_ei)
 339 {
 340         if (dbbuf_db) {
 341                 u16 old_value;
 342
 343                 /*
 344                  * Ensure that the queue is written before updating
 345                  * the doorbell in memory
 346                  */
 347                 wmb();
 348
 349                 old_value = *dbbuf_db;
 350                 *dbbuf_db = value;
 351
 352                 /*
 353                  * Ensure that the doorbell is updated before reading the event
 354                  * index from memory.  The controller needs to provide similar
 355                  * ordering to ensure the envent index is updated before reading
 356                  * the doorbell.
 357                  */
 358                 mb();
 359
 360                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 361                         return false;
 362         }
 363
 364         return true;
 365 }
 366
 367 /*
 368  * Will slightly overestimate the number of pages needed.  This is OK
 369  * as it only leads to a small amount of wasted memory for the lifetime of
 370  * the I/O.
 371  */
 372 static int nvme_pci_npages_prp(void)
 373 {
 374         unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
 375                                       NVME_CTRL_PAGE_SIZE);
 376         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 377 }
 378
 379 /*
 380  * Calculates the number of pages needed for the SGL segments. For example a 4k
 381  * page can accommodate 256 SGL descriptors.
 382  */
 383 static int nvme_pci_npages_sgl(void)
 384 {
 385         return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
 386                         PAGE_SIZE);
 387 }
 388
 389 static size_t nvme_pci_iod_alloc_size(void)
 390 {
 391         size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
 392
 393         return sizeof(__le64 *) * npages +
 394                 sizeof(struct scatterlist) * NVME_MAX_SEGS;
 395 }
 396
 397 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 398                                 unsigned int hctx_idx)
 399 {
 400         struct nvme_dev *dev = data;
 401         struct nvme_queue *nvmeq = &dev->queues[0];
 402
 403         WARN_ON(hctx_idx != 0);
 404         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 405
 406         hctx->driver_data = nvmeq;
 407         return 0;
 408 }
 409
 410 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 411                           unsigned int hctx_idx)
 412 {
 413         struct nvme_dev *dev = data;
 414         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 415
 416         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 417         hctx->driver_data = nvmeq;
 418         return 0;
 419 }
 420
 421 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 422                 unsigned int hctx_idx, unsigned int numa_node)
 423 {
 424         struct nvme_dev *dev = set->driver_data;
 425         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 426         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 427         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 428
 429         BUG_ON(!nvmeq);
 430         iod->nvmeq = nvmeq;
 431
 432         nvme_req(req)->ctrl = &dev->ctrl;
 433         nvme_req(req)->cmd = &iod->cmd;
 434         return 0;
 435 }
 436
 437 static int queue_irq_offset(struct nvme_dev *dev)
 438 {
 439         /* if we have more than 1 vec, admin queue offsets us by 1 */
 440         if (dev->num_vecs > 1)
 441                 return 1;
 442
 443         return 0;
 444 }
 445
 446 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 447 {
 448         struct nvme_dev *dev = set->driver_data;
 449         int i, qoff, offset;
 450
 451         offset = queue_irq_offset(dev);
 452         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 453                 struct blk_mq_queue_map *map = &set->map[i];
 454
 455                 map->nr_queues = dev->io_queues[i];
 456                 if (!map->nr_queues) {
 457                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 458                         continue;
 459                 }
 460
 461                 /*
 462                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 463                  * affinity), so use the regular blk-mq cpu mapping
 464                  */
 465                 map->queue_offset = qoff;
 466                 if (i != HCTX_TYPE_POLL && offset)
 467                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 468                 else
 469                         blk_mq_map_queues(map);
 470                 qoff += map->nr_queues;
 471                 offset += map->nr_queues;
 472         }
 473
 474         return 0;
 475 }
 476
 477 /*
 478  * Write sq tail if we are asked to, or if the next command would wrap.
 479  */
 480 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 481 {
 482         if (!write_sq) {
 483                 u16 next_tail = nvmeq->sq_tail + 1;
 484
 485                 if (next_tail == nvmeq->q_depth)
 486                         next_tail = 0;
 487                 if (next_tail != nvmeq->last_sq_tail)
 488                         return;
 489         }
 490
 491         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 492                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 493                 writel(nvmeq->sq_tail, nvmeq->q_db);
 494         nvmeq->last_sq_tail = nvmeq->sq_tail;
 495 }
 496
 497 /**
 498  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 499  * @nvmeq: The queue to use
 500  * @cmd: The command to send
 501  * @write_sq: whether to write to the SQ doorbell
 502  */
 503 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
 504                             bool write_sq)
 505 {
 506         spin_lock(&nvmeq->sq_lock);
 507         memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 508                cmd, sizeof(*cmd));
 509         if (++nvmeq->sq_tail == nvmeq->q_depth)
 510                 nvmeq->sq_tail = 0;
 511         nvme_write_sq_db(nvmeq, write_sq);
 512         spin_unlock(&nvmeq->sq_lock);
 513 }
 514
 515 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 516 {
 517         struct nvme_queue *nvmeq = hctx->driver_data;
 518
 519         spin_lock(&nvmeq->sq_lock);
 520         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 521                 nvme_write_sq_db(nvmeq, true);
 522         spin_unlock(&nvmeq->sq_lock);
 523 }
 524
 525 static void **nvme_pci_iod_list(struct request *req)
 526 {
 527         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 528         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 529 }
 530
 531 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 532 {
 533         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 534         int nseg = blk_rq_nr_phys_segments(req);
 535         unsigned int avg_seg_size;
 536
 537         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 538
 539         if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
 540                 return false;
 541         if (!iod->nvmeq->qid)
 542                 return false;
 543         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 544                 return false;
 545         return true;
 546 }
 547
 548 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
 549 {
 550         const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 551         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 552         dma_addr_t dma_addr = iod->first_dma;
 553         int i;
 554
 555         for (i = 0; i < iod->npages; i++) {
 556                 __le64 *prp_list = nvme_pci_iod_list(req)[i];
 557                 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 558
 559                 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
 560                 dma_addr = next_dma_addr;
 561         }
 562
 563 }
 564
 565 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
 566 {
 567         const int last_sg = SGES_PER_PAGE - 1;
 568         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 569         dma_addr_t dma_addr = iod->first_dma;
 570         int i;
 571
 572         for (i = 0; i < iod->npages; i++) {
 573                 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
 574                 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
 575
 576                 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
 577                 dma_addr = next_dma_addr;
 578         }
 579
 580 }
 581
 582 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
 583 {
 584         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 585
 586         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 587                 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
 588                                     rq_dma_dir(req));
 589         else
 590                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
 591 }
 592
 593 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 594 {
 595         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 596
 597         if (iod->dma_len) {
 598                 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
 599                                rq_dma_dir(req));
 600                 return;
 601         }
 602
 603         WARN_ON_ONCE(!iod->nents);
 604
 605         nvme_unmap_sg(dev, req);
 606         if (iod->npages == 0)
 607                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 608                               iod->first_dma);
 609         else if (iod->use_sgl)
 610                 nvme_free_sgls(dev, req);
 611         else
 612                 nvme_free_prps(dev, req);
 613         mempool_free(iod->sg, dev->iod_mempool);
 614 }
 615
 616 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 617 {
 618         int i;
 619         struct scatterlist *sg;
 620
 621         for_each_sg(sgl, sg, nents, i) {
 622                 dma_addr_t phys = sg_phys(sg);
 623                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 624                         "dma_address:%pad dma_length:%d\n",
 625                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 626                         sg_dma_len(sg));
 627         }
 628 }
 629
 630 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 631                 struct request *req, struct nvme_rw_command *cmnd)
 632 {
 633         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 634         struct dma_pool *pool;
 635         int length = blk_rq_payload_bytes(req);
 636         struct scatterlist *sg = iod->sg;
 637         int dma_len = sg_dma_len(sg);
 638         u64 dma_addr = sg_dma_address(sg);
 639         int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 640         __le64 *prp_list;
 641         void **list = nvme_pci_iod_list(req);
 642         dma_addr_t prp_dma;
 643         int nprps, i;
 644
 645         length -= (NVME_CTRL_PAGE_SIZE - offset);
 646         if (length <= 0) {
 647                 iod->first_dma = 0;
 648                 goto done;
 649         }
 650
 651         dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 652         if (dma_len) {
 653                 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 654         } else {
 655                 sg = sg_next(sg);
 656                 dma_addr = sg_dma_address(sg);
 657                 dma_len = sg_dma_len(sg);
 658         }
 659
 660         if (length <= NVME_CTRL_PAGE_SIZE) {
 661                 iod->first_dma = dma_addr;
 662                 goto done;
 663         }
 664
 665         nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 666         if (nprps <= (256 / 8)) {
 667                 pool = dev->prp_small_pool;
 668                 iod->npages = 0;
 669         } else {
 670                 pool = dev->prp_page_pool;
 671                 iod->npages = 1;
 672         }
 673
 674         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 675         if (!prp_list) {
 676                 iod->first_dma = dma_addr;
 677                 iod->npages = -1;
 678                 return BLK_STS_RESOURCE;
 679         }
 680         list[0] = prp_list;
 681         iod->first_dma = prp_dma;
 682         i = 0;
 683         for (;;) {
 684                 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 685                         __le64 *old_prp_list = prp_list;
 686                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 687                         if (!prp_list)
 688                                 goto free_prps;
 689                         list[iod->npages++] = prp_list;
 690                         prp_list[0] = old_prp_list[i - 1];
 691                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 692                         i = 1;
 693                 }
 694                 prp_list[i++] = cpu_to_le64(dma_addr);
 695                 dma_len -= NVME_CTRL_PAGE_SIZE;
 696                 dma_addr += NVME_CTRL_PAGE_SIZE;
 697                 length -= NVME_CTRL_PAGE_SIZE;
 698                 if (length <= 0)
 699                         break;
 700                 if (dma_len > 0)
 701                         continue;
 702                 if (unlikely(dma_len < 0))
 703                         goto bad_sgl;
 704                 sg = sg_next(sg);
 705                 dma_addr = sg_dma_address(sg);
 706                 dma_len = sg_dma_len(sg);
 707         }
 708 done:
 709         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 710         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 711         return BLK_STS_OK;
 712 free_prps:
 713         nvme_free_prps(dev, req);
 714         return BLK_STS_RESOURCE;
 715 bad_sgl:
 716         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 717                         "Invalid SGL for payload:%d nents:%d\n",
 718                         blk_rq_payload_bytes(req), iod->nents);
 719         return BLK_STS_IOERR;
 720 }
 721
 722 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 723                 struct scatterlist *sg)
 724 {
 725         sge->addr = cpu_to_le64(sg_dma_address(sg));
 726         sge->length = cpu_to_le32(sg_dma_len(sg));
 727         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 728 }
 729
 730 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 731                 dma_addr_t dma_addr, int entries)
 732 {
 733         sge->addr = cpu_to_le64(dma_addr);
 734         if (entries < SGES_PER_PAGE) {
 735                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 736                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 737         } else {
 738                 sge->length = cpu_to_le32(PAGE_SIZE);
 739                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 740         }
 741 }
 742
 743 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 744                 struct request *req, struct nvme_rw_command *cmd, int entries)
 745 {
 746         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 747         struct dma_pool *pool;
 748         struct nvme_sgl_desc *sg_list;
 749         struct scatterlist *sg = iod->sg;
 750         dma_addr_t sgl_dma;
 751         int i = 0;
 752
 753         /* setting the transfer type as SGL */
 754         cmd->flags = NVME_CMD_SGL_METABUF;
 755
 756         if (entries == 1) {
 757                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 758                 return BLK_STS_OK;
 759         }
 760
 761         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 762                 pool = dev->prp_small_pool;
 763                 iod->npages = 0;
 764         } else {
 765                 pool = dev->prp_page_pool;
 766                 iod->npages = 1;
 767         }
 768
 769         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 770         if (!sg_list) {
 771                 iod->npages = -1;
 772                 return BLK_STS_RESOURCE;
 773         }
 774
 775         nvme_pci_iod_list(req)[0] = sg_list;
 776         iod->first_dma = sgl_dma;
 777
 778         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 779
 780         do {
 781                 if (i == SGES_PER_PAGE) {
 782                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 783                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 784
 785                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 786                         if (!sg_list)
 787                                 goto free_sgls;
 788
 789                         i = 0;
 790                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 791                         sg_list[i++] = *link;
 792                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 793                 }
 794
 795                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 796                 sg = sg_next(sg);
 797         } while (--entries > 0);
 798
 799         return BLK_STS_OK;
 800 free_sgls:
 801         nvme_free_sgls(dev, req);
 802         return BLK_STS_RESOURCE;
 803 }
 804
 805 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 806                 struct request *req, struct nvme_rw_command *cmnd,
 807                 struct bio_vec *bv)
 808 {
 809         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 810         unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 811         unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 812
 813         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 814         if (dma_mapping_error(dev->dev, iod->first_dma))
 815                 return BLK_STS_RESOURCE;
 816         iod->dma_len = bv->bv_len;
 817
 818         cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 819         if (bv->bv_len > first_prp_len)
 820                 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 821         return BLK_STS_OK;
 822 }
 823
 824 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 825                 struct request *req, struct nvme_rw_command *cmnd,
 826                 struct bio_vec *bv)
 827 {
 828         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 829
 830         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 831         if (dma_mapping_error(dev->dev, iod->first_dma))
 832                 return BLK_STS_RESOURCE;
 833         iod->dma_len = bv->bv_len;
 834
 835         cmnd->flags = NVME_CMD_SGL_METABUF;
 836         cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 837         cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 838         cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 839         return BLK_STS_OK;
 840 }
 841
 842 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 843                 struct nvme_command *cmnd)
 844 {
 845         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 846         blk_status_t ret = BLK_STS_RESOURCE;
 847         int nr_mapped;
 848
 849         if (blk_rq_nr_phys_segments(req) == 1) {
 850                 struct bio_vec bv = req_bvec(req);
 851
 852                 if (!is_pci_p2pdma_page(bv.bv_page)) {
 853                         if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 854                                 return nvme_setup_prp_simple(dev, req,
 855                                                              &cmnd->rw, &bv);
 856
 857                         if (iod->nvmeq->qid && sgl_threshold &&
 858                             dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
 859                                 return nvme_setup_sgl_simple(dev, req,
 860                                                              &cmnd->rw, &bv);
 861                 }
 862         }
 863
 864         iod->dma_len = 0;
 865         iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 866         if (!iod->sg)
 867                 return BLK_STS_RESOURCE;
 868         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 869         iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
 870         if (!iod->nents)
 871                 goto out_free_sg;
 872
 873         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 874                 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
 875                                 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
 876         else
 877                 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
 878                                              rq_dma_dir(req), DMA_ATTR_NO_WARN);
 879         if (!nr_mapped)
 880                 goto out_free_sg;
 881
 882         iod->use_sgl = nvme_pci_use_sgls(dev, req);
 883         if (iod->use_sgl)
 884                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
 885         else
 886                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 887         if (ret != BLK_STS_OK)
 888                 goto out_unmap_sg;
 889         return BLK_STS_OK;
 890
 891 out_unmap_sg:
 892         nvme_unmap_sg(dev, req);
 893 out_free_sg:
 894         mempool_free(iod->sg, dev->iod_mempool);
 895         return ret;
 896 }
 897
 898 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 899                 struct nvme_command *cmnd)
 900 {
 901         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 902
 903         iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 904                         rq_dma_dir(req), 0);
 905         if (dma_mapping_error(dev->dev, iod->meta_dma))
 906                 return BLK_STS_IOERR;
 907         cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 908         return BLK_STS_OK;
 909 }
 910
 911 /*
 912  * NOTE: ns is NULL when called on the admin queue.
 913  */
 914 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 915                          const struct blk_mq_queue_data *bd)
 916 {
 917         struct nvme_ns *ns = hctx->queue->queuedata;
 918         struct nvme_queue *nvmeq = hctx->driver_data;
 919         struct nvme_dev *dev = nvmeq->dev;
 920         struct request *req = bd->rq;
 921         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 922         struct nvme_command *cmnd = &iod->cmd;
 923         blk_status_t ret;
 924
 925         iod->aborted = 0;
 926         iod->npages = -1;
 927         iod->nents = 0;
 928
 929         /*
 930          * We should not need to do this, but we're still using this to
 931          * ensure we can drain requests on a dying queue.
 932          */
 933         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 934                 return BLK_STS_IOERR;
 935
 936         if (!nvme_check_ready(&dev->ctrl, req, true))
 937                 return nvme_fail_nonready_command(&dev->ctrl, req);
 938
 939         ret = nvme_setup_cmd(ns, req);
 940         if (ret)
 941                 return ret;
 942
 943         if (blk_rq_nr_phys_segments(req)) {
 944                 ret = nvme_map_data(dev, req, cmnd);
 945                 if (ret)
 946                         goto out_free_cmd;
 947         }
 948
 949         if (blk_integrity_rq(req)) {
 950                 ret = nvme_map_metadata(dev, req, cmnd);
 951                 if (ret)
 952                         goto out_unmap_data;
 953         }
 954
 955         blk_mq_start_request(req);
 956         nvme_submit_cmd(nvmeq, cmnd, bd->last);
 957         return BLK_STS_OK;
 958 out_unmap_data:
 959         nvme_unmap_data(dev, req);
 960 out_free_cmd:
 961         nvme_cleanup_cmd(req);
 962         return ret;
 963 }
 964
 965 static void nvme_pci_complete_rq(struct request *req)
 966 {
 967         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 968         struct nvme_dev *dev = iod->nvmeq->dev;
 969
 970         if (blk_integrity_rq(req))
 971                 dma_unmap_page(dev->dev, iod->meta_dma,
 972                                rq_integrity_vec(req)->bv_len, rq_data_dir(req));
 973         if (blk_rq_nr_phys_segments(req))
 974                 nvme_unmap_data(dev, req);
 975         nvme_complete_rq(req);
 976 }
 977
 978 /* We read the CQE phase first to check if the rest of the entry is valid */
 979 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
 980 {
 981         struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
 982
 983         return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
 984 }
 985
 986 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 987 {
 988         u16 head = nvmeq->cq_head;
 989
 990         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 991                                               nvmeq->dbbuf_cq_ei))
 992                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 993 }
 994
 995 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
 996 {
 997         if (!nvmeq->qid)
 998                 return nvmeq->dev->admin_tagset.tags[0];
 999         return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1000 }
1001
1002 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
1003 {
1004         struct nvme_completion *cqe = &nvmeq->cqes[idx];
1005         __u16 command_id = READ_ONCE(cqe->command_id);
1006         struct request *req;
1007
1008         /*
1009          * AEN requests are special as they don't time out and can
1010          * survive any kind of queue freeze and often don't respond to
1011          * aborts.  We don't even bother to allocate a struct request
1012          * for them but rather special case them here.
1013          */
1014         if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1015                 nvme_complete_async_event(&nvmeq->dev->ctrl,
1016                                 cqe->status, &cqe->result);
1017                 return;
1018         }
1019
1020         req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id);
1021         if (unlikely(!req)) {
1022                 dev_warn(nvmeq->dev->ctrl.device,
1023                         "invalid id %d completed on queue %d\n",
1024                         command_id, le16_to_cpu(cqe->sq_id));
1025                 return;
1026         }
1027
1028         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1029         if (!nvme_try_complete_req(req, cqe->status, cqe->result))
1030                 nvme_pci_complete_rq(req);
1031 }
1032
1033 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1034 {
1035         u16 tmp = nvmeq->cq_head + 1;
1036
1037         if (tmp == nvmeq->q_depth) {
1038                 nvmeq->cq_head = 0;
1039                 nvmeq->cq_phase ^= 1;
1040         } else {
1041                 nvmeq->cq_head = tmp;
1042         }
1043 }
1044
1045 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
1046 {
1047         int found = 0;
1048
1049         while (nvme_cqe_pending(nvmeq)) {
1050                 found++;
1051                 /*
1052                  * load-load control dependency between phase and the rest of
1053                  * the cqe requires a full read memory barrier
1054                  */
1055                 dma_rmb();
1056                 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1057                 nvme_update_cq_head(nvmeq);
1058         }
1059
1060         if (found)
1061                 nvme_ring_cq_doorbell(nvmeq);
1062         return found;
1063 }
1064
1065 static irqreturn_t nvme_irq(int irq, void *data)
1066 {
1067         struct nvme_queue *nvmeq = data;
1068
1069         if (nvme_process_cq(nvmeq))
1070                 return IRQ_HANDLED;
1071         return IRQ_NONE;
1072 }
1073
1074 static irqreturn_t nvme_irq_check(int irq, void *data)
1075 {
1076         struct nvme_queue *nvmeq = data;
1077
1078         if (nvme_cqe_pending(nvmeq))
1079                 return IRQ_WAKE_THREAD;
1080         return IRQ_NONE;
1081 }
1082
1083 /*
1084  * Poll for completions for any interrupt driven queue
1085  * Can be called from any context.
1086  */
1087 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1088 {
1089         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1090
1091         WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1092
1093         disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1094         nvme_process_cq(nvmeq);
1095         enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1096 }
1097
1098 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1099 {
1100         struct nvme_queue *nvmeq = hctx->driver_data;
1101         bool found;
1102
1103         if (!nvme_cqe_pending(nvmeq))
1104                 return 0;
1105
1106         spin_lock(&nvmeq->cq_poll_lock);
1107         found = nvme_process_cq(nvmeq);
1108         spin_unlock(&nvmeq->cq_poll_lock);
1109
1110         return found;
1111 }
1112
1113 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1114 {
1115         struct nvme_dev *dev = to_nvme_dev(ctrl);
1116         struct nvme_queue *nvmeq = &dev->queues[0];
1117         struct nvme_command c;
1118
1119         memset(&c, 0, sizeof(c));
1120         c.common.opcode = nvme_admin_async_event;
1121         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1122         nvme_submit_cmd(nvmeq, &c, true);
1123 }
1124
1125 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1126 {
1127         struct nvme_command c;
1128
1129         memset(&c, 0, sizeof(c));
1130         c.delete_queue.opcode = opcode;
1131         c.delete_queue.qid = cpu_to_le16(id);
1132
1133         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1134 }
1135
1136 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1137                 struct nvme_queue *nvmeq, s16 vector)
1138 {
1139         struct nvme_command c;
1140         int flags = NVME_QUEUE_PHYS_CONTIG;
1141
1142         if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1143                 flags |= NVME_CQ_IRQ_ENABLED;
1144
1145         /*
1146          * Note: we (ab)use the fact that the prp fields survive if no data
1147          * is attached to the request.
1148          */
1149         memset(&c, 0, sizeof(c));
1150         c.create_cq.opcode = nvme_admin_create_cq;
1151         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1152         c.create_cq.cqid = cpu_to_le16(qid);
1153         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1154         c.create_cq.cq_flags = cpu_to_le16(flags);
1155         c.create_cq.irq_vector = cpu_to_le16(vector);
1156
1157         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1158 }
1159
1160 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1161                                                 struct nvme_queue *nvmeq)
1162 {
1163         struct nvme_ctrl *ctrl = &dev->ctrl;
1164         struct nvme_command c;
1165         int flags = NVME_QUEUE_PHYS_CONTIG;
1166
1167         /*
1168          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1169          * set. Since URGENT priority is zeroes, it makes all queues
1170          * URGENT.
1171          */
1172         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1173                 flags |= NVME_SQ_PRIO_MEDIUM;
1174
1175         /*
1176          * Note: we (ab)use the fact that the prp fields survive if no data
1177          * is attached to the request.
1178          */
1179         memset(&c, 0, sizeof(c));
1180         c.create_sq.opcode = nvme_admin_create_sq;
1181         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1182         c.create_sq.sqid = cpu_to_le16(qid);
1183         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1184         c.create_sq.sq_flags = cpu_to_le16(flags);
1185         c.create_sq.cqid = cpu_to_le16(qid);
1186
1187         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1188 }
1189
1190 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1191 {
1192         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1193 }
1194
1195 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1196 {
1197         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1198 }
1199
1200 static void abort_endio(struct request *req, blk_status_t error)
1201 {
1202         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1203         struct nvme_queue *nvmeq = iod->nvmeq;
1204
1205         dev_warn(nvmeq->dev->ctrl.device,
1206                  "Abort status: 0x%x", nvme_req(req)->status);
1207         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1208         blk_mq_free_request(req);
1209 }
1210
1211 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1212 {
1213         /* If true, indicates loss of adapter communication, possibly by a
1214          * NVMe Subsystem reset.
1215          */
1216         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1217
1218         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1219         switch (dev->ctrl.state) {
1220         case NVME_CTRL_RESETTING:
1221         case NVME_CTRL_CONNECTING:
1222                 return false;
1223         default:
1224                 break;
1225         }
1226
1227         /* We shouldn't reset unless the controller is on fatal error state
1228          * _or_ if we lost the communication with it.
1229          */
1230         if (!(csts & NVME_CSTS_CFS) && !nssro)
1231                 return false;
1232
1233         return true;
1234 }
1235
1236 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1237 {
1238         /* Read a config register to help see what died. */
1239         u16 pci_status;
1240         int result;
1241
1242         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1243                                       &pci_status);
1244         if (result == PCIBIOS_SUCCESSFUL)
1245                 dev_warn(dev->ctrl.device,
1246                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1247                          csts, pci_status);
1248         else
1249                 dev_warn(dev->ctrl.device,
1250                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1251                          csts, result);
1252 }
1253
1254 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1255 {
1256         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1257         struct nvme_queue *nvmeq = iod->nvmeq;
1258         struct nvme_dev *dev = nvmeq->dev;
1259         struct request *abort_req;
1260         struct nvme_command cmd;
1261         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1262
1263         /* If PCI error recovery process is happening, we cannot reset or
1264          * the recovery mechanism will surely fail.
1265          */
1266         mb();
1267         if (pci_channel_offline(to_pci_dev(dev->dev)))
1268                 return BLK_EH_RESET_TIMER;
1269
1270         /*
1271          * Reset immediately if the controller is failed
1272          */
1273         if (nvme_should_reset(dev, csts)) {
1274                 nvme_warn_reset(dev, csts);
1275                 nvme_dev_disable(dev, false);
1276                 nvme_reset_ctrl(&dev->ctrl);
1277                 return BLK_EH_DONE;
1278         }
1279
1280         /*
1281          * Did we miss an interrupt?
1282          */
1283         if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1284                 nvme_poll(req->mq_hctx);
1285         else
1286                 nvme_poll_irqdisable(nvmeq);
1287
1288         if (blk_mq_request_completed(req)) {
1289                 dev_warn(dev->ctrl.device,
1290                          "I/O %d QID %d timeout, completion polled\n",
1291                          req->tag, nvmeq->qid);
1292                 return BLK_EH_DONE;
1293         }
1294
1295         /*
1296          * Shutdown immediately if controller times out while starting. The
1297          * reset work will see the pci device disabled when it gets the forced
1298          * cancellation error. All outstanding requests are completed on
1299          * shutdown, so we return BLK_EH_DONE.
1300          */
1301         switch (dev->ctrl.state) {
1302         case NVME_CTRL_CONNECTING:
1303                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1304                 fallthrough;
1305         case NVME_CTRL_DELETING:
1306                 dev_warn_ratelimited(dev->ctrl.device,
1307                          "I/O %d QID %d timeout, disable controller\n",
1308                          req->tag, nvmeq->qid);
1309                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1310                 nvme_dev_disable(dev, true);
1311                 return BLK_EH_DONE;
1312         case NVME_CTRL_RESETTING:
1313                 return BLK_EH_RESET_TIMER;
1314         default:
1315                 break;
1316         }
1317
1318         /*
1319          * Shutdown the controller immediately and schedule a reset if the
1320          * command was already aborted once before and still hasn't been
1321          * returned to the driver, or if this is the admin queue.
1322          */
1323         if (!nvmeq->qid || iod->aborted) {
1324                 dev_warn(dev->ctrl.device,
1325                          "I/O %d QID %d timeout, reset controller\n",
1326                          req->tag, nvmeq->qid);
1327                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1328                 nvme_dev_disable(dev, false);
1329                 nvme_reset_ctrl(&dev->ctrl);
1330
1331                 return BLK_EH_DONE;
1332         }
1333
1334         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1335                 atomic_inc(&dev->ctrl.abort_limit);
1336                 return BLK_EH_RESET_TIMER;
1337         }
1338         iod->aborted = 1;
1339
1340         memset(&cmd, 0, sizeof(cmd));
1341         cmd.abort.opcode = nvme_admin_abort_cmd;
1342         cmd.abort.cid = req->tag;
1343         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1344
1345         dev_warn(nvmeq->dev->ctrl.device,
1346                 "I/O %d QID %d timeout, aborting\n",
1347                  req->tag, nvmeq->qid);
1348
1349         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1350                         BLK_MQ_REQ_NOWAIT);
1351         if (IS_ERR(abort_req)) {
1352                 atomic_inc(&dev->ctrl.abort_limit);
1353                 return BLK_EH_RESET_TIMER;
1354         }
1355
1356         abort_req->end_io_data = NULL;
1357         blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
1358
1359         /*
1360          * The aborted req will be completed on receiving the abort req.
1361          * We enable the timer again. If hit twice, it'll cause a device reset,
1362          * as the device then is in a faulty state.
1363          */
1364         return BLK_EH_RESET_TIMER;
1365 }
1366
1367 static void nvme_free_queue(struct nvme_queue *nvmeq)
1368 {
1369         dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1370                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1371         if (!nvmeq->sq_cmds)
1372                 return;
1373
1374         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1375                 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1376                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1377         } else {
1378                 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1379                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1380         }
1381 }
1382
1383 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1384 {
1385         int i;
1386
1387         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1388                 dev->ctrl.queue_count--;
1389                 nvme_free_queue(&dev->queues[i]);
1390         }
1391 }
1392
1393 /**
1394  * nvme_suspend_queue - put queue into suspended state
1395  * @nvmeq: queue to suspend
1396  */
1397 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1398 {
1399         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1400                 return 1;
1401
1402         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1403         mb();
1404
1405         nvmeq->dev->online_queues--;
1406         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1407                 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1408         if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1409                 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1410         return 0;
1411 }
1412
1413 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1414 {
1415         int i;
1416
1417         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1418                 nvme_suspend_queue(&dev->queues[i]);
1419 }
1420
1421 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1422 {
1423         struct nvme_queue *nvmeq = &dev->queues[0];
1424
1425         if (shutdown)
1426                 nvme_shutdown_ctrl(&dev->ctrl);
1427         else
1428                 nvme_disable_ctrl(&dev->ctrl);
1429
1430         nvme_poll_irqdisable(nvmeq);
1431 }
1432
1433 /*
1434  * Called only on a device that has been disabled and after all other threads
1435  * that can check this device's completion queues have synced, except
1436  * nvme_poll(). This is the last chance for the driver to see a natural
1437  * completion before nvme_cancel_request() terminates all incomplete requests.
1438  */
1439 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1440 {
1441         int i;
1442
1443         for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1444                 spin_lock(&dev->queues[i].cq_poll_lock);
1445                 nvme_process_cq(&dev->queues[i]);
1446                 spin_unlock(&dev->queues[i].cq_poll_lock);
1447         }
1448 }
1449
1450 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1451                                 int entry_size)
1452 {
1453         int q_depth = dev->q_depth;
1454         unsigned q_size_aligned = roundup(q_depth * entry_size,
1455                                           NVME_CTRL_PAGE_SIZE);
1456
1457         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1458                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1459
1460                 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1461                 q_depth = div_u64(mem_per_q, entry_size);
1462
1463                 /*
1464                  * Ensure the reduced q_depth is above some threshold where it
1465                  * would be better to map queues in system memory with the
1466                  * original depth
1467                  */
1468                 if (q_depth < 64)
1469                         return -ENOMEM;
1470         }
1471
1472         return q_depth;
1473 }
1474
1475 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1476                                 int qid)
1477 {
1478         struct pci_dev *pdev = to_pci_dev(dev->dev);
1479
1480         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1481                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1482                 if (nvmeq->sq_cmds) {
1483                         nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1484                                                         nvmeq->sq_cmds);
1485                         if (nvmeq->sq_dma_addr) {
1486                                 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1487                                 return 0;
1488                         }
1489
1490                         pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1491                 }
1492         }
1493
1494         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1495                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1496         if (!nvmeq->sq_cmds)
1497                 return -ENOMEM;
1498         return 0;
1499 }
1500
1501 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1502 {
1503         struct nvme_queue *nvmeq = &dev->queues[qid];
1504
1505         if (dev->ctrl.queue_count > qid)
1506                 return 0;
1507
1508         nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1509         nvmeq->q_depth = depth;
1510         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1511                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1512         if (!nvmeq->cqes)
1513                 goto free_nvmeq;
1514
1515         if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1516                 goto free_cqdma;
1517
1518         nvmeq->dev = dev;
1519         spin_lock_init(&nvmeq->sq_lock);
1520         spin_lock_init(&nvmeq->cq_poll_lock);
1521         nvmeq->cq_head = 0;
1522         nvmeq->cq_phase = 1;
1523         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1524         nvmeq->qid = qid;
1525         dev->ctrl.queue_count++;
1526
1527         return 0;
1528
1529  free_cqdma:
1530         dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1531                           nvmeq->cq_dma_addr);
1532  free_nvmeq:
1533         return -ENOMEM;
1534 }
1535
1536 static int queue_request_irq(struct nvme_queue *nvmeq)
1537 {
1538         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1539         int nr = nvmeq->dev->ctrl.instance;
1540
1541         if (use_threaded_interrupts) {
1542                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1543                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1544         } else {
1545                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1546                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1547         }
1548 }
1549
1550 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1551 {
1552         struct nvme_dev *dev = nvmeq->dev;
1553
1554         nvmeq->sq_tail = 0;
1555         nvmeq->last_sq_tail = 0;
1556         nvmeq->cq_head = 0;
1557         nvmeq->cq_phase = 1;
1558         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1559         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1560         nvme_dbbuf_init(dev, nvmeq, qid);
1561         dev->online_queues++;
1562         wmb(); /* ensure the first interrupt sees the initialization */
1563 }
1564
1565 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1566 {
1567         struct nvme_dev *dev = nvmeq->dev;
1568         int result;
1569         u16 vector = 0;
1570
1571         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1572
1573         /*
1574          * A queue's vector matches the queue identifier unless the controller
1575          * has only one vector available.
1576          */
1577         if (!polled)
1578                 vector = dev->num_vecs == 1 ? 0 : qid;
1579         else
1580                 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1581
1582         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1583         if (result)
1584                 return result;
1585
1586         result = adapter_alloc_sq(dev, qid, nvmeq);
1587         if (result < 0)
1588                 return result;
1589         if (result)
1590                 goto release_cq;
1591
1592         nvmeq->cq_vector = vector;
1593         nvme_init_queue(nvmeq, qid);
1594
1595         if (!polled) {
1596                 result = queue_request_irq(nvmeq);
1597                 if (result < 0)
1598                         goto release_sq;
1599         }
1600
1601         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1602         return result;
1603
1604 release_sq:
1605         dev->online_queues--;
1606         adapter_delete_sq(dev, qid);
1607 release_cq:
1608         adapter_delete_cq(dev, qid);
1609         return result;
1610 }
1611
1612 static const struct blk_mq_ops nvme_mq_admin_ops = {
1613         .queue_rq       = nvme_queue_rq,
1614         .complete       = nvme_pci_complete_rq,
1615         .init_hctx      = nvme_admin_init_hctx,
1616         .init_request   = nvme_init_request,
1617         .timeout        = nvme_timeout,
1618 };
1619
1620 static const struct blk_mq_ops nvme_mq_ops = {
1621         .queue_rq       = nvme_queue_rq,
1622         .complete       = nvme_pci_complete_rq,
1623         .commit_rqs     = nvme_commit_rqs,
1624         .init_hctx      = nvme_init_hctx,
1625         .init_request   = nvme_init_request,
1626         .map_queues     = nvme_pci_map_queues,
1627         .timeout        = nvme_timeout,
1628         .poll           = nvme_poll,
1629 };
1630
1631 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1632 {
1633         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1634                 /*
1635                  * If the controller was reset during removal, it's possible
1636                  * user requests may be waiting on a stopped queue. Start the
1637                  * queue to flush these to completion.
1638                  */
1639                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1640                 blk_cleanup_queue(dev->ctrl.admin_q);
1641                 blk_mq_free_tag_set(&dev->admin_tagset);
1642         }
1643 }
1644
1645 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1646 {
1647         if (!dev->ctrl.admin_q) {
1648                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1649                 dev->admin_tagset.nr_hw_queues = 1;
1650
1651                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1652                 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1653                 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1654                 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1655                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1656                 dev->admin_tagset.driver_data = dev;
1657
1658                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1659                         return -ENOMEM;
1660                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1661
1662                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1663                 if (IS_ERR(dev->ctrl.admin_q)) {
1664                         blk_mq_free_tag_set(&dev->admin_tagset);
1665                         return -ENOMEM;
1666                 }
1667                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1668                         nvme_dev_remove_admin(dev);
1669                         dev->ctrl.admin_q = NULL;
1670                         return -ENODEV;
1671                 }
1672         } else
1673                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1674
1675         return 0;
1676 }
1677
1678 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1679 {
1680         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1681 }
1682
1683 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1684 {
1685         struct pci_dev *pdev = to_pci_dev(dev->dev);
1686
1687         if (size <= dev->bar_mapped_size)
1688                 return 0;
1689         if (size > pci_resource_len(pdev, 0))
1690                 return -ENOMEM;
1691         if (dev->bar)
1692                 iounmap(dev->bar);
1693         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1694         if (!dev->bar) {
1695                 dev->bar_mapped_size = 0;
1696                 return -ENOMEM;
1697         }
1698         dev->bar_mapped_size = size;
1699         dev->dbs = dev->bar + NVME_REG_DBS;
1700
1701         return 0;
1702 }
1703
1704 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1705 {
1706         int result;
1707         u32 aqa;
1708         struct nvme_queue *nvmeq;
1709
1710         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1711         if (result < 0)
1712                 return result;
1713
1714         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1715                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1716
1717         if (dev->subsystem &&
1718             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1719                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1720
1721         result = nvme_disable_ctrl(&dev->ctrl);
1722         if (result < 0)
1723                 return result;
1724
1725         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1726         if (result)
1727                 return result;
1728
1729         dev->ctrl.numa_node = dev_to_node(dev->dev);
1730
1731         nvmeq = &dev->queues[0];
1732         aqa = nvmeq->q_depth - 1;
1733         aqa |= aqa << 16;
1734
1735         writel(aqa, dev->bar + NVME_REG_AQA);
1736         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1737         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1738
1739         result = nvme_enable_ctrl(&dev->ctrl);
1740         if (result)
1741                 return result;
1742
1743         nvmeq->cq_vector = 0;
1744         nvme_init_queue(nvmeq, 0);
1745         result = queue_request_irq(nvmeq);
1746         if (result) {
1747                 dev->online_queues--;
1748                 return result;
1749         }
1750
1751         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1752         return result;
1753 }
1754
1755 static int nvme_create_io_queues(struct nvme_dev *dev)
1756 {
1757         unsigned i, max, rw_queues;
1758         int ret = 0;
1759
1760         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1761                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1762                         ret = -ENOMEM;
1763                         break;
1764                 }
1765         }
1766
1767         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1768         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1769                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1770                                 dev->io_queues[HCTX_TYPE_READ];
1771         } else {
1772                 rw_queues = max;
1773         }
1774
1775         for (i = dev->online_queues; i <= max; i++) {
1776                 bool polled = i > rw_queues;
1777
1778                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1779                 if (ret)
1780                         break;
1781         }
1782
1783         /*
1784          * Ignore failing Create SQ/CQ commands, we can continue with less
1785          * than the desired amount of queues, and even a controller without
1786          * I/O queues can still be used to issue admin commands.  This might
1787          * be useful to upgrade a buggy firmware for example.
1788          */
1789         return ret >= 0 ? 0 : ret;
1790 }
1791
1792 static ssize_t nvme_cmb_show(struct device *dev,
1793                              struct device_attribute *attr,
1794                              char *buf)
1795 {
1796         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1797
1798         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1799                        ndev->cmbloc, ndev->cmbsz);
1800 }
1801 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1802
1803 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1804 {
1805         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1806
1807         return 1ULL << (12 + 4 * szu);
1808 }
1809
1810 static u32 nvme_cmb_size(struct nvme_dev *dev)
1811 {
1812         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1813 }
1814
1815 static void nvme_map_cmb(struct nvme_dev *dev)
1816 {
1817         u64 size, offset;
1818         resource_size_t bar_size;
1819         struct pci_dev *pdev = to_pci_dev(dev->dev);
1820         int bar;
1821
1822         if (dev->cmb_size)
1823                 return;
1824
1825         if (NVME_CAP_CMBS(dev->ctrl.cap))
1826                 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1827
1828         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1829         if (!dev->cmbsz)
1830                 return;
1831         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1832
1833         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1834         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1835         bar = NVME_CMB_BIR(dev->cmbloc);
1836         bar_size = pci_resource_len(pdev, bar);
1837
1838         if (offset > bar_size)
1839                 return;
1840
1841         /*
1842          * Tell the controller about the host side address mapping the CMB,
1843          * and enable CMB decoding for the NVMe 1.4+ scheme:
1844          */
1845         if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1846                 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1847                              (pci_bus_address(pdev, bar) + offset),
1848                              dev->bar + NVME_REG_CMBMSC);
1849         }
1850
1851         /*
1852          * Controllers may support a CMB size larger than their BAR,
1853          * for example, due to being behind a bridge. Reduce the CMB to
1854          * the reported size of the BAR
1855          */
1856         if (size > bar_size - offset)
1857                 size = bar_size - offset;
1858
1859         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1860                 dev_warn(dev->ctrl.device,
1861                          "failed to register the CMB\n");
1862                 return;
1863         }
1864
1865         dev->cmb_size = size;
1866         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1867
1868         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1869                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1870                 pci_p2pmem_publish(pdev, true);
1871
1872         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1873                                     &dev_attr_cmb.attr, NULL))
1874                 dev_warn(dev->ctrl.device,
1875                          "failed to add sysfs attribute for CMB\n");
1876 }
1877
1878 static inline void nvme_release_cmb(struct nvme_dev *dev)
1879 {
1880         if (dev->cmb_size) {
1881                 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1882                                              &dev_attr_cmb.attr, NULL);
1883                 dev->cmb_size = 0;
1884         }
1885 }
1886
1887 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1888 {
1889         u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1890         u64 dma_addr = dev->host_mem_descs_dma;
1891         struct nvme_command c;
1892         int ret;
1893
1894         memset(&c, 0, sizeof(c));
1895         c.features.opcode       = nvme_admin_set_features;
1896         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1897         c.features.dword11      = cpu_to_le32(bits);
1898         c.features.dword12      = cpu_to_le32(host_mem_size);
1899         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1900         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1901         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1902
1903         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1904         if (ret) {
1905                 dev_warn(dev->ctrl.device,
1906                          "failed to set host mem (err %d, flags %#x).\n",
1907                          ret, bits);
1908         }
1909         return ret;
1910 }
1911
1912 static void nvme_free_host_mem(struct nvme_dev *dev)
1913 {
1914         int i;
1915
1916         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1917                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1918                 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1919
1920                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1921                                le64_to_cpu(desc->addr),
1922                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1923         }
1924
1925         kfree(dev->host_mem_desc_bufs);
1926         dev->host_mem_desc_bufs = NULL;
1927         dma_free_coherent(dev->dev,
1928                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1929                         dev->host_mem_descs, dev->host_mem_descs_dma);
1930         dev->host_mem_descs = NULL;
1931         dev->nr_host_mem_descs = 0;
1932 }
1933
1934 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1935                 u32 chunk_size)
1936 {
1937         struct nvme_host_mem_buf_desc *descs;
1938         u32 max_entries, len;
1939         dma_addr_t descs_dma;
1940         int i = 0;
1941         void **bufs;
1942         u64 size, tmp;
1943
1944         tmp = (preferred + chunk_size - 1);
1945         do_div(tmp, chunk_size);
1946         max_entries = tmp;
1947
1948         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1949                 max_entries = dev->ctrl.hmmaxd;
1950
1951         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1952                                    &descs_dma, GFP_KERNEL);
1953         if (!descs)
1954                 goto out;
1955
1956         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1957         if (!bufs)
1958                 goto out_free_descs;
1959
1960         for (size = 0; size < preferred && i < max_entries; size += len) {
1961                 dma_addr_t dma_addr;
1962
1963                 len = min_t(u64, chunk_size, preferred - size);
1964                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1965                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1966                 if (!bufs[i])
1967                         break;
1968
1969                 descs[i].addr = cpu_to_le64(dma_addr);
1970                 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1971                 i++;
1972         }
1973
1974         if (!size)
1975                 goto out_free_bufs;
1976
1977         dev->nr_host_mem_descs = i;
1978         dev->host_mem_size = size;
1979         dev->host_mem_descs = descs;
1980         dev->host_mem_descs_dma = descs_dma;
1981         dev->host_mem_desc_bufs = bufs;
1982         return 0;
1983
1984 out_free_bufs:
1985         while (--i >= 0) {
1986                 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1987
1988                 dma_free_attrs(dev->dev, size, bufs[i],
1989                                le64_to_cpu(descs[i].addr),
1990                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1991         }
1992
1993         kfree(bufs);
1994 out_free_descs:
1995         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1996                         descs_dma);
1997 out:
1998         dev->host_mem_descs = NULL;
1999         return -ENOMEM;
2000 }
2001
2002 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2003 {
2004         u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2005         u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2006         u64 chunk_size;
2007
2008         /* start big and work our way down */
2009         for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2010                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2011                         if (!min || dev->host_mem_size >= min)
2012                                 return 0;
2013                         nvme_free_host_mem(dev);
2014                 }
2015         }
2016
2017         return -ENOMEM;
2018 }
2019
2020 static int nvme_setup_host_mem(struct nvme_dev *dev)
2021 {
2022         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2023         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2024         u64 min = (u64)dev->ctrl.hmmin * 4096;
2025         u32 enable_bits = NVME_HOST_MEM_ENABLE;
2026         int ret;
2027
2028         preferred = min(preferred, max);
2029         if (min > max) {
2030                 dev_warn(dev->ctrl.device,
2031                         "min host memory (%lld MiB) above limit (%d MiB).\n",
2032                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
2033                 nvme_free_host_mem(dev);
2034                 return 0;
2035         }
2036
2037         /*
2038          * If we already have a buffer allocated check if we can reuse it.
2039          */
2040         if (dev->host_mem_descs) {
2041                 if (dev->host_mem_size >= min)
2042                         enable_bits |= NVME_HOST_MEM_RETURN;
2043                 else
2044                         nvme_free_host_mem(dev);
2045         }
2046
2047         if (!dev->host_mem_descs) {
2048                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2049                         dev_warn(dev->ctrl.device,
2050                                 "failed to allocate host memory buffer.\n");
2051                         return 0; /* controller must work without HMB */
2052                 }
2053
2054                 dev_info(dev->ctrl.device,
2055                         "allocated %lld MiB host memory buffer.\n",
2056                         dev->host_mem_size >> ilog2(SZ_1M));
2057         }
2058
2059         ret = nvme_set_host_mem(dev, enable_bits);
2060         if (ret)
2061                 nvme_free_host_mem(dev);
2062         return ret;
2063 }
2064
2065 /*
2066  * nirqs is the number of interrupts available for write and read
2067  * queues. The core already reserved an interrupt for the admin queue.
2068  */
2069 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2070 {
2071         struct nvme_dev *dev = affd->priv;
2072         unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2073
2074         /*
2075          * If there is no interrupt available for queues, ensure that
2076          * the default queue is set to 1. The affinity set size is
2077          * also set to one, but the irq core ignores it for this case.
2078          *
2079          * If only one interrupt is available or 'write_queue' == 0, combine
2080          * write and read queues.
2081          *
2082          * If 'write_queues' > 0, ensure it leaves room for at least one read
2083          * queue.
2084          */
2085         if (!nrirqs) {
2086                 nrirqs = 1;
2087                 nr_read_queues = 0;
2088         } else if (nrirqs == 1 || !nr_write_queues) {
2089                 nr_read_queues = 0;
2090         } else if (nr_write_queues >= nrirqs) {
2091                 nr_read_queues = 1;
2092         } else {
2093                 nr_read_queues = nrirqs - nr_write_queues;
2094         }
2095
2096         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2097         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2098         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2099         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2100         affd->nr_sets = nr_read_queues ? 2 : 1;
2101 }
2102
2103 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2104 {
2105         struct pci_dev *pdev = to_pci_dev(dev->dev);
2106         struct irq_affinity affd = {
2107                 .pre_vectors    = 1,
2108                 .calc_sets      = nvme_calc_irq_sets,
2109                 .priv           = dev,
2110         };
2111         unsigned int irq_queues, poll_queues;
2112
2113         /*
2114          * Poll queues don't need interrupts, but we need at least one I/O queue
2115          * left over for non-polled I/O.
2116          */
2117         poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2118         dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2119
2120         /*
2121          * Initialize for the single interrupt case, will be updated in
2122          * nvme_calc_irq_sets().
2123          */
2124         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2125         dev->io_queues[HCTX_TYPE_READ] = 0;
2126
2127         /*
2128          * We need interrupts for the admin queue and each non-polled I/O queue,
2129          * but some Apple controllers require all queues to use the first
2130          * vector.
2131          */
2132         irq_queues = 1;
2133         if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2134                 irq_queues += (nr_io_queues - poll_queues);
2135         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2136                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2137 }
2138
2139 static void nvme_disable_io_queues(struct nvme_dev *dev)
2140 {
2141         if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2142                 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2143 }
2144
2145 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2146 {
2147         /*
2148          * If tags are shared with admin queue (Apple bug), then
2149          * make sure we only use one IO queue.
2150          */
2151         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2152                 return 1;
2153         return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2154 }
2155
2156 static int nvme_setup_io_queues(struct nvme_dev *dev)
2157 {
2158         struct nvme_queue *adminq = &dev->queues[0];
2159         struct pci_dev *pdev = to_pci_dev(dev->dev);
2160         unsigned int nr_io_queues;
2161         unsigned long size;
2162         int result;
2163
2164         /*
2165          * Sample the module parameters once at reset time so that we have
2166          * stable values to work with.
2167          */
2168         dev->nr_write_queues = write_queues;
2169         dev->nr_poll_queues = poll_queues;
2170
2171         nr_io_queues = dev->nr_allocated_queues - 1;
2172         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2173         if (result < 0)
2174                 return result;
2175
2176         if (nr_io_queues == 0)
2177                 return 0;
2178
2179         clear_bit(NVMEQ_ENABLED, &adminq->flags);
2180
2181         if (dev->cmb_use_sqes) {
2182                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2183                                 sizeof(struct nvme_command));
2184                 if (result > 0)
2185                         dev->q_depth = result;
2186                 else
2187                         dev->cmb_use_sqes = false;
2188         }
2189
2190         do {
2191                 size = db_bar_size(dev, nr_io_queues);
2192                 result = nvme_remap_bar(dev, size);
2193                 if (!result)
2194                         break;
2195                 if (!--nr_io_queues)
2196                         return -ENOMEM;
2197         } while (1);
2198         adminq->q_db = dev->dbs;
2199
2200  retry:
2201         /* Deregister the admin queue's interrupt */
2202         pci_free_irq(pdev, 0, adminq);
2203
2204         /*
2205          * If we enable msix early due to not intx, disable it again before
2206          * setting up the full range we need.
2207          */
2208         pci_free_irq_vectors(pdev);
2209
2210         result = nvme_setup_irqs(dev, nr_io_queues);
2211         if (result <= 0)
2212                 return -EIO;
2213
2214         dev->num_vecs = result;
2215         result = max(result - 1, 1);
2216         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2217
2218         /*
2219          * Should investigate if there's a performance win from allocating
2220          * more queues than interrupt vectors; it might allow the submission
2221          * path to scale better, even if the receive path is limited by the
2222          * number of interrupts.
2223          */
2224         result = queue_request_irq(adminq);
2225         if (result)
2226                 return result;
2227         set_bit(NVMEQ_ENABLED, &adminq->flags);
2228
2229         result = nvme_create_io_queues(dev);
2230         if (result || dev->online_queues < 2)
2231                 return result;
2232
2233         if (dev->online_queues - 1 < dev->max_qid) {
2234                 nr_io_queues = dev->online_queues - 1;
2235                 nvme_disable_io_queues(dev);
2236                 nvme_suspend_io_queues(dev);
2237                 goto retry;
2238         }
2239         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2240                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2241                                         dev->io_queues[HCTX_TYPE_READ],
2242                                         dev->io_queues[HCTX_TYPE_POLL]);
2243         return 0;
2244 }
2245
2246 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2247 {
2248         struct nvme_queue *nvmeq = req->end_io_data;
2249
2250         blk_mq_free_request(req);
2251         complete(&nvmeq->delete_done);
2252 }
2253
2254 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2255 {
2256         struct nvme_queue *nvmeq = req->end_io_data;
2257
2258         if (error)
2259                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2260
2261         nvme_del_queue_end(req, error);
2262 }
2263
2264 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2265 {
2266         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2267         struct request *req;
2268         struct nvme_command cmd;
2269
2270         memset(&cmd, 0, sizeof(cmd));
2271         cmd.delete_queue.opcode = opcode;
2272         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2273
2274         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
2275         if (IS_ERR(req))
2276                 return PTR_ERR(req);
2277
2278         req->end_io_data = nvmeq;
2279
2280         init_completion(&nvmeq->delete_done);
2281         blk_execute_rq_nowait(NULL, req, false,
2282                         opcode == nvme_admin_delete_cq ?
2283                                 nvme_del_cq_end : nvme_del_queue_end);
2284         return 0;
2285 }
2286
2287 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2288 {
2289         int nr_queues = dev->online_queues - 1, sent = 0;
2290         unsigned long timeout;
2291
2292  retry:
2293         timeout = NVME_ADMIN_TIMEOUT;
2294         while (nr_queues > 0) {
2295                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2296                         break;
2297                 nr_queues--;
2298                 sent++;
2299         }
2300         while (sent) {
2301                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2302
2303                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2304                                 timeout);
2305                 if (timeout == 0)
2306                         return false;
2307
2308                 sent--;
2309                 if (nr_queues)
2310                         goto retry;
2311         }
2312         return true;
2313 }
2314
2315 static void nvme_dev_add(struct nvme_dev *dev)
2316 {
2317         int ret;
2318
2319         if (!dev->ctrl.tagset) {
2320                 dev->tagset.ops = &nvme_mq_ops;
2321                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2322                 dev->tagset.nr_maps = 2; /* default + read */
2323                 if (dev->io_queues[HCTX_TYPE_POLL])
2324                         dev->tagset.nr_maps++;
2325                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2326                 dev->tagset.numa_node = dev->ctrl.numa_node;
2327                 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2328                                                 BLK_MQ_MAX_DEPTH) - 1;
2329                 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2330                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2331                 dev->tagset.driver_data = dev;
2332
2333                 /*
2334                  * Some Apple controllers requires tags to be unique
2335                  * across admin and IO queue, so reserve the first 32
2336                  * tags of the IO queue.
2337                  */
2338                 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2339                         dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2340
2341                 ret = blk_mq_alloc_tag_set(&dev->tagset);
2342                 if (ret) {
2343                         dev_warn(dev->ctrl.device,
2344                                 "IO queues tagset allocation failed %d\n", ret);
2345                         return;
2346                 }
2347                 dev->ctrl.tagset = &dev->tagset;
2348         } else {
2349                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2350
2351                 /* Free previously allocated queues that are no longer usable */
2352                 nvme_free_queues(dev, dev->online_queues);
2353         }
2354
2355         nvme_dbbuf_set(dev);
2356 }
2357
2358 static int nvme_pci_enable(struct nvme_dev *dev)
2359 {
2360         int result = -ENOMEM;
2361         struct pci_dev *pdev = to_pci_dev(dev->dev);
2362         int dma_address_bits = 64;
2363
2364         if (pci_enable_device_mem(pdev))
2365                 return result;
2366
2367         pci_set_master(pdev);
2368
2369         if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2370                 dma_address_bits = 48;
2371         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2372                 goto disable;
2373
2374         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2375                 result = -ENODEV;
2376                 goto disable;
2377         }
2378
2379         /*
2380          * Some devices and/or platforms don't advertise or work with INTx
2381          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2382          * adjust this later.
2383          */
2384         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2385         if (result < 0)
2386                 return result;
2387
2388         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2389
2390         dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2391                                 io_queue_depth);
2392         dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2393         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2394         dev->dbs = dev->bar + 4096;
2395
2396         /*
2397          * Some Apple controllers require a non-standard SQE size.
2398          * Interestingly they also seem to ignore the CC:IOSQES register
2399          * so we don't bother updating it here.
2400          */
2401         if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2402                 dev->io_sqes = 7;
2403         else
2404                 dev->io_sqes = NVME_NVM_IOSQES;
2405
2406         /*
2407          * Temporary fix for the Apple controller found in the MacBook8,1 and
2408          * some MacBook7,1 to avoid controller resets and data loss.
2409          */
2410         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2411                 dev->q_depth = 2;
2412                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2413                         "set queue depth=%u to work around controller resets\n",
2414                         dev->q_depth);
2415         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2416                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2417                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2418                 dev->q_depth = 64;
2419                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2420                         "set queue depth=%u\n", dev->q_depth);
2421         }
2422
2423         /*
2424          * Controllers with the shared tags quirk need the IO queue to be
2425          * big enough so that we get 32 tags for the admin queue
2426          */
2427         if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2428             (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2429                 dev->q_depth = NVME_AQ_DEPTH + 2;
2430                 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2431                          dev->q_depth);
2432         }
2433
2434
2435         nvme_map_cmb(dev);
2436
2437         pci_enable_pcie_error_reporting(pdev);
2438         pci_save_state(pdev);
2439         return 0;
2440
2441  disable:
2442         pci_disable_device(pdev);
2443         return result;
2444 }
2445
2446 static void nvme_dev_unmap(struct nvme_dev *dev)
2447 {
2448         if (dev->bar)
2449                 iounmap(dev->bar);
2450         pci_release_mem_regions(to_pci_dev(dev->dev));
2451 }
2452
2453 static void nvme_pci_disable(struct nvme_dev *dev)
2454 {
2455         struct pci_dev *pdev = to_pci_dev(dev->dev);
2456
2457         pci_free_irq_vectors(pdev);
2458
2459         if (pci_is_enabled(pdev)) {
2460                 pci_disable_pcie_error_reporting(pdev);
2461                 pci_disable_device(pdev);
2462         }
2463 }
2464
2465 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2466 {
2467         bool dead = true, freeze = false;
2468         struct pci_dev *pdev = to_pci_dev(dev->dev);
2469
2470         mutex_lock(&dev->shutdown_lock);
2471         if (pci_is_enabled(pdev)) {
2472                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2473
2474                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2475                     dev->ctrl.state == NVME_CTRL_RESETTING) {
2476                         freeze = true;
2477                         nvme_start_freeze(&dev->ctrl);
2478                 }
2479                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2480                         pdev->error_state  != pci_channel_io_normal);
2481         }
2482
2483         /*
2484          * Give the controller a chance to complete all entered requests if
2485          * doing a safe shutdown.
2486          */
2487         if (!dead && shutdown && freeze)
2488                 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2489
2490         nvme_stop_queues(&dev->ctrl);
2491
2492         if (!dead && dev->ctrl.queue_count > 0) {
2493                 nvme_disable_io_queues(dev);
2494                 nvme_disable_admin_queue(dev, shutdown);
2495         }
2496         nvme_suspend_io_queues(dev);
2497         nvme_suspend_queue(&dev->queues[0]);
2498         nvme_pci_disable(dev);
2499         nvme_reap_pending_cqes(dev);
2500
2501         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2502         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2503         blk_mq_tagset_wait_completed_request(&dev->tagset);
2504         blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2505
2506         /*
2507          * The driver will not be starting up queues again if shutting down so
2508          * must flush all entered requests to their failed completion to avoid
2509          * deadlocking blk-mq hot-cpu notifier.
2510          */
2511         if (shutdown) {
2512                 nvme_start_queues(&dev->ctrl);
2513                 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2514                         blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2515         }
2516         mutex_unlock(&dev->shutdown_lock);
2517 }
2518
2519 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2520 {
2521         if (!nvme_wait_reset(&dev->ctrl))
2522                 return -EBUSY;
2523         nvme_dev_disable(dev, shutdown);
2524         return 0;
2525 }
2526
2527 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2528 {
2529         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2530                                                 NVME_CTRL_PAGE_SIZE,
2531                                                 NVME_CTRL_PAGE_SIZE, 0);
2532         if (!dev->prp_page_pool)
2533                 return -ENOMEM;
2534
2535         /* Optimisation for I/Os between 4k and 128k */
2536         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2537                                                 256, 256, 0);
2538         if (!dev->prp_small_pool) {
2539                 dma_pool_destroy(dev->prp_page_pool);
2540                 return -ENOMEM;
2541         }
2542         return 0;
2543 }
2544
2545 static void nvme_release_prp_pools(struct nvme_dev *dev)
2546 {
2547         dma_pool_destroy(dev->prp_page_pool);
2548         dma_pool_destroy(dev->prp_small_pool);
2549 }
2550
2551 static void nvme_free_tagset(struct nvme_dev *dev)
2552 {
2553         if (dev->tagset.tags)
2554                 blk_mq_free_tag_set(&dev->tagset);
2555         dev->ctrl.tagset = NULL;
2556 }
2557
2558 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2559 {
2560         struct nvme_dev *dev = to_nvme_dev(ctrl);
2561
2562         nvme_dbbuf_dma_free(dev);
2563         nvme_free_tagset(dev);
2564         if (dev->ctrl.admin_q)
2565                 blk_put_queue(dev->ctrl.admin_q);
2566         free_opal_dev(dev->ctrl.opal_dev);
2567         mempool_destroy(dev->iod_mempool);
2568         put_device(dev->dev);
2569         kfree(dev->queues);
2570         kfree(dev);
2571 }
2572
2573 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2574 {
2575         /*
2576          * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2577          * may be holding this pci_dev's device lock.
2578          */
2579         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2580         nvme_get_ctrl(&dev->ctrl);
2581         nvme_dev_disable(dev, false);
2582         nvme_kill_queues(&dev->ctrl);
2583         if (!queue_work(nvme_wq, &dev->remove_work))
2584                 nvme_put_ctrl(&dev->ctrl);
2585 }
2586
2587 static void nvme_reset_work(struct work_struct *work)
2588 {
2589         struct nvme_dev *dev =
2590                 container_of(work, struct nvme_dev, ctrl.reset_work);
2591         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2592         int result;
2593
2594         if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2595                 result = -ENODEV;
2596                 goto out;
2597         }
2598
2599         /*
2600          * If we're called to reset a live controller first shut it down before
2601          * moving on.
2602          */
2603         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2604                 nvme_dev_disable(dev, false);
2605         nvme_sync_queues(&dev->ctrl);
2606
2607         mutex_lock(&dev->shutdown_lock);
2608         result = nvme_pci_enable(dev);
2609         if (result)
2610                 goto out_unlock;
2611
2612         result = nvme_pci_configure_admin_queue(dev);
2613         if (result)
2614                 goto out_unlock;
2615
2616         result = nvme_alloc_admin_tags(dev);
2617         if (result)
2618                 goto out_unlock;
2619
2620         /*
2621          * Limit the max command size to prevent iod->sg allocations going
2622          * over a single page.
2623          */
2624         dev->ctrl.max_hw_sectors = min_t(u32,
2625                 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2626         dev->ctrl.max_segments = NVME_MAX_SEGS;
2627
2628         /*
2629          * Don't limit the IOMMU merged segment size.
2630          */
2631         dma_set_max_seg_size(dev->dev, 0xffffffff);
2632         dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2633
2634         mutex_unlock(&dev->shutdown_lock);
2635
2636         /*
2637          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2638          * initializing procedure here.
2639          */
2640         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2641                 dev_warn(dev->ctrl.device,
2642                         "failed to mark controller CONNECTING\n");
2643                 result = -EBUSY;
2644                 goto out;
2645         }
2646
2647         /*
2648          * We do not support an SGL for metadata (yet), so we are limited to a
2649          * single integrity segment for the separate metadata pointer.
2650          */
2651         dev->ctrl.max_integrity_segments = 1;
2652
2653         result = nvme_init_ctrl_finish(&dev->ctrl);
2654         if (result)
2655                 goto out;
2656
2657         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2658                 if (!dev->ctrl.opal_dev)
2659                         dev->ctrl.opal_dev =
2660                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2661                 else if (was_suspend)
2662                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2663         } else {
2664                 free_opal_dev(dev->ctrl.opal_dev);
2665                 dev->ctrl.opal_dev = NULL;
2666         }
2667
2668         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2669                 result = nvme_dbbuf_dma_alloc(dev);
2670                 if (result)
2671                         dev_warn(dev->dev,
2672                                  "unable to allocate dma for dbbuf\n");
2673         }
2674
2675         if (dev->ctrl.hmpre) {
2676                 result = nvme_setup_host_mem(dev);
2677                 if (result < 0)
2678                         goto out;
2679         }
2680
2681         result = nvme_setup_io_queues(dev);
2682         if (result)
2683                 goto out;
2684
2685         /*
2686          * Keep the controller around but remove all namespaces if we don't have
2687          * any working I/O queue.
2688          */
2689         if (dev->online_queues < 2) {
2690                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2691                 nvme_kill_queues(&dev->ctrl);
2692                 nvme_remove_namespaces(&dev->ctrl);
2693                 nvme_free_tagset(dev);
2694         } else {
2695                 nvme_start_queues(&dev->ctrl);
2696                 nvme_wait_freeze(&dev->ctrl);
2697                 nvme_dev_add(dev);
2698                 nvme_unfreeze(&dev->ctrl);
2699         }
2700
2701         /*
2702          * If only admin queue live, keep it to do further investigation or
2703          * recovery.
2704          */
2705         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2706                 dev_warn(dev->ctrl.device,
2707                         "failed to mark controller live state\n");
2708                 result = -ENODEV;
2709                 goto out;
2710         }
2711
2712         nvme_start_ctrl(&dev->ctrl);
2713         return;
2714
2715  out_unlock:
2716         mutex_unlock(&dev->shutdown_lock);
2717  out:
2718         if (result)
2719                 dev_warn(dev->ctrl.device,
2720                          "Removing after probe failure status: %d\n", result);
2721         nvme_remove_dead_ctrl(dev);
2722 }
2723
2724 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2725 {
2726         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2727         struct pci_dev *pdev = to_pci_dev(dev->dev);
2728
2729         if (pci_get_drvdata(pdev))
2730                 device_release_driver(&pdev->dev);
2731         nvme_put_ctrl(&dev->ctrl);
2732 }
2733
2734 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2735 {
2736         *val = readl(to_nvme_dev(ctrl)->bar + off);
2737         return 0;
2738 }
2739
2740 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2741 {
2742         writel(val, to_nvme_dev(ctrl)->bar + off);
2743         return 0;
2744 }
2745
2746 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2747 {
2748         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2749         return 0;
2750 }
2751
2752 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2753 {
2754         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2755
2756         return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2757 }
2758
2759 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2760         .name                   = "pcie",
2761         .module                 = THIS_MODULE,
2762         .flags                  = NVME_F_METADATA_SUPPORTED |
2763                                   NVME_F_PCI_P2PDMA,
2764         .reg_read32             = nvme_pci_reg_read32,
2765         .reg_write32            = nvme_pci_reg_write32,
2766         .reg_read64             = nvme_pci_reg_read64,
2767         .free_ctrl              = nvme_pci_free_ctrl,
2768         .submit_async_event     = nvme_pci_submit_async_event,
2769         .get_address            = nvme_pci_get_address,
2770 };
2771
2772 static int nvme_dev_map(struct nvme_dev *dev)
2773 {
2774         struct pci_dev *pdev = to_pci_dev(dev->dev);
2775
2776         if (pci_request_mem_regions(pdev, "nvme"))
2777                 return -ENODEV;
2778
2779         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2780                 goto release;
2781
2782         return 0;
2783   release:
2784         pci_release_mem_regions(pdev);
2785         return -ENODEV;
2786 }
2787
2788 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2789 {
2790         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2791                 /*
2792                  * Several Samsung devices seem to drop off the PCIe bus
2793                  * randomly when APST is on and uses the deepest sleep state.
2794                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2795                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2796                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2797                  * laptops.
2798                  */
2799                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2800                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2801                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2802                         return NVME_QUIRK_NO_DEEPEST_PS;
2803         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2804                 /*
2805                  * Samsung SSD 960 EVO drops off the PCIe bus after system
2806                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2807                  * within few minutes after bootup on a Coffee Lake board -
2808                  * ASUS PRIME Z370-A
2809                  */
2810                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2811                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2812                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2813                         return NVME_QUIRK_NO_APST;
2814         } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2815                     pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2816                    (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2817                 /*
2818                  * Forcing to use host managed nvme power settings for
2819                  * lowest idle power with quick resume latency on
2820                  * Samsung and Toshiba SSDs based on suspend behavior
2821                  * on Coffee Lake board for LENOVO C640
2822                  */
2823                 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2824                      dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2825                         return NVME_QUIRK_SIMPLE_SUSPEND;
2826         }
2827
2828         return 0;
2829 }
2830
2831 #ifdef CONFIG_ACPI
2832 static bool nvme_acpi_storage_d3(struct pci_dev *dev)
2833 {
2834         struct acpi_device *adev;
2835         struct pci_dev *root;
2836         acpi_handle handle;
2837         acpi_status status;
2838         u8 val;
2839
2840         /*
2841          * Look for _DSD property specifying that the storage device on the port
2842          * must use D3 to support deep platform power savings during
2843          * suspend-to-idle.
2844          */
2845         root = pcie_find_root_port(dev);
2846         if (!root)
2847                 return false;
2848
2849         adev = ACPI_COMPANION(&root->dev);
2850         if (!adev)
2851                 return false;
2852
2853         /*
2854          * The property is defined in the PXSX device for South complex ports
2855          * and in the PEGP device for North complex ports.
2856          */
2857         status = acpi_get_handle(adev->handle, "PXSX", &handle);
2858         if (ACPI_FAILURE(status)) {
2859                 status = acpi_get_handle(adev->handle, "PEGP", &handle);
2860                 if (ACPI_FAILURE(status))
2861                         return false;
2862         }
2863
2864         if (acpi_bus_get_device(handle, &adev))
2865                 return false;
2866
2867         if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
2868                         &val))
2869                 return false;
2870         return val == 1;
2871 }
2872 #else
2873 static inline bool nvme_acpi_storage_d3(struct pci_dev *dev)
2874 {
2875         return false;
2876 }
2877 #endif /* CONFIG_ACPI */
2878
2879 static void nvme_async_probe(void *data, async_cookie_t cookie)
2880 {
2881         struct nvme_dev *dev = data;
2882
2883         flush_work(&dev->ctrl.reset_work);
2884         flush_work(&dev->ctrl.scan_work);
2885         nvme_put_ctrl(&dev->ctrl);
2886 }
2887
2888 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2889 {
2890         int node, result = -ENOMEM;
2891         struct nvme_dev *dev;
2892         unsigned long quirks = id->driver_data;
2893         size_t alloc_size;
2894
2895         node = dev_to_node(&pdev->dev);
2896         if (node == NUMA_NO_NODE)
2897                 set_dev_node(&pdev->dev, first_memory_node);
2898
2899         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2900         if (!dev)
2901                 return -ENOMEM;
2902
2903         dev->nr_write_queues = write_queues;
2904         dev->nr_poll_queues = poll_queues;
2905         dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2906         dev->queues = kcalloc_node(dev->nr_allocated_queues,
2907                         sizeof(struct nvme_queue), GFP_KERNEL, node);
2908         if (!dev->queues)
2909                 goto free;
2910
2911         dev->dev = get_device(&pdev->dev);
2912         pci_set_drvdata(pdev, dev);
2913
2914         result = nvme_dev_map(dev);
2915         if (result)
2916                 goto put_pci;
2917
2918         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2919         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2920         mutex_init(&dev->shutdown_lock);
2921
2922         result = nvme_setup_prp_pools(dev);
2923         if (result)
2924                 goto unmap;
2925
2926         quirks |= check_vendor_combination_bug(pdev);
2927
2928         if (!noacpi && nvme_acpi_storage_d3(pdev)) {
2929                 /*
2930                  * Some systems use a bios work around to ask for D3 on
2931                  * platforms that support kernel managed suspend.
2932                  */
2933                 dev_info(&pdev->dev,
2934                          "platform quirk: setting simple suspend\n");
2935                 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2936         }
2937
2938         /*
2939          * Double check that our mempool alloc size will cover the biggest
2940          * command we support.
2941          */
2942         alloc_size = nvme_pci_iod_alloc_size();
2943         WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2944
2945         dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2946                                                 mempool_kfree,
2947                                                 (void *) alloc_size,
2948                                                 GFP_KERNEL, node);
2949         if (!dev->iod_mempool) {
2950                 result = -ENOMEM;
2951                 goto release_pools;
2952         }
2953
2954         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2955                         quirks);
2956         if (result)
2957                 goto release_mempool;
2958
2959         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2960
2961         nvme_reset_ctrl(&dev->ctrl);
2962         async_schedule(nvme_async_probe, dev);
2963
2964         return 0;
2965
2966  release_mempool:
2967         mempool_destroy(dev->iod_mempool);
2968  release_pools:
2969         nvme_release_prp_pools(dev);
2970  unmap:
2971         nvme_dev_unmap(dev);
2972  put_pci:
2973         put_device(dev->dev);
2974  free:
2975         kfree(dev->queues);
2976         kfree(dev);
2977         return result;
2978 }
2979
2980 static void nvme_reset_prepare(struct pci_dev *pdev)
2981 {
2982         struct nvme_dev *dev = pci_get_drvdata(pdev);
2983
2984         /*
2985          * We don't need to check the return value from waiting for the reset
2986          * state as pci_dev device lock is held, making it impossible to race
2987          * with ->remove().
2988          */
2989         nvme_disable_prepare_reset(dev, false);
2990         nvme_sync_queues(&dev->ctrl);
2991 }
2992
2993 static void nvme_reset_done(struct pci_dev *pdev)
2994 {
2995         struct nvme_dev *dev = pci_get_drvdata(pdev);
2996
2997         if (!nvme_try_sched_reset(&dev->ctrl))
2998                 flush_work(&dev->ctrl.reset_work);
2999 }
3000
3001 static void nvme_shutdown(struct pci_dev *pdev)
3002 {
3003         struct nvme_dev *dev = pci_get_drvdata(pdev);
3004
3005         nvme_disable_prepare_reset(dev, true);
3006 }
3007
3008 /*
3009  * The driver's remove may be called on a device in a partially initialized
3010  * state. This function must not have any dependencies on the device state in
3011  * order to proceed.
3012  */
3013 static void nvme_remove(struct pci_dev *pdev)
3014 {
3015         struct nvme_dev *dev = pci_get_drvdata(pdev);
3016
3017         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3018         pci_set_drvdata(pdev, NULL);
3019
3020         if (!pci_device_is_present(pdev)) {
3021                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3022                 nvme_dev_disable(dev, true);
3023                 nvme_dev_remove_admin(dev);
3024         }
3025
3026         flush_work(&dev->ctrl.reset_work);
3027         nvme_stop_ctrl(&dev->ctrl);
3028         nvme_remove_namespaces(&dev->ctrl);
3029         nvme_dev_disable(dev, true);
3030         nvme_release_cmb(dev);
3031         nvme_free_host_mem(dev);
3032         nvme_dev_remove_admin(dev);
3033         nvme_free_queues(dev, 0);
3034         nvme_release_prp_pools(dev);
3035         nvme_dev_unmap(dev);
3036         nvme_uninit_ctrl(&dev->ctrl);
3037 }
3038
3039 #ifdef CONFIG_PM_SLEEP
3040 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3041 {
3042         return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3043 }
3044
3045 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3046 {
3047         return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3048 }
3049
3050 static int nvme_resume(struct device *dev)
3051 {
3052         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3053         struct nvme_ctrl *ctrl = &ndev->ctrl;
3054
3055         if (ndev->last_ps == U32_MAX ||
3056             nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3057                 return nvme_try_sched_reset(&ndev->ctrl);
3058         return 0;
3059 }
3060
3061 static int nvme_suspend(struct device *dev)
3062 {
3063         struct pci_dev *pdev = to_pci_dev(dev);
3064         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3065         struct nvme_ctrl *ctrl = &ndev->ctrl;
3066         int ret = -EBUSY;
3067
3068         ndev->last_ps = U32_MAX;
3069
3070         /*
3071          * The platform does not remove power for a kernel managed suspend so
3072          * use host managed nvme power settings for lowest idle power if
3073          * possible. This should have quicker resume latency than a full device
3074          * shutdown.  But if the firmware is involved after the suspend or the
3075          * device does not support any non-default power states, shut down the
3076          * device fully.
3077          *
3078          * If ASPM is not enabled for the device, shut down the device and allow
3079          * the PCI bus layer to put it into D3 in order to take the PCIe link
3080          * down, so as to allow the platform to achieve its minimum low-power
3081          * state (which may not be possible if the link is up).
3082          *
3083          * If a host memory buffer is enabled, shut down the device as the NVMe
3084          * specification allows the device to access the host memory buffer in
3085          * host DRAM from all power states, but hosts will fail access to DRAM
3086          * during S3.
3087          */
3088         if (pm_suspend_via_firmware() || !ctrl->npss ||
3089             !pcie_aspm_enabled(pdev) ||
3090             ndev->nr_host_mem_descs ||
3091             (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3092                 return nvme_disable_prepare_reset(ndev, true);
3093
3094         nvme_start_freeze(ctrl);
3095         nvme_wait_freeze(ctrl);
3096         nvme_sync_queues(ctrl);
3097
3098         if (ctrl->state != NVME_CTRL_LIVE)
3099                 goto unfreeze;
3100
3101         ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3102         if (ret < 0)
3103                 goto unfreeze;
3104
3105         /*
3106          * A saved state prevents pci pm from generically controlling the
3107          * device's power. If we're using protocol specific settings, we don't
3108          * want pci interfering.
3109          */
3110         pci_save_state(pdev);
3111
3112         ret = nvme_set_power_state(ctrl, ctrl->npss);
3113         if (ret < 0)
3114                 goto unfreeze;
3115
3116         if (ret) {
3117                 /* discard the saved state */
3118                 pci_load_saved_state(pdev, NULL);
3119
3120                 /*
3121                  * Clearing npss forces a controller reset on resume. The
3122                  * correct value will be rediscovered then.
3123                  */
3124                 ret = nvme_disable_prepare_reset(ndev, true);
3125                 ctrl->npss = 0;
3126         }
3127 unfreeze:
3128         nvme_unfreeze(ctrl);
3129         return ret;
3130 }
3131
3132 static int nvme_simple_suspend(struct device *dev)
3133 {
3134         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3135
3136         return nvme_disable_prepare_reset(ndev, true);
3137 }
3138
3139 static int nvme_simple_resume(struct device *dev)
3140 {
3141         struct pci_dev *pdev = to_pci_dev(dev);
3142         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3143
3144         return nvme_try_sched_reset(&ndev->ctrl);
3145 }
3146
3147 static const struct dev_pm_ops nvme_dev_pm_ops = {
3148         .suspend        = nvme_suspend,
3149         .resume         = nvme_resume,
3150         .freeze         = nvme_simple_suspend,
3151         .thaw           = nvme_simple_resume,
3152         .poweroff       = nvme_simple_suspend,
3153         .restore        = nvme_simple_resume,
3154 };
3155 #endif /* CONFIG_PM_SLEEP */
3156
3157 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3158                                                 pci_channel_state_t state)
3159 {
3160         struct nvme_dev *dev = pci_get_drvdata(pdev);
3161
3162         /*
3163          * A frozen channel requires a reset. When detected, this method will
3164          * shutdown the controller to quiesce. The controller will be restarted
3165          * after the slot reset through driver's slot_reset callback.
3166          */
3167         switch (state) {
3168         case pci_channel_io_normal:
3169                 return PCI_ERS_RESULT_CAN_RECOVER;
3170         case pci_channel_io_frozen:
3171                 dev_warn(dev->ctrl.device,
3172                         "frozen state error detected, reset controller\n");
3173                 nvme_dev_disable(dev, false);
3174                 return PCI_ERS_RESULT_NEED_RESET;
3175         case pci_channel_io_perm_failure:
3176                 dev_warn(dev->ctrl.device,
3177                         "failure state error detected, request disconnect\n");
3178                 return PCI_ERS_RESULT_DISCONNECT;
3179         }
3180         return PCI_ERS_RESULT_NEED_RESET;
3181 }
3182
3183 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3184 {
3185         struct nvme_dev *dev = pci_get_drvdata(pdev);
3186
3187         dev_info(dev->ctrl.device, "restart after slot reset\n");
3188         pci_restore_state(pdev);
3189         nvme_reset_ctrl(&dev->ctrl);
3190         return PCI_ERS_RESULT_RECOVERED;
3191 }
3192
3193 static void nvme_error_resume(struct pci_dev *pdev)
3194 {
3195         struct nvme_dev *dev = pci_get_drvdata(pdev);
3196
3197         flush_work(&dev->ctrl.reset_work);
3198 }
3199
3200 static const struct pci_error_handlers nvme_err_handler = {
3201         .error_detected = nvme_error_detected,
3202         .slot_reset     = nvme_slot_reset,
3203         .resume         = nvme_error_resume,
3204         .reset_prepare  = nvme_reset_prepare,
3205         .reset_done     = nvme_reset_done,
3206 };
3207
3208 static const struct pci_device_id nvme_id_table[] = {
3209         { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3210                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3211                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3212         { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3213                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3214                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3215         { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3216                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3217                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3218         { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3219                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3220                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3221         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3222                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3223                                 NVME_QUIRK_MEDIUM_PRIO_SQ |
3224                                 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3225                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3226         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3227                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3228         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3229                 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3230                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3231         { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3232                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3233         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3234                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3235                                 NVME_QUIRK_NO_NS_DESC_LIST, },
3236         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3237                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3238         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3239                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3240         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3241                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3242         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3243                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3244         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3245                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3246                                 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3247                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3248         { PCI_DEVICE(0x1987, 0x5016),   /* Phison E16 */
3249                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3250         { PCI_DEVICE(0x1b4b, 0x1092),   /* Lexar 256 GB SSD */
3251                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3252                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3253         { PCI_DEVICE(0x1d1d, 0x1f1f),   /* LighNVM qemu device */
3254                 .driver_data = NVME_QUIRK_LIGHTNVM, },
3255         { PCI_DEVICE(0x1d1d, 0x2807),   /* CNEX WL */
3256                 .driver_data = NVME_QUIRK_LIGHTNVM, },
3257         { PCI_DEVICE(0x1d1d, 0x2601),   /* CNEX Granby */
3258                 .driver_data = NVME_QUIRK_LIGHTNVM, },
3259         { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3260                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3261         { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3262                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3263                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3264         { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3265                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3266         { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3267                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3268         { PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
3269                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3270         { PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3271                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3272         { PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3273                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3274         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3275                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3276         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3277                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3278         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3279                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3280         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3281                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3282         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3283                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3284         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3285                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3286         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3287                 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3288         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3289         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3290                 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3291                                 NVME_QUIRK_128_BYTES_SQES |
3292                                 NVME_QUIRK_SHARED_TAGS },
3293
3294         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3295         { 0, }
3296 };
3297 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3298
3299 static struct pci_driver nvme_driver = {
3300         .name           = "nvme",
3301         .id_table       = nvme_id_table,
3302         .probe          = nvme_probe,
3303         .remove         = nvme_remove,
3304         .shutdown       = nvme_shutdown,
3305 #ifdef CONFIG_PM_SLEEP
3306         .driver         = {
3307                 .pm     = &nvme_dev_pm_ops,
3308         },
3309 #endif
3310         .sriov_configure = pci_sriov_configure_simple,
3311         .err_handler    = &nvme_err_handler,
3312 };
3313
3314 static int __init nvme_init(void)
3315 {
3316         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3317         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3318         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3319         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3320
3321         return pci_register_driver(&nvme_driver);
3322 }
3323
3324 static void __exit nvme_exit(void)
3325 {
3326         pci_unregister_driver(&nvme_driver);
3327         flush_workqueue(nvme_wq);
3328 }
3329
3330 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3331 MODULE_LICENSE("GPL");
3332 MODULE_VERSION("1.0");
3333 module_init(nvme_init);
3334 module_exit(nvme_exit);