1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
7 #include <linux/acpi.h>
9 #include <linux/async.h>
10 #include <linux/blkdev.h>
11 #include <linux/blk-mq.h>
12 #include <linux/blk-mq-pci.h>
13 #include <linux/blk-integrity.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
18 #include <linux/memremap.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
22 #include <linux/once.h>
23 #include <linux/pci.h>
24 #include <linux/suspend.h>
25 #include <linux/t10-pi.h>
26 #include <linux/types.h>
27 #include <linux/io-64-nonatomic-lo-hi.h>
28 #include <linux/io-64-nonatomic-hi-lo.h>
29 #include <linux/sed-opal.h>
30 #include <linux/pci-p2pdma.h>
35 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
36 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
38 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
41 * These can be higher, but we need to ensure that any command doesn't
42 * require an sg allocation that needs more than a page of data.
44 #define NVME_MAX_KB_SZ 4096
45 #define NVME_MAX_SEGS 127
47 static int use_threaded_interrupts;
48 module_param(use_threaded_interrupts, int, 0444);
50 static bool use_cmb_sqes = true;
51 module_param(use_cmb_sqes, bool, 0444);
52 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54 static unsigned int max_host_mem_size_mb = 128;
55 module_param(max_host_mem_size_mb, uint, 0444);
56 MODULE_PARM_DESC(max_host_mem_size_mb,
57 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
59 static unsigned int sgl_threshold = SZ_32K;
60 module_param(sgl_threshold, uint, 0644);
61 MODULE_PARM_DESC(sgl_threshold,
62 "Use SGLs when average request segment size is larger or equal to "
63 "this size. Use 0 to disable SGLs.");
65 #define NVME_PCI_MIN_QUEUE_SIZE 2
66 #define NVME_PCI_MAX_QUEUE_SIZE 4095
67 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68 static const struct kernel_param_ops io_queue_depth_ops = {
69 .set = io_queue_depth_set,
70 .get = param_get_uint,
73 static unsigned int io_queue_depth = 1024;
74 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
75 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
77 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
82 ret = kstrtouint(val, 10, &n);
83 if (ret != 0 || n > num_possible_cpus())
85 return param_set_uint(val, kp);
88 static const struct kernel_param_ops io_queue_count_ops = {
89 .set = io_queue_count_set,
90 .get = param_get_uint,
93 static unsigned int write_queues;
94 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
95 MODULE_PARM_DESC(write_queues,
96 "Number of queues to use for writes. If not set, reads and writes "
97 "will share a queue set.");
99 static unsigned int poll_queues;
100 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
101 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
104 module_param(noacpi, bool, 0444);
105 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
110 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
111 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
114 * Represents an NVM Express device. Each nvme_dev is a PCI function.
117 struct nvme_queue *queues;
118 struct blk_mq_tag_set tagset;
119 struct blk_mq_tag_set admin_tagset;
122 struct dma_pool *prp_page_pool;
123 struct dma_pool *prp_small_pool;
124 unsigned online_queues;
126 unsigned io_queues[HCTX_MAX_TYPES];
127 unsigned int num_vecs;
132 unsigned long bar_mapped_size;
133 struct work_struct remove_work;
134 struct mutex shutdown_lock;
140 struct nvme_ctrl ctrl;
144 mempool_t *iod_mempool;
146 /* shadow doorbell buffer support: */
148 dma_addr_t dbbuf_dbs_dma_addr;
150 dma_addr_t dbbuf_eis_dma_addr;
152 /* host memory buffer support: */
154 u32 nr_host_mem_descs;
155 dma_addr_t host_mem_descs_dma;
156 struct nvme_host_mem_buf_desc *host_mem_descs;
157 void **host_mem_desc_bufs;
158 unsigned int nr_allocated_queues;
159 unsigned int nr_write_queues;
160 unsigned int nr_poll_queues;
165 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
167 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
168 NVME_PCI_MAX_QUEUE_SIZE);
171 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
173 return qid * 2 * stride;
176 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
178 return (qid * 2 + 1) * stride;
181 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
183 return container_of(ctrl, struct nvme_dev, ctrl);
187 * An NVM Express queue. Each device has at least two (one for admin
188 * commands and one for I/O commands).
191 struct nvme_dev *dev;
194 /* only used for poll queues: */
195 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
196 struct nvme_completion *cqes;
197 dma_addr_t sq_dma_addr;
198 dma_addr_t cq_dma_addr;
209 #define NVMEQ_ENABLED 0
210 #define NVMEQ_SQ_CMB 1
211 #define NVMEQ_DELETE_ERROR 2
212 #define NVMEQ_POLLED 3
217 struct completion delete_done;
221 * The nvme_iod describes the data in an I/O.
223 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
224 * to the actual struct scatterlist.
227 struct nvme_request req;
228 struct nvme_command cmd;
231 s8 nr_allocations; /* PRP list pool allocations. 0 means small
233 unsigned int dma_len; /* length of single DMA segment mapping */
234 dma_addr_t first_dma;
239 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
241 return dev->nr_allocated_queues * 8 * dev->db_stride;
244 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
246 unsigned int mem_size = nvme_dbbuf_size(dev);
248 if (dev->dbbuf_dbs) {
250 * Clear the dbbuf memory so the driver doesn't observe stale
251 * values from the previous instantiation.
253 memset(dev->dbbuf_dbs, 0, mem_size);
254 memset(dev->dbbuf_eis, 0, mem_size);
258 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
259 &dev->dbbuf_dbs_dma_addr,
263 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
264 &dev->dbbuf_eis_dma_addr,
266 if (!dev->dbbuf_eis) {
267 dma_free_coherent(dev->dev, mem_size,
268 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
269 dev->dbbuf_dbs = NULL;
276 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
278 unsigned int mem_size = nvme_dbbuf_size(dev);
280 if (dev->dbbuf_dbs) {
281 dma_free_coherent(dev->dev, mem_size,
282 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
283 dev->dbbuf_dbs = NULL;
285 if (dev->dbbuf_eis) {
286 dma_free_coherent(dev->dev, mem_size,
287 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
288 dev->dbbuf_eis = NULL;
292 static void nvme_dbbuf_init(struct nvme_dev *dev,
293 struct nvme_queue *nvmeq, int qid)
295 if (!dev->dbbuf_dbs || !qid)
298 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
299 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
300 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
301 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
304 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
309 nvmeq->dbbuf_sq_db = NULL;
310 nvmeq->dbbuf_cq_db = NULL;
311 nvmeq->dbbuf_sq_ei = NULL;
312 nvmeq->dbbuf_cq_ei = NULL;
315 static void nvme_dbbuf_set(struct nvme_dev *dev)
317 struct nvme_command c = { };
323 c.dbbuf.opcode = nvme_admin_dbbuf;
324 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
325 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
327 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
328 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
329 /* Free memory and continue on */
330 nvme_dbbuf_dma_free(dev);
332 for (i = 1; i <= dev->online_queues; i++)
333 nvme_dbbuf_free(&dev->queues[i]);
337 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
339 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
342 /* Update dbbuf and return true if an MMIO is required */
343 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
344 volatile u32 *dbbuf_ei)
350 * Ensure that the queue is written before updating
351 * the doorbell in memory
355 old_value = *dbbuf_db;
359 * Ensure that the doorbell is updated before reading the event
360 * index from memory. The controller needs to provide similar
361 * ordering to ensure the envent index is updated before reading
366 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
374 * Will slightly overestimate the number of pages needed. This is OK
375 * as it only leads to a small amount of wasted memory for the lifetime of
378 static int nvme_pci_npages_prp(void)
380 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
381 NVME_CTRL_PAGE_SIZE);
382 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
386 * Calculates the number of pages needed for the SGL segments. For example a 4k
387 * page can accommodate 256 SGL descriptors.
389 static int nvme_pci_npages_sgl(void)
391 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
395 static size_t nvme_pci_iod_alloc_size(void)
397 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
399 return sizeof(__le64 *) * npages +
400 sizeof(struct scatterlist) * NVME_MAX_SEGS;
403 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
404 unsigned int hctx_idx)
406 struct nvme_dev *dev = data;
407 struct nvme_queue *nvmeq = &dev->queues[0];
409 WARN_ON(hctx_idx != 0);
410 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
412 hctx->driver_data = nvmeq;
416 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
417 unsigned int hctx_idx)
419 struct nvme_dev *dev = data;
420 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
422 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
423 hctx->driver_data = nvmeq;
427 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
428 struct request *req, unsigned int hctx_idx,
429 unsigned int numa_node)
431 struct nvme_dev *dev = set->driver_data;
432 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
434 nvme_req(req)->ctrl = &dev->ctrl;
435 nvme_req(req)->cmd = &iod->cmd;
439 static int queue_irq_offset(struct nvme_dev *dev)
441 /* if we have more than 1 vec, admin queue offsets us by 1 */
442 if (dev->num_vecs > 1)
448 static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
450 struct nvme_dev *dev = set->driver_data;
453 offset = queue_irq_offset(dev);
454 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
455 struct blk_mq_queue_map *map = &set->map[i];
457 map->nr_queues = dev->io_queues[i];
458 if (!map->nr_queues) {
459 BUG_ON(i == HCTX_TYPE_DEFAULT);
464 * The poll queue(s) doesn't have an IRQ (and hence IRQ
465 * affinity), so use the regular blk-mq cpu mapping
467 map->queue_offset = qoff;
468 if (i != HCTX_TYPE_POLL && offset)
469 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
471 blk_mq_map_queues(map);
472 qoff += map->nr_queues;
473 offset += map->nr_queues;
478 * Write sq tail if we are asked to, or if the next command would wrap.
480 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
483 u16 next_tail = nvmeq->sq_tail + 1;
485 if (next_tail == nvmeq->q_depth)
487 if (next_tail != nvmeq->last_sq_tail)
491 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
492 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
493 writel(nvmeq->sq_tail, nvmeq->q_db);
494 nvmeq->last_sq_tail = nvmeq->sq_tail;
497 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
498 struct nvme_command *cmd)
500 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
501 absolute_pointer(cmd), sizeof(*cmd));
502 if (++nvmeq->sq_tail == nvmeq->q_depth)
506 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
508 struct nvme_queue *nvmeq = hctx->driver_data;
510 spin_lock(&nvmeq->sq_lock);
511 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
512 nvme_write_sq_db(nvmeq, true);
513 spin_unlock(&nvmeq->sq_lock);
516 static void **nvme_pci_iod_list(struct request *req)
518 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
519 return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req));
522 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
524 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
525 int nseg = blk_rq_nr_phys_segments(req);
526 unsigned int avg_seg_size;
528 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
530 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
534 if (!sgl_threshold || avg_seg_size < sgl_threshold)
539 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
541 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
542 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
543 dma_addr_t dma_addr = iod->first_dma;
546 for (i = 0; i < iod->nr_allocations; i++) {
547 __le64 *prp_list = nvme_pci_iod_list(req)[i];
548 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
550 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
551 dma_addr = next_dma_addr;
555 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
557 const int last_sg = SGES_PER_PAGE - 1;
558 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
559 dma_addr_t dma_addr = iod->first_dma;
562 for (i = 0; i < iod->nr_allocations; i++) {
563 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
564 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
566 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
567 dma_addr = next_dma_addr;
571 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
573 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
576 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
581 WARN_ON_ONCE(!iod->sgt.nents);
583 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
585 if (iod->nr_allocations == 0)
586 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
588 else if (iod->use_sgl)
589 nvme_free_sgls(dev, req);
591 nvme_free_prps(dev, req);
592 mempool_free(iod->sgt.sgl, dev->iod_mempool);
595 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
598 struct scatterlist *sg;
600 for_each_sg(sgl, sg, nents, i) {
601 dma_addr_t phys = sg_phys(sg);
602 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
603 "dma_address:%pad dma_length:%d\n",
604 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
609 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
610 struct request *req, struct nvme_rw_command *cmnd)
612 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
613 struct dma_pool *pool;
614 int length = blk_rq_payload_bytes(req);
615 struct scatterlist *sg = iod->sgt.sgl;
616 int dma_len = sg_dma_len(sg);
617 u64 dma_addr = sg_dma_address(sg);
618 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
620 void **list = nvme_pci_iod_list(req);
624 length -= (NVME_CTRL_PAGE_SIZE - offset);
630 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
632 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
635 dma_addr = sg_dma_address(sg);
636 dma_len = sg_dma_len(sg);
639 if (length <= NVME_CTRL_PAGE_SIZE) {
640 iod->first_dma = dma_addr;
644 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
645 if (nprps <= (256 / 8)) {
646 pool = dev->prp_small_pool;
647 iod->nr_allocations = 0;
649 pool = dev->prp_page_pool;
650 iod->nr_allocations = 1;
653 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
655 iod->nr_allocations = -1;
656 return BLK_STS_RESOURCE;
659 iod->first_dma = prp_dma;
662 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
663 __le64 *old_prp_list = prp_list;
664 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
667 list[iod->nr_allocations++] = prp_list;
668 prp_list[0] = old_prp_list[i - 1];
669 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
672 prp_list[i++] = cpu_to_le64(dma_addr);
673 dma_len -= NVME_CTRL_PAGE_SIZE;
674 dma_addr += NVME_CTRL_PAGE_SIZE;
675 length -= NVME_CTRL_PAGE_SIZE;
680 if (unlikely(dma_len < 0))
683 dma_addr = sg_dma_address(sg);
684 dma_len = sg_dma_len(sg);
687 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
688 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
691 nvme_free_prps(dev, req);
692 return BLK_STS_RESOURCE;
694 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
695 "Invalid SGL for payload:%d nents:%d\n",
696 blk_rq_payload_bytes(req), iod->sgt.nents);
697 return BLK_STS_IOERR;
700 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
701 struct scatterlist *sg)
703 sge->addr = cpu_to_le64(sg_dma_address(sg));
704 sge->length = cpu_to_le32(sg_dma_len(sg));
705 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
708 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
709 dma_addr_t dma_addr, int entries)
711 sge->addr = cpu_to_le64(dma_addr);
712 if (entries < SGES_PER_PAGE) {
713 sge->length = cpu_to_le32(entries * sizeof(*sge));
714 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
716 sge->length = cpu_to_le32(PAGE_SIZE);
717 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
721 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
722 struct request *req, struct nvme_rw_command *cmd)
724 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
725 struct dma_pool *pool;
726 struct nvme_sgl_desc *sg_list;
727 struct scatterlist *sg = iod->sgt.sgl;
728 unsigned int entries = iod->sgt.nents;
732 /* setting the transfer type as SGL */
733 cmd->flags = NVME_CMD_SGL_METABUF;
736 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
740 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
741 pool = dev->prp_small_pool;
742 iod->nr_allocations = 0;
744 pool = dev->prp_page_pool;
745 iod->nr_allocations = 1;
748 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
750 iod->nr_allocations = -1;
751 return BLK_STS_RESOURCE;
754 nvme_pci_iod_list(req)[0] = sg_list;
755 iod->first_dma = sgl_dma;
757 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
760 if (i == SGES_PER_PAGE) {
761 struct nvme_sgl_desc *old_sg_desc = sg_list;
762 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
764 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
769 nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list;
770 sg_list[i++] = *link;
771 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
774 nvme_pci_sgl_set_data(&sg_list[i++], sg);
776 } while (--entries > 0);
780 nvme_free_sgls(dev, req);
781 return BLK_STS_RESOURCE;
784 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
785 struct request *req, struct nvme_rw_command *cmnd,
788 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
789 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
790 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
792 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
793 if (dma_mapping_error(dev->dev, iod->first_dma))
794 return BLK_STS_RESOURCE;
795 iod->dma_len = bv->bv_len;
797 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
798 if (bv->bv_len > first_prp_len)
799 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
803 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
804 struct request *req, struct nvme_rw_command *cmnd,
807 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
809 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
810 if (dma_mapping_error(dev->dev, iod->first_dma))
811 return BLK_STS_RESOURCE;
812 iod->dma_len = bv->bv_len;
814 cmnd->flags = NVME_CMD_SGL_METABUF;
815 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
816 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
817 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
821 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
822 struct nvme_command *cmnd)
824 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
825 blk_status_t ret = BLK_STS_RESOURCE;
828 if (blk_rq_nr_phys_segments(req) == 1) {
829 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
830 struct bio_vec bv = req_bvec(req);
832 if (!is_pci_p2pdma_page(bv.bv_page)) {
833 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
834 return nvme_setup_prp_simple(dev, req,
837 if (nvmeq->qid && sgl_threshold &&
838 nvme_ctrl_sgl_supported(&dev->ctrl))
839 return nvme_setup_sgl_simple(dev, req,
845 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
847 return BLK_STS_RESOURCE;
848 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
849 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
850 if (!iod->sgt.orig_nents)
853 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
856 if (rc == -EREMOTEIO)
857 ret = BLK_STS_TARGET;
861 iod->use_sgl = nvme_pci_use_sgls(dev, req);
863 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
865 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
866 if (ret != BLK_STS_OK)
871 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
873 mempool_free(iod->sgt.sgl, dev->iod_mempool);
877 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
878 struct nvme_command *cmnd)
880 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
882 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
884 if (dma_mapping_error(dev->dev, iod->meta_dma))
885 return BLK_STS_IOERR;
886 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
890 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
892 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
895 iod->aborted = false;
896 iod->nr_allocations = -1;
899 ret = nvme_setup_cmd(req->q->queuedata, req);
903 if (blk_rq_nr_phys_segments(req)) {
904 ret = nvme_map_data(dev, req, &iod->cmd);
909 if (blk_integrity_rq(req)) {
910 ret = nvme_map_metadata(dev, req, &iod->cmd);
915 blk_mq_start_request(req);
918 nvme_unmap_data(dev, req);
920 nvme_cleanup_cmd(req);
925 * NOTE: ns is NULL when called on the admin queue.
927 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
928 const struct blk_mq_queue_data *bd)
930 struct nvme_queue *nvmeq = hctx->driver_data;
931 struct nvme_dev *dev = nvmeq->dev;
932 struct request *req = bd->rq;
933 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
937 * We should not need to do this, but we're still using this to
938 * ensure we can drain requests on a dying queue.
940 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
941 return BLK_STS_IOERR;
943 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
944 return nvme_fail_nonready_command(&dev->ctrl, req);
946 ret = nvme_prep_rq(dev, req);
949 spin_lock(&nvmeq->sq_lock);
950 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
951 nvme_write_sq_db(nvmeq, bd->last);
952 spin_unlock(&nvmeq->sq_lock);
956 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
958 spin_lock(&nvmeq->sq_lock);
959 while (!rq_list_empty(*rqlist)) {
960 struct request *req = rq_list_pop(rqlist);
961 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
963 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
965 nvme_write_sq_db(nvmeq, true);
966 spin_unlock(&nvmeq->sq_lock);
969 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
972 * We should not need to do this, but we're still using this to
973 * ensure we can drain requests on a dying queue.
975 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
977 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
980 req->mq_hctx->tags->rqs[req->tag] = req;
981 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
984 static void nvme_queue_rqs(struct request **rqlist)
986 struct request *req, *next, *prev = NULL;
987 struct request *requeue_list = NULL;
989 rq_list_for_each_safe(rqlist, req, next) {
990 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
992 if (!nvme_prep_rq_batch(nvmeq, req)) {
993 /* detach 'req' and add to remainder list */
994 rq_list_move(rqlist, &requeue_list, req, prev);
1001 if (!next || req->mq_hctx != next->mq_hctx) {
1002 /* detach rest of list, and submit */
1003 req->rq_next = NULL;
1004 nvme_submit_cmds(nvmeq, rqlist);
1011 *rqlist = requeue_list;
1014 static __always_inline void nvme_pci_unmap_rq(struct request *req)
1016 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1017 struct nvme_dev *dev = nvmeq->dev;
1019 if (blk_integrity_rq(req)) {
1020 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1022 dma_unmap_page(dev->dev, iod->meta_dma,
1023 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
1026 if (blk_rq_nr_phys_segments(req))
1027 nvme_unmap_data(dev, req);
1030 static void nvme_pci_complete_rq(struct request *req)
1032 nvme_pci_unmap_rq(req);
1033 nvme_complete_rq(req);
1036 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1038 nvme_complete_batch(iob, nvme_pci_unmap_rq);
1041 /* We read the CQE phase first to check if the rest of the entry is valid */
1042 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
1044 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1046 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
1049 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
1051 u16 head = nvmeq->cq_head;
1053 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1054 nvmeq->dbbuf_cq_ei))
1055 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1058 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1061 return nvmeq->dev->admin_tagset.tags[0];
1062 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1065 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1066 struct io_comp_batch *iob, u16 idx)
1068 struct nvme_completion *cqe = &nvmeq->cqes[idx];
1069 __u16 command_id = READ_ONCE(cqe->command_id);
1070 struct request *req;
1073 * AEN requests are special as they don't time out and can
1074 * survive any kind of queue freeze and often don't respond to
1075 * aborts. We don't even bother to allocate a struct request
1076 * for them but rather special case them here.
1078 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1079 nvme_complete_async_event(&nvmeq->dev->ctrl,
1080 cqe->status, &cqe->result);
1084 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1085 if (unlikely(!req)) {
1086 dev_warn(nvmeq->dev->ctrl.device,
1087 "invalid id %d completed on queue %d\n",
1088 command_id, le16_to_cpu(cqe->sq_id));
1092 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1093 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1094 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1095 nvme_pci_complete_batch))
1096 nvme_pci_complete_rq(req);
1099 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1101 u32 tmp = nvmeq->cq_head + 1;
1103 if (tmp == nvmeq->q_depth) {
1105 nvmeq->cq_phase ^= 1;
1107 nvmeq->cq_head = tmp;
1111 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1112 struct io_comp_batch *iob)
1116 while (nvme_cqe_pending(nvmeq)) {
1119 * load-load control dependency between phase and the rest of
1120 * the cqe requires a full read memory barrier
1123 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1124 nvme_update_cq_head(nvmeq);
1128 nvme_ring_cq_doorbell(nvmeq);
1132 static irqreturn_t nvme_irq(int irq, void *data)
1134 struct nvme_queue *nvmeq = data;
1135 DEFINE_IO_COMP_BATCH(iob);
1137 if (nvme_poll_cq(nvmeq, &iob)) {
1138 if (!rq_list_empty(iob.req_list))
1139 nvme_pci_complete_batch(&iob);
1145 static irqreturn_t nvme_irq_check(int irq, void *data)
1147 struct nvme_queue *nvmeq = data;
1149 if (nvme_cqe_pending(nvmeq))
1150 return IRQ_WAKE_THREAD;
1155 * Poll for completions for any interrupt driven queue
1156 * Can be called from any context.
1158 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1160 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1162 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1164 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1165 nvme_poll_cq(nvmeq, NULL);
1166 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1169 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1171 struct nvme_queue *nvmeq = hctx->driver_data;
1174 if (!nvme_cqe_pending(nvmeq))
1177 spin_lock(&nvmeq->cq_poll_lock);
1178 found = nvme_poll_cq(nvmeq, iob);
1179 spin_unlock(&nvmeq->cq_poll_lock);
1184 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1186 struct nvme_dev *dev = to_nvme_dev(ctrl);
1187 struct nvme_queue *nvmeq = &dev->queues[0];
1188 struct nvme_command c = { };
1190 c.common.opcode = nvme_admin_async_event;
1191 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1193 spin_lock(&nvmeq->sq_lock);
1194 nvme_sq_copy_cmd(nvmeq, &c);
1195 nvme_write_sq_db(nvmeq, true);
1196 spin_unlock(&nvmeq->sq_lock);
1199 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1201 struct nvme_command c = { };
1203 c.delete_queue.opcode = opcode;
1204 c.delete_queue.qid = cpu_to_le16(id);
1206 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1209 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1210 struct nvme_queue *nvmeq, s16 vector)
1212 struct nvme_command c = { };
1213 int flags = NVME_QUEUE_PHYS_CONTIG;
1215 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1216 flags |= NVME_CQ_IRQ_ENABLED;
1219 * Note: we (ab)use the fact that the prp fields survive if no data
1220 * is attached to the request.
1222 c.create_cq.opcode = nvme_admin_create_cq;
1223 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1224 c.create_cq.cqid = cpu_to_le16(qid);
1225 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1226 c.create_cq.cq_flags = cpu_to_le16(flags);
1227 c.create_cq.irq_vector = cpu_to_le16(vector);
1229 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1232 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1233 struct nvme_queue *nvmeq)
1235 struct nvme_ctrl *ctrl = &dev->ctrl;
1236 struct nvme_command c = { };
1237 int flags = NVME_QUEUE_PHYS_CONTIG;
1240 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1241 * set. Since URGENT priority is zeroes, it makes all queues
1244 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1245 flags |= NVME_SQ_PRIO_MEDIUM;
1248 * Note: we (ab)use the fact that the prp fields survive if no data
1249 * is attached to the request.
1251 c.create_sq.opcode = nvme_admin_create_sq;
1252 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1253 c.create_sq.sqid = cpu_to_le16(qid);
1254 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1255 c.create_sq.sq_flags = cpu_to_le16(flags);
1256 c.create_sq.cqid = cpu_to_le16(qid);
1258 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1261 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1263 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1266 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1268 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1271 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
1273 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1275 dev_warn(nvmeq->dev->ctrl.device,
1276 "Abort status: 0x%x", nvme_req(req)->status);
1277 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1278 blk_mq_free_request(req);
1279 return RQ_END_IO_NONE;
1282 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1284 /* If true, indicates loss of adapter communication, possibly by a
1285 * NVMe Subsystem reset.
1287 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1289 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1290 switch (dev->ctrl.state) {
1291 case NVME_CTRL_RESETTING:
1292 case NVME_CTRL_CONNECTING:
1298 /* We shouldn't reset unless the controller is on fatal error state
1299 * _or_ if we lost the communication with it.
1301 if (!(csts & NVME_CSTS_CFS) && !nssro)
1307 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1309 /* Read a config register to help see what died. */
1313 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1315 if (result == PCIBIOS_SUCCESSFUL)
1316 dev_warn(dev->ctrl.device,
1317 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1320 dev_warn(dev->ctrl.device,
1321 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1327 dev_warn(dev->ctrl.device,
1328 "Does your device have a faulty power saving mode enabled?\n");
1329 dev_warn(dev->ctrl.device,
1330 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
1333 static enum blk_eh_timer_return nvme_timeout(struct request *req)
1335 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1336 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1337 struct nvme_dev *dev = nvmeq->dev;
1338 struct request *abort_req;
1339 struct nvme_command cmd = { };
1340 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1342 /* If PCI error recovery process is happening, we cannot reset or
1343 * the recovery mechanism will surely fail.
1346 if (pci_channel_offline(to_pci_dev(dev->dev)))
1347 return BLK_EH_RESET_TIMER;
1350 * Reset immediately if the controller is failed
1352 if (nvme_should_reset(dev, csts)) {
1353 nvme_warn_reset(dev, csts);
1354 nvme_dev_disable(dev, false);
1355 nvme_reset_ctrl(&dev->ctrl);
1360 * Did we miss an interrupt?
1362 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1363 nvme_poll(req->mq_hctx, NULL);
1365 nvme_poll_irqdisable(nvmeq);
1367 if (blk_mq_request_completed(req)) {
1368 dev_warn(dev->ctrl.device,
1369 "I/O %d QID %d timeout, completion polled\n",
1370 req->tag, nvmeq->qid);
1375 * Shutdown immediately if controller times out while starting. The
1376 * reset work will see the pci device disabled when it gets the forced
1377 * cancellation error. All outstanding requests are completed on
1378 * shutdown, so we return BLK_EH_DONE.
1380 switch (dev->ctrl.state) {
1381 case NVME_CTRL_CONNECTING:
1382 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1384 case NVME_CTRL_DELETING:
1385 dev_warn_ratelimited(dev->ctrl.device,
1386 "I/O %d QID %d timeout, disable controller\n",
1387 req->tag, nvmeq->qid);
1388 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1389 nvme_dev_disable(dev, true);
1391 case NVME_CTRL_RESETTING:
1392 return BLK_EH_RESET_TIMER;
1398 * Shutdown the controller immediately and schedule a reset if the
1399 * command was already aborted once before and still hasn't been
1400 * returned to the driver, or if this is the admin queue.
1402 if (!nvmeq->qid || iod->aborted) {
1403 dev_warn(dev->ctrl.device,
1404 "I/O %d QID %d timeout, reset controller\n",
1405 req->tag, nvmeq->qid);
1406 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1407 nvme_dev_disable(dev, false);
1408 nvme_reset_ctrl(&dev->ctrl);
1413 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1414 atomic_inc(&dev->ctrl.abort_limit);
1415 return BLK_EH_RESET_TIMER;
1417 iod->aborted = true;
1419 cmd.abort.opcode = nvme_admin_abort_cmd;
1420 cmd.abort.cid = nvme_cid(req);
1421 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1423 dev_warn(nvmeq->dev->ctrl.device,
1424 "I/O %d (%s) QID %d timeout, aborting\n",
1426 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1429 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1431 if (IS_ERR(abort_req)) {
1432 atomic_inc(&dev->ctrl.abort_limit);
1433 return BLK_EH_RESET_TIMER;
1435 nvme_init_request(abort_req, &cmd);
1437 abort_req->end_io = abort_endio;
1438 abort_req->end_io_data = NULL;
1439 abort_req->rq_flags |= RQF_QUIET;
1440 blk_execute_rq_nowait(abort_req, false);
1443 * The aborted req will be completed on receiving the abort req.
1444 * We enable the timer again. If hit twice, it'll cause a device reset,
1445 * as the device then is in a faulty state.
1447 return BLK_EH_RESET_TIMER;
1450 static void nvme_free_queue(struct nvme_queue *nvmeq)
1452 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1453 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1454 if (!nvmeq->sq_cmds)
1457 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1458 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1459 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1461 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1462 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1466 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1470 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1471 dev->ctrl.queue_count--;
1472 nvme_free_queue(&dev->queues[i]);
1477 * nvme_suspend_queue - put queue into suspended state
1478 * @nvmeq: queue to suspend
1480 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1482 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1485 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1488 nvmeq->dev->online_queues--;
1489 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1490 nvme_stop_admin_queue(&nvmeq->dev->ctrl);
1491 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1492 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1496 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1500 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1501 nvme_suspend_queue(&dev->queues[i]);
1504 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1506 struct nvme_queue *nvmeq = &dev->queues[0];
1509 nvme_shutdown_ctrl(&dev->ctrl);
1511 nvme_disable_ctrl(&dev->ctrl);
1513 nvme_poll_irqdisable(nvmeq);
1517 * Called only on a device that has been disabled and after all other threads
1518 * that can check this device's completion queues have synced, except
1519 * nvme_poll(). This is the last chance for the driver to see a natural
1520 * completion before nvme_cancel_request() terminates all incomplete requests.
1522 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1526 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1527 spin_lock(&dev->queues[i].cq_poll_lock);
1528 nvme_poll_cq(&dev->queues[i], NULL);
1529 spin_unlock(&dev->queues[i].cq_poll_lock);
1533 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1536 int q_depth = dev->q_depth;
1537 unsigned q_size_aligned = roundup(q_depth * entry_size,
1538 NVME_CTRL_PAGE_SIZE);
1540 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1541 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1543 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1544 q_depth = div_u64(mem_per_q, entry_size);
1547 * Ensure the reduced q_depth is above some threshold where it
1548 * would be better to map queues in system memory with the
1558 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1561 struct pci_dev *pdev = to_pci_dev(dev->dev);
1563 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1564 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1565 if (nvmeq->sq_cmds) {
1566 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1568 if (nvmeq->sq_dma_addr) {
1569 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1573 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1577 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1578 &nvmeq->sq_dma_addr, GFP_KERNEL);
1579 if (!nvmeq->sq_cmds)
1584 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1586 struct nvme_queue *nvmeq = &dev->queues[qid];
1588 if (dev->ctrl.queue_count > qid)
1591 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1592 nvmeq->q_depth = depth;
1593 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1594 &nvmeq->cq_dma_addr, GFP_KERNEL);
1598 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1602 spin_lock_init(&nvmeq->sq_lock);
1603 spin_lock_init(&nvmeq->cq_poll_lock);
1605 nvmeq->cq_phase = 1;
1606 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1608 dev->ctrl.queue_count++;
1613 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1614 nvmeq->cq_dma_addr);
1619 static int queue_request_irq(struct nvme_queue *nvmeq)
1621 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1622 int nr = nvmeq->dev->ctrl.instance;
1624 if (use_threaded_interrupts) {
1625 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1626 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1628 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1629 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1633 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1635 struct nvme_dev *dev = nvmeq->dev;
1638 nvmeq->last_sq_tail = 0;
1640 nvmeq->cq_phase = 1;
1641 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1642 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1643 nvme_dbbuf_init(dev, nvmeq, qid);
1644 dev->online_queues++;
1645 wmb(); /* ensure the first interrupt sees the initialization */
1649 * Try getting shutdown_lock while setting up IO queues.
1651 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1654 * Give up if the lock is being held by nvme_dev_disable.
1656 if (!mutex_trylock(&dev->shutdown_lock))
1660 * Controller is in wrong state, fail early.
1662 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1663 mutex_unlock(&dev->shutdown_lock);
1670 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1672 struct nvme_dev *dev = nvmeq->dev;
1676 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1679 * A queue's vector matches the queue identifier unless the controller
1680 * has only one vector available.
1683 vector = dev->num_vecs == 1 ? 0 : qid;
1685 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1687 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1691 result = adapter_alloc_sq(dev, qid, nvmeq);
1697 nvmeq->cq_vector = vector;
1699 result = nvme_setup_io_queues_trylock(dev);
1702 nvme_init_queue(nvmeq, qid);
1704 result = queue_request_irq(nvmeq);
1709 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1710 mutex_unlock(&dev->shutdown_lock);
1714 dev->online_queues--;
1715 mutex_unlock(&dev->shutdown_lock);
1716 adapter_delete_sq(dev, qid);
1718 adapter_delete_cq(dev, qid);
1722 static const struct blk_mq_ops nvme_mq_admin_ops = {
1723 .queue_rq = nvme_queue_rq,
1724 .complete = nvme_pci_complete_rq,
1725 .init_hctx = nvme_admin_init_hctx,
1726 .init_request = nvme_pci_init_request,
1727 .timeout = nvme_timeout,
1730 static const struct blk_mq_ops nvme_mq_ops = {
1731 .queue_rq = nvme_queue_rq,
1732 .queue_rqs = nvme_queue_rqs,
1733 .complete = nvme_pci_complete_rq,
1734 .commit_rqs = nvme_commit_rqs,
1735 .init_hctx = nvme_init_hctx,
1736 .init_request = nvme_pci_init_request,
1737 .map_queues = nvme_pci_map_queues,
1738 .timeout = nvme_timeout,
1742 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1744 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1746 * If the controller was reset during removal, it's possible
1747 * user requests may be waiting on a stopped queue. Start the
1748 * queue to flush these to completion.
1750 nvme_start_admin_queue(&dev->ctrl);
1751 blk_mq_destroy_queue(dev->ctrl.admin_q);
1752 blk_mq_free_tag_set(&dev->admin_tagset);
1756 static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev)
1758 struct blk_mq_tag_set *set = &dev->admin_tagset;
1760 set->ops = &nvme_mq_admin_ops;
1761 set->nr_hw_queues = 1;
1763 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1764 set->timeout = NVME_ADMIN_TIMEOUT;
1765 set->numa_node = dev->ctrl.numa_node;
1766 set->cmd_size = sizeof(struct nvme_iod);
1767 set->flags = BLK_MQ_F_NO_SCHED;
1768 set->driver_data = dev;
1770 if (blk_mq_alloc_tag_set(set))
1772 dev->ctrl.admin_tagset = set;
1774 dev->ctrl.admin_q = blk_mq_init_queue(set);
1775 if (IS_ERR(dev->ctrl.admin_q)) {
1776 blk_mq_free_tag_set(set);
1777 dev->ctrl.admin_q = NULL;
1780 if (!blk_get_queue(dev->ctrl.admin_q)) {
1781 nvme_dev_remove_admin(dev);
1782 dev->ctrl.admin_q = NULL;
1788 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1790 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1793 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1795 struct pci_dev *pdev = to_pci_dev(dev->dev);
1797 if (size <= dev->bar_mapped_size)
1799 if (size > pci_resource_len(pdev, 0))
1803 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1805 dev->bar_mapped_size = 0;
1808 dev->bar_mapped_size = size;
1809 dev->dbs = dev->bar + NVME_REG_DBS;
1814 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1818 struct nvme_queue *nvmeq;
1820 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1824 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1825 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1827 if (dev->subsystem &&
1828 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1829 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1831 result = nvme_disable_ctrl(&dev->ctrl);
1835 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1839 dev->ctrl.numa_node = dev_to_node(dev->dev);
1841 nvmeq = &dev->queues[0];
1842 aqa = nvmeq->q_depth - 1;
1845 writel(aqa, dev->bar + NVME_REG_AQA);
1846 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1847 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1849 result = nvme_enable_ctrl(&dev->ctrl);
1853 nvmeq->cq_vector = 0;
1854 nvme_init_queue(nvmeq, 0);
1855 result = queue_request_irq(nvmeq);
1857 dev->online_queues--;
1861 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1865 static int nvme_create_io_queues(struct nvme_dev *dev)
1867 unsigned i, max, rw_queues;
1870 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1871 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1877 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1878 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1879 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1880 dev->io_queues[HCTX_TYPE_READ];
1885 for (i = dev->online_queues; i <= max; i++) {
1886 bool polled = i > rw_queues;
1888 ret = nvme_create_queue(&dev->queues[i], i, polled);
1894 * Ignore failing Create SQ/CQ commands, we can continue with less
1895 * than the desired amount of queues, and even a controller without
1896 * I/O queues can still be used to issue admin commands. This might
1897 * be useful to upgrade a buggy firmware for example.
1899 return ret >= 0 ? 0 : ret;
1902 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1904 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1906 return 1ULL << (12 + 4 * szu);
1909 static u32 nvme_cmb_size(struct nvme_dev *dev)
1911 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1914 static void nvme_map_cmb(struct nvme_dev *dev)
1917 resource_size_t bar_size;
1918 struct pci_dev *pdev = to_pci_dev(dev->dev);
1924 if (NVME_CAP_CMBS(dev->ctrl.cap))
1925 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1927 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1930 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1932 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1933 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1934 bar = NVME_CMB_BIR(dev->cmbloc);
1935 bar_size = pci_resource_len(pdev, bar);
1937 if (offset > bar_size)
1941 * Tell the controller about the host side address mapping the CMB,
1942 * and enable CMB decoding for the NVMe 1.4+ scheme:
1944 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1945 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1946 (pci_bus_address(pdev, bar) + offset),
1947 dev->bar + NVME_REG_CMBMSC);
1951 * Controllers may support a CMB size larger than their BAR,
1952 * for example, due to being behind a bridge. Reduce the CMB to
1953 * the reported size of the BAR
1955 if (size > bar_size - offset)
1956 size = bar_size - offset;
1958 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1959 dev_warn(dev->ctrl.device,
1960 "failed to register the CMB\n");
1964 dev->cmb_size = size;
1965 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1967 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1968 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1969 pci_p2pmem_publish(pdev, true);
1972 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1974 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1975 u64 dma_addr = dev->host_mem_descs_dma;
1976 struct nvme_command c = { };
1979 c.features.opcode = nvme_admin_set_features;
1980 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1981 c.features.dword11 = cpu_to_le32(bits);
1982 c.features.dword12 = cpu_to_le32(host_mem_size);
1983 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1984 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1985 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1987 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1989 dev_warn(dev->ctrl.device,
1990 "failed to set host mem (err %d, flags %#x).\n",
1993 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1998 static void nvme_free_host_mem(struct nvme_dev *dev)
2002 for (i = 0; i < dev->nr_host_mem_descs; i++) {
2003 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
2004 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
2006 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2007 le64_to_cpu(desc->addr),
2008 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2011 kfree(dev->host_mem_desc_bufs);
2012 dev->host_mem_desc_bufs = NULL;
2013 dma_free_coherent(dev->dev,
2014 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
2015 dev->host_mem_descs, dev->host_mem_descs_dma);
2016 dev->host_mem_descs = NULL;
2017 dev->nr_host_mem_descs = 0;
2020 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
2023 struct nvme_host_mem_buf_desc *descs;
2024 u32 max_entries, len;
2025 dma_addr_t descs_dma;
2030 tmp = (preferred + chunk_size - 1);
2031 do_div(tmp, chunk_size);
2034 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2035 max_entries = dev->ctrl.hmmaxd;
2037 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
2038 &descs_dma, GFP_KERNEL);
2042 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2044 goto out_free_descs;
2046 for (size = 0; size < preferred && i < max_entries; size += len) {
2047 dma_addr_t dma_addr;
2049 len = min_t(u64, chunk_size, preferred - size);
2050 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2051 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2055 descs[i].addr = cpu_to_le64(dma_addr);
2056 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
2063 dev->nr_host_mem_descs = i;
2064 dev->host_mem_size = size;
2065 dev->host_mem_descs = descs;
2066 dev->host_mem_descs_dma = descs_dma;
2067 dev->host_mem_desc_bufs = bufs;
2072 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
2074 dma_free_attrs(dev->dev, size, bufs[i],
2075 le64_to_cpu(descs[i].addr),
2076 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2081 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2084 dev->host_mem_descs = NULL;
2088 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2090 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2091 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2094 /* start big and work our way down */
2095 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2096 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2097 if (!min || dev->host_mem_size >= min)
2099 nvme_free_host_mem(dev);
2106 static int nvme_setup_host_mem(struct nvme_dev *dev)
2108 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2109 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2110 u64 min = (u64)dev->ctrl.hmmin * 4096;
2111 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2114 preferred = min(preferred, max);
2116 dev_warn(dev->ctrl.device,
2117 "min host memory (%lld MiB) above limit (%d MiB).\n",
2118 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2119 nvme_free_host_mem(dev);
2124 * If we already have a buffer allocated check if we can reuse it.
2126 if (dev->host_mem_descs) {
2127 if (dev->host_mem_size >= min)
2128 enable_bits |= NVME_HOST_MEM_RETURN;
2130 nvme_free_host_mem(dev);
2133 if (!dev->host_mem_descs) {
2134 if (nvme_alloc_host_mem(dev, min, preferred)) {
2135 dev_warn(dev->ctrl.device,
2136 "failed to allocate host memory buffer.\n");
2137 return 0; /* controller must work without HMB */
2140 dev_info(dev->ctrl.device,
2141 "allocated %lld MiB host memory buffer.\n",
2142 dev->host_mem_size >> ilog2(SZ_1M));
2145 ret = nvme_set_host_mem(dev, enable_bits);
2147 nvme_free_host_mem(dev);
2151 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2154 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2156 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2157 ndev->cmbloc, ndev->cmbsz);
2159 static DEVICE_ATTR_RO(cmb);
2161 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2164 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2166 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2168 static DEVICE_ATTR_RO(cmbloc);
2170 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2173 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2175 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2177 static DEVICE_ATTR_RO(cmbsz);
2179 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2182 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2184 return sysfs_emit(buf, "%d\n", ndev->hmb);
2187 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2188 const char *buf, size_t count)
2190 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2194 if (strtobool(buf, &new) < 0)
2197 if (new == ndev->hmb)
2201 ret = nvme_setup_host_mem(ndev);
2203 ret = nvme_set_host_mem(ndev, 0);
2205 nvme_free_host_mem(ndev);
2213 static DEVICE_ATTR_RW(hmb);
2215 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2216 struct attribute *a, int n)
2218 struct nvme_ctrl *ctrl =
2219 dev_get_drvdata(container_of(kobj, struct device, kobj));
2220 struct nvme_dev *dev = to_nvme_dev(ctrl);
2222 if (a == &dev_attr_cmb.attr ||
2223 a == &dev_attr_cmbloc.attr ||
2224 a == &dev_attr_cmbsz.attr) {
2228 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2234 static struct attribute *nvme_pci_attrs[] = {
2236 &dev_attr_cmbloc.attr,
2237 &dev_attr_cmbsz.attr,
2242 static const struct attribute_group nvme_pci_attr_group = {
2243 .attrs = nvme_pci_attrs,
2244 .is_visible = nvme_pci_attrs_are_visible,
2248 * nirqs is the number of interrupts available for write and read
2249 * queues. The core already reserved an interrupt for the admin queue.
2251 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2253 struct nvme_dev *dev = affd->priv;
2254 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2257 * If there is no interrupt available for queues, ensure that
2258 * the default queue is set to 1. The affinity set size is
2259 * also set to one, but the irq core ignores it for this case.
2261 * If only one interrupt is available or 'write_queue' == 0, combine
2262 * write and read queues.
2264 * If 'write_queues' > 0, ensure it leaves room for at least one read
2270 } else if (nrirqs == 1 || !nr_write_queues) {
2272 } else if (nr_write_queues >= nrirqs) {
2275 nr_read_queues = nrirqs - nr_write_queues;
2278 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2279 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2280 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2281 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2282 affd->nr_sets = nr_read_queues ? 2 : 1;
2285 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2287 struct pci_dev *pdev = to_pci_dev(dev->dev);
2288 struct irq_affinity affd = {
2290 .calc_sets = nvme_calc_irq_sets,
2293 unsigned int irq_queues, poll_queues;
2296 * Poll queues don't need interrupts, but we need at least one I/O queue
2297 * left over for non-polled I/O.
2299 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2300 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2303 * Initialize for the single interrupt case, will be updated in
2304 * nvme_calc_irq_sets().
2306 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2307 dev->io_queues[HCTX_TYPE_READ] = 0;
2310 * We need interrupts for the admin queue and each non-polled I/O queue,
2311 * but some Apple controllers require all queues to use the first
2315 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2316 irq_queues += (nr_io_queues - poll_queues);
2317 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2318 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2321 static void nvme_disable_io_queues(struct nvme_dev *dev)
2323 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2324 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2327 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2330 * If tags are shared with admin queue (Apple bug), then
2331 * make sure we only use one IO queue.
2333 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2335 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2338 static int nvme_setup_io_queues(struct nvme_dev *dev)
2340 struct nvme_queue *adminq = &dev->queues[0];
2341 struct pci_dev *pdev = to_pci_dev(dev->dev);
2342 unsigned int nr_io_queues;
2347 * Sample the module parameters once at reset time so that we have
2348 * stable values to work with.
2350 dev->nr_write_queues = write_queues;
2351 dev->nr_poll_queues = poll_queues;
2353 nr_io_queues = dev->nr_allocated_queues - 1;
2354 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2358 if (nr_io_queues == 0)
2362 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2363 * from set to unset. If there is a window to it is truely freed,
2364 * pci_free_irq_vectors() jumping into this window will crash.
2365 * And take lock to avoid racing with pci_free_irq_vectors() in
2366 * nvme_dev_disable() path.
2368 result = nvme_setup_io_queues_trylock(dev);
2371 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2372 pci_free_irq(pdev, 0, adminq);
2374 if (dev->cmb_use_sqes) {
2375 result = nvme_cmb_qdepth(dev, nr_io_queues,
2376 sizeof(struct nvme_command));
2378 dev->q_depth = result;
2380 dev->cmb_use_sqes = false;
2384 size = db_bar_size(dev, nr_io_queues);
2385 result = nvme_remap_bar(dev, size);
2388 if (!--nr_io_queues) {
2393 adminq->q_db = dev->dbs;
2396 /* Deregister the admin queue's interrupt */
2397 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2398 pci_free_irq(pdev, 0, adminq);
2401 * If we enable msix early due to not intx, disable it again before
2402 * setting up the full range we need.
2404 pci_free_irq_vectors(pdev);
2406 result = nvme_setup_irqs(dev, nr_io_queues);
2412 dev->num_vecs = result;
2413 result = max(result - 1, 1);
2414 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2417 * Should investigate if there's a performance win from allocating
2418 * more queues than interrupt vectors; it might allow the submission
2419 * path to scale better, even if the receive path is limited by the
2420 * number of interrupts.
2422 result = queue_request_irq(adminq);
2425 set_bit(NVMEQ_ENABLED, &adminq->flags);
2426 mutex_unlock(&dev->shutdown_lock);
2428 result = nvme_create_io_queues(dev);
2429 if (result || dev->online_queues < 2)
2432 if (dev->online_queues - 1 < dev->max_qid) {
2433 nr_io_queues = dev->online_queues - 1;
2434 nvme_disable_io_queues(dev);
2435 result = nvme_setup_io_queues_trylock(dev);
2438 nvme_suspend_io_queues(dev);
2441 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2442 dev->io_queues[HCTX_TYPE_DEFAULT],
2443 dev->io_queues[HCTX_TYPE_READ],
2444 dev->io_queues[HCTX_TYPE_POLL]);
2447 mutex_unlock(&dev->shutdown_lock);
2451 static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2454 struct nvme_queue *nvmeq = req->end_io_data;
2456 blk_mq_free_request(req);
2457 complete(&nvmeq->delete_done);
2458 return RQ_END_IO_NONE;
2461 static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2464 struct nvme_queue *nvmeq = req->end_io_data;
2467 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2469 return nvme_del_queue_end(req, error);
2472 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2474 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2475 struct request *req;
2476 struct nvme_command cmd = { };
2478 cmd.delete_queue.opcode = opcode;
2479 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2481 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2483 return PTR_ERR(req);
2484 nvme_init_request(req, &cmd);
2486 if (opcode == nvme_admin_delete_cq)
2487 req->end_io = nvme_del_cq_end;
2489 req->end_io = nvme_del_queue_end;
2490 req->end_io_data = nvmeq;
2492 init_completion(&nvmeq->delete_done);
2493 req->rq_flags |= RQF_QUIET;
2494 blk_execute_rq_nowait(req, false);
2498 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2500 int nr_queues = dev->online_queues - 1, sent = 0;
2501 unsigned long timeout;
2504 timeout = NVME_ADMIN_TIMEOUT;
2505 while (nr_queues > 0) {
2506 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2512 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2514 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2526 static void nvme_pci_alloc_tag_set(struct nvme_dev *dev)
2528 struct blk_mq_tag_set * set = &dev->tagset;
2531 set->ops = &nvme_mq_ops;
2532 set->nr_hw_queues = dev->online_queues - 1;
2534 if (dev->io_queues[HCTX_TYPE_READ])
2536 if (dev->io_queues[HCTX_TYPE_POLL])
2538 set->timeout = NVME_IO_TIMEOUT;
2539 set->numa_node = dev->ctrl.numa_node;
2540 set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2541 set->cmd_size = sizeof(struct nvme_iod);
2542 set->flags = BLK_MQ_F_SHOULD_MERGE;
2543 set->driver_data = dev;
2546 * Some Apple controllers requires tags to be unique
2547 * across admin and IO queue, so reserve the first 32
2548 * tags of the IO queue.
2550 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2551 set->reserved_tags = NVME_AQ_DEPTH;
2553 ret = blk_mq_alloc_tag_set(set);
2555 dev_warn(dev->ctrl.device,
2556 "IO queues tagset allocation failed %d\n", ret);
2559 dev->ctrl.tagset = set;
2562 static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2564 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2565 /* free previously allocated queues that are no longer usable */
2566 nvme_free_queues(dev, dev->online_queues);
2569 static int nvme_pci_enable(struct nvme_dev *dev)
2571 int result = -ENOMEM;
2572 struct pci_dev *pdev = to_pci_dev(dev->dev);
2573 int dma_address_bits = 64;
2575 if (pci_enable_device_mem(pdev))
2578 pci_set_master(pdev);
2580 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2581 dma_address_bits = 48;
2582 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2585 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2591 * Some devices and/or platforms don't advertise or work with INTx
2592 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2593 * adjust this later.
2595 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2599 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2601 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2603 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2604 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2605 dev->dbs = dev->bar + 4096;
2608 * Some Apple controllers require a non-standard SQE size.
2609 * Interestingly they also seem to ignore the CC:IOSQES register
2610 * so we don't bother updating it here.
2612 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2615 dev->io_sqes = NVME_NVM_IOSQES;
2618 * Temporary fix for the Apple controller found in the MacBook8,1 and
2619 * some MacBook7,1 to avoid controller resets and data loss.
2621 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2623 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2624 "set queue depth=%u to work around controller resets\n",
2626 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2627 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2628 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2630 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2631 "set queue depth=%u\n", dev->q_depth);
2635 * Controllers with the shared tags quirk need the IO queue to be
2636 * big enough so that we get 32 tags for the admin queue
2638 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2639 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2640 dev->q_depth = NVME_AQ_DEPTH + 2;
2641 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2648 pci_enable_pcie_error_reporting(pdev);
2649 pci_save_state(pdev);
2653 pci_disable_device(pdev);
2657 static void nvme_dev_unmap(struct nvme_dev *dev)
2661 pci_release_mem_regions(to_pci_dev(dev->dev));
2664 static void nvme_pci_disable(struct nvme_dev *dev)
2666 struct pci_dev *pdev = to_pci_dev(dev->dev);
2668 pci_free_irq_vectors(pdev);
2670 if (pci_is_enabled(pdev)) {
2671 pci_disable_pcie_error_reporting(pdev);
2672 pci_disable_device(pdev);
2676 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2678 bool dead = true, freeze = false;
2679 struct pci_dev *pdev = to_pci_dev(dev->dev);
2681 mutex_lock(&dev->shutdown_lock);
2682 if (pci_is_enabled(pdev)) {
2685 if (pci_device_is_present(pdev))
2686 csts = readl(dev->bar + NVME_REG_CSTS);
2690 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2691 dev->ctrl.state == NVME_CTRL_RESETTING) {
2693 nvme_start_freeze(&dev->ctrl);
2695 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2696 pdev->error_state != pci_channel_io_normal);
2700 * Give the controller a chance to complete all entered requests if
2701 * doing a safe shutdown.
2703 if (!dead && shutdown && freeze)
2704 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2706 nvme_stop_queues(&dev->ctrl);
2708 if (!dead && dev->ctrl.queue_count > 0) {
2709 nvme_disable_io_queues(dev);
2710 nvme_disable_admin_queue(dev, shutdown);
2712 nvme_suspend_io_queues(dev);
2713 nvme_suspend_queue(&dev->queues[0]);
2714 nvme_pci_disable(dev);
2715 nvme_reap_pending_cqes(dev);
2717 nvme_cancel_tagset(&dev->ctrl);
2718 nvme_cancel_admin_tagset(&dev->ctrl);
2721 * The driver will not be starting up queues again if shutting down so
2722 * must flush all entered requests to their failed completion to avoid
2723 * deadlocking blk-mq hot-cpu notifier.
2726 nvme_start_queues(&dev->ctrl);
2727 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2728 nvme_start_admin_queue(&dev->ctrl);
2730 mutex_unlock(&dev->shutdown_lock);
2733 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2735 if (!nvme_wait_reset(&dev->ctrl))
2737 nvme_dev_disable(dev, shutdown);
2741 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2743 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2744 NVME_CTRL_PAGE_SIZE,
2745 NVME_CTRL_PAGE_SIZE, 0);
2746 if (!dev->prp_page_pool)
2749 /* Optimisation for I/Os between 4k and 128k */
2750 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2752 if (!dev->prp_small_pool) {
2753 dma_pool_destroy(dev->prp_page_pool);
2759 static void nvme_release_prp_pools(struct nvme_dev *dev)
2761 dma_pool_destroy(dev->prp_page_pool);
2762 dma_pool_destroy(dev->prp_small_pool);
2765 static void nvme_free_tagset(struct nvme_dev *dev)
2767 if (dev->tagset.tags)
2768 blk_mq_free_tag_set(&dev->tagset);
2769 dev->ctrl.tagset = NULL;
2772 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2774 struct nvme_dev *dev = to_nvme_dev(ctrl);
2776 nvme_dbbuf_dma_free(dev);
2777 nvme_free_tagset(dev);
2778 if (dev->ctrl.admin_q)
2779 blk_put_queue(dev->ctrl.admin_q);
2780 free_opal_dev(dev->ctrl.opal_dev);
2781 mempool_destroy(dev->iod_mempool);
2782 put_device(dev->dev);
2787 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2790 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2791 * may be holding this pci_dev's device lock.
2793 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2794 nvme_get_ctrl(&dev->ctrl);
2795 nvme_dev_disable(dev, false);
2796 nvme_kill_queues(&dev->ctrl);
2797 if (!queue_work(nvme_wq, &dev->remove_work))
2798 nvme_put_ctrl(&dev->ctrl);
2801 static void nvme_reset_work(struct work_struct *work)
2803 struct nvme_dev *dev =
2804 container_of(work, struct nvme_dev, ctrl.reset_work);
2805 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2808 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2809 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2816 * If we're called to reset a live controller first shut it down before
2819 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2820 nvme_dev_disable(dev, false);
2821 nvme_sync_queues(&dev->ctrl);
2823 mutex_lock(&dev->shutdown_lock);
2824 result = nvme_pci_enable(dev);
2828 result = nvme_pci_configure_admin_queue(dev);
2832 if (!dev->ctrl.admin_q) {
2833 result = nvme_pci_alloc_admin_tag_set(dev);
2837 nvme_start_admin_queue(&dev->ctrl);
2840 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2843 * Limit the max command size to prevent iod->sg allocations going
2844 * over a single page.
2846 dev->ctrl.max_hw_sectors = min_t(u32,
2847 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2848 dev->ctrl.max_segments = NVME_MAX_SEGS;
2851 * Don't limit the IOMMU merged segment size.
2853 dma_set_max_seg_size(dev->dev, 0xffffffff);
2855 mutex_unlock(&dev->shutdown_lock);
2858 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2859 * initializing procedure here.
2861 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2862 dev_warn(dev->ctrl.device,
2863 "failed to mark controller CONNECTING\n");
2869 * We do not support an SGL for metadata (yet), so we are limited to a
2870 * single integrity segment for the separate metadata pointer.
2872 dev->ctrl.max_integrity_segments = 1;
2874 result = nvme_init_ctrl_finish(&dev->ctrl);
2878 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2879 if (!dev->ctrl.opal_dev)
2880 dev->ctrl.opal_dev =
2881 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2882 else if (was_suspend)
2883 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2885 free_opal_dev(dev->ctrl.opal_dev);
2886 dev->ctrl.opal_dev = NULL;
2889 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2890 result = nvme_dbbuf_dma_alloc(dev);
2893 "unable to allocate dma for dbbuf\n");
2896 if (dev->ctrl.hmpre) {
2897 result = nvme_setup_host_mem(dev);
2902 result = nvme_setup_io_queues(dev);
2907 * Keep the controller around but remove all namespaces if we don't have
2908 * any working I/O queue.
2910 if (dev->online_queues < 2) {
2911 dev_warn(dev->ctrl.device, "IO queues not created\n");
2912 nvme_kill_queues(&dev->ctrl);
2913 nvme_remove_namespaces(&dev->ctrl);
2914 nvme_free_tagset(dev);
2916 nvme_start_queues(&dev->ctrl);
2917 nvme_wait_freeze(&dev->ctrl);
2918 if (!dev->ctrl.tagset)
2919 nvme_pci_alloc_tag_set(dev);
2921 nvme_pci_update_nr_queues(dev);
2922 nvme_dbbuf_set(dev);
2923 nvme_unfreeze(&dev->ctrl);
2927 * If only admin queue live, keep it to do further investigation or
2930 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2931 dev_warn(dev->ctrl.device,
2932 "failed to mark controller live state\n");
2937 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2938 &nvme_pci_attr_group))
2939 dev->attrs_added = true;
2941 nvme_start_ctrl(&dev->ctrl);
2945 mutex_unlock(&dev->shutdown_lock);
2948 dev_warn(dev->ctrl.device,
2949 "Removing after probe failure status: %d\n", result);
2950 nvme_remove_dead_ctrl(dev);
2953 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2955 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2956 struct pci_dev *pdev = to_pci_dev(dev->dev);
2958 if (pci_get_drvdata(pdev))
2959 device_release_driver(&pdev->dev);
2960 nvme_put_ctrl(&dev->ctrl);
2963 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2965 *val = readl(to_nvme_dev(ctrl)->bar + off);
2969 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2971 writel(val, to_nvme_dev(ctrl)->bar + off);
2975 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2977 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2981 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2983 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2985 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2988 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2990 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2991 struct nvme_subsystem *subsys = ctrl->subsys;
2993 dev_err(ctrl->device,
2994 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2995 pdev->vendor, pdev->device,
2996 nvme_strlen(subsys->model, sizeof(subsys->model)),
2997 subsys->model, nvme_strlen(subsys->firmware_rev,
2998 sizeof(subsys->firmware_rev)),
2999 subsys->firmware_rev);
3002 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
3004 struct nvme_dev *dev = to_nvme_dev(ctrl);
3006 return dma_pci_p2pdma_supported(dev->dev);
3009 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
3011 .module = THIS_MODULE,
3012 .flags = NVME_F_METADATA_SUPPORTED,
3013 .reg_read32 = nvme_pci_reg_read32,
3014 .reg_write32 = nvme_pci_reg_write32,
3015 .reg_read64 = nvme_pci_reg_read64,
3016 .free_ctrl = nvme_pci_free_ctrl,
3017 .submit_async_event = nvme_pci_submit_async_event,
3018 .get_address = nvme_pci_get_address,
3019 .print_device_info = nvme_pci_print_device_info,
3020 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
3023 static int nvme_dev_map(struct nvme_dev *dev)
3025 struct pci_dev *pdev = to_pci_dev(dev->dev);
3027 if (pci_request_mem_regions(pdev, "nvme"))
3030 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
3035 pci_release_mem_regions(pdev);
3039 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
3041 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3043 * Several Samsung devices seem to drop off the PCIe bus
3044 * randomly when APST is on and uses the deepest sleep state.
3045 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3046 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3047 * 950 PRO 256GB", but it seems to be restricted to two Dell
3050 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3051 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3052 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3053 return NVME_QUIRK_NO_DEEPEST_PS;
3054 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3056 * Samsung SSD 960 EVO drops off the PCIe bus after system
3057 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3058 * within few minutes after bootup on a Coffee Lake board -
3061 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
3062 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3063 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
3064 return NVME_QUIRK_NO_APST;
3065 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3066 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3067 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3069 * Forcing to use host managed nvme power settings for
3070 * lowest idle power with quick resume latency on
3071 * Samsung and Toshiba SSDs based on suspend behavior
3072 * on Coffee Lake board for LENOVO C640
3074 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3075 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3076 return NVME_QUIRK_SIMPLE_SUSPEND;
3082 static void nvme_async_probe(void *data, async_cookie_t cookie)
3084 struct nvme_dev *dev = data;
3086 flush_work(&dev->ctrl.reset_work);
3087 flush_work(&dev->ctrl.scan_work);
3088 nvme_put_ctrl(&dev->ctrl);
3091 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3093 int node, result = -ENOMEM;
3094 struct nvme_dev *dev;
3095 unsigned long quirks = id->driver_data;
3098 node = dev_to_node(&pdev->dev);
3099 if (node == NUMA_NO_NODE)
3100 set_dev_node(&pdev->dev, first_memory_node);
3102 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3106 dev->nr_write_queues = write_queues;
3107 dev->nr_poll_queues = poll_queues;
3108 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3109 dev->queues = kcalloc_node(dev->nr_allocated_queues,
3110 sizeof(struct nvme_queue), GFP_KERNEL, node);
3114 dev->dev = get_device(&pdev->dev);
3115 pci_set_drvdata(pdev, dev);
3117 result = nvme_dev_map(dev);
3121 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
3122 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
3123 mutex_init(&dev->shutdown_lock);
3125 result = nvme_setup_prp_pools(dev);
3129 quirks |= check_vendor_combination_bug(pdev);
3131 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
3133 * Some systems use a bios work around to ask for D3 on
3134 * platforms that support kernel managed suspend.
3136 dev_info(&pdev->dev,
3137 "platform quirk: setting simple suspend\n");
3138 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3142 * Double check that our mempool alloc size will cover the biggest
3143 * command we support.
3145 alloc_size = nvme_pci_iod_alloc_size();
3146 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3148 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3150 (void *) alloc_size,
3152 if (!dev->iod_mempool) {
3157 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3160 goto release_mempool;
3162 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3164 nvme_reset_ctrl(&dev->ctrl);
3165 async_schedule(nvme_async_probe, dev);
3170 mempool_destroy(dev->iod_mempool);
3172 nvme_release_prp_pools(dev);
3174 nvme_dev_unmap(dev);
3176 put_device(dev->dev);
3183 static void nvme_reset_prepare(struct pci_dev *pdev)
3185 struct nvme_dev *dev = pci_get_drvdata(pdev);
3188 * We don't need to check the return value from waiting for the reset
3189 * state as pci_dev device lock is held, making it impossible to race
3192 nvme_disable_prepare_reset(dev, false);
3193 nvme_sync_queues(&dev->ctrl);
3196 static void nvme_reset_done(struct pci_dev *pdev)
3198 struct nvme_dev *dev = pci_get_drvdata(pdev);
3200 if (!nvme_try_sched_reset(&dev->ctrl))
3201 flush_work(&dev->ctrl.reset_work);
3204 static void nvme_shutdown(struct pci_dev *pdev)
3206 struct nvme_dev *dev = pci_get_drvdata(pdev);
3208 nvme_disable_prepare_reset(dev, true);
3211 static void nvme_remove_attrs(struct nvme_dev *dev)
3213 if (dev->attrs_added)
3214 sysfs_remove_group(&dev->ctrl.device->kobj,
3215 &nvme_pci_attr_group);
3219 * The driver's remove may be called on a device in a partially initialized
3220 * state. This function must not have any dependencies on the device state in
3223 static void nvme_remove(struct pci_dev *pdev)
3225 struct nvme_dev *dev = pci_get_drvdata(pdev);
3227 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3228 pci_set_drvdata(pdev, NULL);
3230 if (!pci_device_is_present(pdev)) {
3231 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3232 nvme_dev_disable(dev, true);
3235 flush_work(&dev->ctrl.reset_work);
3236 nvme_stop_ctrl(&dev->ctrl);
3237 nvme_remove_namespaces(&dev->ctrl);
3238 nvme_dev_disable(dev, true);
3239 nvme_remove_attrs(dev);
3240 nvme_free_host_mem(dev);
3241 nvme_dev_remove_admin(dev);
3242 nvme_free_queues(dev, 0);
3243 nvme_release_prp_pools(dev);
3244 nvme_dev_unmap(dev);
3245 nvme_uninit_ctrl(&dev->ctrl);
3248 #ifdef CONFIG_PM_SLEEP
3249 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3251 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3254 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3256 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3259 static int nvme_resume(struct device *dev)
3261 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3262 struct nvme_ctrl *ctrl = &ndev->ctrl;
3264 if (ndev->last_ps == U32_MAX ||
3265 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3267 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3272 return nvme_try_sched_reset(ctrl);
3275 static int nvme_suspend(struct device *dev)
3277 struct pci_dev *pdev = to_pci_dev(dev);
3278 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3279 struct nvme_ctrl *ctrl = &ndev->ctrl;
3282 ndev->last_ps = U32_MAX;
3285 * The platform does not remove power for a kernel managed suspend so
3286 * use host managed nvme power settings for lowest idle power if
3287 * possible. This should have quicker resume latency than a full device
3288 * shutdown. But if the firmware is involved after the suspend or the
3289 * device does not support any non-default power states, shut down the
3292 * If ASPM is not enabled for the device, shut down the device and allow
3293 * the PCI bus layer to put it into D3 in order to take the PCIe link
3294 * down, so as to allow the platform to achieve its minimum low-power
3295 * state (which may not be possible if the link is up).
3297 if (pm_suspend_via_firmware() || !ctrl->npss ||
3298 !pcie_aspm_enabled(pdev) ||
3299 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3300 return nvme_disable_prepare_reset(ndev, true);
3302 nvme_start_freeze(ctrl);
3303 nvme_wait_freeze(ctrl);
3304 nvme_sync_queues(ctrl);
3306 if (ctrl->state != NVME_CTRL_LIVE)
3310 * Host memory access may not be successful in a system suspend state,
3311 * but the specification allows the controller to access memory in a
3312 * non-operational power state.
3315 ret = nvme_set_host_mem(ndev, 0);
3320 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3325 * A saved state prevents pci pm from generically controlling the
3326 * device's power. If we're using protocol specific settings, we don't
3327 * want pci interfering.
3329 pci_save_state(pdev);
3331 ret = nvme_set_power_state(ctrl, ctrl->npss);
3336 /* discard the saved state */
3337 pci_load_saved_state(pdev, NULL);
3340 * Clearing npss forces a controller reset on resume. The
3341 * correct value will be rediscovered then.
3343 ret = nvme_disable_prepare_reset(ndev, true);
3347 nvme_unfreeze(ctrl);
3351 static int nvme_simple_suspend(struct device *dev)
3353 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3355 return nvme_disable_prepare_reset(ndev, true);
3358 static int nvme_simple_resume(struct device *dev)
3360 struct pci_dev *pdev = to_pci_dev(dev);
3361 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3363 return nvme_try_sched_reset(&ndev->ctrl);
3366 static const struct dev_pm_ops nvme_dev_pm_ops = {
3367 .suspend = nvme_suspend,
3368 .resume = nvme_resume,
3369 .freeze = nvme_simple_suspend,
3370 .thaw = nvme_simple_resume,
3371 .poweroff = nvme_simple_suspend,
3372 .restore = nvme_simple_resume,
3374 #endif /* CONFIG_PM_SLEEP */
3376 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3377 pci_channel_state_t state)
3379 struct nvme_dev *dev = pci_get_drvdata(pdev);
3382 * A frozen channel requires a reset. When detected, this method will
3383 * shutdown the controller to quiesce. The controller will be restarted
3384 * after the slot reset through driver's slot_reset callback.
3387 case pci_channel_io_normal:
3388 return PCI_ERS_RESULT_CAN_RECOVER;
3389 case pci_channel_io_frozen:
3390 dev_warn(dev->ctrl.device,
3391 "frozen state error detected, reset controller\n");
3392 nvme_dev_disable(dev, false);
3393 return PCI_ERS_RESULT_NEED_RESET;
3394 case pci_channel_io_perm_failure:
3395 dev_warn(dev->ctrl.device,
3396 "failure state error detected, request disconnect\n");
3397 return PCI_ERS_RESULT_DISCONNECT;
3399 return PCI_ERS_RESULT_NEED_RESET;
3402 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3404 struct nvme_dev *dev = pci_get_drvdata(pdev);
3406 dev_info(dev->ctrl.device, "restart after slot reset\n");
3407 pci_restore_state(pdev);
3408 nvme_reset_ctrl(&dev->ctrl);
3409 return PCI_ERS_RESULT_RECOVERED;
3412 static void nvme_error_resume(struct pci_dev *pdev)
3414 struct nvme_dev *dev = pci_get_drvdata(pdev);
3416 flush_work(&dev->ctrl.reset_work);
3419 static const struct pci_error_handlers nvme_err_handler = {
3420 .error_detected = nvme_error_detected,
3421 .slot_reset = nvme_slot_reset,
3422 .resume = nvme_error_resume,
3423 .reset_prepare = nvme_reset_prepare,
3424 .reset_done = nvme_reset_done,
3427 static const struct pci_device_id nvme_id_table[] = {
3428 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3429 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3430 NVME_QUIRK_DEALLOCATE_ZEROES, },
3431 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
3432 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3433 NVME_QUIRK_DEALLOCATE_ZEROES, },
3434 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
3435 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3436 NVME_QUIRK_DEALLOCATE_ZEROES |
3437 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3438 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
3439 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3440 NVME_QUIRK_DEALLOCATE_ZEROES, },
3441 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3442 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3443 NVME_QUIRK_MEDIUM_PRIO_SQ |
3444 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3445 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3446 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3447 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3448 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3449 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3450 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3451 NVME_QUIRK_BOGUS_NID, },
3452 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3453 .driver_data = NVME_QUIRK_BOGUS_NID, },
3454 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3455 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3456 NVME_QUIRK_BOGUS_NID, },
3457 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3458 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3459 NVME_QUIRK_NO_NS_DESC_LIST, },
3460 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3461 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3462 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3463 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3464 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3465 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3466 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3467 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3468 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3469 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3470 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3471 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3472 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3473 .driver_data = NVME_QUIRK_BOGUS_NID, },
3474 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3475 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3476 NVME_QUIRK_BOGUS_NID, },
3477 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3478 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3479 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3480 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3481 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3482 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3483 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3484 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3485 .driver_data = NVME_QUIRK_BOGUS_NID, },
3486 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3487 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3488 NVME_QUIRK_BOGUS_NID, },
3489 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3490 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3491 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3492 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3493 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3494 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3495 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3496 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3497 .driver_data = NVME_QUIRK_BOGUS_NID, },
3498 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3499 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3500 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3501 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3502 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3503 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3504 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3505 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3506 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3507 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3508 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3509 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3510 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3511 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3512 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3513 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3514 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3515 .driver_data = NVME_QUIRK_BOGUS_NID, },
3516 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3517 .driver_data = NVME_QUIRK_BOGUS_NID, },
3518 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3519 .driver_data = NVME_QUIRK_BOGUS_NID, },
3520 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3521 .driver_data = NVME_QUIRK_BOGUS_NID, },
3522 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3523 .driver_data = NVME_QUIRK_BOGUS_NID, },
3524 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3525 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3526 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3527 .driver_data = NVME_QUIRK_BOGUS_NID, },
3528 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3529 .driver_data = NVME_QUIRK_BOGUS_NID, },
3530 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3531 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3532 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3533 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3534 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3535 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3536 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3537 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3538 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3539 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3540 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3541 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3542 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3543 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3544 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3545 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3546 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3547 NVME_QUIRK_128_BYTES_SQES |
3548 NVME_QUIRK_SHARED_TAGS |
3549 NVME_QUIRK_SKIP_CID_GEN },
3550 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3553 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3555 static struct pci_driver nvme_driver = {
3557 .id_table = nvme_id_table,
3558 .probe = nvme_probe,
3559 .remove = nvme_remove,
3560 .shutdown = nvme_shutdown,
3561 #ifdef CONFIG_PM_SLEEP
3563 .pm = &nvme_dev_pm_ops,
3566 .sriov_configure = pci_sriov_configure_simple,
3567 .err_handler = &nvme_err_handler,
3570 static int __init nvme_init(void)
3572 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3573 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3574 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3575 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3576 BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) >
3579 return pci_register_driver(&nvme_driver);
3582 static void __exit nvme_exit(void)
3584 pci_unregister_driver(&nvme_driver);
3585 flush_workqueue(nvme_wq);
3588 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3589 MODULE_LICENSE("GPL");
3590 MODULE_VERSION("1.0");
3591 module_init(nvme_init);
3592 module_exit(nvme_exit);