1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
7 #include <linux/acpi.h>
9 #include <linux/async.h>
10 #include <linux/blkdev.h>
11 #include <linux/blk-mq.h>
12 #include <linux/blk-mq-pci.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/once.h>
21 #include <linux/pci.h>
22 #include <linux/suspend.h>
23 #include <linux/t10-pi.h>
24 #include <linux/types.h>
25 #include <linux/io-64-nonatomic-lo-hi.h>
26 #include <linux/io-64-nonatomic-hi-lo.h>
27 #include <linux/sed-opal.h>
28 #include <linux/pci-p2pdma.h>
33 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
34 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
36 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
39 * These can be higher, but we need to ensure that any command doesn't
40 * require an sg allocation that needs more than a page of data.
42 #define NVME_MAX_KB_SZ 4096
43 #define NVME_MAX_SEGS 127
45 static int use_threaded_interrupts;
46 module_param(use_threaded_interrupts, int, 0);
48 static bool use_cmb_sqes = true;
49 module_param(use_cmb_sqes, bool, 0444);
50 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
52 static unsigned int max_host_mem_size_mb = 128;
53 module_param(max_host_mem_size_mb, uint, 0444);
54 MODULE_PARM_DESC(max_host_mem_size_mb,
55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
57 static unsigned int sgl_threshold = SZ_32K;
58 module_param(sgl_threshold, uint, 0644);
59 MODULE_PARM_DESC(sgl_threshold,
60 "Use SGLs when average request segment size is larger or equal to "
61 "this size. Use 0 to disable SGLs.");
63 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
64 static const struct kernel_param_ops io_queue_depth_ops = {
65 .set = io_queue_depth_set,
66 .get = param_get_uint,
69 static unsigned int io_queue_depth = 1024;
70 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
71 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
73 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
78 ret = kstrtouint(val, 10, &n);
79 if (ret != 0 || n > num_possible_cpus())
81 return param_set_uint(val, kp);
84 static const struct kernel_param_ops io_queue_count_ops = {
85 .set = io_queue_count_set,
86 .get = param_get_uint,
89 static unsigned int write_queues;
90 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
91 MODULE_PARM_DESC(write_queues,
92 "Number of queues to use for writes. If not set, reads and writes "
93 "will share a queue set.");
95 static unsigned int poll_queues;
96 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
97 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
100 module_param(noacpi, bool, 0444);
101 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
106 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
107 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
110 * Represents an NVM Express device. Each nvme_dev is a PCI function.
113 struct nvme_queue *queues;
114 struct blk_mq_tag_set tagset;
115 struct blk_mq_tag_set admin_tagset;
118 struct dma_pool *prp_page_pool;
119 struct dma_pool *prp_small_pool;
120 unsigned online_queues;
122 unsigned io_queues[HCTX_MAX_TYPES];
123 unsigned int num_vecs;
128 unsigned long bar_mapped_size;
129 struct work_struct remove_work;
130 struct mutex shutdown_lock;
136 struct nvme_ctrl ctrl;
139 mempool_t *iod_mempool;
141 /* shadow doorbell buffer support: */
143 dma_addr_t dbbuf_dbs_dma_addr;
145 dma_addr_t dbbuf_eis_dma_addr;
147 /* host memory buffer support: */
149 u32 nr_host_mem_descs;
150 dma_addr_t host_mem_descs_dma;
151 struct nvme_host_mem_buf_desc *host_mem_descs;
152 void **host_mem_desc_bufs;
153 unsigned int nr_allocated_queues;
154 unsigned int nr_write_queues;
155 unsigned int nr_poll_queues;
158 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
163 ret = kstrtou32(val, 10, &n);
164 if (ret != 0 || n < 2)
167 return param_set_uint(val, kp);
170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
172 return qid * 2 * stride;
175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
177 return (qid * 2 + 1) * stride;
180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
182 return container_of(ctrl, struct nvme_dev, ctrl);
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
190 struct nvme_dev *dev;
193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
195 struct nvme_completion *cqes;
196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
208 #define NVMEQ_ENABLED 0
209 #define NVMEQ_SQ_CMB 1
210 #define NVMEQ_DELETE_ERROR 2
211 #define NVMEQ_POLLED 3
216 struct completion delete_done;
220 * The nvme_iod describes the data in an I/O.
222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
223 * to the actual struct scatterlist.
226 struct nvme_request req;
227 struct nvme_command cmd;
228 struct nvme_queue *nvmeq;
231 int npages; /* In the PRP list. 0 means small pool in use */
232 int nents; /* Used in scatterlist */
233 dma_addr_t first_dma;
234 unsigned int dma_len; /* length of single DMA segment mapping */
236 struct scatterlist *sg;
239 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
241 return dev->nr_allocated_queues * 8 * dev->db_stride;
244 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
246 unsigned int mem_size = nvme_dbbuf_size(dev);
251 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
252 &dev->dbbuf_dbs_dma_addr,
256 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
257 &dev->dbbuf_eis_dma_addr,
259 if (!dev->dbbuf_eis) {
260 dma_free_coherent(dev->dev, mem_size,
261 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
262 dev->dbbuf_dbs = NULL;
269 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
271 unsigned int mem_size = nvme_dbbuf_size(dev);
273 if (dev->dbbuf_dbs) {
274 dma_free_coherent(dev->dev, mem_size,
275 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
276 dev->dbbuf_dbs = NULL;
278 if (dev->dbbuf_eis) {
279 dma_free_coherent(dev->dev, mem_size,
280 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
281 dev->dbbuf_eis = NULL;
285 static void nvme_dbbuf_init(struct nvme_dev *dev,
286 struct nvme_queue *nvmeq, int qid)
288 if (!dev->dbbuf_dbs || !qid)
291 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
292 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
293 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
294 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
297 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
302 nvmeq->dbbuf_sq_db = NULL;
303 nvmeq->dbbuf_cq_db = NULL;
304 nvmeq->dbbuf_sq_ei = NULL;
305 nvmeq->dbbuf_cq_ei = NULL;
308 static void nvme_dbbuf_set(struct nvme_dev *dev)
310 struct nvme_command c;
316 memset(&c, 0, sizeof(c));
317 c.dbbuf.opcode = nvme_admin_dbbuf;
318 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
319 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
321 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
322 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
323 /* Free memory and continue on */
324 nvme_dbbuf_dma_free(dev);
326 for (i = 1; i <= dev->online_queues; i++)
327 nvme_dbbuf_free(&dev->queues[i]);
331 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
333 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
336 /* Update dbbuf and return true if an MMIO is required */
337 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
338 volatile u32 *dbbuf_ei)
344 * Ensure that the queue is written before updating
345 * the doorbell in memory
349 old_value = *dbbuf_db;
353 * Ensure that the doorbell is updated before reading the event
354 * index from memory. The controller needs to provide similar
355 * ordering to ensure the envent index is updated before reading
360 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
368 * Will slightly overestimate the number of pages needed. This is OK
369 * as it only leads to a small amount of wasted memory for the lifetime of
372 static int nvme_pci_npages_prp(void)
374 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
375 NVME_CTRL_PAGE_SIZE);
376 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
380 * Calculates the number of pages needed for the SGL segments. For example a 4k
381 * page can accommodate 256 SGL descriptors.
383 static int nvme_pci_npages_sgl(void)
385 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
389 static size_t nvme_pci_iod_alloc_size(void)
391 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
393 return sizeof(__le64 *) * npages +
394 sizeof(struct scatterlist) * NVME_MAX_SEGS;
397 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
398 unsigned int hctx_idx)
400 struct nvme_dev *dev = data;
401 struct nvme_queue *nvmeq = &dev->queues[0];
403 WARN_ON(hctx_idx != 0);
404 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
406 hctx->driver_data = nvmeq;
410 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
411 unsigned int hctx_idx)
413 struct nvme_dev *dev = data;
414 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
416 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
417 hctx->driver_data = nvmeq;
421 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
422 unsigned int hctx_idx, unsigned int numa_node)
424 struct nvme_dev *dev = set->driver_data;
425 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
426 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
427 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
432 nvme_req(req)->ctrl = &dev->ctrl;
433 nvme_req(req)->cmd = &iod->cmd;
437 static int queue_irq_offset(struct nvme_dev *dev)
439 /* if we have more than 1 vec, admin queue offsets us by 1 */
440 if (dev->num_vecs > 1)
446 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
448 struct nvme_dev *dev = set->driver_data;
451 offset = queue_irq_offset(dev);
452 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
453 struct blk_mq_queue_map *map = &set->map[i];
455 map->nr_queues = dev->io_queues[i];
456 if (!map->nr_queues) {
457 BUG_ON(i == HCTX_TYPE_DEFAULT);
462 * The poll queue(s) doesn't have an IRQ (and hence IRQ
463 * affinity), so use the regular blk-mq cpu mapping
465 map->queue_offset = qoff;
466 if (i != HCTX_TYPE_POLL && offset)
467 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
469 blk_mq_map_queues(map);
470 qoff += map->nr_queues;
471 offset += map->nr_queues;
478 * Write sq tail if we are asked to, or if the next command would wrap.
480 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
483 u16 next_tail = nvmeq->sq_tail + 1;
485 if (next_tail == nvmeq->q_depth)
487 if (next_tail != nvmeq->last_sq_tail)
491 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
492 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
493 writel(nvmeq->sq_tail, nvmeq->q_db);
494 nvmeq->last_sq_tail = nvmeq->sq_tail;
498 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
499 * @nvmeq: The queue to use
500 * @cmd: The command to send
501 * @write_sq: whether to write to the SQ doorbell
503 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
506 spin_lock(&nvmeq->sq_lock);
507 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
509 if (++nvmeq->sq_tail == nvmeq->q_depth)
511 nvme_write_sq_db(nvmeq, write_sq);
512 spin_unlock(&nvmeq->sq_lock);
515 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
517 struct nvme_queue *nvmeq = hctx->driver_data;
519 spin_lock(&nvmeq->sq_lock);
520 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
521 nvme_write_sq_db(nvmeq, true);
522 spin_unlock(&nvmeq->sq_lock);
525 static void **nvme_pci_iod_list(struct request *req)
527 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
528 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
531 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
533 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
534 int nseg = blk_rq_nr_phys_segments(req);
535 unsigned int avg_seg_size;
537 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
539 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
541 if (!iod->nvmeq->qid)
543 if (!sgl_threshold || avg_seg_size < sgl_threshold)
548 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
550 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
551 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
552 dma_addr_t dma_addr = iod->first_dma;
555 for (i = 0; i < iod->npages; i++) {
556 __le64 *prp_list = nvme_pci_iod_list(req)[i];
557 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
559 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
560 dma_addr = next_dma_addr;
565 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
567 const int last_sg = SGES_PER_PAGE - 1;
568 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
569 dma_addr_t dma_addr = iod->first_dma;
572 for (i = 0; i < iod->npages; i++) {
573 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
574 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
576 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
577 dma_addr = next_dma_addr;
582 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
584 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
586 if (is_pci_p2pdma_page(sg_page(iod->sg)))
587 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
590 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
593 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
595 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
598 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
603 WARN_ON_ONCE(!iod->nents);
605 nvme_unmap_sg(dev, req);
606 if (iod->npages == 0)
607 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
609 else if (iod->use_sgl)
610 nvme_free_sgls(dev, req);
612 nvme_free_prps(dev, req);
613 mempool_free(iod->sg, dev->iod_mempool);
616 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
619 struct scatterlist *sg;
621 for_each_sg(sgl, sg, nents, i) {
622 dma_addr_t phys = sg_phys(sg);
623 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
624 "dma_address:%pad dma_length:%d\n",
625 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
630 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
631 struct request *req, struct nvme_rw_command *cmnd)
633 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
634 struct dma_pool *pool;
635 int length = blk_rq_payload_bytes(req);
636 struct scatterlist *sg = iod->sg;
637 int dma_len = sg_dma_len(sg);
638 u64 dma_addr = sg_dma_address(sg);
639 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
641 void **list = nvme_pci_iod_list(req);
645 length -= (NVME_CTRL_PAGE_SIZE - offset);
651 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
653 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
656 dma_addr = sg_dma_address(sg);
657 dma_len = sg_dma_len(sg);
660 if (length <= NVME_CTRL_PAGE_SIZE) {
661 iod->first_dma = dma_addr;
665 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
666 if (nprps <= (256 / 8)) {
667 pool = dev->prp_small_pool;
670 pool = dev->prp_page_pool;
674 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
676 iod->first_dma = dma_addr;
678 return BLK_STS_RESOURCE;
681 iod->first_dma = prp_dma;
684 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
685 __le64 *old_prp_list = prp_list;
686 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
689 list[iod->npages++] = prp_list;
690 prp_list[0] = old_prp_list[i - 1];
691 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
694 prp_list[i++] = cpu_to_le64(dma_addr);
695 dma_len -= NVME_CTRL_PAGE_SIZE;
696 dma_addr += NVME_CTRL_PAGE_SIZE;
697 length -= NVME_CTRL_PAGE_SIZE;
702 if (unlikely(dma_len < 0))
705 dma_addr = sg_dma_address(sg);
706 dma_len = sg_dma_len(sg);
709 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
710 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
713 nvme_free_prps(dev, req);
714 return BLK_STS_RESOURCE;
716 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
717 "Invalid SGL for payload:%d nents:%d\n",
718 blk_rq_payload_bytes(req), iod->nents);
719 return BLK_STS_IOERR;
722 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
723 struct scatterlist *sg)
725 sge->addr = cpu_to_le64(sg_dma_address(sg));
726 sge->length = cpu_to_le32(sg_dma_len(sg));
727 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
730 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
731 dma_addr_t dma_addr, int entries)
733 sge->addr = cpu_to_le64(dma_addr);
734 if (entries < SGES_PER_PAGE) {
735 sge->length = cpu_to_le32(entries * sizeof(*sge));
736 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
738 sge->length = cpu_to_le32(PAGE_SIZE);
739 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
743 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
744 struct request *req, struct nvme_rw_command *cmd, int entries)
746 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
747 struct dma_pool *pool;
748 struct nvme_sgl_desc *sg_list;
749 struct scatterlist *sg = iod->sg;
753 /* setting the transfer type as SGL */
754 cmd->flags = NVME_CMD_SGL_METABUF;
757 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
761 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
762 pool = dev->prp_small_pool;
765 pool = dev->prp_page_pool;
769 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
772 return BLK_STS_RESOURCE;
775 nvme_pci_iod_list(req)[0] = sg_list;
776 iod->first_dma = sgl_dma;
778 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
781 if (i == SGES_PER_PAGE) {
782 struct nvme_sgl_desc *old_sg_desc = sg_list;
783 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
785 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
790 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
791 sg_list[i++] = *link;
792 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
795 nvme_pci_sgl_set_data(&sg_list[i++], sg);
797 } while (--entries > 0);
801 nvme_free_sgls(dev, req);
802 return BLK_STS_RESOURCE;
805 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
806 struct request *req, struct nvme_rw_command *cmnd,
809 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
810 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
811 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
813 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
814 if (dma_mapping_error(dev->dev, iod->first_dma))
815 return BLK_STS_RESOURCE;
816 iod->dma_len = bv->bv_len;
818 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
819 if (bv->bv_len > first_prp_len)
820 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
824 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
825 struct request *req, struct nvme_rw_command *cmnd,
828 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
830 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
831 if (dma_mapping_error(dev->dev, iod->first_dma))
832 return BLK_STS_RESOURCE;
833 iod->dma_len = bv->bv_len;
835 cmnd->flags = NVME_CMD_SGL_METABUF;
836 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
837 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
838 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
842 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
843 struct nvme_command *cmnd)
845 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
846 blk_status_t ret = BLK_STS_RESOURCE;
849 if (blk_rq_nr_phys_segments(req) == 1) {
850 struct bio_vec bv = req_bvec(req);
852 if (!is_pci_p2pdma_page(bv.bv_page)) {
853 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
854 return nvme_setup_prp_simple(dev, req,
857 if (iod->nvmeq->qid && sgl_threshold &&
858 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
859 return nvme_setup_sgl_simple(dev, req,
865 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
867 return BLK_STS_RESOURCE;
868 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
869 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
873 if (is_pci_p2pdma_page(sg_page(iod->sg)))
874 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
875 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
877 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
878 rq_dma_dir(req), DMA_ATTR_NO_WARN);
882 iod->use_sgl = nvme_pci_use_sgls(dev, req);
884 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
886 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
887 if (ret != BLK_STS_OK)
892 nvme_unmap_sg(dev, req);
894 mempool_free(iod->sg, dev->iod_mempool);
898 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
899 struct nvme_command *cmnd)
901 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
903 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
905 if (dma_mapping_error(dev->dev, iod->meta_dma))
906 return BLK_STS_IOERR;
907 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
912 * NOTE: ns is NULL when called on the admin queue.
914 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
915 const struct blk_mq_queue_data *bd)
917 struct nvme_ns *ns = hctx->queue->queuedata;
918 struct nvme_queue *nvmeq = hctx->driver_data;
919 struct nvme_dev *dev = nvmeq->dev;
920 struct request *req = bd->rq;
921 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
922 struct nvme_command *cmnd = &iod->cmd;
930 * We should not need to do this, but we're still using this to
931 * ensure we can drain requests on a dying queue.
933 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
934 return BLK_STS_IOERR;
936 if (!nvme_check_ready(&dev->ctrl, req, true))
937 return nvme_fail_nonready_command(&dev->ctrl, req);
939 ret = nvme_setup_cmd(ns, req);
943 if (blk_rq_nr_phys_segments(req)) {
944 ret = nvme_map_data(dev, req, cmnd);
949 if (blk_integrity_rq(req)) {
950 ret = nvme_map_metadata(dev, req, cmnd);
955 blk_mq_start_request(req);
956 nvme_submit_cmd(nvmeq, cmnd, bd->last);
959 nvme_unmap_data(dev, req);
961 nvme_cleanup_cmd(req);
965 static void nvme_pci_complete_rq(struct request *req)
967 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
968 struct nvme_dev *dev = iod->nvmeq->dev;
970 if (blk_integrity_rq(req))
971 dma_unmap_page(dev->dev, iod->meta_dma,
972 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
973 if (blk_rq_nr_phys_segments(req))
974 nvme_unmap_data(dev, req);
975 nvme_complete_rq(req);
978 /* We read the CQE phase first to check if the rest of the entry is valid */
979 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
981 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
983 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
986 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
988 u16 head = nvmeq->cq_head;
990 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
992 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
995 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
998 return nvmeq->dev->admin_tagset.tags[0];
999 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1002 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
1004 struct nvme_completion *cqe = &nvmeq->cqes[idx];
1005 __u16 command_id = READ_ONCE(cqe->command_id);
1006 struct request *req;
1009 * AEN requests are special as they don't time out and can
1010 * survive any kind of queue freeze and often don't respond to
1011 * aborts. We don't even bother to allocate a struct request
1012 * for them but rather special case them here.
1014 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1015 nvme_complete_async_event(&nvmeq->dev->ctrl,
1016 cqe->status, &cqe->result);
1020 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id);
1021 if (unlikely(!req)) {
1022 dev_warn(nvmeq->dev->ctrl.device,
1023 "invalid id %d completed on queue %d\n",
1024 command_id, le16_to_cpu(cqe->sq_id));
1028 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1029 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
1030 nvme_pci_complete_rq(req);
1033 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1035 u16 tmp = nvmeq->cq_head + 1;
1037 if (tmp == nvmeq->q_depth) {
1039 nvmeq->cq_phase ^= 1;
1041 nvmeq->cq_head = tmp;
1045 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
1049 while (nvme_cqe_pending(nvmeq)) {
1052 * load-load control dependency between phase and the rest of
1053 * the cqe requires a full read memory barrier
1056 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1057 nvme_update_cq_head(nvmeq);
1061 nvme_ring_cq_doorbell(nvmeq);
1065 static irqreturn_t nvme_irq(int irq, void *data)
1067 struct nvme_queue *nvmeq = data;
1069 if (nvme_process_cq(nvmeq))
1074 static irqreturn_t nvme_irq_check(int irq, void *data)
1076 struct nvme_queue *nvmeq = data;
1078 if (nvme_cqe_pending(nvmeq))
1079 return IRQ_WAKE_THREAD;
1084 * Poll for completions for any interrupt driven queue
1085 * Can be called from any context.
1087 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1089 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1091 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1093 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1094 nvme_process_cq(nvmeq);
1095 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1098 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1100 struct nvme_queue *nvmeq = hctx->driver_data;
1103 if (!nvme_cqe_pending(nvmeq))
1106 spin_lock(&nvmeq->cq_poll_lock);
1107 found = nvme_process_cq(nvmeq);
1108 spin_unlock(&nvmeq->cq_poll_lock);
1113 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1115 struct nvme_dev *dev = to_nvme_dev(ctrl);
1116 struct nvme_queue *nvmeq = &dev->queues[0];
1117 struct nvme_command c;
1119 memset(&c, 0, sizeof(c));
1120 c.common.opcode = nvme_admin_async_event;
1121 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1122 nvme_submit_cmd(nvmeq, &c, true);
1125 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1127 struct nvme_command c;
1129 memset(&c, 0, sizeof(c));
1130 c.delete_queue.opcode = opcode;
1131 c.delete_queue.qid = cpu_to_le16(id);
1133 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1136 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1137 struct nvme_queue *nvmeq, s16 vector)
1139 struct nvme_command c;
1140 int flags = NVME_QUEUE_PHYS_CONTIG;
1142 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1143 flags |= NVME_CQ_IRQ_ENABLED;
1146 * Note: we (ab)use the fact that the prp fields survive if no data
1147 * is attached to the request.
1149 memset(&c, 0, sizeof(c));
1150 c.create_cq.opcode = nvme_admin_create_cq;
1151 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1152 c.create_cq.cqid = cpu_to_le16(qid);
1153 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1154 c.create_cq.cq_flags = cpu_to_le16(flags);
1155 c.create_cq.irq_vector = cpu_to_le16(vector);
1157 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1160 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1161 struct nvme_queue *nvmeq)
1163 struct nvme_ctrl *ctrl = &dev->ctrl;
1164 struct nvme_command c;
1165 int flags = NVME_QUEUE_PHYS_CONTIG;
1168 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1169 * set. Since URGENT priority is zeroes, it makes all queues
1172 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1173 flags |= NVME_SQ_PRIO_MEDIUM;
1176 * Note: we (ab)use the fact that the prp fields survive if no data
1177 * is attached to the request.
1179 memset(&c, 0, sizeof(c));
1180 c.create_sq.opcode = nvme_admin_create_sq;
1181 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1182 c.create_sq.sqid = cpu_to_le16(qid);
1183 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1184 c.create_sq.sq_flags = cpu_to_le16(flags);
1185 c.create_sq.cqid = cpu_to_le16(qid);
1187 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1190 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1192 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1195 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1197 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1200 static void abort_endio(struct request *req, blk_status_t error)
1202 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1203 struct nvme_queue *nvmeq = iod->nvmeq;
1205 dev_warn(nvmeq->dev->ctrl.device,
1206 "Abort status: 0x%x", nvme_req(req)->status);
1207 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1208 blk_mq_free_request(req);
1211 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1213 /* If true, indicates loss of adapter communication, possibly by a
1214 * NVMe Subsystem reset.
1216 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1218 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1219 switch (dev->ctrl.state) {
1220 case NVME_CTRL_RESETTING:
1221 case NVME_CTRL_CONNECTING:
1227 /* We shouldn't reset unless the controller is on fatal error state
1228 * _or_ if we lost the communication with it.
1230 if (!(csts & NVME_CSTS_CFS) && !nssro)
1236 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1238 /* Read a config register to help see what died. */
1242 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1244 if (result == PCIBIOS_SUCCESSFUL)
1245 dev_warn(dev->ctrl.device,
1246 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1249 dev_warn(dev->ctrl.device,
1250 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1254 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1256 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1257 struct nvme_queue *nvmeq = iod->nvmeq;
1258 struct nvme_dev *dev = nvmeq->dev;
1259 struct request *abort_req;
1260 struct nvme_command cmd;
1261 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1263 /* If PCI error recovery process is happening, we cannot reset or
1264 * the recovery mechanism will surely fail.
1267 if (pci_channel_offline(to_pci_dev(dev->dev)))
1268 return BLK_EH_RESET_TIMER;
1271 * Reset immediately if the controller is failed
1273 if (nvme_should_reset(dev, csts)) {
1274 nvme_warn_reset(dev, csts);
1275 nvme_dev_disable(dev, false);
1276 nvme_reset_ctrl(&dev->ctrl);
1281 * Did we miss an interrupt?
1283 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1284 nvme_poll(req->mq_hctx);
1286 nvme_poll_irqdisable(nvmeq);
1288 if (blk_mq_request_completed(req)) {
1289 dev_warn(dev->ctrl.device,
1290 "I/O %d QID %d timeout, completion polled\n",
1291 req->tag, nvmeq->qid);
1296 * Shutdown immediately if controller times out while starting. The
1297 * reset work will see the pci device disabled when it gets the forced
1298 * cancellation error. All outstanding requests are completed on
1299 * shutdown, so we return BLK_EH_DONE.
1301 switch (dev->ctrl.state) {
1302 case NVME_CTRL_CONNECTING:
1303 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1305 case NVME_CTRL_DELETING:
1306 dev_warn_ratelimited(dev->ctrl.device,
1307 "I/O %d QID %d timeout, disable controller\n",
1308 req->tag, nvmeq->qid);
1309 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1310 nvme_dev_disable(dev, true);
1312 case NVME_CTRL_RESETTING:
1313 return BLK_EH_RESET_TIMER;
1319 * Shutdown the controller immediately and schedule a reset if the
1320 * command was already aborted once before and still hasn't been
1321 * returned to the driver, or if this is the admin queue.
1323 if (!nvmeq->qid || iod->aborted) {
1324 dev_warn(dev->ctrl.device,
1325 "I/O %d QID %d timeout, reset controller\n",
1326 req->tag, nvmeq->qid);
1327 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1328 nvme_dev_disable(dev, false);
1329 nvme_reset_ctrl(&dev->ctrl);
1334 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1335 atomic_inc(&dev->ctrl.abort_limit);
1336 return BLK_EH_RESET_TIMER;
1340 memset(&cmd, 0, sizeof(cmd));
1341 cmd.abort.opcode = nvme_admin_abort_cmd;
1342 cmd.abort.cid = req->tag;
1343 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1345 dev_warn(nvmeq->dev->ctrl.device,
1346 "I/O %d QID %d timeout, aborting\n",
1347 req->tag, nvmeq->qid);
1349 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1351 if (IS_ERR(abort_req)) {
1352 atomic_inc(&dev->ctrl.abort_limit);
1353 return BLK_EH_RESET_TIMER;
1356 abort_req->end_io_data = NULL;
1357 blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
1360 * The aborted req will be completed on receiving the abort req.
1361 * We enable the timer again. If hit twice, it'll cause a device reset,
1362 * as the device then is in a faulty state.
1364 return BLK_EH_RESET_TIMER;
1367 static void nvme_free_queue(struct nvme_queue *nvmeq)
1369 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1370 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1371 if (!nvmeq->sq_cmds)
1374 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1375 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1376 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1378 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1379 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1383 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1387 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1388 dev->ctrl.queue_count--;
1389 nvme_free_queue(&dev->queues[i]);
1394 * nvme_suspend_queue - put queue into suspended state
1395 * @nvmeq: queue to suspend
1397 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1399 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1402 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1405 nvmeq->dev->online_queues--;
1406 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1407 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1408 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1409 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1413 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1417 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1418 nvme_suspend_queue(&dev->queues[i]);
1421 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1423 struct nvme_queue *nvmeq = &dev->queues[0];
1426 nvme_shutdown_ctrl(&dev->ctrl);
1428 nvme_disable_ctrl(&dev->ctrl);
1430 nvme_poll_irqdisable(nvmeq);
1434 * Called only on a device that has been disabled and after all other threads
1435 * that can check this device's completion queues have synced, except
1436 * nvme_poll(). This is the last chance for the driver to see a natural
1437 * completion before nvme_cancel_request() terminates all incomplete requests.
1439 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1443 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1444 spin_lock(&dev->queues[i].cq_poll_lock);
1445 nvme_process_cq(&dev->queues[i]);
1446 spin_unlock(&dev->queues[i].cq_poll_lock);
1450 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1453 int q_depth = dev->q_depth;
1454 unsigned q_size_aligned = roundup(q_depth * entry_size,
1455 NVME_CTRL_PAGE_SIZE);
1457 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1458 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1460 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1461 q_depth = div_u64(mem_per_q, entry_size);
1464 * Ensure the reduced q_depth is above some threshold where it
1465 * would be better to map queues in system memory with the
1475 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1478 struct pci_dev *pdev = to_pci_dev(dev->dev);
1480 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1481 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1482 if (nvmeq->sq_cmds) {
1483 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1485 if (nvmeq->sq_dma_addr) {
1486 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1490 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1494 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1495 &nvmeq->sq_dma_addr, GFP_KERNEL);
1496 if (!nvmeq->sq_cmds)
1501 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1503 struct nvme_queue *nvmeq = &dev->queues[qid];
1505 if (dev->ctrl.queue_count > qid)
1508 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1509 nvmeq->q_depth = depth;
1510 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1511 &nvmeq->cq_dma_addr, GFP_KERNEL);
1515 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1519 spin_lock_init(&nvmeq->sq_lock);
1520 spin_lock_init(&nvmeq->cq_poll_lock);
1522 nvmeq->cq_phase = 1;
1523 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1525 dev->ctrl.queue_count++;
1530 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1531 nvmeq->cq_dma_addr);
1536 static int queue_request_irq(struct nvme_queue *nvmeq)
1538 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1539 int nr = nvmeq->dev->ctrl.instance;
1541 if (use_threaded_interrupts) {
1542 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1543 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1545 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1546 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1550 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1552 struct nvme_dev *dev = nvmeq->dev;
1555 nvmeq->last_sq_tail = 0;
1557 nvmeq->cq_phase = 1;
1558 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1559 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1560 nvme_dbbuf_init(dev, nvmeq, qid);
1561 dev->online_queues++;
1562 wmb(); /* ensure the first interrupt sees the initialization */
1565 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1567 struct nvme_dev *dev = nvmeq->dev;
1571 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1574 * A queue's vector matches the queue identifier unless the controller
1575 * has only one vector available.
1578 vector = dev->num_vecs == 1 ? 0 : qid;
1580 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1582 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1586 result = adapter_alloc_sq(dev, qid, nvmeq);
1592 nvmeq->cq_vector = vector;
1593 nvme_init_queue(nvmeq, qid);
1596 result = queue_request_irq(nvmeq);
1601 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1605 dev->online_queues--;
1606 adapter_delete_sq(dev, qid);
1608 adapter_delete_cq(dev, qid);
1612 static const struct blk_mq_ops nvme_mq_admin_ops = {
1613 .queue_rq = nvme_queue_rq,
1614 .complete = nvme_pci_complete_rq,
1615 .init_hctx = nvme_admin_init_hctx,
1616 .init_request = nvme_init_request,
1617 .timeout = nvme_timeout,
1620 static const struct blk_mq_ops nvme_mq_ops = {
1621 .queue_rq = nvme_queue_rq,
1622 .complete = nvme_pci_complete_rq,
1623 .commit_rqs = nvme_commit_rqs,
1624 .init_hctx = nvme_init_hctx,
1625 .init_request = nvme_init_request,
1626 .map_queues = nvme_pci_map_queues,
1627 .timeout = nvme_timeout,
1631 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1633 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1635 * If the controller was reset during removal, it's possible
1636 * user requests may be waiting on a stopped queue. Start the
1637 * queue to flush these to completion.
1639 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1640 blk_cleanup_queue(dev->ctrl.admin_q);
1641 blk_mq_free_tag_set(&dev->admin_tagset);
1645 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1647 if (!dev->ctrl.admin_q) {
1648 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1649 dev->admin_tagset.nr_hw_queues = 1;
1651 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1652 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1653 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1654 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1655 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1656 dev->admin_tagset.driver_data = dev;
1658 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1660 dev->ctrl.admin_tagset = &dev->admin_tagset;
1662 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1663 if (IS_ERR(dev->ctrl.admin_q)) {
1664 blk_mq_free_tag_set(&dev->admin_tagset);
1667 if (!blk_get_queue(dev->ctrl.admin_q)) {
1668 nvme_dev_remove_admin(dev);
1669 dev->ctrl.admin_q = NULL;
1673 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1678 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1680 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1683 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1685 struct pci_dev *pdev = to_pci_dev(dev->dev);
1687 if (size <= dev->bar_mapped_size)
1689 if (size > pci_resource_len(pdev, 0))
1693 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1695 dev->bar_mapped_size = 0;
1698 dev->bar_mapped_size = size;
1699 dev->dbs = dev->bar + NVME_REG_DBS;
1704 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1708 struct nvme_queue *nvmeq;
1710 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1714 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1715 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1717 if (dev->subsystem &&
1718 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1719 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1721 result = nvme_disable_ctrl(&dev->ctrl);
1725 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1729 dev->ctrl.numa_node = dev_to_node(dev->dev);
1731 nvmeq = &dev->queues[0];
1732 aqa = nvmeq->q_depth - 1;
1735 writel(aqa, dev->bar + NVME_REG_AQA);
1736 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1737 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1739 result = nvme_enable_ctrl(&dev->ctrl);
1743 nvmeq->cq_vector = 0;
1744 nvme_init_queue(nvmeq, 0);
1745 result = queue_request_irq(nvmeq);
1747 dev->online_queues--;
1751 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1755 static int nvme_create_io_queues(struct nvme_dev *dev)
1757 unsigned i, max, rw_queues;
1760 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1761 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1767 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1768 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1769 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1770 dev->io_queues[HCTX_TYPE_READ];
1775 for (i = dev->online_queues; i <= max; i++) {
1776 bool polled = i > rw_queues;
1778 ret = nvme_create_queue(&dev->queues[i], i, polled);
1784 * Ignore failing Create SQ/CQ commands, we can continue with less
1785 * than the desired amount of queues, and even a controller without
1786 * I/O queues can still be used to issue admin commands. This might
1787 * be useful to upgrade a buggy firmware for example.
1789 return ret >= 0 ? 0 : ret;
1792 static ssize_t nvme_cmb_show(struct device *dev,
1793 struct device_attribute *attr,
1796 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1798 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1799 ndev->cmbloc, ndev->cmbsz);
1801 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1803 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1805 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1807 return 1ULL << (12 + 4 * szu);
1810 static u32 nvme_cmb_size(struct nvme_dev *dev)
1812 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1815 static void nvme_map_cmb(struct nvme_dev *dev)
1818 resource_size_t bar_size;
1819 struct pci_dev *pdev = to_pci_dev(dev->dev);
1825 if (NVME_CAP_CMBS(dev->ctrl.cap))
1826 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1828 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1831 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1833 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1834 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1835 bar = NVME_CMB_BIR(dev->cmbloc);
1836 bar_size = pci_resource_len(pdev, bar);
1838 if (offset > bar_size)
1842 * Tell the controller about the host side address mapping the CMB,
1843 * and enable CMB decoding for the NVMe 1.4+ scheme:
1845 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1846 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1847 (pci_bus_address(pdev, bar) + offset),
1848 dev->bar + NVME_REG_CMBMSC);
1852 * Controllers may support a CMB size larger than their BAR,
1853 * for example, due to being behind a bridge. Reduce the CMB to
1854 * the reported size of the BAR
1856 if (size > bar_size - offset)
1857 size = bar_size - offset;
1859 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1860 dev_warn(dev->ctrl.device,
1861 "failed to register the CMB\n");
1865 dev->cmb_size = size;
1866 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1868 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1869 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1870 pci_p2pmem_publish(pdev, true);
1872 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1873 &dev_attr_cmb.attr, NULL))
1874 dev_warn(dev->ctrl.device,
1875 "failed to add sysfs attribute for CMB\n");
1878 static inline void nvme_release_cmb(struct nvme_dev *dev)
1880 if (dev->cmb_size) {
1881 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1882 &dev_attr_cmb.attr, NULL);
1887 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1889 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1890 u64 dma_addr = dev->host_mem_descs_dma;
1891 struct nvme_command c;
1894 memset(&c, 0, sizeof(c));
1895 c.features.opcode = nvme_admin_set_features;
1896 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1897 c.features.dword11 = cpu_to_le32(bits);
1898 c.features.dword12 = cpu_to_le32(host_mem_size);
1899 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1900 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1901 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1903 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1905 dev_warn(dev->ctrl.device,
1906 "failed to set host mem (err %d, flags %#x).\n",
1912 static void nvme_free_host_mem(struct nvme_dev *dev)
1916 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1917 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1918 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1920 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1921 le64_to_cpu(desc->addr),
1922 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1925 kfree(dev->host_mem_desc_bufs);
1926 dev->host_mem_desc_bufs = NULL;
1927 dma_free_coherent(dev->dev,
1928 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1929 dev->host_mem_descs, dev->host_mem_descs_dma);
1930 dev->host_mem_descs = NULL;
1931 dev->nr_host_mem_descs = 0;
1934 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1937 struct nvme_host_mem_buf_desc *descs;
1938 u32 max_entries, len;
1939 dma_addr_t descs_dma;
1944 tmp = (preferred + chunk_size - 1);
1945 do_div(tmp, chunk_size);
1948 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1949 max_entries = dev->ctrl.hmmaxd;
1951 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1952 &descs_dma, GFP_KERNEL);
1956 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1958 goto out_free_descs;
1960 for (size = 0; size < preferred && i < max_entries; size += len) {
1961 dma_addr_t dma_addr;
1963 len = min_t(u64, chunk_size, preferred - size);
1964 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1965 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1969 descs[i].addr = cpu_to_le64(dma_addr);
1970 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1977 dev->nr_host_mem_descs = i;
1978 dev->host_mem_size = size;
1979 dev->host_mem_descs = descs;
1980 dev->host_mem_descs_dma = descs_dma;
1981 dev->host_mem_desc_bufs = bufs;
1986 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1988 dma_free_attrs(dev->dev, size, bufs[i],
1989 le64_to_cpu(descs[i].addr),
1990 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1995 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1998 dev->host_mem_descs = NULL;
2002 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2004 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2005 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2008 /* start big and work our way down */
2009 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2010 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2011 if (!min || dev->host_mem_size >= min)
2013 nvme_free_host_mem(dev);
2020 static int nvme_setup_host_mem(struct nvme_dev *dev)
2022 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2023 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2024 u64 min = (u64)dev->ctrl.hmmin * 4096;
2025 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2028 preferred = min(preferred, max);
2030 dev_warn(dev->ctrl.device,
2031 "min host memory (%lld MiB) above limit (%d MiB).\n",
2032 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2033 nvme_free_host_mem(dev);
2038 * If we already have a buffer allocated check if we can reuse it.
2040 if (dev->host_mem_descs) {
2041 if (dev->host_mem_size >= min)
2042 enable_bits |= NVME_HOST_MEM_RETURN;
2044 nvme_free_host_mem(dev);
2047 if (!dev->host_mem_descs) {
2048 if (nvme_alloc_host_mem(dev, min, preferred)) {
2049 dev_warn(dev->ctrl.device,
2050 "failed to allocate host memory buffer.\n");
2051 return 0; /* controller must work without HMB */
2054 dev_info(dev->ctrl.device,
2055 "allocated %lld MiB host memory buffer.\n",
2056 dev->host_mem_size >> ilog2(SZ_1M));
2059 ret = nvme_set_host_mem(dev, enable_bits);
2061 nvme_free_host_mem(dev);
2066 * nirqs is the number of interrupts available for write and read
2067 * queues. The core already reserved an interrupt for the admin queue.
2069 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2071 struct nvme_dev *dev = affd->priv;
2072 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2075 * If there is no interrupt available for queues, ensure that
2076 * the default queue is set to 1. The affinity set size is
2077 * also set to one, but the irq core ignores it for this case.
2079 * If only one interrupt is available or 'write_queue' == 0, combine
2080 * write and read queues.
2082 * If 'write_queues' > 0, ensure it leaves room for at least one read
2088 } else if (nrirqs == 1 || !nr_write_queues) {
2090 } else if (nr_write_queues >= nrirqs) {
2093 nr_read_queues = nrirqs - nr_write_queues;
2096 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2097 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2098 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2099 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2100 affd->nr_sets = nr_read_queues ? 2 : 1;
2103 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2105 struct pci_dev *pdev = to_pci_dev(dev->dev);
2106 struct irq_affinity affd = {
2108 .calc_sets = nvme_calc_irq_sets,
2111 unsigned int irq_queues, poll_queues;
2114 * Poll queues don't need interrupts, but we need at least one I/O queue
2115 * left over for non-polled I/O.
2117 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2118 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2121 * Initialize for the single interrupt case, will be updated in
2122 * nvme_calc_irq_sets().
2124 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2125 dev->io_queues[HCTX_TYPE_READ] = 0;
2128 * We need interrupts for the admin queue and each non-polled I/O queue,
2129 * but some Apple controllers require all queues to use the first
2133 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2134 irq_queues += (nr_io_queues - poll_queues);
2135 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2136 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2139 static void nvme_disable_io_queues(struct nvme_dev *dev)
2141 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2142 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2145 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2148 * If tags are shared with admin queue (Apple bug), then
2149 * make sure we only use one IO queue.
2151 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2153 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2156 static int nvme_setup_io_queues(struct nvme_dev *dev)
2158 struct nvme_queue *adminq = &dev->queues[0];
2159 struct pci_dev *pdev = to_pci_dev(dev->dev);
2160 unsigned int nr_io_queues;
2165 * Sample the module parameters once at reset time so that we have
2166 * stable values to work with.
2168 dev->nr_write_queues = write_queues;
2169 dev->nr_poll_queues = poll_queues;
2171 nr_io_queues = dev->nr_allocated_queues - 1;
2172 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2176 if (nr_io_queues == 0)
2179 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2181 if (dev->cmb_use_sqes) {
2182 result = nvme_cmb_qdepth(dev, nr_io_queues,
2183 sizeof(struct nvme_command));
2185 dev->q_depth = result;
2187 dev->cmb_use_sqes = false;
2191 size = db_bar_size(dev, nr_io_queues);
2192 result = nvme_remap_bar(dev, size);
2195 if (!--nr_io_queues)
2198 adminq->q_db = dev->dbs;
2201 /* Deregister the admin queue's interrupt */
2202 pci_free_irq(pdev, 0, adminq);
2205 * If we enable msix early due to not intx, disable it again before
2206 * setting up the full range we need.
2208 pci_free_irq_vectors(pdev);
2210 result = nvme_setup_irqs(dev, nr_io_queues);
2214 dev->num_vecs = result;
2215 result = max(result - 1, 1);
2216 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2219 * Should investigate if there's a performance win from allocating
2220 * more queues than interrupt vectors; it might allow the submission
2221 * path to scale better, even if the receive path is limited by the
2222 * number of interrupts.
2224 result = queue_request_irq(adminq);
2227 set_bit(NVMEQ_ENABLED, &adminq->flags);
2229 result = nvme_create_io_queues(dev);
2230 if (result || dev->online_queues < 2)
2233 if (dev->online_queues - 1 < dev->max_qid) {
2234 nr_io_queues = dev->online_queues - 1;
2235 nvme_disable_io_queues(dev);
2236 nvme_suspend_io_queues(dev);
2239 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2240 dev->io_queues[HCTX_TYPE_DEFAULT],
2241 dev->io_queues[HCTX_TYPE_READ],
2242 dev->io_queues[HCTX_TYPE_POLL]);
2246 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2248 struct nvme_queue *nvmeq = req->end_io_data;
2250 blk_mq_free_request(req);
2251 complete(&nvmeq->delete_done);
2254 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2256 struct nvme_queue *nvmeq = req->end_io_data;
2259 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2261 nvme_del_queue_end(req, error);
2264 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2266 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2267 struct request *req;
2268 struct nvme_command cmd;
2270 memset(&cmd, 0, sizeof(cmd));
2271 cmd.delete_queue.opcode = opcode;
2272 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2274 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
2276 return PTR_ERR(req);
2278 req->end_io_data = nvmeq;
2280 init_completion(&nvmeq->delete_done);
2281 blk_execute_rq_nowait(NULL, req, false,
2282 opcode == nvme_admin_delete_cq ?
2283 nvme_del_cq_end : nvme_del_queue_end);
2287 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2289 int nr_queues = dev->online_queues - 1, sent = 0;
2290 unsigned long timeout;
2293 timeout = NVME_ADMIN_TIMEOUT;
2294 while (nr_queues > 0) {
2295 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2301 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2303 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2315 static void nvme_dev_add(struct nvme_dev *dev)
2319 if (!dev->ctrl.tagset) {
2320 dev->tagset.ops = &nvme_mq_ops;
2321 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2322 dev->tagset.nr_maps = 2; /* default + read */
2323 if (dev->io_queues[HCTX_TYPE_POLL])
2324 dev->tagset.nr_maps++;
2325 dev->tagset.timeout = NVME_IO_TIMEOUT;
2326 dev->tagset.numa_node = dev->ctrl.numa_node;
2327 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2328 BLK_MQ_MAX_DEPTH) - 1;
2329 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2330 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2331 dev->tagset.driver_data = dev;
2334 * Some Apple controllers requires tags to be unique
2335 * across admin and IO queue, so reserve the first 32
2336 * tags of the IO queue.
2338 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2339 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2341 ret = blk_mq_alloc_tag_set(&dev->tagset);
2343 dev_warn(dev->ctrl.device,
2344 "IO queues tagset allocation failed %d\n", ret);
2347 dev->ctrl.tagset = &dev->tagset;
2349 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2351 /* Free previously allocated queues that are no longer usable */
2352 nvme_free_queues(dev, dev->online_queues);
2355 nvme_dbbuf_set(dev);
2358 static int nvme_pci_enable(struct nvme_dev *dev)
2360 int result = -ENOMEM;
2361 struct pci_dev *pdev = to_pci_dev(dev->dev);
2362 int dma_address_bits = 64;
2364 if (pci_enable_device_mem(pdev))
2367 pci_set_master(pdev);
2369 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2370 dma_address_bits = 48;
2371 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2374 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2380 * Some devices and/or platforms don't advertise or work with INTx
2381 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2382 * adjust this later.
2384 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2388 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2390 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2392 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2393 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2394 dev->dbs = dev->bar + 4096;
2397 * Some Apple controllers require a non-standard SQE size.
2398 * Interestingly they also seem to ignore the CC:IOSQES register
2399 * so we don't bother updating it here.
2401 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2404 dev->io_sqes = NVME_NVM_IOSQES;
2407 * Temporary fix for the Apple controller found in the MacBook8,1 and
2408 * some MacBook7,1 to avoid controller resets and data loss.
2410 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2412 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2413 "set queue depth=%u to work around controller resets\n",
2415 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2416 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2417 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2419 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2420 "set queue depth=%u\n", dev->q_depth);
2424 * Controllers with the shared tags quirk need the IO queue to be
2425 * big enough so that we get 32 tags for the admin queue
2427 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2428 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2429 dev->q_depth = NVME_AQ_DEPTH + 2;
2430 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2437 pci_enable_pcie_error_reporting(pdev);
2438 pci_save_state(pdev);
2442 pci_disable_device(pdev);
2446 static void nvme_dev_unmap(struct nvme_dev *dev)
2450 pci_release_mem_regions(to_pci_dev(dev->dev));
2453 static void nvme_pci_disable(struct nvme_dev *dev)
2455 struct pci_dev *pdev = to_pci_dev(dev->dev);
2457 pci_free_irq_vectors(pdev);
2459 if (pci_is_enabled(pdev)) {
2460 pci_disable_pcie_error_reporting(pdev);
2461 pci_disable_device(pdev);
2465 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2467 bool dead = true, freeze = false;
2468 struct pci_dev *pdev = to_pci_dev(dev->dev);
2470 mutex_lock(&dev->shutdown_lock);
2471 if (pci_is_enabled(pdev)) {
2472 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2474 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2475 dev->ctrl.state == NVME_CTRL_RESETTING) {
2477 nvme_start_freeze(&dev->ctrl);
2479 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2480 pdev->error_state != pci_channel_io_normal);
2484 * Give the controller a chance to complete all entered requests if
2485 * doing a safe shutdown.
2487 if (!dead && shutdown && freeze)
2488 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2490 nvme_stop_queues(&dev->ctrl);
2492 if (!dead && dev->ctrl.queue_count > 0) {
2493 nvme_disable_io_queues(dev);
2494 nvme_disable_admin_queue(dev, shutdown);
2496 nvme_suspend_io_queues(dev);
2497 nvme_suspend_queue(&dev->queues[0]);
2498 nvme_pci_disable(dev);
2499 nvme_reap_pending_cqes(dev);
2501 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2502 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2503 blk_mq_tagset_wait_completed_request(&dev->tagset);
2504 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2507 * The driver will not be starting up queues again if shutting down so
2508 * must flush all entered requests to their failed completion to avoid
2509 * deadlocking blk-mq hot-cpu notifier.
2512 nvme_start_queues(&dev->ctrl);
2513 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2514 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2516 mutex_unlock(&dev->shutdown_lock);
2519 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2521 if (!nvme_wait_reset(&dev->ctrl))
2523 nvme_dev_disable(dev, shutdown);
2527 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2529 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2530 NVME_CTRL_PAGE_SIZE,
2531 NVME_CTRL_PAGE_SIZE, 0);
2532 if (!dev->prp_page_pool)
2535 /* Optimisation for I/Os between 4k and 128k */
2536 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2538 if (!dev->prp_small_pool) {
2539 dma_pool_destroy(dev->prp_page_pool);
2545 static void nvme_release_prp_pools(struct nvme_dev *dev)
2547 dma_pool_destroy(dev->prp_page_pool);
2548 dma_pool_destroy(dev->prp_small_pool);
2551 static void nvme_free_tagset(struct nvme_dev *dev)
2553 if (dev->tagset.tags)
2554 blk_mq_free_tag_set(&dev->tagset);
2555 dev->ctrl.tagset = NULL;
2558 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2560 struct nvme_dev *dev = to_nvme_dev(ctrl);
2562 nvme_dbbuf_dma_free(dev);
2563 nvme_free_tagset(dev);
2564 if (dev->ctrl.admin_q)
2565 blk_put_queue(dev->ctrl.admin_q);
2566 free_opal_dev(dev->ctrl.opal_dev);
2567 mempool_destroy(dev->iod_mempool);
2568 put_device(dev->dev);
2573 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2576 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2577 * may be holding this pci_dev's device lock.
2579 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2580 nvme_get_ctrl(&dev->ctrl);
2581 nvme_dev_disable(dev, false);
2582 nvme_kill_queues(&dev->ctrl);
2583 if (!queue_work(nvme_wq, &dev->remove_work))
2584 nvme_put_ctrl(&dev->ctrl);
2587 static void nvme_reset_work(struct work_struct *work)
2589 struct nvme_dev *dev =
2590 container_of(work, struct nvme_dev, ctrl.reset_work);
2591 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2594 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2600 * If we're called to reset a live controller first shut it down before
2603 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2604 nvme_dev_disable(dev, false);
2605 nvme_sync_queues(&dev->ctrl);
2607 mutex_lock(&dev->shutdown_lock);
2608 result = nvme_pci_enable(dev);
2612 result = nvme_pci_configure_admin_queue(dev);
2616 result = nvme_alloc_admin_tags(dev);
2621 * Limit the max command size to prevent iod->sg allocations going
2622 * over a single page.
2624 dev->ctrl.max_hw_sectors = min_t(u32,
2625 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2626 dev->ctrl.max_segments = NVME_MAX_SEGS;
2629 * Don't limit the IOMMU merged segment size.
2631 dma_set_max_seg_size(dev->dev, 0xffffffff);
2632 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2634 mutex_unlock(&dev->shutdown_lock);
2637 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2638 * initializing procedure here.
2640 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2641 dev_warn(dev->ctrl.device,
2642 "failed to mark controller CONNECTING\n");
2648 * We do not support an SGL for metadata (yet), so we are limited to a
2649 * single integrity segment for the separate metadata pointer.
2651 dev->ctrl.max_integrity_segments = 1;
2653 result = nvme_init_ctrl_finish(&dev->ctrl);
2657 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2658 if (!dev->ctrl.opal_dev)
2659 dev->ctrl.opal_dev =
2660 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2661 else if (was_suspend)
2662 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2664 free_opal_dev(dev->ctrl.opal_dev);
2665 dev->ctrl.opal_dev = NULL;
2668 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2669 result = nvme_dbbuf_dma_alloc(dev);
2672 "unable to allocate dma for dbbuf\n");
2675 if (dev->ctrl.hmpre) {
2676 result = nvme_setup_host_mem(dev);
2681 result = nvme_setup_io_queues(dev);
2686 * Keep the controller around but remove all namespaces if we don't have
2687 * any working I/O queue.
2689 if (dev->online_queues < 2) {
2690 dev_warn(dev->ctrl.device, "IO queues not created\n");
2691 nvme_kill_queues(&dev->ctrl);
2692 nvme_remove_namespaces(&dev->ctrl);
2693 nvme_free_tagset(dev);
2695 nvme_start_queues(&dev->ctrl);
2696 nvme_wait_freeze(&dev->ctrl);
2698 nvme_unfreeze(&dev->ctrl);
2702 * If only admin queue live, keep it to do further investigation or
2705 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2706 dev_warn(dev->ctrl.device,
2707 "failed to mark controller live state\n");
2712 nvme_start_ctrl(&dev->ctrl);
2716 mutex_unlock(&dev->shutdown_lock);
2719 dev_warn(dev->ctrl.device,
2720 "Removing after probe failure status: %d\n", result);
2721 nvme_remove_dead_ctrl(dev);
2724 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2726 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2727 struct pci_dev *pdev = to_pci_dev(dev->dev);
2729 if (pci_get_drvdata(pdev))
2730 device_release_driver(&pdev->dev);
2731 nvme_put_ctrl(&dev->ctrl);
2734 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2736 *val = readl(to_nvme_dev(ctrl)->bar + off);
2740 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2742 writel(val, to_nvme_dev(ctrl)->bar + off);
2746 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2748 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2752 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2754 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2756 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2759 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2761 .module = THIS_MODULE,
2762 .flags = NVME_F_METADATA_SUPPORTED |
2764 .reg_read32 = nvme_pci_reg_read32,
2765 .reg_write32 = nvme_pci_reg_write32,
2766 .reg_read64 = nvme_pci_reg_read64,
2767 .free_ctrl = nvme_pci_free_ctrl,
2768 .submit_async_event = nvme_pci_submit_async_event,
2769 .get_address = nvme_pci_get_address,
2772 static int nvme_dev_map(struct nvme_dev *dev)
2774 struct pci_dev *pdev = to_pci_dev(dev->dev);
2776 if (pci_request_mem_regions(pdev, "nvme"))
2779 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2784 pci_release_mem_regions(pdev);
2788 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2790 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2792 * Several Samsung devices seem to drop off the PCIe bus
2793 * randomly when APST is on and uses the deepest sleep state.
2794 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2795 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2796 * 950 PRO 256GB", but it seems to be restricted to two Dell
2799 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2800 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2801 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2802 return NVME_QUIRK_NO_DEEPEST_PS;
2803 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2805 * Samsung SSD 960 EVO drops off the PCIe bus after system
2806 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2807 * within few minutes after bootup on a Coffee Lake board -
2810 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2811 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2812 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2813 return NVME_QUIRK_NO_APST;
2814 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2815 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2816 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2818 * Forcing to use host managed nvme power settings for
2819 * lowest idle power with quick resume latency on
2820 * Samsung and Toshiba SSDs based on suspend behavior
2821 * on Coffee Lake board for LENOVO C640
2823 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2824 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2825 return NVME_QUIRK_SIMPLE_SUSPEND;
2832 static bool nvme_acpi_storage_d3(struct pci_dev *dev)
2834 struct acpi_device *adev;
2835 struct pci_dev *root;
2841 * Look for _DSD property specifying that the storage device on the port
2842 * must use D3 to support deep platform power savings during
2845 root = pcie_find_root_port(dev);
2849 adev = ACPI_COMPANION(&root->dev);
2854 * The property is defined in the PXSX device for South complex ports
2855 * and in the PEGP device for North complex ports.
2857 status = acpi_get_handle(adev->handle, "PXSX", &handle);
2858 if (ACPI_FAILURE(status)) {
2859 status = acpi_get_handle(adev->handle, "PEGP", &handle);
2860 if (ACPI_FAILURE(status))
2864 if (acpi_bus_get_device(handle, &adev))
2867 if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
2873 static inline bool nvme_acpi_storage_d3(struct pci_dev *dev)
2877 #endif /* CONFIG_ACPI */
2879 static void nvme_async_probe(void *data, async_cookie_t cookie)
2881 struct nvme_dev *dev = data;
2883 flush_work(&dev->ctrl.reset_work);
2884 flush_work(&dev->ctrl.scan_work);
2885 nvme_put_ctrl(&dev->ctrl);
2888 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2890 int node, result = -ENOMEM;
2891 struct nvme_dev *dev;
2892 unsigned long quirks = id->driver_data;
2895 node = dev_to_node(&pdev->dev);
2896 if (node == NUMA_NO_NODE)
2897 set_dev_node(&pdev->dev, first_memory_node);
2899 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2903 dev->nr_write_queues = write_queues;
2904 dev->nr_poll_queues = poll_queues;
2905 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2906 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2907 sizeof(struct nvme_queue), GFP_KERNEL, node);
2911 dev->dev = get_device(&pdev->dev);
2912 pci_set_drvdata(pdev, dev);
2914 result = nvme_dev_map(dev);
2918 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2919 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2920 mutex_init(&dev->shutdown_lock);
2922 result = nvme_setup_prp_pools(dev);
2926 quirks |= check_vendor_combination_bug(pdev);
2928 if (!noacpi && nvme_acpi_storage_d3(pdev)) {
2930 * Some systems use a bios work around to ask for D3 on
2931 * platforms that support kernel managed suspend.
2933 dev_info(&pdev->dev,
2934 "platform quirk: setting simple suspend\n");
2935 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2939 * Double check that our mempool alloc size will cover the biggest
2940 * command we support.
2942 alloc_size = nvme_pci_iod_alloc_size();
2943 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2945 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2947 (void *) alloc_size,
2949 if (!dev->iod_mempool) {
2954 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2957 goto release_mempool;
2959 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2961 nvme_reset_ctrl(&dev->ctrl);
2962 async_schedule(nvme_async_probe, dev);
2967 mempool_destroy(dev->iod_mempool);
2969 nvme_release_prp_pools(dev);
2971 nvme_dev_unmap(dev);
2973 put_device(dev->dev);
2980 static void nvme_reset_prepare(struct pci_dev *pdev)
2982 struct nvme_dev *dev = pci_get_drvdata(pdev);
2985 * We don't need to check the return value from waiting for the reset
2986 * state as pci_dev device lock is held, making it impossible to race
2989 nvme_disable_prepare_reset(dev, false);
2990 nvme_sync_queues(&dev->ctrl);
2993 static void nvme_reset_done(struct pci_dev *pdev)
2995 struct nvme_dev *dev = pci_get_drvdata(pdev);
2997 if (!nvme_try_sched_reset(&dev->ctrl))
2998 flush_work(&dev->ctrl.reset_work);
3001 static void nvme_shutdown(struct pci_dev *pdev)
3003 struct nvme_dev *dev = pci_get_drvdata(pdev);
3005 nvme_disable_prepare_reset(dev, true);
3009 * The driver's remove may be called on a device in a partially initialized
3010 * state. This function must not have any dependencies on the device state in
3013 static void nvme_remove(struct pci_dev *pdev)
3015 struct nvme_dev *dev = pci_get_drvdata(pdev);
3017 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3018 pci_set_drvdata(pdev, NULL);
3020 if (!pci_device_is_present(pdev)) {
3021 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3022 nvme_dev_disable(dev, true);
3023 nvme_dev_remove_admin(dev);
3026 flush_work(&dev->ctrl.reset_work);
3027 nvme_stop_ctrl(&dev->ctrl);
3028 nvme_remove_namespaces(&dev->ctrl);
3029 nvme_dev_disable(dev, true);
3030 nvme_release_cmb(dev);
3031 nvme_free_host_mem(dev);
3032 nvme_dev_remove_admin(dev);
3033 nvme_free_queues(dev, 0);
3034 nvme_release_prp_pools(dev);
3035 nvme_dev_unmap(dev);
3036 nvme_uninit_ctrl(&dev->ctrl);
3039 #ifdef CONFIG_PM_SLEEP
3040 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3042 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3045 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3047 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3050 static int nvme_resume(struct device *dev)
3052 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3053 struct nvme_ctrl *ctrl = &ndev->ctrl;
3055 if (ndev->last_ps == U32_MAX ||
3056 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3057 return nvme_try_sched_reset(&ndev->ctrl);
3061 static int nvme_suspend(struct device *dev)
3063 struct pci_dev *pdev = to_pci_dev(dev);
3064 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3065 struct nvme_ctrl *ctrl = &ndev->ctrl;
3068 ndev->last_ps = U32_MAX;
3071 * The platform does not remove power for a kernel managed suspend so
3072 * use host managed nvme power settings for lowest idle power if
3073 * possible. This should have quicker resume latency than a full device
3074 * shutdown. But if the firmware is involved after the suspend or the
3075 * device does not support any non-default power states, shut down the
3078 * If ASPM is not enabled for the device, shut down the device and allow
3079 * the PCI bus layer to put it into D3 in order to take the PCIe link
3080 * down, so as to allow the platform to achieve its minimum low-power
3081 * state (which may not be possible if the link is up).
3083 * If a host memory buffer is enabled, shut down the device as the NVMe
3084 * specification allows the device to access the host memory buffer in
3085 * host DRAM from all power states, but hosts will fail access to DRAM
3088 if (pm_suspend_via_firmware() || !ctrl->npss ||
3089 !pcie_aspm_enabled(pdev) ||
3090 ndev->nr_host_mem_descs ||
3091 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3092 return nvme_disable_prepare_reset(ndev, true);
3094 nvme_start_freeze(ctrl);
3095 nvme_wait_freeze(ctrl);
3096 nvme_sync_queues(ctrl);
3098 if (ctrl->state != NVME_CTRL_LIVE)
3101 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3106 * A saved state prevents pci pm from generically controlling the
3107 * device's power. If we're using protocol specific settings, we don't
3108 * want pci interfering.
3110 pci_save_state(pdev);
3112 ret = nvme_set_power_state(ctrl, ctrl->npss);
3117 /* discard the saved state */
3118 pci_load_saved_state(pdev, NULL);
3121 * Clearing npss forces a controller reset on resume. The
3122 * correct value will be rediscovered then.
3124 ret = nvme_disable_prepare_reset(ndev, true);
3128 nvme_unfreeze(ctrl);
3132 static int nvme_simple_suspend(struct device *dev)
3134 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3136 return nvme_disable_prepare_reset(ndev, true);
3139 static int nvme_simple_resume(struct device *dev)
3141 struct pci_dev *pdev = to_pci_dev(dev);
3142 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3144 return nvme_try_sched_reset(&ndev->ctrl);
3147 static const struct dev_pm_ops nvme_dev_pm_ops = {
3148 .suspend = nvme_suspend,
3149 .resume = nvme_resume,
3150 .freeze = nvme_simple_suspend,
3151 .thaw = nvme_simple_resume,
3152 .poweroff = nvme_simple_suspend,
3153 .restore = nvme_simple_resume,
3155 #endif /* CONFIG_PM_SLEEP */
3157 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3158 pci_channel_state_t state)
3160 struct nvme_dev *dev = pci_get_drvdata(pdev);
3163 * A frozen channel requires a reset. When detected, this method will
3164 * shutdown the controller to quiesce. The controller will be restarted
3165 * after the slot reset through driver's slot_reset callback.
3168 case pci_channel_io_normal:
3169 return PCI_ERS_RESULT_CAN_RECOVER;
3170 case pci_channel_io_frozen:
3171 dev_warn(dev->ctrl.device,
3172 "frozen state error detected, reset controller\n");
3173 nvme_dev_disable(dev, false);
3174 return PCI_ERS_RESULT_NEED_RESET;
3175 case pci_channel_io_perm_failure:
3176 dev_warn(dev->ctrl.device,
3177 "failure state error detected, request disconnect\n");
3178 return PCI_ERS_RESULT_DISCONNECT;
3180 return PCI_ERS_RESULT_NEED_RESET;
3183 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3185 struct nvme_dev *dev = pci_get_drvdata(pdev);
3187 dev_info(dev->ctrl.device, "restart after slot reset\n");
3188 pci_restore_state(pdev);
3189 nvme_reset_ctrl(&dev->ctrl);
3190 return PCI_ERS_RESULT_RECOVERED;
3193 static void nvme_error_resume(struct pci_dev *pdev)
3195 struct nvme_dev *dev = pci_get_drvdata(pdev);
3197 flush_work(&dev->ctrl.reset_work);
3200 static const struct pci_error_handlers nvme_err_handler = {
3201 .error_detected = nvme_error_detected,
3202 .slot_reset = nvme_slot_reset,
3203 .resume = nvme_error_resume,
3204 .reset_prepare = nvme_reset_prepare,
3205 .reset_done = nvme_reset_done,
3208 static const struct pci_device_id nvme_id_table[] = {
3209 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3210 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3211 NVME_QUIRK_DEALLOCATE_ZEROES, },
3212 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
3213 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3214 NVME_QUIRK_DEALLOCATE_ZEROES, },
3215 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
3216 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3217 NVME_QUIRK_DEALLOCATE_ZEROES, },
3218 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
3219 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3220 NVME_QUIRK_DEALLOCATE_ZEROES, },
3221 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3222 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3223 NVME_QUIRK_MEDIUM_PRIO_SQ |
3224 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3225 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3226 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3227 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3228 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3229 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3230 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3231 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3232 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3233 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3234 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3235 NVME_QUIRK_NO_NS_DESC_LIST, },
3236 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3237 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3238 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3239 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3240 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3241 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3242 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3243 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3244 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3245 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3246 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3247 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3248 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3249 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3250 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3251 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3252 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3253 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3254 .driver_data = NVME_QUIRK_LIGHTNVM, },
3255 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3256 .driver_data = NVME_QUIRK_LIGHTNVM, },
3257 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3258 .driver_data = NVME_QUIRK_LIGHTNVM, },
3259 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3260 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3261 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3262 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3263 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3264 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3265 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3266 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3267 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3268 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3269 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3270 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3271 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3272 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3273 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3274 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3275 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3276 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3277 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3278 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3279 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3280 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3281 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3282 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3283 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3284 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3285 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3286 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3287 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3288 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3289 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3290 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3291 NVME_QUIRK_128_BYTES_SQES |
3292 NVME_QUIRK_SHARED_TAGS },
3294 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3297 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3299 static struct pci_driver nvme_driver = {
3301 .id_table = nvme_id_table,
3302 .probe = nvme_probe,
3303 .remove = nvme_remove,
3304 .shutdown = nvme_shutdown,
3305 #ifdef CONFIG_PM_SLEEP
3307 .pm = &nvme_dev_pm_ops,
3310 .sriov_configure = pci_sriov_configure_simple,
3311 .err_handler = &nvme_err_handler,
3314 static int __init nvme_init(void)
3316 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3317 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3318 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3319 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3321 return pci_register_driver(&nvme_driver);
3324 static void __exit nvme_exit(void)
3326 pci_unregister_driver(&nvme_driver);
3327 flush_workqueue(nvme_wq);
3330 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3331 MODULE_LICENSE("GPL");
3332 MODULE_VERSION("1.0");
3333 module_init(nvme_init);
3334 module_exit(nvme_exit);