drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/blk-mq-pci.h>
  20 #include <linux/cpu.h>
  21 #include <linux/delay.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/hdreg.h>
  26 #include <linux/idr.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/kdev_t.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/mutex.h>
  36 #include <linux/pci.h>
  37 #include <linux/poison.h>
  38 #include <linux/ptrace.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/t10-pi.h>
  42 #include <linux/timer.h>
  43 #include <linux/types.h>
  44 #include <linux/io-64-nonatomic-lo-hi.h>
  45 #include <asm/unaligned.h>
  46 #include <linux/sed-opal.h>
  47
  48 #include "nvme.h"
  49
  50 #define NVME_Q_DEPTH            1024
  51 #define NVME_AQ_DEPTH           256
  52 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  53 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  54
  55 /*
  56  * We handle AEN commands ourselves and don't even let the
  57  * block layer know about them.
  58  */
  59 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AERS)
  60
  61 static int use_threaded_interrupts;
  62 module_param(use_threaded_interrupts, int, 0);
  63
  64 static bool use_cmb_sqes = true;
  65 module_param(use_cmb_sqes, bool, 0644);
  66 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  67
  68 static struct workqueue_struct *nvme_workq;
  69
  70 struct nvme_dev;
  71 struct nvme_queue;
  72
  73 static int nvme_reset(struct nvme_dev *dev);
  74 static void nvme_process_cq(struct nvme_queue *nvmeq);
  75 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  76
  77 /*
  78  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  79  */
  80 struct nvme_dev {
  81         struct nvme_queue **queues;
  82         struct blk_mq_tag_set tagset;
  83         struct blk_mq_tag_set admin_tagset;
  84         u32 __iomem *dbs;
  85         struct device *dev;
  86         struct dma_pool *prp_page_pool;
  87         struct dma_pool *prp_small_pool;
  88         unsigned queue_count;
  89         unsigned online_queues;
  90         unsigned max_qid;
  91         int q_depth;
  92         u32 db_stride;
  93         void __iomem *bar;
  94         struct work_struct reset_work;
  95         struct work_struct remove_work;
  96         struct timer_list watchdog_timer;
  97         struct mutex shutdown_lock;
  98         bool subsystem;
  99         void __iomem *cmb;
 100         dma_addr_t cmb_dma_addr;
 101         u64 cmb_size;
 102         u32 cmbsz;
 103         u32 cmbloc;
 104         struct nvme_ctrl ctrl;
 105         struct completion ioq_wait;
 106 };
 107
 108 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 109 {
 110         return container_of(ctrl, struct nvme_dev, ctrl);
 111 }
 112
 113 /*
 114  * An NVM Express queue.  Each device has at least two (one for admin
 115  * commands and one for I/O commands).
 116  */
 117 struct nvme_queue {
 118         struct device *q_dmadev;
 119         struct nvme_dev *dev;
 120         char irqname[24];       /* nvme4294967295-65535\0 */
 121         spinlock_t q_lock;
 122         struct nvme_command *sq_cmds;
 123         struct nvme_command __iomem *sq_cmds_io;
 124         volatile struct nvme_completion *cqes;
 125         struct blk_mq_tags **tags;
 126         dma_addr_t sq_dma_addr;
 127         dma_addr_t cq_dma_addr;
 128         u32 __iomem *q_db;
 129         u16 q_depth;
 130         s16 cq_vector;
 131         u16 sq_tail;
 132         u16 cq_head;
 133         u16 qid;
 134         u8 cq_phase;
 135         u8 cqe_seen;
 136 };
 137
 138 /*
 139  * The nvme_iod describes the data in an I/O, including the list of PRP
 140  * entries.  You can't see it in this data structure because C doesn't let
 141  * me express that.  Use nvme_init_iod to ensure there's enough space
 142  * allocated to store the PRP list.
 143  */
 144 struct nvme_iod {
 145         struct nvme_request req;
 146         struct nvme_queue *nvmeq;
 147         int aborted;
 148         int npages;             /* In the PRP list. 0 means small pool in use */
 149         int nents;              /* Used in scatterlist */
 150         int length;             /* Of data, in bytes */
 151         dma_addr_t first_dma;
 152         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 153         struct scatterlist *sg;
 154         struct scatterlist inline_sg[0];
 155 };
 156
 157 /*
 158  * Check we didin't inadvertently grow the command struct
 159  */
 160 static inline void _nvme_check_size(void)
 161 {
 162         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 163         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 164         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 165         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 166         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 167         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 168         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 169         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 170         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 171         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 172         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 173         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 174 }
 175
 176 /*
 177  * Max size of iod being embedded in the request payload
 178  */
 179 #define NVME_INT_PAGES          2
 180 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 181
 182 /*
 183  * Will slightly overestimate the number of pages needed.  This is OK
 184  * as it only leads to a small amount of wasted memory for the lifetime of
 185  * the I/O.
 186  */
 187 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 188 {
 189         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 190                                       dev->ctrl.page_size);
 191         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 192 }
 193
 194 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 195                 unsigned int size, unsigned int nseg)
 196 {
 197         return sizeof(__le64 *) * nvme_npages(size, dev) +
 198                         sizeof(struct scatterlist) * nseg;
 199 }
 200
 201 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 202 {
 203         return sizeof(struct nvme_iod) +
 204                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 205 }
 206
 207 static int nvmeq_irq(struct nvme_queue *nvmeq)
 208 {
 209         return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector);
 210 }
 211
 212 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 213                                 unsigned int hctx_idx)
 214 {
 215         struct nvme_dev *dev = data;
 216         struct nvme_queue *nvmeq = dev->queues[0];
 217
 218         WARN_ON(hctx_idx != 0);
 219         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 220         WARN_ON(nvmeq->tags);
 221
 222         hctx->driver_data = nvmeq;
 223         nvmeq->tags = &dev->admin_tagset.tags[0];
 224         return 0;
 225 }
 226
 227 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 228 {
 229         struct nvme_queue *nvmeq = hctx->driver_data;
 230
 231         nvmeq->tags = NULL;
 232 }
 233
 234 static int nvme_admin_init_request(void *data, struct request *req,
 235                                 unsigned int hctx_idx, unsigned int rq_idx,
 236                                 unsigned int numa_node)
 237 {
 238         struct nvme_dev *dev = data;
 239         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 240         struct nvme_queue *nvmeq = dev->queues[0];
 241
 242         BUG_ON(!nvmeq);
 243         iod->nvmeq = nvmeq;
 244         return 0;
 245 }
 246
 247 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 248                           unsigned int hctx_idx)
 249 {
 250         struct nvme_dev *dev = data;
 251         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 252
 253         if (!nvmeq->tags)
 254                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 255
 256         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 257         hctx->driver_data = nvmeq;
 258         return 0;
 259 }
 260
 261 static int nvme_init_request(void *data, struct request *req,
 262                                 unsigned int hctx_idx, unsigned int rq_idx,
 263                                 unsigned int numa_node)
 264 {
 265         struct nvme_dev *dev = data;
 266         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 267         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 268
 269         BUG_ON(!nvmeq);
 270         iod->nvmeq = nvmeq;
 271         return 0;
 272 }
 273
 274 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 275 {
 276         struct nvme_dev *dev = set->driver_data;
 277
 278         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
 279 }
 280
 281 /**
 282  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 283  * @nvmeq: The queue to use
 284  * @cmd: The command to send
 285  *
 286  * Safe to use from interrupt context
 287  */
 288 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 289                                                 struct nvme_command *cmd)
 290 {
 291         u16 tail = nvmeq->sq_tail;
 292
 293         if (nvmeq->sq_cmds_io)
 294                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 295         else
 296                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 297
 298         if (++tail == nvmeq->q_depth)
 299                 tail = 0;
 300         writel(tail, nvmeq->q_db);
 301         nvmeq->sq_tail = tail;
 302 }
 303
 304 static __le64 **iod_list(struct request *req)
 305 {
 306         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 307         return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
 308 }
 309
 310 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 311 {
 312         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 313         int nseg = blk_rq_nr_phys_segments(rq);
 314         unsigned int size = blk_rq_payload_bytes(rq);
 315
 316         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 317                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 318                 if (!iod->sg)
 319                         return BLK_MQ_RQ_QUEUE_BUSY;
 320         } else {
 321                 iod->sg = iod->inline_sg;
 322         }
 323
 324         iod->aborted = 0;
 325         iod->npages = -1;
 326         iod->nents = 0;
 327         iod->length = size;
 328
 329         if (!(rq->rq_flags & RQF_DONTPREP)) {
 330                 rq->retries = 0;
 331                 rq->rq_flags |= RQF_DONTPREP;
 332         }
 333         return BLK_MQ_RQ_QUEUE_OK;
 334 }
 335
 336 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 337 {
 338         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 339         const int last_prp = dev->ctrl.page_size / 8 - 1;
 340         int i;
 341         __le64 **list = iod_list(req);
 342         dma_addr_t prp_dma = iod->first_dma;
 343
 344         if (iod->npages == 0)
 345                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 346         for (i = 0; i < iod->npages; i++) {
 347                 __le64 *prp_list = list[i];
 348                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 349                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 350                 prp_dma = next_prp_dma;
 351         }
 352
 353         if (iod->sg != iod->inline_sg)
 354                 kfree(iod->sg);
 355 }
 356
 357 #ifdef CONFIG_BLK_DEV_INTEGRITY
 358 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 359 {
 360         if (be32_to_cpu(pi->ref_tag) == v)
 361                 pi->ref_tag = cpu_to_be32(p);
 362 }
 363
 364 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 365 {
 366         if (be32_to_cpu(pi->ref_tag) == p)
 367                 pi->ref_tag = cpu_to_be32(v);
 368 }
 369
 370 /**
 371  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 372  *
 373  * The virtual start sector is the one that was originally submitted by the
 374  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 375  * start sector may be different. Remap protection information to match the
 376  * physical LBA on writes, and back to the original seed on reads.
 377  *
 378  * Type 0 and 3 do not have a ref tag, so no remapping required.
 379  */
 380 static void nvme_dif_remap(struct request *req,
 381                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 382 {
 383         struct nvme_ns *ns = req->rq_disk->private_data;
 384         struct bio_integrity_payload *bip;
 385         struct t10_pi_tuple *pi;
 386         void *p, *pmap;
 387         u32 i, nlb, ts, phys, virt;
 388
 389         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 390                 return;
 391
 392         bip = bio_integrity(req->bio);
 393         if (!bip)
 394                 return;
 395
 396         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 397
 398         p = pmap;
 399         virt = bip_get_seed(bip);
 400         phys = nvme_block_nr(ns, blk_rq_pos(req));
 401         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 402         ts = ns->disk->queue->integrity.tuple_size;
 403
 404         for (i = 0; i < nlb; i++, virt++, phys++) {
 405                 pi = (struct t10_pi_tuple *)p;
 406                 dif_swap(phys, virt, pi);
 407                 p += ts;
 408         }
 409         kunmap_atomic(pmap);
 410 }
 411 #else /* CONFIG_BLK_DEV_INTEGRITY */
 412 static void nvme_dif_remap(struct request *req,
 413                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 414 {
 415 }
 416 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 417 {
 418 }
 419 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 420 {
 421 }
 422 #endif
 423
 424 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req)
 425 {
 426         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 427         struct dma_pool *pool;
 428         int length = blk_rq_payload_bytes(req);
 429         struct scatterlist *sg = iod->sg;
 430         int dma_len = sg_dma_len(sg);
 431         u64 dma_addr = sg_dma_address(sg);
 432         u32 page_size = dev->ctrl.page_size;
 433         int offset = dma_addr & (page_size - 1);
 434         __le64 *prp_list;
 435         __le64 **list = iod_list(req);
 436         dma_addr_t prp_dma;
 437         int nprps, i;
 438
 439         length -= (page_size - offset);
 440         if (length <= 0)
 441                 return true;
 442
 443         dma_len -= (page_size - offset);
 444         if (dma_len) {
 445                 dma_addr += (page_size - offset);
 446         } else {
 447                 sg = sg_next(sg);
 448                 dma_addr = sg_dma_address(sg);
 449                 dma_len = sg_dma_len(sg);
 450         }
 451
 452         if (length <= page_size) {
 453                 iod->first_dma = dma_addr;
 454                 return true;
 455         }
 456
 457         nprps = DIV_ROUND_UP(length, page_size);
 458         if (nprps <= (256 / 8)) {
 459                 pool = dev->prp_small_pool;
 460                 iod->npages = 0;
 461         } else {
 462                 pool = dev->prp_page_pool;
 463                 iod->npages = 1;
 464         }
 465
 466         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 467         if (!prp_list) {
 468                 iod->first_dma = dma_addr;
 469                 iod->npages = -1;
 470                 return false;
 471         }
 472         list[0] = prp_list;
 473         iod->first_dma = prp_dma;
 474         i = 0;
 475         for (;;) {
 476                 if (i == page_size >> 3) {
 477                         __le64 *old_prp_list = prp_list;
 478                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 479                         if (!prp_list)
 480                                 return false;
 481                         list[iod->npages++] = prp_list;
 482                         prp_list[0] = old_prp_list[i - 1];
 483                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 484                         i = 1;
 485                 }
 486                 prp_list[i++] = cpu_to_le64(dma_addr);
 487                 dma_len -= page_size;
 488                 dma_addr += page_size;
 489                 length -= page_size;
 490                 if (length <= 0)
 491                         break;
 492                 if (dma_len > 0)
 493                         continue;
 494                 BUG_ON(dma_len < 0);
 495                 sg = sg_next(sg);
 496                 dma_addr = sg_dma_address(sg);
 497                 dma_len = sg_dma_len(sg);
 498         }
 499
 500         return true;
 501 }
 502
 503 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 504                 struct nvme_command *cmnd)
 505 {
 506         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 507         struct request_queue *q = req->q;
 508         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 509                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 510         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 511
 512         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 513         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 514         if (!iod->nents)
 515                 goto out;
 516
 517         ret = BLK_MQ_RQ_QUEUE_BUSY;
 518         if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 519                                 DMA_ATTR_NO_WARN))
 520                 goto out;
 521
 522         if (!nvme_setup_prps(dev, req))
 523                 goto out_unmap;
 524
 525         ret = BLK_MQ_RQ_QUEUE_ERROR;
 526         if (blk_integrity_rq(req)) {
 527                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 528                         goto out_unmap;
 529
 530                 sg_init_table(&iod->meta_sg, 1);
 531                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 532                         goto out_unmap;
 533
 534                 if (rq_data_dir(req))
 535                         nvme_dif_remap(req, nvme_dif_prep);
 536
 537                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 538                         goto out_unmap;
 539         }
 540
 541         cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 542         cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
 543         if (blk_integrity_rq(req))
 544                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 545         return BLK_MQ_RQ_QUEUE_OK;
 546
 547 out_unmap:
 548         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 549 out:
 550         return ret;
 551 }
 552
 553 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 554 {
 555         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 556         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 557                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 558
 559         if (iod->nents) {
 560                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 561                 if (blk_integrity_rq(req)) {
 562                         if (!rq_data_dir(req))
 563                                 nvme_dif_remap(req, nvme_dif_complete);
 564                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 565                 }
 566         }
 567
 568         nvme_cleanup_cmd(req);
 569         nvme_free_iod(dev, req);
 570 }
 571
 572 /*
 573  * NOTE: ns is NULL when called on the admin queue.
 574  */
 575 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 576                          const struct blk_mq_queue_data *bd)
 577 {
 578         struct nvme_ns *ns = hctx->queue->queuedata;
 579         struct nvme_queue *nvmeq = hctx->driver_data;
 580         struct nvme_dev *dev = nvmeq->dev;
 581         struct request *req = bd->rq;
 582         struct nvme_command cmnd;
 583         int ret = BLK_MQ_RQ_QUEUE_OK;
 584
 585         /*
 586          * If formated with metadata, require the block layer provide a buffer
 587          * unless this namespace is formated such that the metadata can be
 588          * stripped/generated by the controller with PRACT=1.
 589          */
 590         if (ns && ns->ms && !blk_integrity_rq(req)) {
 591                 if (!(ns->pi_type && ns->ms == 8) &&
 592                     !blk_rq_is_passthrough(req)) {
 593                         blk_mq_end_request(req, -EFAULT);
 594                         return BLK_MQ_RQ_QUEUE_OK;
 595                 }
 596         }
 597
 598         ret = nvme_setup_cmd(ns, req, &cmnd);
 599         if (ret != BLK_MQ_RQ_QUEUE_OK)
 600                 return ret;
 601
 602         ret = nvme_init_iod(req, dev);
 603         if (ret != BLK_MQ_RQ_QUEUE_OK)
 604                 goto out_free_cmd;
 605
 606         if (blk_rq_nr_phys_segments(req))
 607                 ret = nvme_map_data(dev, req, &cmnd);
 608
 609         if (ret != BLK_MQ_RQ_QUEUE_OK)
 610                 goto out_cleanup_iod;
 611
 612         blk_mq_start_request(req);
 613
 614         spin_lock_irq(&nvmeq->q_lock);
 615         if (unlikely(nvmeq->cq_vector < 0)) {
 616                 ret = BLK_MQ_RQ_QUEUE_ERROR;
 617                 spin_unlock_irq(&nvmeq->q_lock);
 618                 goto out_cleanup_iod;
 619         }
 620         __nvme_submit_cmd(nvmeq, &cmnd);
 621         nvme_process_cq(nvmeq);
 622         spin_unlock_irq(&nvmeq->q_lock);
 623         return BLK_MQ_RQ_QUEUE_OK;
 624 out_cleanup_iod:
 625         nvme_free_iod(dev, req);
 626 out_free_cmd:
 627         nvme_cleanup_cmd(req);
 628         return ret;
 629 }
 630
 631 static void nvme_pci_complete_rq(struct request *req)
 632 {
 633         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 634
 635         nvme_unmap_data(iod->nvmeq->dev, req);
 636         nvme_complete_rq(req);
 637 }
 638
 639 /* We read the CQE phase first to check if the rest of the entry is valid */
 640 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 641                 u16 phase)
 642 {
 643         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 644 }
 645
 646 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 647 {
 648         u16 head, phase;
 649
 650         head = nvmeq->cq_head;
 651         phase = nvmeq->cq_phase;
 652
 653         while (nvme_cqe_valid(nvmeq, head, phase)) {
 654                 struct nvme_completion cqe = nvmeq->cqes[head];
 655                 struct request *req;
 656
 657                 if (++head == nvmeq->q_depth) {
 658                         head = 0;
 659                         phase = !phase;
 660                 }
 661
 662                 if (tag && *tag == cqe.command_id)
 663                         *tag = -1;
 664
 665                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 666                         dev_warn(nvmeq->dev->ctrl.device,
 667                                 "invalid id %d completed on queue %d\n",
 668                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 669                         continue;
 670                 }
 671
 672                 /*
 673                  * AEN requests are special as they don't time out and can
 674                  * survive any kind of queue freeze and often don't respond to
 675                  * aborts.  We don't even bother to allocate a struct request
 676                  * for them but rather special case them here.
 677                  */
 678                 if (unlikely(nvmeq->qid == 0 &&
 679                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 680                         nvme_complete_async_event(&nvmeq->dev->ctrl,
 681                                         cqe.status, &cqe.result);
 682                         continue;
 683                 }
 684
 685                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 686                 nvme_req(req)->result = cqe.result;
 687                 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
 688         }
 689
 690         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 691                 return;
 692
 693         if (likely(nvmeq->cq_vector >= 0))
 694                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 695         nvmeq->cq_head = head;
 696         nvmeq->cq_phase = phase;
 697
 698         nvmeq->cqe_seen = 1;
 699 }
 700
 701 static void nvme_process_cq(struct nvme_queue *nvmeq)
 702 {
 703         __nvme_process_cq(nvmeq, NULL);
 704 }
 705
 706 static irqreturn_t nvme_irq(int irq, void *data)
 707 {
 708         irqreturn_t result;
 709         struct nvme_queue *nvmeq = data;
 710         spin_lock(&nvmeq->q_lock);
 711         nvme_process_cq(nvmeq);
 712         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 713         nvmeq->cqe_seen = 0;
 714         spin_unlock(&nvmeq->q_lock);
 715         return result;
 716 }
 717
 718 static irqreturn_t nvme_irq_check(int irq, void *data)
 719 {
 720         struct nvme_queue *nvmeq = data;
 721         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 722                 return IRQ_WAKE_THREAD;
 723         return IRQ_NONE;
 724 }
 725
 726 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 727 {
 728         struct nvme_queue *nvmeq = hctx->driver_data;
 729
 730         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 731                 spin_lock_irq(&nvmeq->q_lock);
 732                 __nvme_process_cq(nvmeq, &tag);
 733                 spin_unlock_irq(&nvmeq->q_lock);
 734
 735                 if (tag == -1)
 736                         return 1;
 737         }
 738
 739         return 0;
 740 }
 741
 742 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
 743 {
 744         struct nvme_dev *dev = to_nvme_dev(ctrl);
 745         struct nvme_queue *nvmeq = dev->queues[0];
 746         struct nvme_command c;
 747
 748         memset(&c, 0, sizeof(c));
 749         c.common.opcode = nvme_admin_async_event;
 750         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
 751
 752         spin_lock_irq(&nvmeq->q_lock);
 753         __nvme_submit_cmd(nvmeq, &c);
 754         spin_unlock_irq(&nvmeq->q_lock);
 755 }
 756
 757 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 758 {
 759         struct nvme_command c;
 760
 761         memset(&c, 0, sizeof(c));
 762         c.delete_queue.opcode = opcode;
 763         c.delete_queue.qid = cpu_to_le16(id);
 764
 765         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 766 }
 767
 768 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 769                                                 struct nvme_queue *nvmeq)
 770 {
 771         struct nvme_command c;
 772         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 773
 774         /*
 775          * Note: we (ab)use the fact the the prp fields survive if no data
 776          * is attached to the request.
 777          */
 778         memset(&c, 0, sizeof(c));
 779         c.create_cq.opcode = nvme_admin_create_cq;
 780         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 781         c.create_cq.cqid = cpu_to_le16(qid);
 782         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 783         c.create_cq.cq_flags = cpu_to_le16(flags);
 784         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 785
 786         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 787 }
 788
 789 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 790                                                 struct nvme_queue *nvmeq)
 791 {
 792         struct nvme_command c;
 793         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 794
 795         /*
 796          * Note: we (ab)use the fact the the prp fields survive if no data
 797          * is attached to the request.
 798          */
 799         memset(&c, 0, sizeof(c));
 800         c.create_sq.opcode = nvme_admin_create_sq;
 801         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 802         c.create_sq.sqid = cpu_to_le16(qid);
 803         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 804         c.create_sq.sq_flags = cpu_to_le16(flags);
 805         c.create_sq.cqid = cpu_to_le16(qid);
 806
 807         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 808 }
 809
 810 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 811 {
 812         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 813 }
 814
 815 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 816 {
 817         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 818 }
 819
 820 static void abort_endio(struct request *req, int error)
 821 {
 822         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 823         struct nvme_queue *nvmeq = iod->nvmeq;
 824         u16 status = req->errors;
 825
 826         dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
 827         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 828         blk_mq_free_request(req);
 829 }
 830
 831 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 832 {
 833         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 834         struct nvme_queue *nvmeq = iod->nvmeq;
 835         struct nvme_dev *dev = nvmeq->dev;
 836         struct request *abort_req;
 837         struct nvme_command cmd;
 838
 839         /*
 840          * Shutdown immediately if controller times out while starting. The
 841          * reset work will see the pci device disabled when it gets the forced
 842          * cancellation error. All outstanding requests are completed on
 843          * shutdown, so we return BLK_EH_HANDLED.
 844          */
 845         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
 846                 dev_warn(dev->ctrl.device,
 847                          "I/O %d QID %d timeout, disable controller\n",
 848                          req->tag, nvmeq->qid);
 849                 nvme_dev_disable(dev, false);
 850                 req->errors = NVME_SC_CANCELLED;
 851                 return BLK_EH_HANDLED;
 852         }
 853
 854         /*
 855          * Shutdown the controller immediately and schedule a reset if the
 856          * command was already aborted once before and still hasn't been
 857          * returned to the driver, or if this is the admin queue.
 858          */
 859         if (!nvmeq->qid || iod->aborted) {
 860                 dev_warn(dev->ctrl.device,
 861                          "I/O %d QID %d timeout, reset controller\n",
 862                          req->tag, nvmeq->qid);
 863                 nvme_dev_disable(dev, false);
 864                 nvme_reset(dev);
 865
 866                 /*
 867                  * Mark the request as handled, since the inline shutdown
 868                  * forces all outstanding requests to complete.
 869                  */
 870                 req->errors = NVME_SC_CANCELLED;
 871                 return BLK_EH_HANDLED;
 872         }
 873
 874         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 875                 atomic_inc(&dev->ctrl.abort_limit);
 876                 return BLK_EH_RESET_TIMER;
 877         }
 878         iod->aborted = 1;
 879
 880         memset(&cmd, 0, sizeof(cmd));
 881         cmd.abort.opcode = nvme_admin_abort_cmd;
 882         cmd.abort.cid = req->tag;
 883         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 884
 885         dev_warn(nvmeq->dev->ctrl.device,
 886                 "I/O %d QID %d timeout, aborting\n",
 887                  req->tag, nvmeq->qid);
 888
 889         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 890                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
 891         if (IS_ERR(abort_req)) {
 892                 atomic_inc(&dev->ctrl.abort_limit);
 893                 return BLK_EH_RESET_TIMER;
 894         }
 895
 896         abort_req->timeout = ADMIN_TIMEOUT;
 897         abort_req->end_io_data = NULL;
 898         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 899
 900         /*
 901          * The aborted req will be completed on receiving the abort req.
 902          * We enable the timer again. If hit twice, it'll cause a device reset,
 903          * as the device then is in a faulty state.
 904          */
 905         return BLK_EH_RESET_TIMER;
 906 }
 907
 908 static void nvme_free_queue(struct nvme_queue *nvmeq)
 909 {
 910         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 911                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 912         if (nvmeq->sq_cmds)
 913                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 914                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 915         kfree(nvmeq);
 916 }
 917
 918 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
 919 {
 920         int i;
 921
 922         for (i = dev->queue_count - 1; i >= lowest; i--) {
 923                 struct nvme_queue *nvmeq = dev->queues[i];
 924                 dev->queue_count--;
 925                 dev->queues[i] = NULL;
 926                 nvme_free_queue(nvmeq);
 927         }
 928 }
 929
 930 /**
 931  * nvme_suspend_queue - put queue into suspended state
 932  * @nvmeq - queue to suspend
 933  */
 934 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
 935 {
 936         int vector;
 937
 938         spin_lock_irq(&nvmeq->q_lock);
 939         if (nvmeq->cq_vector == -1) {
 940                 spin_unlock_irq(&nvmeq->q_lock);
 941                 return 1;
 942         }
 943         vector = nvmeq_irq(nvmeq);
 944         nvmeq->dev->online_queues--;
 945         nvmeq->cq_vector = -1;
 946         spin_unlock_irq(&nvmeq->q_lock);
 947
 948         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
 949                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
 950
 951         free_irq(vector, nvmeq);
 952
 953         return 0;
 954 }
 955
 956 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
 957 {
 958         struct nvme_queue *nvmeq = dev->queues[0];
 959
 960         if (!nvmeq)
 961                 return;
 962         if (nvme_suspend_queue(nvmeq))
 963                 return;
 964
 965         if (shutdown)
 966                 nvme_shutdown_ctrl(&dev->ctrl);
 967         else
 968                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
 969                                                 dev->bar + NVME_REG_CAP));
 970
 971         spin_lock_irq(&nvmeq->q_lock);
 972         nvme_process_cq(nvmeq);
 973         spin_unlock_irq(&nvmeq->q_lock);
 974 }
 975
 976 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
 977                                 int entry_size)
 978 {
 979         int q_depth = dev->q_depth;
 980         unsigned q_size_aligned = roundup(q_depth * entry_size,
 981                                           dev->ctrl.page_size);
 982
 983         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
 984                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
 985                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
 986                 q_depth = div_u64(mem_per_q, entry_size);
 987
 988                 /*
 989                  * Ensure the reduced q_depth is above some threshold where it
 990                  * would be better to map queues in system memory with the
 991                  * original depth
 992                  */
 993                 if (q_depth < 64)
 994                         return -ENOMEM;
 995         }
 996
 997         return q_depth;
 998 }
 999
1000 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1001                                 int qid, int depth)
1002 {
1003         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1004                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1005                                                       dev->ctrl.page_size);
1006                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1007                 nvmeq->sq_cmds_io = dev->cmb + offset;
1008         } else {
1009                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1010                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1011                 if (!nvmeq->sq_cmds)
1012                         return -ENOMEM;
1013         }
1014
1015         return 0;
1016 }
1017
1018 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1019                                                         int depth, int node)
1020 {
1021         struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1022                                                         node);
1023         if (!nvmeq)
1024                 return NULL;
1025
1026         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1027                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1028         if (!nvmeq->cqes)
1029                 goto free_nvmeq;
1030
1031         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1032                 goto free_cqdma;
1033
1034         nvmeq->q_dmadev = dev->dev;
1035         nvmeq->dev = dev;
1036         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1037                         dev->ctrl.instance, qid);
1038         spin_lock_init(&nvmeq->q_lock);
1039         nvmeq->cq_head = 0;
1040         nvmeq->cq_phase = 1;
1041         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1042         nvmeq->q_depth = depth;
1043         nvmeq->qid = qid;
1044         nvmeq->cq_vector = -1;
1045         dev->queues[qid] = nvmeq;
1046         dev->queue_count++;
1047
1048         return nvmeq;
1049
1050  free_cqdma:
1051         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1052                                                         nvmeq->cq_dma_addr);
1053  free_nvmeq:
1054         kfree(nvmeq);
1055         return NULL;
1056 }
1057
1058 static int queue_request_irq(struct nvme_queue *nvmeq)
1059 {
1060         if (use_threaded_interrupts)
1061                 return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check,
1062                                 nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq);
1063         else
1064                 return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED,
1065                                 nvmeq->irqname, nvmeq);
1066 }
1067
1068 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1069 {
1070         struct nvme_dev *dev = nvmeq->dev;
1071
1072         spin_lock_irq(&nvmeq->q_lock);
1073         nvmeq->sq_tail = 0;
1074         nvmeq->cq_head = 0;
1075         nvmeq->cq_phase = 1;
1076         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1077         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1078         dev->online_queues++;
1079         spin_unlock_irq(&nvmeq->q_lock);
1080 }
1081
1082 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1083 {
1084         struct nvme_dev *dev = nvmeq->dev;
1085         int result;
1086
1087         nvmeq->cq_vector = qid - 1;
1088         result = adapter_alloc_cq(dev, qid, nvmeq);
1089         if (result < 0)
1090                 return result;
1091
1092         result = adapter_alloc_sq(dev, qid, nvmeq);
1093         if (result < 0)
1094                 goto release_cq;
1095
1096         result = queue_request_irq(nvmeq);
1097         if (result < 0)
1098                 goto release_sq;
1099
1100         nvme_init_queue(nvmeq, qid);
1101         return result;
1102
1103  release_sq:
1104         adapter_delete_sq(dev, qid);
1105  release_cq:
1106         adapter_delete_cq(dev, qid);
1107         return result;
1108 }
1109
1110 static const struct blk_mq_ops nvme_mq_admin_ops = {
1111         .queue_rq       = nvme_queue_rq,
1112         .complete       = nvme_pci_complete_rq,
1113         .init_hctx      = nvme_admin_init_hctx,
1114         .exit_hctx      = nvme_admin_exit_hctx,
1115         .init_request   = nvme_admin_init_request,
1116         .timeout        = nvme_timeout,
1117 };
1118
1119 static const struct blk_mq_ops nvme_mq_ops = {
1120         .queue_rq       = nvme_queue_rq,
1121         .complete       = nvme_pci_complete_rq,
1122         .init_hctx      = nvme_init_hctx,
1123         .init_request   = nvme_init_request,
1124         .map_queues     = nvme_pci_map_queues,
1125         .timeout        = nvme_timeout,
1126         .poll           = nvme_poll,
1127 };
1128
1129 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1130 {
1131         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1132                 /*
1133                  * If the controller was reset during removal, it's possible
1134                  * user requests may be waiting on a stopped queue. Start the
1135                  * queue to flush these to completion.
1136                  */
1137                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1138                 blk_cleanup_queue(dev->ctrl.admin_q);
1139                 blk_mq_free_tag_set(&dev->admin_tagset);
1140         }
1141 }
1142
1143 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1144 {
1145         if (!dev->ctrl.admin_q) {
1146                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1147                 dev->admin_tagset.nr_hw_queues = 1;
1148
1149                 /*
1150                  * Subtract one to leave an empty queue entry for 'Full Queue'
1151                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1152                  */
1153                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1154                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1155                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1156                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1157                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1158                 dev->admin_tagset.driver_data = dev;
1159
1160                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1161                         return -ENOMEM;
1162
1163                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1164                 if (IS_ERR(dev->ctrl.admin_q)) {
1165                         blk_mq_free_tag_set(&dev->admin_tagset);
1166                         return -ENOMEM;
1167                 }
1168                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1169                         nvme_dev_remove_admin(dev);
1170                         dev->ctrl.admin_q = NULL;
1171                         return -ENODEV;
1172                 }
1173         } else
1174                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1175
1176         return 0;
1177 }
1178
1179 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1180 {
1181         int result;
1182         u32 aqa;
1183         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1184         struct nvme_queue *nvmeq;
1185
1186         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1187                                                 NVME_CAP_NSSRC(cap) : 0;
1188
1189         if (dev->subsystem &&
1190             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1191                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1192
1193         result = nvme_disable_ctrl(&dev->ctrl, cap);
1194         if (result < 0)
1195                 return result;
1196
1197         nvmeq = dev->queues[0];
1198         if (!nvmeq) {
1199                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1200                                         dev_to_node(dev->dev));
1201                 if (!nvmeq)
1202                         return -ENOMEM;
1203         }
1204
1205         aqa = nvmeq->q_depth - 1;
1206         aqa |= aqa << 16;
1207
1208         writel(aqa, dev->bar + NVME_REG_AQA);
1209         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1210         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1211
1212         result = nvme_enable_ctrl(&dev->ctrl, cap);
1213         if (result)
1214                 return result;
1215
1216         nvmeq->cq_vector = 0;
1217         result = queue_request_irq(nvmeq);
1218         if (result) {
1219                 nvmeq->cq_vector = -1;
1220                 return result;
1221         }
1222
1223         return result;
1224 }
1225
1226 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1227 {
1228
1229         /* If true, indicates loss of adapter communication, possibly by a
1230          * NVMe Subsystem reset.
1231          */
1232         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1233
1234         /* If there is a reset ongoing, we shouldn't reset again. */
1235         if (work_busy(&dev->reset_work))
1236                 return false;
1237
1238         /* We shouldn't reset unless the controller is on fatal error state
1239          * _or_ if we lost the communication with it.
1240          */
1241         if (!(csts & NVME_CSTS_CFS) && !nssro)
1242                 return false;
1243
1244         /* If PCI error recovery process is happening, we cannot reset or
1245          * the recovery mechanism will surely fail.
1246          */
1247         if (pci_channel_offline(to_pci_dev(dev->dev)))
1248                 return false;
1249
1250         return true;
1251 }
1252
1253 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1254 {
1255         /* Read a config register to help see what died. */
1256         u16 pci_status;
1257         int result;
1258
1259         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1260                                       &pci_status);
1261         if (result == PCIBIOS_SUCCESSFUL)
1262                 dev_warn(dev->dev,
1263                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1264                          csts, pci_status);
1265         else
1266                 dev_warn(dev->dev,
1267                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1268                          csts, result);
1269 }
1270
1271 static void nvme_watchdog_timer(unsigned long data)
1272 {
1273         struct nvme_dev *dev = (struct nvme_dev *)data;
1274         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1275
1276         /* Skip controllers under certain specific conditions. */
1277         if (nvme_should_reset(dev, csts)) {
1278                 if (!nvme_reset(dev))
1279                         nvme_warn_reset(dev, csts);
1280                 return;
1281         }
1282
1283         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1284 }
1285
1286 static int nvme_create_io_queues(struct nvme_dev *dev)
1287 {
1288         unsigned i, max;
1289         int ret = 0;
1290
1291         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1292                 /* vector == qid - 1, match nvme_create_queue */
1293                 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1294                      pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1295                         ret = -ENOMEM;
1296                         break;
1297                 }
1298         }
1299
1300         max = min(dev->max_qid, dev->queue_count - 1);
1301         for (i = dev->online_queues; i <= max; i++) {
1302                 ret = nvme_create_queue(dev->queues[i], i);
1303                 if (ret)
1304                         break;
1305         }
1306
1307         /*
1308          * Ignore failing Create SQ/CQ commands, we can continue with less
1309          * than the desired aount of queues, and even a controller without
1310          * I/O queues an still be used to issue admin commands.  This might
1311          * be useful to upgrade a buggy firmware for example.
1312          */
1313         return ret >= 0 ? 0 : ret;
1314 }
1315
1316 static ssize_t nvme_cmb_show(struct device *dev,
1317                              struct device_attribute *attr,
1318                              char *buf)
1319 {
1320         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1321
1322         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1323                        ndev->cmbloc, ndev->cmbsz);
1324 }
1325 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1326
1327 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1328 {
1329         u64 szu, size, offset;
1330         resource_size_t bar_size;
1331         struct pci_dev *pdev = to_pci_dev(dev->dev);
1332         void __iomem *cmb;
1333         dma_addr_t dma_addr;
1334
1335         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1336         if (!(NVME_CMB_SZ(dev->cmbsz)))
1337                 return NULL;
1338         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1339
1340         if (!use_cmb_sqes)
1341                 return NULL;
1342
1343         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1344         size = szu * NVME_CMB_SZ(dev->cmbsz);
1345         offset = szu * NVME_CMB_OFST(dev->cmbloc);
1346         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1347
1348         if (offset > bar_size)
1349                 return NULL;
1350
1351         /*
1352          * Controllers may support a CMB size larger than their BAR,
1353          * for example, due to being behind a bridge. Reduce the CMB to
1354          * the reported size of the BAR
1355          */
1356         if (size > bar_size - offset)
1357                 size = bar_size - offset;
1358
1359         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1360         cmb = ioremap_wc(dma_addr, size);
1361         if (!cmb)
1362                 return NULL;
1363
1364         dev->cmb_dma_addr = dma_addr;
1365         dev->cmb_size = size;
1366         return cmb;
1367 }
1368
1369 static inline void nvme_release_cmb(struct nvme_dev *dev)
1370 {
1371         if (dev->cmb) {
1372                 iounmap(dev->cmb);
1373                 dev->cmb = NULL;
1374         }
1375 }
1376
1377 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1378 {
1379         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1380 }
1381
1382 static int nvme_setup_io_queues(struct nvme_dev *dev)
1383 {
1384         struct nvme_queue *adminq = dev->queues[0];
1385         struct pci_dev *pdev = to_pci_dev(dev->dev);
1386         int result, nr_io_queues, size;
1387
1388         nr_io_queues = num_online_cpus();
1389         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1390         if (result < 0)
1391                 return result;
1392
1393         if (nr_io_queues == 0)
1394                 return 0;
1395
1396         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1397                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1398                                 sizeof(struct nvme_command));
1399                 if (result > 0)
1400                         dev->q_depth = result;
1401                 else
1402                         nvme_release_cmb(dev);
1403         }
1404
1405         size = db_bar_size(dev, nr_io_queues);
1406         if (size > 8192) {
1407                 iounmap(dev->bar);
1408                 do {
1409                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1410                         if (dev->bar)
1411                                 break;
1412                         if (!--nr_io_queues)
1413                                 return -ENOMEM;
1414                         size = db_bar_size(dev, nr_io_queues);
1415                 } while (1);
1416                 dev->dbs = dev->bar + 4096;
1417                 adminq->q_db = dev->dbs;
1418         }
1419
1420         /* Deregister the admin queue's interrupt */
1421         free_irq(pci_irq_vector(pdev, 0), adminq);
1422
1423         /*
1424          * If we enable msix early due to not intx, disable it again before
1425          * setting up the full range we need.
1426          */
1427         pci_free_irq_vectors(pdev);
1428         nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1429                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1430         if (nr_io_queues <= 0)
1431                 return -EIO;
1432         dev->max_qid = nr_io_queues;
1433
1434         /*
1435          * Should investigate if there's a performance win from allocating
1436          * more queues than interrupt vectors; it might allow the submission
1437          * path to scale better, even if the receive path is limited by the
1438          * number of interrupts.
1439          */
1440
1441         result = queue_request_irq(adminq);
1442         if (result) {
1443                 adminq->cq_vector = -1;
1444                 return result;
1445         }
1446         return nvme_create_io_queues(dev);
1447 }
1448
1449 static void nvme_del_queue_end(struct request *req, int error)
1450 {
1451         struct nvme_queue *nvmeq = req->end_io_data;
1452
1453         blk_mq_free_request(req);
1454         complete(&nvmeq->dev->ioq_wait);
1455 }
1456
1457 static void nvme_del_cq_end(struct request *req, int error)
1458 {
1459         struct nvme_queue *nvmeq = req->end_io_data;
1460
1461         if (!error) {
1462                 unsigned long flags;
1463
1464                 /*
1465                  * We might be called with the AQ q_lock held
1466                  * and the I/O queue q_lock should always
1467                  * nest inside the AQ one.
1468                  */
1469                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1470                                         SINGLE_DEPTH_NESTING);
1471                 nvme_process_cq(nvmeq);
1472                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1473         }
1474
1475         nvme_del_queue_end(req, error);
1476 }
1477
1478 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1479 {
1480         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1481         struct request *req;
1482         struct nvme_command cmd;
1483
1484         memset(&cmd, 0, sizeof(cmd));
1485         cmd.delete_queue.opcode = opcode;
1486         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1487
1488         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1489         if (IS_ERR(req))
1490                 return PTR_ERR(req);
1491
1492         req->timeout = ADMIN_TIMEOUT;
1493         req->end_io_data = nvmeq;
1494
1495         blk_execute_rq_nowait(q, NULL, req, false,
1496                         opcode == nvme_admin_delete_cq ?
1497                                 nvme_del_cq_end : nvme_del_queue_end);
1498         return 0;
1499 }
1500
1501 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1502 {
1503         int pass;
1504         unsigned long timeout;
1505         u8 opcode = nvme_admin_delete_sq;
1506
1507         for (pass = 0; pass < 2; pass++) {
1508                 int sent = 0, i = queues;
1509
1510                 reinit_completion(&dev->ioq_wait);
1511  retry:
1512                 timeout = ADMIN_TIMEOUT;
1513                 for (; i > 0; i--, sent++)
1514                         if (nvme_delete_queue(dev->queues[i], opcode))
1515                                 break;
1516
1517                 while (sent--) {
1518                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1519                         if (timeout == 0)
1520                                 return;
1521                         if (i)
1522                                 goto retry;
1523                 }
1524                 opcode = nvme_admin_delete_cq;
1525         }
1526 }
1527
1528 /*
1529  * Return: error value if an error occurred setting up the queues or calling
1530  * Identify Device.  0 if these succeeded, even if adding some of the
1531  * namespaces failed.  At the moment, these failures are silent.  TBD which
1532  * failures should be reported.
1533  */
1534 static int nvme_dev_add(struct nvme_dev *dev)
1535 {
1536         if (!dev->ctrl.tagset) {
1537                 dev->tagset.ops = &nvme_mq_ops;
1538                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1539                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1540                 dev->tagset.numa_node = dev_to_node(dev->dev);
1541                 dev->tagset.queue_depth =
1542                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1543                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1544                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1545                 dev->tagset.driver_data = dev;
1546
1547                 if (blk_mq_alloc_tag_set(&dev->tagset))
1548                         return 0;
1549                 dev->ctrl.tagset = &dev->tagset;
1550         } else {
1551                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1552
1553                 /* Free previously allocated queues that are no longer usable */
1554                 nvme_free_queues(dev, dev->online_queues);
1555         }
1556
1557         return 0;
1558 }
1559
1560 static int nvme_pci_enable(struct nvme_dev *dev)
1561 {
1562         u64 cap;
1563         int result = -ENOMEM;
1564         struct pci_dev *pdev = to_pci_dev(dev->dev);
1565
1566         if (pci_enable_device_mem(pdev))
1567                 return result;
1568
1569         pci_set_master(pdev);
1570
1571         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1572             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1573                 goto disable;
1574
1575         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1576                 result = -ENODEV;
1577                 goto disable;
1578         }
1579
1580         /*
1581          * Some devices and/or platforms don't advertise or work with INTx
1582          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1583          * adjust this later.
1584          */
1585         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1586         if (result < 0)
1587                 return result;
1588
1589         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1590
1591         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1592         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1593         dev->dbs = dev->bar + 4096;
1594
1595         /*
1596          * Temporary fix for the Apple controller found in the MacBook8,1 and
1597          * some MacBook7,1 to avoid controller resets and data loss.
1598          */
1599         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1600                 dev->q_depth = 2;
1601                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1602                         "queue depth=%u to work around controller resets\n",
1603                         dev->q_depth);
1604         }
1605
1606         /*
1607          * CMBs can currently only exist on >=1.2 PCIe devices. We only
1608          * populate sysfs if a CMB is implemented. Note that we add the
1609          * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1610          * it on exit. Since nvme_dev_attrs_group has no name we can pass
1611          * NULL as final argument to sysfs_add_file_to_group.
1612          */
1613
1614         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1615                 dev->cmb = nvme_map_cmb(dev);
1616
1617                 if (dev->cmbsz) {
1618                         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1619                                                     &dev_attr_cmb.attr, NULL))
1620                                 dev_warn(dev->dev,
1621                                          "failed to add sysfs attribute for CMB\n");
1622                 }
1623         }
1624
1625         pci_enable_pcie_error_reporting(pdev);
1626         pci_save_state(pdev);
1627         return 0;
1628
1629  disable:
1630         pci_disable_device(pdev);
1631         return result;
1632 }
1633
1634 static void nvme_dev_unmap(struct nvme_dev *dev)
1635 {
1636         if (dev->bar)
1637                 iounmap(dev->bar);
1638         pci_release_mem_regions(to_pci_dev(dev->dev));
1639 }
1640
1641 static void nvme_pci_disable(struct nvme_dev *dev)
1642 {
1643         struct pci_dev *pdev = to_pci_dev(dev->dev);
1644
1645         pci_free_irq_vectors(pdev);
1646
1647         if (pci_is_enabled(pdev)) {
1648                 pci_disable_pcie_error_reporting(pdev);
1649                 pci_disable_device(pdev);
1650         }
1651 }
1652
1653 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1654 {
1655         int i, queues;
1656         bool dead = true;
1657         struct pci_dev *pdev = to_pci_dev(dev->dev);
1658
1659         del_timer_sync(&dev->watchdog_timer);
1660
1661         mutex_lock(&dev->shutdown_lock);
1662         if (pci_is_enabled(pdev)) {
1663                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1664
1665                 if (dev->ctrl.state == NVME_CTRL_LIVE)
1666                         nvme_start_freeze(&dev->ctrl);
1667                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
1668                         pdev->error_state  != pci_channel_io_normal);
1669         }
1670
1671         /*
1672          * Give the controller a chance to complete all entered requests if
1673          * doing a safe shutdown.
1674          */
1675         if (!dead && shutdown)
1676                 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
1677         nvme_stop_queues(&dev->ctrl);
1678
1679         queues = dev->online_queues - 1;
1680         for (i = dev->queue_count - 1; i > 0; i--)
1681                 nvme_suspend_queue(dev->queues[i]);
1682
1683         if (dead) {
1684                 /* A device might become IO incapable very soon during
1685                  * probe, before the admin queue is configured. Thus,
1686                  * queue_count can be 0 here.
1687                  */
1688                 if (dev->queue_count)
1689                         nvme_suspend_queue(dev->queues[0]);
1690         } else {
1691                 nvme_disable_io_queues(dev, queues);
1692                 nvme_disable_admin_queue(dev, shutdown);
1693         }
1694         nvme_pci_disable(dev);
1695
1696         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
1697         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
1698
1699         /*
1700          * The driver will not be starting up queues again if shutting down so
1701          * must flush all entered requests to their failed completion to avoid
1702          * deadlocking blk-mq hot-cpu notifier.
1703          */
1704         if (shutdown)
1705                 nvme_start_queues(&dev->ctrl);
1706         mutex_unlock(&dev->shutdown_lock);
1707 }
1708
1709 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1710 {
1711         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1712                                                 PAGE_SIZE, PAGE_SIZE, 0);
1713         if (!dev->prp_page_pool)
1714                 return -ENOMEM;
1715
1716         /* Optimisation for I/Os between 4k and 128k */
1717         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1718                                                 256, 256, 0);
1719         if (!dev->prp_small_pool) {
1720                 dma_pool_destroy(dev->prp_page_pool);
1721                 return -ENOMEM;
1722         }
1723         return 0;
1724 }
1725
1726 static void nvme_release_prp_pools(struct nvme_dev *dev)
1727 {
1728         dma_pool_destroy(dev->prp_page_pool);
1729         dma_pool_destroy(dev->prp_small_pool);
1730 }
1731
1732 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1733 {
1734         struct nvme_dev *dev = to_nvme_dev(ctrl);
1735
1736         put_device(dev->dev);
1737         if (dev->tagset.tags)
1738                 blk_mq_free_tag_set(&dev->tagset);
1739         if (dev->ctrl.admin_q)
1740                 blk_put_queue(dev->ctrl.admin_q);
1741         kfree(dev->queues);
1742         free_opal_dev(dev->ctrl.opal_dev);
1743         kfree(dev);
1744 }
1745
1746 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1747 {
1748         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1749
1750         kref_get(&dev->ctrl.kref);
1751         nvme_dev_disable(dev, false);
1752         if (!schedule_work(&dev->remove_work))
1753                 nvme_put_ctrl(&dev->ctrl);
1754 }
1755
1756 static void nvme_reset_work(struct work_struct *work)
1757 {
1758         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1759         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
1760         int result = -ENODEV;
1761
1762         if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1763                 goto out;
1764
1765         /*
1766          * If we're called to reset a live controller first shut it down before
1767          * moving on.
1768          */
1769         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1770                 nvme_dev_disable(dev, false);
1771
1772         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1773                 goto out;
1774
1775         result = nvme_pci_enable(dev);
1776         if (result)
1777                 goto out;
1778
1779         result = nvme_configure_admin_queue(dev);
1780         if (result)
1781                 goto out;
1782
1783         nvme_init_queue(dev->queues[0], 0);
1784         result = nvme_alloc_admin_tags(dev);
1785         if (result)
1786                 goto out;
1787
1788         result = nvme_init_identify(&dev->ctrl);
1789         if (result)
1790                 goto out;
1791
1792         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
1793                 if (!dev->ctrl.opal_dev)
1794                         dev->ctrl.opal_dev =
1795                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
1796                 else if (was_suspend)
1797                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
1798         } else {
1799                 free_opal_dev(dev->ctrl.opal_dev);
1800                 dev->ctrl.opal_dev = NULL;
1801         }
1802
1803         result = nvme_setup_io_queues(dev);
1804         if (result)
1805                 goto out;
1806
1807         /*
1808          * A controller that can not execute IO typically requires user
1809          * intervention to correct. For such degraded controllers, the driver
1810          * should not submit commands the user did not request, so skip
1811          * registering for asynchronous event notification on this condition.
1812          */
1813         if (dev->online_queues > 1)
1814                 nvme_queue_async_events(&dev->ctrl);
1815
1816         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1817
1818         /*
1819          * Keep the controller around but remove all namespaces if we don't have
1820          * any working I/O queue.
1821          */
1822         if (dev->online_queues < 2) {
1823                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1824                 nvme_kill_queues(&dev->ctrl);
1825                 nvme_remove_namespaces(&dev->ctrl);
1826         } else {
1827                 nvme_start_queues(&dev->ctrl);
1828                 nvme_wait_freeze(&dev->ctrl);
1829                 nvme_dev_add(dev);
1830                 nvme_unfreeze(&dev->ctrl);
1831         }
1832
1833         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1834                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1835                 goto out;
1836         }
1837
1838         if (dev->online_queues > 1)
1839                 nvme_queue_scan(&dev->ctrl);
1840         return;
1841
1842  out:
1843         nvme_remove_dead_ctrl(dev, result);
1844 }
1845
1846 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1847 {
1848         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1849         struct pci_dev *pdev = to_pci_dev(dev->dev);
1850
1851         nvme_kill_queues(&dev->ctrl);
1852         if (pci_get_drvdata(pdev))
1853                 device_release_driver(&pdev->dev);
1854         nvme_put_ctrl(&dev->ctrl);
1855 }
1856
1857 static int nvme_reset(struct nvme_dev *dev)
1858 {
1859         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1860                 return -ENODEV;
1861         if (work_busy(&dev->reset_work))
1862                 return -ENODEV;
1863         if (!queue_work(nvme_workq, &dev->reset_work))
1864                 return -EBUSY;
1865         return 0;
1866 }
1867
1868 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1869 {
1870         *val = readl(to_nvme_dev(ctrl)->bar + off);
1871         return 0;
1872 }
1873
1874 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1875 {
1876         writel(val, to_nvme_dev(ctrl)->bar + off);
1877         return 0;
1878 }
1879
1880 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1881 {
1882         *val = readq(to_nvme_dev(ctrl)->bar + off);
1883         return 0;
1884 }
1885
1886 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1887 {
1888         struct nvme_dev *dev = to_nvme_dev(ctrl);
1889         int ret = nvme_reset(dev);
1890
1891         if (!ret)
1892                 flush_work(&dev->reset_work);
1893         return ret;
1894 }
1895
1896 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1897         .name                   = "pcie",
1898         .module                 = THIS_MODULE,
1899         .reg_read32             = nvme_pci_reg_read32,
1900         .reg_write32            = nvme_pci_reg_write32,
1901         .reg_read64             = nvme_pci_reg_read64,
1902         .reset_ctrl             = nvme_pci_reset_ctrl,
1903         .free_ctrl              = nvme_pci_free_ctrl,
1904         .submit_async_event     = nvme_pci_submit_async_event,
1905 };
1906
1907 static int nvme_dev_map(struct nvme_dev *dev)
1908 {
1909         struct pci_dev *pdev = to_pci_dev(dev->dev);
1910
1911         if (pci_request_mem_regions(pdev, "nvme"))
1912                 return -ENODEV;
1913
1914         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1915         if (!dev->bar)
1916                 goto release;
1917
1918         return 0;
1919   release:
1920         pci_release_mem_regions(pdev);
1921         return -ENODEV;
1922 }
1923
1924 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1925 {
1926         int node, result = -ENOMEM;
1927         struct nvme_dev *dev;
1928
1929         node = dev_to_node(&pdev->dev);
1930         if (node == NUMA_NO_NODE)
1931                 set_dev_node(&pdev->dev, first_memory_node);
1932
1933         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1934         if (!dev)
1935                 return -ENOMEM;
1936         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1937                                                         GFP_KERNEL, node);
1938         if (!dev->queues)
1939                 goto free;
1940
1941         dev->dev = get_device(&pdev->dev);
1942         pci_set_drvdata(pdev, dev);
1943
1944         result = nvme_dev_map(dev);
1945         if (result)
1946                 goto free;
1947
1948         INIT_WORK(&dev->reset_work, nvme_reset_work);
1949         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1950         setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1951                 (unsigned long)dev);
1952         mutex_init(&dev->shutdown_lock);
1953         init_completion(&dev->ioq_wait);
1954
1955         result = nvme_setup_prp_pools(dev);
1956         if (result)
1957                 goto put_pci;
1958
1959         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
1960                         id->driver_data);
1961         if (result)
1962                 goto release_pools;
1963
1964         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
1965
1966         queue_work(nvme_workq, &dev->reset_work);
1967         return 0;
1968
1969  release_pools:
1970         nvme_release_prp_pools(dev);
1971  put_pci:
1972         put_device(dev->dev);
1973         nvme_dev_unmap(dev);
1974  free:
1975         kfree(dev->queues);
1976         kfree(dev);
1977         return result;
1978 }
1979
1980 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
1981 {
1982         struct nvme_dev *dev = pci_get_drvdata(pdev);
1983
1984         if (prepare)
1985                 nvme_dev_disable(dev, false);
1986         else
1987                 nvme_reset(dev);
1988 }
1989
1990 static void nvme_shutdown(struct pci_dev *pdev)
1991 {
1992         struct nvme_dev *dev = pci_get_drvdata(pdev);
1993         nvme_dev_disable(dev, true);
1994 }
1995
1996 /*
1997  * The driver's remove may be called on a device in a partially initialized
1998  * state. This function must not have any dependencies on the device state in
1999  * order to proceed.
2000  */
2001 static void nvme_remove(struct pci_dev *pdev)
2002 {
2003         struct nvme_dev *dev = pci_get_drvdata(pdev);
2004
2005         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2006
2007         pci_set_drvdata(pdev, NULL);
2008
2009         if (!pci_device_is_present(pdev)) {
2010                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2011                 nvme_dev_disable(dev, false);
2012         }
2013
2014         flush_work(&dev->reset_work);
2015         nvme_uninit_ctrl(&dev->ctrl);
2016         nvme_dev_disable(dev, true);
2017         nvme_dev_remove_admin(dev);
2018         nvme_free_queues(dev, 0);
2019         nvme_release_cmb(dev);
2020         nvme_release_prp_pools(dev);
2021         nvme_dev_unmap(dev);
2022         nvme_put_ctrl(&dev->ctrl);
2023 }
2024
2025 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2026 {
2027         int ret = 0;
2028
2029         if (numvfs == 0) {
2030                 if (pci_vfs_assigned(pdev)) {
2031                         dev_warn(&pdev->dev,
2032                                 "Cannot disable SR-IOV VFs while assigned\n");
2033                         return -EPERM;
2034                 }
2035                 pci_disable_sriov(pdev);
2036                 return 0;
2037         }
2038
2039         ret = pci_enable_sriov(pdev, numvfs);
2040         return ret ? ret : numvfs;
2041 }
2042
2043 #ifdef CONFIG_PM_SLEEP
2044 static int nvme_suspend(struct device *dev)
2045 {
2046         struct pci_dev *pdev = to_pci_dev(dev);
2047         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2048
2049         nvme_dev_disable(ndev, true);
2050         return 0;
2051 }
2052
2053 static int nvme_resume(struct device *dev)
2054 {
2055         struct pci_dev *pdev = to_pci_dev(dev);
2056         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2057
2058         nvme_reset(ndev);
2059         return 0;
2060 }
2061 #endif
2062
2063 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2064
2065 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2066                                                 pci_channel_state_t state)
2067 {
2068         struct nvme_dev *dev = pci_get_drvdata(pdev);
2069
2070         /*
2071          * A frozen channel requires a reset. When detected, this method will
2072          * shutdown the controller to quiesce. The controller will be restarted
2073          * after the slot reset through driver's slot_reset callback.
2074          */
2075         switch (state) {
2076         case pci_channel_io_normal:
2077                 return PCI_ERS_RESULT_CAN_RECOVER;
2078         case pci_channel_io_frozen:
2079                 dev_warn(dev->ctrl.device,
2080                         "frozen state error detected, reset controller\n");
2081                 nvme_dev_disable(dev, false);
2082                 return PCI_ERS_RESULT_NEED_RESET;
2083         case pci_channel_io_perm_failure:
2084                 dev_warn(dev->ctrl.device,
2085                         "failure state error detected, request disconnect\n");
2086                 return PCI_ERS_RESULT_DISCONNECT;
2087         }
2088         return PCI_ERS_RESULT_NEED_RESET;
2089 }
2090
2091 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2092 {
2093         struct nvme_dev *dev = pci_get_drvdata(pdev);
2094
2095         dev_info(dev->ctrl.device, "restart after slot reset\n");
2096         pci_restore_state(pdev);
2097         nvme_reset(dev);
2098         return PCI_ERS_RESULT_RECOVERED;
2099 }
2100
2101 static void nvme_error_resume(struct pci_dev *pdev)
2102 {
2103         pci_cleanup_aer_uncorrect_error_status(pdev);
2104 }
2105
2106 static const struct pci_error_handlers nvme_err_handler = {
2107         .error_detected = nvme_error_detected,
2108         .slot_reset     = nvme_slot_reset,
2109         .resume         = nvme_error_resume,
2110         .reset_notify   = nvme_reset_notify,
2111 };
2112
2113 static const struct pci_device_id nvme_id_table[] = {
2114         { PCI_VDEVICE(INTEL, 0x0953),
2115                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2116                                 NVME_QUIRK_DISCARD_ZEROES, },
2117         { PCI_VDEVICE(INTEL, 0x0a53),
2118                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2119                                 NVME_QUIRK_DISCARD_ZEROES, },
2120         { PCI_VDEVICE(INTEL, 0x0a54),
2121                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2122                                 NVME_QUIRK_DISCARD_ZEROES, },
2123         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2124                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2125         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2126                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2127         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2128                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2129         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2130         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2131         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2132         { 0, }
2133 };
2134 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2135
2136 static struct pci_driver nvme_driver = {
2137         .name           = "nvme",
2138         .id_table       = nvme_id_table,
2139         .probe          = nvme_probe,
2140         .remove         = nvme_remove,
2141         .shutdown       = nvme_shutdown,
2142         .driver         = {
2143                 .pm     = &nvme_dev_pm_ops,
2144         },
2145         .sriov_configure = nvme_pci_sriov_configure,
2146         .err_handler    = &nvme_err_handler,
2147 };
2148
2149 static int __init nvme_init(void)
2150 {
2151         int result;
2152
2153         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2154         if (!nvme_workq)
2155                 return -ENOMEM;
2156
2157         result = pci_register_driver(&nvme_driver);
2158         if (result)
2159                 destroy_workqueue(nvme_workq);
2160         return result;
2161 }
2162
2163 static void __exit nvme_exit(void)
2164 {
2165         pci_unregister_driver(&nvme_driver);
2166         destroy_workqueue(nvme_workq);
2167         _nvme_check_size();
2168 }
2169
2170 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2171 MODULE_LICENSE("GPL");
2172 MODULE_VERSION("1.0");
2173 module_init(nvme_init);
2174 module_exit(nvme_exit);