2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/cpu.h>
21 #include <linux/delay.h>
22 #include <linux/dmi.h>
23 #include <linux/errno.h>
25 #include <linux/genhd.h>
26 #include <linux/hdreg.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/mutex.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/ptrace.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/t10-pi.h>
43 #include <linux/timer.h>
44 #include <linux/types.h>
45 #include <linux/io-64-nonatomic-lo-hi.h>
46 #include <asm/unaligned.h>
47 #include <linux/sed-opal.h>
51 #define NVME_Q_DEPTH 1024
52 #define NVME_AQ_DEPTH 256
53 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
57 * We handle AEN commands ourselves and don't even let the
58 * block layer know about them.
60 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
62 static int use_threaded_interrupts;
63 module_param(use_threaded_interrupts, int, 0);
65 static bool use_cmb_sqes = true;
66 module_param(use_cmb_sqes, bool, 0644);
67 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
69 static struct workqueue_struct *nvme_workq;
74 static int nvme_reset(struct nvme_dev *dev);
75 static void nvme_process_cq(struct nvme_queue *nvmeq);
76 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
79 * Represents an NVM Express device. Each nvme_dev is a PCI function.
82 struct nvme_queue **queues;
83 struct blk_mq_tag_set tagset;
84 struct blk_mq_tag_set admin_tagset;
87 struct dma_pool *prp_page_pool;
88 struct dma_pool *prp_small_pool;
90 unsigned online_queues;
95 struct work_struct reset_work;
96 struct work_struct remove_work;
97 struct timer_list watchdog_timer;
98 struct mutex shutdown_lock;
101 dma_addr_t cmb_dma_addr;
105 struct nvme_ctrl ctrl;
106 struct completion ioq_wait;
108 dma_addr_t dbbuf_dbs_dma_addr;
110 dma_addr_t dbbuf_eis_dma_addr;
113 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
115 return qid * 2 * stride;
118 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
120 return (qid * 2 + 1) * stride;
123 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
125 return container_of(ctrl, struct nvme_dev, ctrl);
129 * An NVM Express queue. Each device has at least two (one for admin
130 * commands and one for I/O commands).
133 struct device *q_dmadev;
134 struct nvme_dev *dev;
135 char irqname[24]; /* nvme4294967295-65535\0 */
137 struct nvme_command *sq_cmds;
138 struct nvme_command __iomem *sq_cmds_io;
139 volatile struct nvme_completion *cqes;
140 struct blk_mq_tags **tags;
141 dma_addr_t sq_dma_addr;
142 dma_addr_t cq_dma_addr;
158 * The nvme_iod describes the data in an I/O, including the list of PRP
159 * entries. You can't see it in this data structure because C doesn't let
160 * me express that. Use nvme_init_iod to ensure there's enough space
161 * allocated to store the PRP list.
164 struct nvme_request req;
165 struct nvme_queue *nvmeq;
167 int npages; /* In the PRP list. 0 means small pool in use */
168 int nents; /* Used in scatterlist */
169 int length; /* Of data, in bytes */
170 dma_addr_t first_dma;
171 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
172 struct scatterlist *sg;
173 struct scatterlist inline_sg[0];
177 * Check we didin't inadvertently grow the command struct
179 static inline void _nvme_check_size(void)
181 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
182 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
183 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
184 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
185 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
186 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
187 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
188 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
189 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
190 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
191 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
192 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
193 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
196 static inline unsigned int nvme_dbbuf_size(u32 stride)
198 return ((num_possible_cpus() + 1) * 8 * stride);
201 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
203 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
208 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
209 &dev->dbbuf_dbs_dma_addr,
213 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
214 &dev->dbbuf_eis_dma_addr,
216 if (!dev->dbbuf_eis) {
217 dma_free_coherent(dev->dev, mem_size,
218 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
219 dev->dbbuf_dbs = NULL;
226 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
228 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
230 if (dev->dbbuf_dbs) {
231 dma_free_coherent(dev->dev, mem_size,
232 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
233 dev->dbbuf_dbs = NULL;
235 if (dev->dbbuf_eis) {
236 dma_free_coherent(dev->dev, mem_size,
237 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
238 dev->dbbuf_eis = NULL;
242 static void nvme_dbbuf_init(struct nvme_dev *dev,
243 struct nvme_queue *nvmeq, int qid)
245 if (!dev->dbbuf_dbs || !qid)
248 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
249 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
250 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
251 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
254 static void nvme_dbbuf_set(struct nvme_dev *dev)
256 struct nvme_command c;
261 memset(&c, 0, sizeof(c));
262 c.dbbuf.opcode = nvme_admin_dbbuf;
263 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
264 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
266 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
267 dev_warn(dev->dev, "unable to set dbbuf\n");
268 /* Free memory and continue on */
269 nvme_dbbuf_dma_free(dev);
273 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
275 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
278 /* Update dbbuf and return true if an MMIO is required */
279 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
280 volatile u32 *dbbuf_ei)
286 * Ensure that the queue is written before updating
287 * the doorbell in memory
291 old_value = *dbbuf_db;
294 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
302 * Max size of iod being embedded in the request payload
304 #define NVME_INT_PAGES 2
305 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
308 * Will slightly overestimate the number of pages needed. This is OK
309 * as it only leads to a small amount of wasted memory for the lifetime of
312 static int nvme_npages(unsigned size, struct nvme_dev *dev)
314 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
315 dev->ctrl.page_size);
316 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
319 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
320 unsigned int size, unsigned int nseg)
322 return sizeof(__le64 *) * nvme_npages(size, dev) +
323 sizeof(struct scatterlist) * nseg;
326 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
328 return sizeof(struct nvme_iod) +
329 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
332 static int nvmeq_irq(struct nvme_queue *nvmeq)
334 return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector);
337 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
338 unsigned int hctx_idx)
340 struct nvme_dev *dev = data;
341 struct nvme_queue *nvmeq = dev->queues[0];
343 WARN_ON(hctx_idx != 0);
344 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
345 WARN_ON(nvmeq->tags);
347 hctx->driver_data = nvmeq;
348 nvmeq->tags = &dev->admin_tagset.tags[0];
352 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
354 struct nvme_queue *nvmeq = hctx->driver_data;
359 static int nvme_admin_init_request(void *data, struct request *req,
360 unsigned int hctx_idx, unsigned int rq_idx,
361 unsigned int numa_node)
363 struct nvme_dev *dev = data;
364 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
365 struct nvme_queue *nvmeq = dev->queues[0];
372 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
373 unsigned int hctx_idx)
375 struct nvme_dev *dev = data;
376 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
379 nvmeq->tags = &dev->tagset.tags[hctx_idx];
381 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
382 hctx->driver_data = nvmeq;
386 static int nvme_init_request(void *data, struct request *req,
387 unsigned int hctx_idx, unsigned int rq_idx,
388 unsigned int numa_node)
390 struct nvme_dev *dev = data;
391 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
392 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
399 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
401 struct nvme_dev *dev = set->driver_data;
403 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
407 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
408 * @nvmeq: The queue to use
409 * @cmd: The command to send
411 * Safe to use from interrupt context
413 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
414 struct nvme_command *cmd)
416 u16 tail = nvmeq->sq_tail;
418 if (nvmeq->sq_cmds_io)
419 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
421 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
423 if (++tail == nvmeq->q_depth)
425 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
427 writel(tail, nvmeq->q_db);
428 nvmeq->sq_tail = tail;
431 static __le64 **iod_list(struct request *req)
433 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
434 return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
437 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev)
439 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
440 int nseg = blk_rq_nr_phys_segments(rq);
441 unsigned int size = blk_rq_payload_bytes(rq);
443 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
444 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
446 return BLK_MQ_RQ_QUEUE_BUSY;
448 iod->sg = iod->inline_sg;
456 return BLK_MQ_RQ_QUEUE_OK;
459 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
461 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
462 const int last_prp = dev->ctrl.page_size / 8 - 1;
464 __le64 **list = iod_list(req);
465 dma_addr_t prp_dma = iod->first_dma;
467 if (iod->npages == 0)
468 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
469 for (i = 0; i < iod->npages; i++) {
470 __le64 *prp_list = list[i];
471 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
472 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
473 prp_dma = next_prp_dma;
476 if (iod->sg != iod->inline_sg)
480 #ifdef CONFIG_BLK_DEV_INTEGRITY
481 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
483 if (be32_to_cpu(pi->ref_tag) == v)
484 pi->ref_tag = cpu_to_be32(p);
487 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
489 if (be32_to_cpu(pi->ref_tag) == p)
490 pi->ref_tag = cpu_to_be32(v);
494 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
496 * The virtual start sector is the one that was originally submitted by the
497 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
498 * start sector may be different. Remap protection information to match the
499 * physical LBA on writes, and back to the original seed on reads.
501 * Type 0 and 3 do not have a ref tag, so no remapping required.
503 static void nvme_dif_remap(struct request *req,
504 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
506 struct nvme_ns *ns = req->rq_disk->private_data;
507 struct bio_integrity_payload *bip;
508 struct t10_pi_tuple *pi;
510 u32 i, nlb, ts, phys, virt;
512 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
515 bip = bio_integrity(req->bio);
519 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
522 virt = bip_get_seed(bip);
523 phys = nvme_block_nr(ns, blk_rq_pos(req));
524 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
525 ts = ns->disk->queue->integrity.tuple_size;
527 for (i = 0; i < nlb; i++, virt++, phys++) {
528 pi = (struct t10_pi_tuple *)p;
529 dif_swap(phys, virt, pi);
534 #else /* CONFIG_BLK_DEV_INTEGRITY */
535 static void nvme_dif_remap(struct request *req,
536 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
539 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
542 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
547 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req)
549 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
550 struct dma_pool *pool;
551 int length = blk_rq_payload_bytes(req);
552 struct scatterlist *sg = iod->sg;
553 int dma_len = sg_dma_len(sg);
554 u64 dma_addr = sg_dma_address(sg);
555 u32 page_size = dev->ctrl.page_size;
556 int offset = dma_addr & (page_size - 1);
558 __le64 **list = iod_list(req);
562 length -= (page_size - offset);
566 dma_len -= (page_size - offset);
568 dma_addr += (page_size - offset);
571 dma_addr = sg_dma_address(sg);
572 dma_len = sg_dma_len(sg);
575 if (length <= page_size) {
576 iod->first_dma = dma_addr;
580 nprps = DIV_ROUND_UP(length, page_size);
581 if (nprps <= (256 / 8)) {
582 pool = dev->prp_small_pool;
585 pool = dev->prp_page_pool;
589 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
591 iod->first_dma = dma_addr;
596 iod->first_dma = prp_dma;
599 if (i == page_size >> 3) {
600 __le64 *old_prp_list = prp_list;
601 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
604 list[iod->npages++] = prp_list;
605 prp_list[0] = old_prp_list[i - 1];
606 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
609 prp_list[i++] = cpu_to_le64(dma_addr);
610 dma_len -= page_size;
611 dma_addr += page_size;
619 dma_addr = sg_dma_address(sg);
620 dma_len = sg_dma_len(sg);
626 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
627 struct nvme_command *cmnd)
629 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
630 struct request_queue *q = req->q;
631 enum dma_data_direction dma_dir = rq_data_dir(req) ?
632 DMA_TO_DEVICE : DMA_FROM_DEVICE;
633 int ret = BLK_MQ_RQ_QUEUE_ERROR;
635 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
636 iod->nents = blk_rq_map_sg(q, req, iod->sg);
640 ret = BLK_MQ_RQ_QUEUE_BUSY;
641 if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
645 if (!nvme_setup_prps(dev, req))
648 ret = BLK_MQ_RQ_QUEUE_ERROR;
649 if (blk_integrity_rq(req)) {
650 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
653 sg_init_table(&iod->meta_sg, 1);
654 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
657 if (rq_data_dir(req))
658 nvme_dif_remap(req, nvme_dif_prep);
660 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
664 cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
665 cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
666 if (blk_integrity_rq(req))
667 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
668 return BLK_MQ_RQ_QUEUE_OK;
671 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
676 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
678 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
679 enum dma_data_direction dma_dir = rq_data_dir(req) ?
680 DMA_TO_DEVICE : DMA_FROM_DEVICE;
683 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
684 if (blk_integrity_rq(req)) {
685 if (!rq_data_dir(req))
686 nvme_dif_remap(req, nvme_dif_complete);
687 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
691 nvme_cleanup_cmd(req);
692 nvme_free_iod(dev, req);
696 * NOTE: ns is NULL when called on the admin queue.
698 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
699 const struct blk_mq_queue_data *bd)
701 struct nvme_ns *ns = hctx->queue->queuedata;
702 struct nvme_queue *nvmeq = hctx->driver_data;
703 struct nvme_dev *dev = nvmeq->dev;
704 struct request *req = bd->rq;
705 struct nvme_command cmnd;
706 int ret = BLK_MQ_RQ_QUEUE_OK;
709 * If formated with metadata, require the block layer provide a buffer
710 * unless this namespace is formated such that the metadata can be
711 * stripped/generated by the controller with PRACT=1.
713 if (ns && ns->ms && !blk_integrity_rq(req)) {
714 if (!(ns->pi_type && ns->ms == 8) &&
715 !blk_rq_is_passthrough(req)) {
716 blk_mq_end_request(req, -EFAULT);
717 return BLK_MQ_RQ_QUEUE_OK;
721 ret = nvme_setup_cmd(ns, req, &cmnd);
722 if (ret != BLK_MQ_RQ_QUEUE_OK)
725 ret = nvme_init_iod(req, dev);
726 if (ret != BLK_MQ_RQ_QUEUE_OK)
729 if (blk_rq_nr_phys_segments(req))
730 ret = nvme_map_data(dev, req, &cmnd);
732 if (ret != BLK_MQ_RQ_QUEUE_OK)
733 goto out_cleanup_iod;
735 blk_mq_start_request(req);
737 spin_lock_irq(&nvmeq->q_lock);
738 if (unlikely(nvmeq->cq_vector < 0)) {
739 ret = BLK_MQ_RQ_QUEUE_ERROR;
740 spin_unlock_irq(&nvmeq->q_lock);
741 goto out_cleanup_iod;
743 __nvme_submit_cmd(nvmeq, &cmnd);
744 nvme_process_cq(nvmeq);
745 spin_unlock_irq(&nvmeq->q_lock);
746 return BLK_MQ_RQ_QUEUE_OK;
748 nvme_free_iod(dev, req);
750 nvme_cleanup_cmd(req);
754 static void nvme_pci_complete_rq(struct request *req)
756 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
758 nvme_unmap_data(iod->nvmeq->dev, req);
759 nvme_complete_rq(req);
762 /* We read the CQE phase first to check if the rest of the entry is valid */
763 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
766 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
769 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
773 head = nvmeq->cq_head;
774 phase = nvmeq->cq_phase;
776 while (nvme_cqe_valid(nvmeq, head, phase)) {
777 struct nvme_completion cqe = nvmeq->cqes[head];
780 if (++head == nvmeq->q_depth) {
785 if (tag && *tag == cqe.command_id)
788 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
789 dev_warn(nvmeq->dev->ctrl.device,
790 "invalid id %d completed on queue %d\n",
791 cqe.command_id, le16_to_cpu(cqe.sq_id));
796 * AEN requests are special as they don't time out and can
797 * survive any kind of queue freeze and often don't respond to
798 * aborts. We don't even bother to allocate a struct request
799 * for them but rather special case them here.
801 if (unlikely(nvmeq->qid == 0 &&
802 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
803 nvme_complete_async_event(&nvmeq->dev->ctrl,
804 cqe.status, &cqe.result);
808 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
809 nvme_end_request(req, cqe.status, cqe.result);
812 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
815 if (likely(nvmeq->cq_vector >= 0))
816 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
818 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
819 nvmeq->cq_head = head;
820 nvmeq->cq_phase = phase;
825 static void nvme_process_cq(struct nvme_queue *nvmeq)
827 __nvme_process_cq(nvmeq, NULL);
830 static irqreturn_t nvme_irq(int irq, void *data)
833 struct nvme_queue *nvmeq = data;
834 spin_lock(&nvmeq->q_lock);
835 nvme_process_cq(nvmeq);
836 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
838 spin_unlock(&nvmeq->q_lock);
842 static irqreturn_t nvme_irq_check(int irq, void *data)
844 struct nvme_queue *nvmeq = data;
845 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
846 return IRQ_WAKE_THREAD;
850 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
852 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
853 spin_lock_irq(&nvmeq->q_lock);
854 __nvme_process_cq(nvmeq, &tag);
855 spin_unlock_irq(&nvmeq->q_lock);
864 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
866 struct nvme_queue *nvmeq = hctx->driver_data;
868 return __nvme_poll(nvmeq, tag);
871 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
873 struct nvme_dev *dev = to_nvme_dev(ctrl);
874 struct nvme_queue *nvmeq = dev->queues[0];
875 struct nvme_command c;
877 memset(&c, 0, sizeof(c));
878 c.common.opcode = nvme_admin_async_event;
879 c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
881 spin_lock_irq(&nvmeq->q_lock);
882 __nvme_submit_cmd(nvmeq, &c);
883 spin_unlock_irq(&nvmeq->q_lock);
886 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
888 struct nvme_command c;
890 memset(&c, 0, sizeof(c));
891 c.delete_queue.opcode = opcode;
892 c.delete_queue.qid = cpu_to_le16(id);
894 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
897 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
898 struct nvme_queue *nvmeq)
900 struct nvme_command c;
901 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
904 * Note: we (ab)use the fact the the prp fields survive if no data
905 * is attached to the request.
907 memset(&c, 0, sizeof(c));
908 c.create_cq.opcode = nvme_admin_create_cq;
909 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
910 c.create_cq.cqid = cpu_to_le16(qid);
911 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
912 c.create_cq.cq_flags = cpu_to_le16(flags);
913 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
915 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
918 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
919 struct nvme_queue *nvmeq)
921 struct nvme_command c;
922 int flags = NVME_QUEUE_PHYS_CONTIG;
925 * Note: we (ab)use the fact the the prp fields survive if no data
926 * is attached to the request.
928 memset(&c, 0, sizeof(c));
929 c.create_sq.opcode = nvme_admin_create_sq;
930 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
931 c.create_sq.sqid = cpu_to_le16(qid);
932 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
933 c.create_sq.sq_flags = cpu_to_le16(flags);
934 c.create_sq.cqid = cpu_to_le16(qid);
936 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
939 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
941 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
944 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
946 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
949 static void abort_endio(struct request *req, int error)
951 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
952 struct nvme_queue *nvmeq = iod->nvmeq;
954 dev_warn(nvmeq->dev->ctrl.device,
955 "Abort status: 0x%x", nvme_req(req)->status);
956 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
957 blk_mq_free_request(req);
960 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
962 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
963 struct nvme_queue *nvmeq = iod->nvmeq;
964 struct nvme_dev *dev = nvmeq->dev;
965 struct request *abort_req;
966 struct nvme_command cmd;
969 * Did we miss an interrupt?
971 if (__nvme_poll(nvmeq, req->tag)) {
972 dev_warn(dev->ctrl.device,
973 "I/O %d QID %d timeout, completion polled\n",
974 req->tag, nvmeq->qid);
975 return BLK_EH_HANDLED;
979 * Shutdown immediately if controller times out while starting. The
980 * reset work will see the pci device disabled when it gets the forced
981 * cancellation error. All outstanding requests are completed on
982 * shutdown, so we return BLK_EH_HANDLED.
984 if (dev->ctrl.state == NVME_CTRL_RESETTING) {
985 dev_warn(dev->ctrl.device,
986 "I/O %d QID %d timeout, disable controller\n",
987 req->tag, nvmeq->qid);
988 nvme_dev_disable(dev, false);
989 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
990 return BLK_EH_HANDLED;
994 * Shutdown the controller immediately and schedule a reset if the
995 * command was already aborted once before and still hasn't been
996 * returned to the driver, or if this is the admin queue.
998 if (!nvmeq->qid || iod->aborted) {
999 dev_warn(dev->ctrl.device,
1000 "I/O %d QID %d timeout, reset controller\n",
1001 req->tag, nvmeq->qid);
1002 nvme_dev_disable(dev, false);
1006 * Mark the request as handled, since the inline shutdown
1007 * forces all outstanding requests to complete.
1009 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1010 return BLK_EH_HANDLED;
1013 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1014 atomic_inc(&dev->ctrl.abort_limit);
1015 return BLK_EH_RESET_TIMER;
1019 memset(&cmd, 0, sizeof(cmd));
1020 cmd.abort.opcode = nvme_admin_abort_cmd;
1021 cmd.abort.cid = req->tag;
1022 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1024 dev_warn(nvmeq->dev->ctrl.device,
1025 "I/O %d QID %d timeout, aborting\n",
1026 req->tag, nvmeq->qid);
1028 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1029 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1030 if (IS_ERR(abort_req)) {
1031 atomic_inc(&dev->ctrl.abort_limit);
1032 return BLK_EH_RESET_TIMER;
1035 abort_req->timeout = ADMIN_TIMEOUT;
1036 abort_req->end_io_data = NULL;
1037 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1040 * The aborted req will be completed on receiving the abort req.
1041 * We enable the timer again. If hit twice, it'll cause a device reset,
1042 * as the device then is in a faulty state.
1044 return BLK_EH_RESET_TIMER;
1047 static void nvme_free_queue(struct nvme_queue *nvmeq)
1049 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1050 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1052 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1053 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1057 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1061 for (i = dev->queue_count - 1; i >= lowest; i--) {
1062 struct nvme_queue *nvmeq = dev->queues[i];
1064 dev->queues[i] = NULL;
1065 nvme_free_queue(nvmeq);
1070 * nvme_suspend_queue - put queue into suspended state
1071 * @nvmeq - queue to suspend
1073 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1077 spin_lock_irq(&nvmeq->q_lock);
1078 if (nvmeq->cq_vector == -1) {
1079 spin_unlock_irq(&nvmeq->q_lock);
1082 vector = nvmeq_irq(nvmeq);
1083 nvmeq->dev->online_queues--;
1084 nvmeq->cq_vector = -1;
1085 spin_unlock_irq(&nvmeq->q_lock);
1087 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1088 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1090 free_irq(vector, nvmeq);
1095 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1097 struct nvme_queue *nvmeq = dev->queues[0];
1101 if (nvme_suspend_queue(nvmeq))
1105 nvme_shutdown_ctrl(&dev->ctrl);
1107 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1108 dev->bar + NVME_REG_CAP));
1110 spin_lock_irq(&nvmeq->q_lock);
1111 nvme_process_cq(nvmeq);
1112 spin_unlock_irq(&nvmeq->q_lock);
1115 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1118 int q_depth = dev->q_depth;
1119 unsigned q_size_aligned = roundup(q_depth * entry_size,
1120 dev->ctrl.page_size);
1122 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1123 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1124 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1125 q_depth = div_u64(mem_per_q, entry_size);
1128 * Ensure the reduced q_depth is above some threshold where it
1129 * would be better to map queues in system memory with the
1139 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1142 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1143 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1144 dev->ctrl.page_size);
1145 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1146 nvmeq->sq_cmds_io = dev->cmb + offset;
1148 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1149 &nvmeq->sq_dma_addr, GFP_KERNEL);
1150 if (!nvmeq->sq_cmds)
1157 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1158 int depth, int node)
1160 struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1165 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1166 &nvmeq->cq_dma_addr, GFP_KERNEL);
1170 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1173 nvmeq->q_dmadev = dev->dev;
1175 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1176 dev->ctrl.instance, qid);
1177 spin_lock_init(&nvmeq->q_lock);
1179 nvmeq->cq_phase = 1;
1180 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1181 nvmeq->q_depth = depth;
1183 nvmeq->cq_vector = -1;
1184 dev->queues[qid] = nvmeq;
1190 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1191 nvmeq->cq_dma_addr);
1197 static int queue_request_irq(struct nvme_queue *nvmeq)
1199 if (use_threaded_interrupts)
1200 return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check,
1201 nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq);
1203 return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED,
1204 nvmeq->irqname, nvmeq);
1207 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1209 struct nvme_dev *dev = nvmeq->dev;
1211 spin_lock_irq(&nvmeq->q_lock);
1214 nvmeq->cq_phase = 1;
1215 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1216 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1217 nvme_dbbuf_init(dev, nvmeq, qid);
1218 dev->online_queues++;
1219 spin_unlock_irq(&nvmeq->q_lock);
1222 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1224 struct nvme_dev *dev = nvmeq->dev;
1227 nvmeq->cq_vector = qid - 1;
1228 result = adapter_alloc_cq(dev, qid, nvmeq);
1232 result = adapter_alloc_sq(dev, qid, nvmeq);
1236 result = queue_request_irq(nvmeq);
1240 nvme_init_queue(nvmeq, qid);
1244 adapter_delete_sq(dev, qid);
1246 adapter_delete_cq(dev, qid);
1250 static const struct blk_mq_ops nvme_mq_admin_ops = {
1251 .queue_rq = nvme_queue_rq,
1252 .complete = nvme_pci_complete_rq,
1253 .init_hctx = nvme_admin_init_hctx,
1254 .exit_hctx = nvme_admin_exit_hctx,
1255 .init_request = nvme_admin_init_request,
1256 .timeout = nvme_timeout,
1259 static const struct blk_mq_ops nvme_mq_ops = {
1260 .queue_rq = nvme_queue_rq,
1261 .complete = nvme_pci_complete_rq,
1262 .init_hctx = nvme_init_hctx,
1263 .init_request = nvme_init_request,
1264 .map_queues = nvme_pci_map_queues,
1265 .timeout = nvme_timeout,
1269 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1271 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1273 * If the controller was reset during removal, it's possible
1274 * user requests may be waiting on a stopped queue. Start the
1275 * queue to flush these to completion.
1277 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1278 blk_cleanup_queue(dev->ctrl.admin_q);
1279 blk_mq_free_tag_set(&dev->admin_tagset);
1283 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1285 if (!dev->ctrl.admin_q) {
1286 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1287 dev->admin_tagset.nr_hw_queues = 1;
1290 * Subtract one to leave an empty queue entry for 'Full Queue'
1291 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1293 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1294 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1295 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1296 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1297 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1298 dev->admin_tagset.driver_data = dev;
1300 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1303 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1304 if (IS_ERR(dev->ctrl.admin_q)) {
1305 blk_mq_free_tag_set(&dev->admin_tagset);
1308 if (!blk_get_queue(dev->ctrl.admin_q)) {
1309 nvme_dev_remove_admin(dev);
1310 dev->ctrl.admin_q = NULL;
1314 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1319 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1323 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1324 struct nvme_queue *nvmeq;
1326 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1327 NVME_CAP_NSSRC(cap) : 0;
1329 if (dev->subsystem &&
1330 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1331 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1333 result = nvme_disable_ctrl(&dev->ctrl, cap);
1337 nvmeq = dev->queues[0];
1339 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1340 dev_to_node(dev->dev));
1345 aqa = nvmeq->q_depth - 1;
1348 writel(aqa, dev->bar + NVME_REG_AQA);
1349 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1350 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1352 result = nvme_enable_ctrl(&dev->ctrl, cap);
1356 nvmeq->cq_vector = 0;
1357 result = queue_request_irq(nvmeq);
1359 nvmeq->cq_vector = -1;
1366 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1369 /* If true, indicates loss of adapter communication, possibly by a
1370 * NVMe Subsystem reset.
1372 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1374 /* If there is a reset ongoing, we shouldn't reset again. */
1375 if (work_busy(&dev->reset_work))
1378 /* We shouldn't reset unless the controller is on fatal error state
1379 * _or_ if we lost the communication with it.
1381 if (!(csts & NVME_CSTS_CFS) && !nssro)
1384 /* If PCI error recovery process is happening, we cannot reset or
1385 * the recovery mechanism will surely fail.
1387 if (pci_channel_offline(to_pci_dev(dev->dev)))
1393 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1395 /* Read a config register to help see what died. */
1399 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1401 if (result == PCIBIOS_SUCCESSFUL)
1403 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1407 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1411 static void nvme_watchdog_timer(unsigned long data)
1413 struct nvme_dev *dev = (struct nvme_dev *)data;
1414 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1416 /* Skip controllers under certain specific conditions. */
1417 if (nvme_should_reset(dev, csts)) {
1418 if (!nvme_reset(dev))
1419 nvme_warn_reset(dev, csts);
1423 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1426 static int nvme_create_io_queues(struct nvme_dev *dev)
1431 for (i = dev->queue_count; i <= dev->max_qid; i++) {
1432 /* vector == qid - 1, match nvme_create_queue */
1433 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1434 pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1440 max = min(dev->max_qid, dev->queue_count - 1);
1441 for (i = dev->online_queues; i <= max; i++) {
1442 ret = nvme_create_queue(dev->queues[i], i);
1448 * Ignore failing Create SQ/CQ commands, we can continue with less
1449 * than the desired aount of queues, and even a controller without
1450 * I/O queues an still be used to issue admin commands. This might
1451 * be useful to upgrade a buggy firmware for example.
1453 return ret >= 0 ? 0 : ret;
1456 static ssize_t nvme_cmb_show(struct device *dev,
1457 struct device_attribute *attr,
1460 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1462 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1463 ndev->cmbloc, ndev->cmbsz);
1465 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1467 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1469 u64 szu, size, offset;
1470 resource_size_t bar_size;
1471 struct pci_dev *pdev = to_pci_dev(dev->dev);
1473 dma_addr_t dma_addr;
1475 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1476 if (!(NVME_CMB_SZ(dev->cmbsz)))
1478 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1483 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1484 size = szu * NVME_CMB_SZ(dev->cmbsz);
1485 offset = szu * NVME_CMB_OFST(dev->cmbloc);
1486 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1488 if (offset > bar_size)
1492 * Controllers may support a CMB size larger than their BAR,
1493 * for example, due to being behind a bridge. Reduce the CMB to
1494 * the reported size of the BAR
1496 if (size > bar_size - offset)
1497 size = bar_size - offset;
1499 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1500 cmb = ioremap_wc(dma_addr, size);
1504 dev->cmb_dma_addr = dma_addr;
1505 dev->cmb_size = size;
1509 static inline void nvme_release_cmb(struct nvme_dev *dev)
1517 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1519 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1522 static int nvme_setup_io_queues(struct nvme_dev *dev)
1524 struct nvme_queue *adminq = dev->queues[0];
1525 struct pci_dev *pdev = to_pci_dev(dev->dev);
1526 int result, nr_io_queues, size;
1528 nr_io_queues = num_online_cpus();
1529 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1533 if (nr_io_queues == 0)
1536 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1537 result = nvme_cmb_qdepth(dev, nr_io_queues,
1538 sizeof(struct nvme_command));
1540 dev->q_depth = result;
1542 nvme_release_cmb(dev);
1545 size = db_bar_size(dev, nr_io_queues);
1549 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1552 if (!--nr_io_queues)
1554 size = db_bar_size(dev, nr_io_queues);
1556 dev->dbs = dev->bar + 4096;
1557 adminq->q_db = dev->dbs;
1560 /* Deregister the admin queue's interrupt */
1561 free_irq(pci_irq_vector(pdev, 0), adminq);
1564 * If we enable msix early due to not intx, disable it again before
1565 * setting up the full range we need.
1567 pci_free_irq_vectors(pdev);
1568 nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1569 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1570 if (nr_io_queues <= 0)
1572 dev->max_qid = nr_io_queues;
1575 * Should investigate if there's a performance win from allocating
1576 * more queues than interrupt vectors; it might allow the submission
1577 * path to scale better, even if the receive path is limited by the
1578 * number of interrupts.
1581 result = queue_request_irq(adminq);
1583 adminq->cq_vector = -1;
1586 return nvme_create_io_queues(dev);
1589 static void nvme_del_queue_end(struct request *req, int error)
1591 struct nvme_queue *nvmeq = req->end_io_data;
1593 blk_mq_free_request(req);
1594 complete(&nvmeq->dev->ioq_wait);
1597 static void nvme_del_cq_end(struct request *req, int error)
1599 struct nvme_queue *nvmeq = req->end_io_data;
1602 unsigned long flags;
1605 * We might be called with the AQ q_lock held
1606 * and the I/O queue q_lock should always
1607 * nest inside the AQ one.
1609 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1610 SINGLE_DEPTH_NESTING);
1611 nvme_process_cq(nvmeq);
1612 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1615 nvme_del_queue_end(req, error);
1618 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1620 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1621 struct request *req;
1622 struct nvme_command cmd;
1624 memset(&cmd, 0, sizeof(cmd));
1625 cmd.delete_queue.opcode = opcode;
1626 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1628 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1630 return PTR_ERR(req);
1632 req->timeout = ADMIN_TIMEOUT;
1633 req->end_io_data = nvmeq;
1635 blk_execute_rq_nowait(q, NULL, req, false,
1636 opcode == nvme_admin_delete_cq ?
1637 nvme_del_cq_end : nvme_del_queue_end);
1641 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1644 unsigned long timeout;
1645 u8 opcode = nvme_admin_delete_sq;
1647 for (pass = 0; pass < 2; pass++) {
1648 int sent = 0, i = queues;
1650 reinit_completion(&dev->ioq_wait);
1652 timeout = ADMIN_TIMEOUT;
1653 for (; i > 0; i--, sent++)
1654 if (nvme_delete_queue(dev->queues[i], opcode))
1658 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1664 opcode = nvme_admin_delete_cq;
1669 * Return: error value if an error occurred setting up the queues or calling
1670 * Identify Device. 0 if these succeeded, even if adding some of the
1671 * namespaces failed. At the moment, these failures are silent. TBD which
1672 * failures should be reported.
1674 static int nvme_dev_add(struct nvme_dev *dev)
1676 if (!dev->ctrl.tagset) {
1677 dev->tagset.ops = &nvme_mq_ops;
1678 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1679 dev->tagset.timeout = NVME_IO_TIMEOUT;
1680 dev->tagset.numa_node = dev_to_node(dev->dev);
1681 dev->tagset.queue_depth =
1682 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1683 dev->tagset.cmd_size = nvme_cmd_size(dev);
1684 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1685 dev->tagset.driver_data = dev;
1687 if (blk_mq_alloc_tag_set(&dev->tagset))
1689 dev->ctrl.tagset = &dev->tagset;
1691 nvme_dbbuf_set(dev);
1693 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1695 /* Free previously allocated queues that are no longer usable */
1696 nvme_free_queues(dev, dev->online_queues);
1702 static int nvme_pci_enable(struct nvme_dev *dev)
1705 int result = -ENOMEM;
1706 struct pci_dev *pdev = to_pci_dev(dev->dev);
1708 if (pci_enable_device_mem(pdev))
1711 pci_set_master(pdev);
1713 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1714 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1717 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1723 * Some devices and/or platforms don't advertise or work with INTx
1724 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1725 * adjust this later.
1727 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1731 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1733 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1734 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1735 dev->dbs = dev->bar + 4096;
1738 * Temporary fix for the Apple controller found in the MacBook8,1 and
1739 * some MacBook7,1 to avoid controller resets and data loss.
1741 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1743 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1744 "queue depth=%u to work around controller resets\n",
1749 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1750 * populate sysfs if a CMB is implemented. Note that we add the
1751 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1752 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1753 * NULL as final argument to sysfs_add_file_to_group.
1756 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1757 dev->cmb = nvme_map_cmb(dev);
1760 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1761 &dev_attr_cmb.attr, NULL))
1763 "failed to add sysfs attribute for CMB\n");
1767 pci_enable_pcie_error_reporting(pdev);
1768 pci_save_state(pdev);
1772 pci_disable_device(pdev);
1776 static void nvme_dev_unmap(struct nvme_dev *dev)
1780 pci_release_mem_regions(to_pci_dev(dev->dev));
1783 static void nvme_pci_disable(struct nvme_dev *dev)
1785 struct pci_dev *pdev = to_pci_dev(dev->dev);
1787 pci_free_irq_vectors(pdev);
1789 if (pci_is_enabled(pdev)) {
1790 pci_disable_pcie_error_reporting(pdev);
1791 pci_disable_device(pdev);
1795 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1799 struct pci_dev *pdev = to_pci_dev(dev->dev);
1801 del_timer_sync(&dev->watchdog_timer);
1803 mutex_lock(&dev->shutdown_lock);
1804 if (pci_is_enabled(pdev)) {
1805 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1807 if (dev->ctrl.state == NVME_CTRL_LIVE)
1808 nvme_start_freeze(&dev->ctrl);
1809 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
1810 pdev->error_state != pci_channel_io_normal);
1814 * Give the controller a chance to complete all entered requests if
1815 * doing a safe shutdown.
1817 if (!dead && shutdown)
1818 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
1819 nvme_stop_queues(&dev->ctrl);
1821 queues = dev->online_queues - 1;
1822 for (i = dev->queue_count - 1; i > 0; i--)
1823 nvme_suspend_queue(dev->queues[i]);
1826 /* A device might become IO incapable very soon during
1827 * probe, before the admin queue is configured. Thus,
1828 * queue_count can be 0 here.
1830 if (dev->queue_count)
1831 nvme_suspend_queue(dev->queues[0]);
1833 nvme_disable_io_queues(dev, queues);
1834 nvme_disable_admin_queue(dev, shutdown);
1836 nvme_pci_disable(dev);
1838 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
1839 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
1842 * The driver will not be starting up queues again if shutting down so
1843 * must flush all entered requests to their failed completion to avoid
1844 * deadlocking blk-mq hot-cpu notifier.
1847 nvme_start_queues(&dev->ctrl);
1848 mutex_unlock(&dev->shutdown_lock);
1851 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1853 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1854 PAGE_SIZE, PAGE_SIZE, 0);
1855 if (!dev->prp_page_pool)
1858 /* Optimisation for I/Os between 4k and 128k */
1859 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1861 if (!dev->prp_small_pool) {
1862 dma_pool_destroy(dev->prp_page_pool);
1868 static void nvme_release_prp_pools(struct nvme_dev *dev)
1870 dma_pool_destroy(dev->prp_page_pool);
1871 dma_pool_destroy(dev->prp_small_pool);
1874 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1876 struct nvme_dev *dev = to_nvme_dev(ctrl);
1878 nvme_dbbuf_dma_free(dev);
1879 put_device(dev->dev);
1880 if (dev->tagset.tags)
1881 blk_mq_free_tag_set(&dev->tagset);
1882 if (dev->ctrl.admin_q)
1883 blk_put_queue(dev->ctrl.admin_q);
1885 free_opal_dev(dev->ctrl.opal_dev);
1889 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1891 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1893 kref_get(&dev->ctrl.kref);
1894 nvme_dev_disable(dev, false);
1895 if (!schedule_work(&dev->remove_work))
1896 nvme_put_ctrl(&dev->ctrl);
1899 static void nvme_reset_work(struct work_struct *work)
1901 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1902 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
1903 int result = -ENODEV;
1905 if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1909 * If we're called to reset a live controller first shut it down before
1912 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1913 nvme_dev_disable(dev, false);
1915 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1918 result = nvme_pci_enable(dev);
1922 result = nvme_configure_admin_queue(dev);
1926 nvme_init_queue(dev->queues[0], 0);
1927 result = nvme_alloc_admin_tags(dev);
1931 result = nvme_init_identify(&dev->ctrl);
1935 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
1936 if (!dev->ctrl.opal_dev)
1937 dev->ctrl.opal_dev =
1938 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
1939 else if (was_suspend)
1940 opal_unlock_from_suspend(dev->ctrl.opal_dev);
1942 free_opal_dev(dev->ctrl.opal_dev);
1943 dev->ctrl.opal_dev = NULL;
1946 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
1947 result = nvme_dbbuf_dma_alloc(dev);
1950 "unable to allocate dma for dbbuf\n");
1953 result = nvme_setup_io_queues(dev);
1958 * A controller that can not execute IO typically requires user
1959 * intervention to correct. For such degraded controllers, the driver
1960 * should not submit commands the user did not request, so skip
1961 * registering for asynchronous event notification on this condition.
1963 if (dev->online_queues > 1)
1964 nvme_queue_async_events(&dev->ctrl);
1966 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1969 * Keep the controller around but remove all namespaces if we don't have
1970 * any working I/O queue.
1972 if (dev->online_queues < 2) {
1973 dev_warn(dev->ctrl.device, "IO queues not created\n");
1974 nvme_kill_queues(&dev->ctrl);
1975 nvme_remove_namespaces(&dev->ctrl);
1977 nvme_start_queues(&dev->ctrl);
1978 nvme_wait_freeze(&dev->ctrl);
1980 nvme_unfreeze(&dev->ctrl);
1983 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1984 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1988 if (dev->online_queues > 1)
1989 nvme_queue_scan(&dev->ctrl);
1993 nvme_remove_dead_ctrl(dev, result);
1996 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1998 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1999 struct pci_dev *pdev = to_pci_dev(dev->dev);
2001 nvme_kill_queues(&dev->ctrl);
2002 if (pci_get_drvdata(pdev))
2003 device_release_driver(&pdev->dev);
2004 nvme_put_ctrl(&dev->ctrl);
2007 static int nvme_reset(struct nvme_dev *dev)
2009 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
2011 if (work_busy(&dev->reset_work))
2013 if (!queue_work(nvme_workq, &dev->reset_work))
2018 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2020 *val = readl(to_nvme_dev(ctrl)->bar + off);
2024 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2026 writel(val, to_nvme_dev(ctrl)->bar + off);
2030 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2032 *val = readq(to_nvme_dev(ctrl)->bar + off);
2036 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2038 struct nvme_dev *dev = to_nvme_dev(ctrl);
2039 int ret = nvme_reset(dev);
2042 flush_work(&dev->reset_work);
2046 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2048 .module = THIS_MODULE,
2049 .reg_read32 = nvme_pci_reg_read32,
2050 .reg_write32 = nvme_pci_reg_write32,
2051 .reg_read64 = nvme_pci_reg_read64,
2052 .reset_ctrl = nvme_pci_reset_ctrl,
2053 .free_ctrl = nvme_pci_free_ctrl,
2054 .submit_async_event = nvme_pci_submit_async_event,
2057 static int nvme_dev_map(struct nvme_dev *dev)
2059 struct pci_dev *pdev = to_pci_dev(dev->dev);
2061 if (pci_request_mem_regions(pdev, "nvme"))
2064 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2070 pci_release_mem_regions(pdev);
2074 static unsigned long check_dell_samsung_bug(struct pci_dev *pdev)
2076 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2078 * Several Samsung devices seem to drop off the PCIe bus
2079 * randomly when APST is on and uses the deepest sleep state.
2080 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2081 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2082 * 950 PRO 256GB", but it seems to be restricted to two Dell
2085 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2086 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2087 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2088 return NVME_QUIRK_NO_DEEPEST_PS;
2094 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2096 int node, result = -ENOMEM;
2097 struct nvme_dev *dev;
2098 unsigned long quirks = id->driver_data;
2100 node = dev_to_node(&pdev->dev);
2101 if (node == NUMA_NO_NODE)
2102 set_dev_node(&pdev->dev, first_memory_node);
2104 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2107 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2112 dev->dev = get_device(&pdev->dev);
2113 pci_set_drvdata(pdev, dev);
2115 result = nvme_dev_map(dev);
2119 INIT_WORK(&dev->reset_work, nvme_reset_work);
2120 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2121 setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
2122 (unsigned long)dev);
2123 mutex_init(&dev->shutdown_lock);
2124 init_completion(&dev->ioq_wait);
2126 result = nvme_setup_prp_pools(dev);
2130 quirks |= check_dell_samsung_bug(pdev);
2132 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2137 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2139 queue_work(nvme_workq, &dev->reset_work);
2143 nvme_release_prp_pools(dev);
2145 put_device(dev->dev);
2146 nvme_dev_unmap(dev);
2153 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2155 struct nvme_dev *dev = pci_get_drvdata(pdev);
2158 nvme_dev_disable(dev, false);
2163 static void nvme_shutdown(struct pci_dev *pdev)
2165 struct nvme_dev *dev = pci_get_drvdata(pdev);
2166 nvme_dev_disable(dev, true);
2170 * The driver's remove may be called on a device in a partially initialized
2171 * state. This function must not have any dependencies on the device state in
2174 static void nvme_remove(struct pci_dev *pdev)
2176 struct nvme_dev *dev = pci_get_drvdata(pdev);
2178 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2180 pci_set_drvdata(pdev, NULL);
2182 if (!pci_device_is_present(pdev)) {
2183 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2184 nvme_dev_disable(dev, false);
2187 flush_work(&dev->reset_work);
2188 nvme_uninit_ctrl(&dev->ctrl);
2189 nvme_dev_disable(dev, true);
2190 nvme_dev_remove_admin(dev);
2191 nvme_free_queues(dev, 0);
2192 nvme_release_cmb(dev);
2193 nvme_release_prp_pools(dev);
2194 nvme_dev_unmap(dev);
2195 nvme_put_ctrl(&dev->ctrl);
2198 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2203 if (pci_vfs_assigned(pdev)) {
2204 dev_warn(&pdev->dev,
2205 "Cannot disable SR-IOV VFs while assigned\n");
2208 pci_disable_sriov(pdev);
2212 ret = pci_enable_sriov(pdev, numvfs);
2213 return ret ? ret : numvfs;
2216 #ifdef CONFIG_PM_SLEEP
2217 static int nvme_suspend(struct device *dev)
2219 struct pci_dev *pdev = to_pci_dev(dev);
2220 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2222 nvme_dev_disable(ndev, true);
2226 static int nvme_resume(struct device *dev)
2228 struct pci_dev *pdev = to_pci_dev(dev);
2229 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2236 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2238 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2239 pci_channel_state_t state)
2241 struct nvme_dev *dev = pci_get_drvdata(pdev);
2244 * A frozen channel requires a reset. When detected, this method will
2245 * shutdown the controller to quiesce. The controller will be restarted
2246 * after the slot reset through driver's slot_reset callback.
2249 case pci_channel_io_normal:
2250 return PCI_ERS_RESULT_CAN_RECOVER;
2251 case pci_channel_io_frozen:
2252 dev_warn(dev->ctrl.device,
2253 "frozen state error detected, reset controller\n");
2254 nvme_dev_disable(dev, false);
2255 return PCI_ERS_RESULT_NEED_RESET;
2256 case pci_channel_io_perm_failure:
2257 dev_warn(dev->ctrl.device,
2258 "failure state error detected, request disconnect\n");
2259 return PCI_ERS_RESULT_DISCONNECT;
2261 return PCI_ERS_RESULT_NEED_RESET;
2264 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2266 struct nvme_dev *dev = pci_get_drvdata(pdev);
2268 dev_info(dev->ctrl.device, "restart after slot reset\n");
2269 pci_restore_state(pdev);
2271 return PCI_ERS_RESULT_RECOVERED;
2274 static void nvme_error_resume(struct pci_dev *pdev)
2276 pci_cleanup_aer_uncorrect_error_status(pdev);
2279 static const struct pci_error_handlers nvme_err_handler = {
2280 .error_detected = nvme_error_detected,
2281 .slot_reset = nvme_slot_reset,
2282 .resume = nvme_error_resume,
2283 .reset_notify = nvme_reset_notify,
2286 static const struct pci_device_id nvme_id_table[] = {
2287 { PCI_VDEVICE(INTEL, 0x0953),
2288 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2289 NVME_QUIRK_DEALLOCATE_ZEROES, },
2290 { PCI_VDEVICE(INTEL, 0x0a53),
2291 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2292 NVME_QUIRK_DEALLOCATE_ZEROES, },
2293 { PCI_VDEVICE(INTEL, 0x0a54),
2294 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2295 NVME_QUIRK_DEALLOCATE_ZEROES, },
2296 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2297 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2298 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2299 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2300 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2301 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2302 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2303 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2304 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2307 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2309 static struct pci_driver nvme_driver = {
2311 .id_table = nvme_id_table,
2312 .probe = nvme_probe,
2313 .remove = nvme_remove,
2314 .shutdown = nvme_shutdown,
2316 .pm = &nvme_dev_pm_ops,
2318 .sriov_configure = nvme_pci_sriov_configure,
2319 .err_handler = &nvme_err_handler,
2322 static int __init nvme_init(void)
2326 nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2330 result = pci_register_driver(&nvme_driver);
2332 destroy_workqueue(nvme_workq);
2336 static void __exit nvme_exit(void)
2338 pci_unregister_driver(&nvme_driver);
2339 destroy_workqueue(nvme_workq);
2343 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2344 MODULE_LICENSE("GPL");
2345 MODULE_VERSION("1.0");
2346 module_init(nvme_init);
2347 module_exit(nvme_exit);