2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/async.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/once.h>
28 #include <linux/pci.h>
29 #include <linux/t10-pi.h>
30 #include <linux/types.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include <linux/sed-opal.h>
33 #include <linux/pci-p2pdma.h>
37 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
38 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
40 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
43 * These can be higher, but we need to ensure that any command doesn't
44 * require an sg allocation that needs more than a page of data.
46 #define NVME_MAX_KB_SZ 4096
47 #define NVME_MAX_SEGS 127
49 static int use_threaded_interrupts;
50 module_param(use_threaded_interrupts, int, 0);
52 static bool use_cmb_sqes = true;
53 module_param(use_cmb_sqes, bool, 0444);
54 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
56 static unsigned int max_host_mem_size_mb = 128;
57 module_param(max_host_mem_size_mb, uint, 0444);
58 MODULE_PARM_DESC(max_host_mem_size_mb,
59 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
61 static unsigned int sgl_threshold = SZ_32K;
62 module_param(sgl_threshold, uint, 0644);
63 MODULE_PARM_DESC(sgl_threshold,
64 "Use SGLs when average request segment size is larger or equal to "
65 "this size. Use 0 to disable SGLs.");
67 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68 static const struct kernel_param_ops io_queue_depth_ops = {
69 .set = io_queue_depth_set,
73 static int io_queue_depth = 1024;
74 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
75 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
80 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
83 * Represents an NVM Express device. Each nvme_dev is a PCI function.
86 struct nvme_queue *queues;
87 struct blk_mq_tag_set tagset;
88 struct blk_mq_tag_set admin_tagset;
91 struct dma_pool *prp_page_pool;
92 struct dma_pool *prp_small_pool;
93 unsigned online_queues;
95 unsigned int num_vecs;
99 unsigned long bar_mapped_size;
100 struct work_struct remove_work;
101 struct mutex shutdown_lock;
107 struct nvme_ctrl ctrl;
108 struct completion ioq_wait;
110 mempool_t *iod_mempool;
112 /* shadow doorbell buffer support: */
114 dma_addr_t dbbuf_dbs_dma_addr;
116 dma_addr_t dbbuf_eis_dma_addr;
118 /* host memory buffer support: */
120 u32 nr_host_mem_descs;
121 dma_addr_t host_mem_descs_dma;
122 struct nvme_host_mem_buf_desc *host_mem_descs;
123 void **host_mem_desc_bufs;
126 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
130 ret = kstrtoint(val, 10, &n);
131 if (ret != 0 || n < 2)
134 return param_set_int(val, kp);
137 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
139 return qid * 2 * stride;
142 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
144 return (qid * 2 + 1) * stride;
147 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
149 return container_of(ctrl, struct nvme_dev, ctrl);
153 * An NVM Express queue. Each device has at least two (one for admin
154 * commands and one for I/O commands).
157 struct device *q_dmadev;
158 struct nvme_dev *dev;
160 struct nvme_command *sq_cmds;
162 spinlock_t cq_lock ____cacheline_aligned_in_smp;
163 volatile struct nvme_completion *cqes;
164 struct blk_mq_tags **tags;
165 dma_addr_t sq_dma_addr;
166 dma_addr_t cq_dma_addr;
182 * The nvme_iod describes the data in an I/O, including the list of PRP
183 * entries. You can't see it in this data structure because C doesn't let
184 * me express that. Use nvme_init_iod to ensure there's enough space
185 * allocated to store the PRP list.
188 struct nvme_request req;
189 struct nvme_queue *nvmeq;
192 int npages; /* In the PRP list. 0 means small pool in use */
193 int nents; /* Used in scatterlist */
194 int length; /* Of data, in bytes */
195 dma_addr_t first_dma;
196 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
197 struct scatterlist *sg;
198 struct scatterlist inline_sg[0];
202 * Check we didin't inadvertently grow the command struct
204 static inline void _nvme_check_size(void)
206 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
207 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
208 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
209 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
210 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
211 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
212 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
213 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
214 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
215 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
216 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
217 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
218 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
221 static inline unsigned int nvme_dbbuf_size(u32 stride)
223 return ((num_possible_cpus() + 1) * 8 * stride);
226 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
228 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
233 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
234 &dev->dbbuf_dbs_dma_addr,
238 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
239 &dev->dbbuf_eis_dma_addr,
241 if (!dev->dbbuf_eis) {
242 dma_free_coherent(dev->dev, mem_size,
243 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
244 dev->dbbuf_dbs = NULL;
251 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
253 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
255 if (dev->dbbuf_dbs) {
256 dma_free_coherent(dev->dev, mem_size,
257 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
258 dev->dbbuf_dbs = NULL;
260 if (dev->dbbuf_eis) {
261 dma_free_coherent(dev->dev, mem_size,
262 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
263 dev->dbbuf_eis = NULL;
267 static void nvme_dbbuf_init(struct nvme_dev *dev,
268 struct nvme_queue *nvmeq, int qid)
270 if (!dev->dbbuf_dbs || !qid)
273 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
274 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
275 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
276 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
279 static void nvme_dbbuf_set(struct nvme_dev *dev)
281 struct nvme_command c;
286 memset(&c, 0, sizeof(c));
287 c.dbbuf.opcode = nvme_admin_dbbuf;
288 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
289 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
291 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
292 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
293 /* Free memory and continue on */
294 nvme_dbbuf_dma_free(dev);
298 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
300 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
303 /* Update dbbuf and return true if an MMIO is required */
304 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
305 volatile u32 *dbbuf_ei)
311 * Ensure that the queue is written before updating
312 * the doorbell in memory
316 old_value = *dbbuf_db;
320 * Ensure that the doorbell is updated before reading the event
321 * index from memory. The controller needs to provide similar
322 * ordering to ensure the envent index is updated before reading
327 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
335 * Max size of iod being embedded in the request payload
337 #define NVME_INT_PAGES 2
338 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
341 * Will slightly overestimate the number of pages needed. This is OK
342 * as it only leads to a small amount of wasted memory for the lifetime of
345 static int nvme_npages(unsigned size, struct nvme_dev *dev)
347 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
348 dev->ctrl.page_size);
349 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
353 * Calculates the number of pages needed for the SGL segments. For example a 4k
354 * page can accommodate 256 SGL descriptors.
356 static int nvme_pci_npages_sgl(unsigned int num_seg)
358 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
361 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
362 unsigned int size, unsigned int nseg, bool use_sgl)
367 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
369 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
371 return alloc_size + sizeof(struct scatterlist) * nseg;
374 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
376 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
377 NVME_INT_BYTES(dev), NVME_INT_PAGES,
380 return sizeof(struct nvme_iod) + alloc_size;
383 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
384 unsigned int hctx_idx)
386 struct nvme_dev *dev = data;
387 struct nvme_queue *nvmeq = &dev->queues[0];
389 WARN_ON(hctx_idx != 0);
390 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
391 WARN_ON(nvmeq->tags);
393 hctx->driver_data = nvmeq;
394 nvmeq->tags = &dev->admin_tagset.tags[0];
398 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
400 struct nvme_queue *nvmeq = hctx->driver_data;
405 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
406 unsigned int hctx_idx)
408 struct nvme_dev *dev = data;
409 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
412 nvmeq->tags = &dev->tagset.tags[hctx_idx];
414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
415 hctx->driver_data = nvmeq;
419 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
420 unsigned int hctx_idx, unsigned int numa_node)
422 struct nvme_dev *dev = set->driver_data;
423 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
424 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
425 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
430 nvme_req(req)->ctrl = &dev->ctrl;
434 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
436 struct nvme_dev *dev = set->driver_data;
438 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
439 dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
443 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
444 * @nvmeq: The queue to use
445 * @cmd: The command to send
447 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
449 spin_lock(&nvmeq->sq_lock);
451 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
453 if (++nvmeq->sq_tail == nvmeq->q_depth)
455 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
456 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
457 writel(nvmeq->sq_tail, nvmeq->q_db);
458 spin_unlock(&nvmeq->sq_lock);
461 static void **nvme_pci_iod_list(struct request *req)
463 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
464 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
467 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
469 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
470 int nseg = blk_rq_nr_phys_segments(req);
471 unsigned int avg_seg_size;
476 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
478 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
480 if (!iod->nvmeq->qid)
482 if (!sgl_threshold || avg_seg_size < sgl_threshold)
487 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
489 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
490 int nseg = blk_rq_nr_phys_segments(rq);
491 unsigned int size = blk_rq_payload_bytes(rq);
493 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
495 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
496 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
498 return BLK_STS_RESOURCE;
500 iod->sg = iod->inline_sg;
511 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
513 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
514 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
515 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
519 if (iod->npages == 0)
520 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
523 for (i = 0; i < iod->npages; i++) {
524 void *addr = nvme_pci_iod_list(req)[i];
527 struct nvme_sgl_desc *sg_list = addr;
530 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
532 __le64 *prp_list = addr;
534 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
537 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
538 dma_addr = next_dma_addr;
541 if (iod->sg != iod->inline_sg)
542 mempool_free(iod->sg, dev->iod_mempool);
545 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
548 struct scatterlist *sg;
550 for_each_sg(sgl, sg, nents, i) {
551 dma_addr_t phys = sg_phys(sg);
552 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
553 "dma_address:%pad dma_length:%d\n",
554 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
559 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
560 struct request *req, struct nvme_rw_command *cmnd)
562 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
563 struct dma_pool *pool;
564 int length = blk_rq_payload_bytes(req);
565 struct scatterlist *sg = iod->sg;
566 int dma_len = sg_dma_len(sg);
567 u64 dma_addr = sg_dma_address(sg);
568 u32 page_size = dev->ctrl.page_size;
569 int offset = dma_addr & (page_size - 1);
571 void **list = nvme_pci_iod_list(req);
575 length -= (page_size - offset);
581 dma_len -= (page_size - offset);
583 dma_addr += (page_size - offset);
586 dma_addr = sg_dma_address(sg);
587 dma_len = sg_dma_len(sg);
590 if (length <= page_size) {
591 iod->first_dma = dma_addr;
595 nprps = DIV_ROUND_UP(length, page_size);
596 if (nprps <= (256 / 8)) {
597 pool = dev->prp_small_pool;
600 pool = dev->prp_page_pool;
604 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
606 iod->first_dma = dma_addr;
608 return BLK_STS_RESOURCE;
611 iod->first_dma = prp_dma;
614 if (i == page_size >> 3) {
615 __le64 *old_prp_list = prp_list;
616 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
618 return BLK_STS_RESOURCE;
619 list[iod->npages++] = prp_list;
620 prp_list[0] = old_prp_list[i - 1];
621 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
624 prp_list[i++] = cpu_to_le64(dma_addr);
625 dma_len -= page_size;
626 dma_addr += page_size;
632 if (unlikely(dma_len < 0))
635 dma_addr = sg_dma_address(sg);
636 dma_len = sg_dma_len(sg);
640 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
641 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
646 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
647 "Invalid SGL for payload:%d nents:%d\n",
648 blk_rq_payload_bytes(req), iod->nents);
649 return BLK_STS_IOERR;
652 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
653 struct scatterlist *sg)
655 sge->addr = cpu_to_le64(sg_dma_address(sg));
656 sge->length = cpu_to_le32(sg_dma_len(sg));
657 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
660 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
661 dma_addr_t dma_addr, int entries)
663 sge->addr = cpu_to_le64(dma_addr);
664 if (entries < SGES_PER_PAGE) {
665 sge->length = cpu_to_le32(entries * sizeof(*sge));
666 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
668 sge->length = cpu_to_le32(PAGE_SIZE);
669 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
673 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
674 struct request *req, struct nvme_rw_command *cmd, int entries)
676 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
677 struct dma_pool *pool;
678 struct nvme_sgl_desc *sg_list;
679 struct scatterlist *sg = iod->sg;
683 /* setting the transfer type as SGL */
684 cmd->flags = NVME_CMD_SGL_METABUF;
687 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
691 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
692 pool = dev->prp_small_pool;
695 pool = dev->prp_page_pool;
699 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
702 return BLK_STS_RESOURCE;
705 nvme_pci_iod_list(req)[0] = sg_list;
706 iod->first_dma = sgl_dma;
708 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
711 if (i == SGES_PER_PAGE) {
712 struct nvme_sgl_desc *old_sg_desc = sg_list;
713 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
715 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
717 return BLK_STS_RESOURCE;
720 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
721 sg_list[i++] = *link;
722 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
725 nvme_pci_sgl_set_data(&sg_list[i++], sg);
727 } while (--entries > 0);
732 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
733 struct nvme_command *cmnd)
735 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
736 struct request_queue *q = req->q;
737 enum dma_data_direction dma_dir = rq_data_dir(req) ?
738 DMA_TO_DEVICE : DMA_FROM_DEVICE;
739 blk_status_t ret = BLK_STS_IOERR;
742 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
743 iod->nents = blk_rq_map_sg(q, req, iod->sg);
747 ret = BLK_STS_RESOURCE;
749 if (is_pci_p2pdma_page(sg_page(iod->sg)))
750 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
753 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
754 dma_dir, DMA_ATTR_NO_WARN);
759 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
761 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
763 if (ret != BLK_STS_OK)
767 if (blk_integrity_rq(req)) {
768 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
771 sg_init_table(&iod->meta_sg, 1);
772 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
775 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
778 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
784 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
789 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
791 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
792 enum dma_data_direction dma_dir = rq_data_dir(req) ?
793 DMA_TO_DEVICE : DMA_FROM_DEVICE;
796 /* P2PDMA requests do not need to be unmapped */
797 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
798 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
800 if (blk_integrity_rq(req))
801 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
804 nvme_cleanup_cmd(req);
805 nvme_free_iod(dev, req);
809 * NOTE: ns is NULL when called on the admin queue.
811 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
812 const struct blk_mq_queue_data *bd)
814 struct nvme_ns *ns = hctx->queue->queuedata;
815 struct nvme_queue *nvmeq = hctx->driver_data;
816 struct nvme_dev *dev = nvmeq->dev;
817 struct request *req = bd->rq;
818 struct nvme_command cmnd;
822 * We should not need to do this, but we're still using this to
823 * ensure we can drain requests on a dying queue.
825 if (unlikely(nvmeq->cq_vector < 0))
826 return BLK_STS_IOERR;
828 ret = nvme_setup_cmd(ns, req, &cmnd);
832 ret = nvme_init_iod(req, dev);
836 if (blk_rq_nr_phys_segments(req)) {
837 ret = nvme_map_data(dev, req, &cmnd);
839 goto out_cleanup_iod;
842 blk_mq_start_request(req);
843 nvme_submit_cmd(nvmeq, &cmnd);
846 nvme_free_iod(dev, req);
848 nvme_cleanup_cmd(req);
852 static void nvme_pci_complete_rq(struct request *req)
854 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
856 nvme_unmap_data(iod->nvmeq->dev, req);
857 nvme_complete_rq(req);
860 /* We read the CQE phase first to check if the rest of the entry is valid */
861 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
863 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
867 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
869 u16 head = nvmeq->cq_head;
871 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
873 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
876 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
878 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
881 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
882 dev_warn(nvmeq->dev->ctrl.device,
883 "invalid id %d completed on queue %d\n",
884 cqe->command_id, le16_to_cpu(cqe->sq_id));
889 * AEN requests are special as they don't time out and can
890 * survive any kind of queue freeze and often don't respond to
891 * aborts. We don't even bother to allocate a struct request
892 * for them but rather special case them here.
894 if (unlikely(nvmeq->qid == 0 &&
895 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
896 nvme_complete_async_event(&nvmeq->dev->ctrl,
897 cqe->status, &cqe->result);
901 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
902 nvme_end_request(req, cqe->status, cqe->result);
905 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
907 while (start != end) {
908 nvme_handle_cqe(nvmeq, start);
909 if (++start == nvmeq->q_depth)
914 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
916 if (++nvmeq->cq_head == nvmeq->q_depth) {
918 nvmeq->cq_phase = !nvmeq->cq_phase;
922 static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
927 *start = nvmeq->cq_head;
928 while (!found && nvme_cqe_pending(nvmeq)) {
929 if (nvmeq->cqes[nvmeq->cq_head].command_id == tag)
931 nvme_update_cq_head(nvmeq);
933 *end = nvmeq->cq_head;
936 nvme_ring_cq_doorbell(nvmeq);
940 static irqreturn_t nvme_irq(int irq, void *data)
942 struct nvme_queue *nvmeq = data;
943 irqreturn_t ret = IRQ_NONE;
946 spin_lock(&nvmeq->cq_lock);
947 if (nvmeq->cq_head != nvmeq->last_cq_head)
949 nvme_process_cq(nvmeq, &start, &end, -1);
950 nvmeq->last_cq_head = nvmeq->cq_head;
951 spin_unlock(&nvmeq->cq_lock);
954 nvme_complete_cqes(nvmeq, start, end);
961 static irqreturn_t nvme_irq_check(int irq, void *data)
963 struct nvme_queue *nvmeq = data;
964 if (nvme_cqe_pending(nvmeq))
965 return IRQ_WAKE_THREAD;
969 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
974 if (!nvme_cqe_pending(nvmeq))
977 spin_lock_irq(&nvmeq->cq_lock);
978 found = nvme_process_cq(nvmeq, &start, &end, tag);
979 spin_unlock_irq(&nvmeq->cq_lock);
981 nvme_complete_cqes(nvmeq, start, end);
985 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
987 struct nvme_queue *nvmeq = hctx->driver_data;
989 return __nvme_poll(nvmeq, tag);
992 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
994 struct nvme_dev *dev = to_nvme_dev(ctrl);
995 struct nvme_queue *nvmeq = &dev->queues[0];
996 struct nvme_command c;
998 memset(&c, 0, sizeof(c));
999 c.common.opcode = nvme_admin_async_event;
1000 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1001 nvme_submit_cmd(nvmeq, &c);
1004 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1006 struct nvme_command c;
1008 memset(&c, 0, sizeof(c));
1009 c.delete_queue.opcode = opcode;
1010 c.delete_queue.qid = cpu_to_le16(id);
1012 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1015 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1016 struct nvme_queue *nvmeq, s16 vector)
1018 struct nvme_command c;
1019 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1022 * Note: we (ab)use the fact that the prp fields survive if no data
1023 * is attached to the request.
1025 memset(&c, 0, sizeof(c));
1026 c.create_cq.opcode = nvme_admin_create_cq;
1027 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1028 c.create_cq.cqid = cpu_to_le16(qid);
1029 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1030 c.create_cq.cq_flags = cpu_to_le16(flags);
1031 c.create_cq.irq_vector = cpu_to_le16(vector);
1033 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1036 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1037 struct nvme_queue *nvmeq)
1039 struct nvme_ctrl *ctrl = &dev->ctrl;
1040 struct nvme_command c;
1041 int flags = NVME_QUEUE_PHYS_CONTIG;
1044 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1045 * set. Since URGENT priority is zeroes, it makes all queues
1048 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1049 flags |= NVME_SQ_PRIO_MEDIUM;
1052 * Note: we (ab)use the fact that the prp fields survive if no data
1053 * is attached to the request.
1055 memset(&c, 0, sizeof(c));
1056 c.create_sq.opcode = nvme_admin_create_sq;
1057 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1058 c.create_sq.sqid = cpu_to_le16(qid);
1059 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1060 c.create_sq.sq_flags = cpu_to_le16(flags);
1061 c.create_sq.cqid = cpu_to_le16(qid);
1063 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1066 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1068 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1071 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1073 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1076 static void abort_endio(struct request *req, blk_status_t error)
1078 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1079 struct nvme_queue *nvmeq = iod->nvmeq;
1081 dev_warn(nvmeq->dev->ctrl.device,
1082 "Abort status: 0x%x", nvme_req(req)->status);
1083 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1084 blk_mq_free_request(req);
1087 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1090 /* If true, indicates loss of adapter communication, possibly by a
1091 * NVMe Subsystem reset.
1093 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1095 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1096 switch (dev->ctrl.state) {
1097 case NVME_CTRL_RESETTING:
1098 case NVME_CTRL_CONNECTING:
1104 /* We shouldn't reset unless the controller is on fatal error state
1105 * _or_ if we lost the communication with it.
1107 if (!(csts & NVME_CSTS_CFS) && !nssro)
1113 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1115 /* Read a config register to help see what died. */
1119 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1121 if (result == PCIBIOS_SUCCESSFUL)
1122 dev_warn(dev->ctrl.device,
1123 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1126 dev_warn(dev->ctrl.device,
1127 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1131 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1133 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1134 struct nvme_queue *nvmeq = iod->nvmeq;
1135 struct nvme_dev *dev = nvmeq->dev;
1136 struct request *abort_req;
1137 struct nvme_command cmd;
1138 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1140 /* If PCI error recovery process is happening, we cannot reset or
1141 * the recovery mechanism will surely fail.
1144 if (pci_channel_offline(to_pci_dev(dev->dev)))
1145 return BLK_EH_RESET_TIMER;
1148 * Reset immediately if the controller is failed
1150 if (nvme_should_reset(dev, csts)) {
1151 nvme_warn_reset(dev, csts);
1152 nvme_dev_disable(dev, false);
1153 nvme_reset_ctrl(&dev->ctrl);
1158 * Did we miss an interrupt?
1160 if (__nvme_poll(nvmeq, req->tag)) {
1161 dev_warn(dev->ctrl.device,
1162 "I/O %d QID %d timeout, completion polled\n",
1163 req->tag, nvmeq->qid);
1168 * Shutdown immediately if controller times out while starting. The
1169 * reset work will see the pci device disabled when it gets the forced
1170 * cancellation error. All outstanding requests are completed on
1171 * shutdown, so we return BLK_EH_DONE.
1173 switch (dev->ctrl.state) {
1174 case NVME_CTRL_CONNECTING:
1175 case NVME_CTRL_RESETTING:
1176 dev_warn_ratelimited(dev->ctrl.device,
1177 "I/O %d QID %d timeout, disable controller\n",
1178 req->tag, nvmeq->qid);
1179 nvme_dev_disable(dev, false);
1180 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1187 * Shutdown the controller immediately and schedule a reset if the
1188 * command was already aborted once before and still hasn't been
1189 * returned to the driver, or if this is the admin queue.
1191 if (!nvmeq->qid || iod->aborted) {
1192 dev_warn(dev->ctrl.device,
1193 "I/O %d QID %d timeout, reset controller\n",
1194 req->tag, nvmeq->qid);
1195 nvme_dev_disable(dev, false);
1196 nvme_reset_ctrl(&dev->ctrl);
1198 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1202 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1203 atomic_inc(&dev->ctrl.abort_limit);
1204 return BLK_EH_RESET_TIMER;
1208 memset(&cmd, 0, sizeof(cmd));
1209 cmd.abort.opcode = nvme_admin_abort_cmd;
1210 cmd.abort.cid = req->tag;
1211 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1213 dev_warn(nvmeq->dev->ctrl.device,
1214 "I/O %d QID %d timeout, aborting\n",
1215 req->tag, nvmeq->qid);
1217 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1218 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1219 if (IS_ERR(abort_req)) {
1220 atomic_inc(&dev->ctrl.abort_limit);
1221 return BLK_EH_RESET_TIMER;
1224 abort_req->timeout = ADMIN_TIMEOUT;
1225 abort_req->end_io_data = NULL;
1226 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1229 * The aborted req will be completed on receiving the abort req.
1230 * We enable the timer again. If hit twice, it'll cause a device reset,
1231 * as the device then is in a faulty state.
1233 return BLK_EH_RESET_TIMER;
1236 static void nvme_free_queue(struct nvme_queue *nvmeq)
1238 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1239 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1241 if (nvmeq->sq_cmds) {
1242 if (nvmeq->sq_cmds_is_io)
1243 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1245 SQ_SIZE(nvmeq->q_depth));
1247 dma_free_coherent(nvmeq->q_dmadev,
1248 SQ_SIZE(nvmeq->q_depth),
1250 nvmeq->sq_dma_addr);
1254 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1258 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1259 dev->ctrl.queue_count--;
1260 nvme_free_queue(&dev->queues[i]);
1265 * nvme_suspend_queue - put queue into suspended state
1266 * @nvmeq: queue to suspend
1268 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1272 spin_lock_irq(&nvmeq->cq_lock);
1273 if (nvmeq->cq_vector == -1) {
1274 spin_unlock_irq(&nvmeq->cq_lock);
1277 vector = nvmeq->cq_vector;
1278 nvmeq->dev->online_queues--;
1279 nvmeq->cq_vector = -1;
1280 spin_unlock_irq(&nvmeq->cq_lock);
1283 * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without
1284 * having to grab the lock.
1288 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1289 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1291 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1296 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1298 struct nvme_queue *nvmeq = &dev->queues[0];
1302 nvme_shutdown_ctrl(&dev->ctrl);
1304 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1306 spin_lock_irq(&nvmeq->cq_lock);
1307 nvme_process_cq(nvmeq, &start, &end, -1);
1308 spin_unlock_irq(&nvmeq->cq_lock);
1310 nvme_complete_cqes(nvmeq, start, end);
1313 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1316 int q_depth = dev->q_depth;
1317 unsigned q_size_aligned = roundup(q_depth * entry_size,
1318 dev->ctrl.page_size);
1320 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1321 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1322 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1323 q_depth = div_u64(mem_per_q, entry_size);
1326 * Ensure the reduced q_depth is above some threshold where it
1327 * would be better to map queues in system memory with the
1337 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1340 struct pci_dev *pdev = to_pci_dev(dev->dev);
1342 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1343 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1344 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1346 nvmeq->sq_cmds_is_io = true;
1349 if (!nvmeq->sq_cmds) {
1350 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1351 &nvmeq->sq_dma_addr, GFP_KERNEL);
1352 nvmeq->sq_cmds_is_io = false;
1355 if (!nvmeq->sq_cmds)
1360 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1362 struct nvme_queue *nvmeq = &dev->queues[qid];
1364 if (dev->ctrl.queue_count > qid)
1367 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1368 &nvmeq->cq_dma_addr, GFP_KERNEL);
1372 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1375 nvmeq->q_dmadev = dev->dev;
1377 spin_lock_init(&nvmeq->sq_lock);
1378 spin_lock_init(&nvmeq->cq_lock);
1380 nvmeq->cq_phase = 1;
1381 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1382 nvmeq->q_depth = depth;
1384 nvmeq->cq_vector = -1;
1385 dev->ctrl.queue_count++;
1390 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1391 nvmeq->cq_dma_addr);
1396 static int queue_request_irq(struct nvme_queue *nvmeq)
1398 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1399 int nr = nvmeq->dev->ctrl.instance;
1401 if (use_threaded_interrupts) {
1402 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1403 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1405 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1406 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1410 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1412 struct nvme_dev *dev = nvmeq->dev;
1414 spin_lock_irq(&nvmeq->cq_lock);
1417 nvmeq->cq_phase = 1;
1418 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1419 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1420 nvme_dbbuf_init(dev, nvmeq, qid);
1421 dev->online_queues++;
1422 spin_unlock_irq(&nvmeq->cq_lock);
1425 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1427 struct nvme_dev *dev = nvmeq->dev;
1432 * A queue's vector matches the queue identifier unless the controller
1433 * has only one vector available.
1435 vector = dev->num_vecs == 1 ? 0 : qid;
1436 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1440 result = adapter_alloc_sq(dev, qid, nvmeq);
1447 * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will
1448 * invoke free_irq for it and cause a 'Trying to free already-free IRQ
1449 * xxx' warning if the create CQ/SQ command times out.
1451 nvmeq->cq_vector = vector;
1452 nvme_init_queue(nvmeq, qid);
1453 result = queue_request_irq(nvmeq);
1460 nvmeq->cq_vector = -1;
1461 dev->online_queues--;
1462 adapter_delete_sq(dev, qid);
1464 adapter_delete_cq(dev, qid);
1468 static const struct blk_mq_ops nvme_mq_admin_ops = {
1469 .queue_rq = nvme_queue_rq,
1470 .complete = nvme_pci_complete_rq,
1471 .init_hctx = nvme_admin_init_hctx,
1472 .exit_hctx = nvme_admin_exit_hctx,
1473 .init_request = nvme_init_request,
1474 .timeout = nvme_timeout,
1477 static const struct blk_mq_ops nvme_mq_ops = {
1478 .queue_rq = nvme_queue_rq,
1479 .complete = nvme_pci_complete_rq,
1480 .init_hctx = nvme_init_hctx,
1481 .init_request = nvme_init_request,
1482 .map_queues = nvme_pci_map_queues,
1483 .timeout = nvme_timeout,
1487 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1489 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1491 * If the controller was reset during removal, it's possible
1492 * user requests may be waiting on a stopped queue. Start the
1493 * queue to flush these to completion.
1495 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1496 blk_cleanup_queue(dev->ctrl.admin_q);
1497 blk_mq_free_tag_set(&dev->admin_tagset);
1501 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1503 if (!dev->ctrl.admin_q) {
1504 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1505 dev->admin_tagset.nr_hw_queues = 1;
1507 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1508 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1509 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1510 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1511 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1512 dev->admin_tagset.driver_data = dev;
1514 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1516 dev->ctrl.admin_tagset = &dev->admin_tagset;
1518 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1519 if (IS_ERR(dev->ctrl.admin_q)) {
1520 blk_mq_free_tag_set(&dev->admin_tagset);
1523 if (!blk_get_queue(dev->ctrl.admin_q)) {
1524 nvme_dev_remove_admin(dev);
1525 dev->ctrl.admin_q = NULL;
1529 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1534 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1536 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1539 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1541 struct pci_dev *pdev = to_pci_dev(dev->dev);
1543 if (size <= dev->bar_mapped_size)
1545 if (size > pci_resource_len(pdev, 0))
1549 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1551 dev->bar_mapped_size = 0;
1554 dev->bar_mapped_size = size;
1555 dev->dbs = dev->bar + NVME_REG_DBS;
1560 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1564 struct nvme_queue *nvmeq;
1566 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1570 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1571 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1573 if (dev->subsystem &&
1574 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1575 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1577 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1581 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1585 nvmeq = &dev->queues[0];
1586 aqa = nvmeq->q_depth - 1;
1589 writel(aqa, dev->bar + NVME_REG_AQA);
1590 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1591 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1593 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1597 nvmeq->cq_vector = 0;
1598 nvme_init_queue(nvmeq, 0);
1599 result = queue_request_irq(nvmeq);
1601 nvmeq->cq_vector = -1;
1608 static int nvme_create_io_queues(struct nvme_dev *dev)
1613 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1614 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1620 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1621 for (i = dev->online_queues; i <= max; i++) {
1622 ret = nvme_create_queue(&dev->queues[i], i);
1628 * Ignore failing Create SQ/CQ commands, we can continue with less
1629 * than the desired amount of queues, and even a controller without
1630 * I/O queues can still be used to issue admin commands. This might
1631 * be useful to upgrade a buggy firmware for example.
1633 return ret >= 0 ? 0 : ret;
1636 static ssize_t nvme_cmb_show(struct device *dev,
1637 struct device_attribute *attr,
1640 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1642 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1643 ndev->cmbloc, ndev->cmbsz);
1645 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1647 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1649 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1651 return 1ULL << (12 + 4 * szu);
1654 static u32 nvme_cmb_size(struct nvme_dev *dev)
1656 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1659 static void nvme_map_cmb(struct nvme_dev *dev)
1662 resource_size_t bar_size;
1663 struct pci_dev *pdev = to_pci_dev(dev->dev);
1669 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1672 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1674 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1675 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1676 bar = NVME_CMB_BIR(dev->cmbloc);
1677 bar_size = pci_resource_len(pdev, bar);
1679 if (offset > bar_size)
1683 * Controllers may support a CMB size larger than their BAR,
1684 * for example, due to being behind a bridge. Reduce the CMB to
1685 * the reported size of the BAR
1687 if (size > bar_size - offset)
1688 size = bar_size - offset;
1690 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1691 dev_warn(dev->ctrl.device,
1692 "failed to register the CMB\n");
1696 dev->cmb_size = size;
1697 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1699 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1700 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1701 pci_p2pmem_publish(pdev, true);
1703 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1704 &dev_attr_cmb.attr, NULL))
1705 dev_warn(dev->ctrl.device,
1706 "failed to add sysfs attribute for CMB\n");
1709 static inline void nvme_release_cmb(struct nvme_dev *dev)
1711 if (dev->cmb_size) {
1712 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1713 &dev_attr_cmb.attr, NULL);
1718 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1720 u64 dma_addr = dev->host_mem_descs_dma;
1721 struct nvme_command c;
1724 memset(&c, 0, sizeof(c));
1725 c.features.opcode = nvme_admin_set_features;
1726 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1727 c.features.dword11 = cpu_to_le32(bits);
1728 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1729 ilog2(dev->ctrl.page_size));
1730 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1731 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1732 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1734 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1736 dev_warn(dev->ctrl.device,
1737 "failed to set host mem (err %d, flags %#x).\n",
1743 static void nvme_free_host_mem(struct nvme_dev *dev)
1747 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1748 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1749 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1751 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1752 le64_to_cpu(desc->addr));
1755 kfree(dev->host_mem_desc_bufs);
1756 dev->host_mem_desc_bufs = NULL;
1757 dma_free_coherent(dev->dev,
1758 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1759 dev->host_mem_descs, dev->host_mem_descs_dma);
1760 dev->host_mem_descs = NULL;
1761 dev->nr_host_mem_descs = 0;
1764 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1767 struct nvme_host_mem_buf_desc *descs;
1768 u32 max_entries, len;
1769 dma_addr_t descs_dma;
1774 tmp = (preferred + chunk_size - 1);
1775 do_div(tmp, chunk_size);
1778 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1779 max_entries = dev->ctrl.hmmaxd;
1781 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1782 &descs_dma, GFP_KERNEL);
1786 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1788 goto out_free_descs;
1790 for (size = 0; size < preferred && i < max_entries; size += len) {
1791 dma_addr_t dma_addr;
1793 len = min_t(u64, chunk_size, preferred - size);
1794 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1795 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1799 descs[i].addr = cpu_to_le64(dma_addr);
1800 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1807 dev->nr_host_mem_descs = i;
1808 dev->host_mem_size = size;
1809 dev->host_mem_descs = descs;
1810 dev->host_mem_descs_dma = descs_dma;
1811 dev->host_mem_desc_bufs = bufs;
1816 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1818 dma_free_coherent(dev->dev, size, bufs[i],
1819 le64_to_cpu(descs[i].addr));
1824 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1827 dev->host_mem_descs = NULL;
1831 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1835 /* start big and work our way down */
1836 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1837 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1839 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1840 if (!min || dev->host_mem_size >= min)
1842 nvme_free_host_mem(dev);
1849 static int nvme_setup_host_mem(struct nvme_dev *dev)
1851 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1852 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1853 u64 min = (u64)dev->ctrl.hmmin * 4096;
1854 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1857 preferred = min(preferred, max);
1859 dev_warn(dev->ctrl.device,
1860 "min host memory (%lld MiB) above limit (%d MiB).\n",
1861 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1862 nvme_free_host_mem(dev);
1867 * If we already have a buffer allocated check if we can reuse it.
1869 if (dev->host_mem_descs) {
1870 if (dev->host_mem_size >= min)
1871 enable_bits |= NVME_HOST_MEM_RETURN;
1873 nvme_free_host_mem(dev);
1876 if (!dev->host_mem_descs) {
1877 if (nvme_alloc_host_mem(dev, min, preferred)) {
1878 dev_warn(dev->ctrl.device,
1879 "failed to allocate host memory buffer.\n");
1880 return 0; /* controller must work without HMB */
1883 dev_info(dev->ctrl.device,
1884 "allocated %lld MiB host memory buffer.\n",
1885 dev->host_mem_size >> ilog2(SZ_1M));
1888 ret = nvme_set_host_mem(dev, enable_bits);
1890 nvme_free_host_mem(dev);
1894 static int nvme_setup_io_queues(struct nvme_dev *dev)
1896 struct nvme_queue *adminq = &dev->queues[0];
1897 struct pci_dev *pdev = to_pci_dev(dev->dev);
1898 int result, nr_io_queues;
1901 struct irq_affinity affd = {
1905 nr_io_queues = num_possible_cpus();
1906 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1910 if (nr_io_queues == 0)
1913 if (dev->cmb_use_sqes) {
1914 result = nvme_cmb_qdepth(dev, nr_io_queues,
1915 sizeof(struct nvme_command));
1917 dev->q_depth = result;
1919 dev->cmb_use_sqes = false;
1923 size = db_bar_size(dev, nr_io_queues);
1924 result = nvme_remap_bar(dev, size);
1927 if (!--nr_io_queues)
1930 adminq->q_db = dev->dbs;
1932 /* Deregister the admin queue's interrupt */
1933 pci_free_irq(pdev, 0, adminq);
1936 * If we enable msix early due to not intx, disable it again before
1937 * setting up the full range we need.
1939 pci_free_irq_vectors(pdev);
1940 result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
1941 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
1944 dev->num_vecs = result;
1945 dev->max_qid = max(result - 1, 1);
1948 * Should investigate if there's a performance win from allocating
1949 * more queues than interrupt vectors; it might allow the submission
1950 * path to scale better, even if the receive path is limited by the
1951 * number of interrupts.
1954 result = queue_request_irq(adminq);
1956 adminq->cq_vector = -1;
1959 return nvme_create_io_queues(dev);
1962 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1964 struct nvme_queue *nvmeq = req->end_io_data;
1966 blk_mq_free_request(req);
1967 complete(&nvmeq->dev->ioq_wait);
1970 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1972 struct nvme_queue *nvmeq = req->end_io_data;
1976 unsigned long flags;
1978 spin_lock_irqsave(&nvmeq->cq_lock, flags);
1979 nvme_process_cq(nvmeq, &start, &end, -1);
1980 spin_unlock_irqrestore(&nvmeq->cq_lock, flags);
1982 nvme_complete_cqes(nvmeq, start, end);
1985 nvme_del_queue_end(req, error);
1988 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1990 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1991 struct request *req;
1992 struct nvme_command cmd;
1994 memset(&cmd, 0, sizeof(cmd));
1995 cmd.delete_queue.opcode = opcode;
1996 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1998 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2000 return PTR_ERR(req);
2002 req->timeout = ADMIN_TIMEOUT;
2003 req->end_io_data = nvmeq;
2005 blk_execute_rq_nowait(q, NULL, req, false,
2006 opcode == nvme_admin_delete_cq ?
2007 nvme_del_cq_end : nvme_del_queue_end);
2011 static void nvme_disable_io_queues(struct nvme_dev *dev)
2013 int pass, queues = dev->online_queues - 1;
2014 unsigned long timeout;
2015 u8 opcode = nvme_admin_delete_sq;
2017 for (pass = 0; pass < 2; pass++) {
2018 int sent = 0, i = queues;
2020 reinit_completion(&dev->ioq_wait);
2022 timeout = ADMIN_TIMEOUT;
2023 for (; i > 0; i--, sent++)
2024 if (nvme_delete_queue(&dev->queues[i], opcode))
2028 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2034 opcode = nvme_admin_delete_cq;
2039 * return error value only when tagset allocation failed
2041 static int nvme_dev_add(struct nvme_dev *dev)
2045 if (!dev->ctrl.tagset) {
2046 dev->tagset.ops = &nvme_mq_ops;
2047 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2048 dev->tagset.timeout = NVME_IO_TIMEOUT;
2049 dev->tagset.numa_node = dev_to_node(dev->dev);
2050 dev->tagset.queue_depth =
2051 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2052 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2053 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2054 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2055 nvme_pci_cmd_size(dev, true));
2057 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2058 dev->tagset.driver_data = dev;
2060 ret = blk_mq_alloc_tag_set(&dev->tagset);
2062 dev_warn(dev->ctrl.device,
2063 "IO queues tagset allocation failed %d\n", ret);
2066 dev->ctrl.tagset = &dev->tagset;
2068 nvme_dbbuf_set(dev);
2070 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2072 /* Free previously allocated queues that are no longer usable */
2073 nvme_free_queues(dev, dev->online_queues);
2079 static int nvme_pci_enable(struct nvme_dev *dev)
2081 int result = -ENOMEM;
2082 struct pci_dev *pdev = to_pci_dev(dev->dev);
2084 if (pci_enable_device_mem(pdev))
2087 pci_set_master(pdev);
2089 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2090 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2093 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2099 * Some devices and/or platforms don't advertise or work with INTx
2100 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2101 * adjust this later.
2103 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2107 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2109 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2111 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2112 dev->dbs = dev->bar + 4096;
2115 * Temporary fix for the Apple controller found in the MacBook8,1 and
2116 * some MacBook7,1 to avoid controller resets and data loss.
2118 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2120 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2121 "set queue depth=%u to work around controller resets\n",
2123 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2124 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2125 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2127 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2128 "set queue depth=%u\n", dev->q_depth);
2133 pci_enable_pcie_error_reporting(pdev);
2134 pci_save_state(pdev);
2138 pci_disable_device(pdev);
2142 static void nvme_dev_unmap(struct nvme_dev *dev)
2146 pci_release_mem_regions(to_pci_dev(dev->dev));
2149 static void nvme_pci_disable(struct nvme_dev *dev)
2151 struct pci_dev *pdev = to_pci_dev(dev->dev);
2153 pci_free_irq_vectors(pdev);
2155 if (pci_is_enabled(pdev)) {
2156 pci_disable_pcie_error_reporting(pdev);
2157 pci_disable_device(pdev);
2161 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2165 struct pci_dev *pdev = to_pci_dev(dev->dev);
2167 mutex_lock(&dev->shutdown_lock);
2168 if (pci_is_enabled(pdev)) {
2169 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2171 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2172 dev->ctrl.state == NVME_CTRL_RESETTING)
2173 nvme_start_freeze(&dev->ctrl);
2174 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2175 pdev->error_state != pci_channel_io_normal);
2179 * Give the controller a chance to complete all entered requests if
2180 * doing a safe shutdown.
2184 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2187 nvme_stop_queues(&dev->ctrl);
2189 if (!dead && dev->ctrl.queue_count > 0) {
2190 nvme_disable_io_queues(dev);
2191 nvme_disable_admin_queue(dev, shutdown);
2193 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2194 nvme_suspend_queue(&dev->queues[i]);
2196 nvme_pci_disable(dev);
2198 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2199 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2202 * The driver will not be starting up queues again if shutting down so
2203 * must flush all entered requests to their failed completion to avoid
2204 * deadlocking blk-mq hot-cpu notifier.
2207 nvme_start_queues(&dev->ctrl);
2208 mutex_unlock(&dev->shutdown_lock);
2211 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2213 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2214 PAGE_SIZE, PAGE_SIZE, 0);
2215 if (!dev->prp_page_pool)
2218 /* Optimisation for I/Os between 4k and 128k */
2219 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2221 if (!dev->prp_small_pool) {
2222 dma_pool_destroy(dev->prp_page_pool);
2228 static void nvme_release_prp_pools(struct nvme_dev *dev)
2230 dma_pool_destroy(dev->prp_page_pool);
2231 dma_pool_destroy(dev->prp_small_pool);
2234 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2236 struct nvme_dev *dev = to_nvme_dev(ctrl);
2238 nvme_dbbuf_dma_free(dev);
2239 put_device(dev->dev);
2240 if (dev->tagset.tags)
2241 blk_mq_free_tag_set(&dev->tagset);
2242 if (dev->ctrl.admin_q)
2243 blk_put_queue(dev->ctrl.admin_q);
2245 free_opal_dev(dev->ctrl.opal_dev);
2246 mempool_destroy(dev->iod_mempool);
2250 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2252 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2254 nvme_get_ctrl(&dev->ctrl);
2255 nvme_dev_disable(dev, false);
2256 nvme_kill_queues(&dev->ctrl);
2257 if (!queue_work(nvme_wq, &dev->remove_work))
2258 nvme_put_ctrl(&dev->ctrl);
2261 static void nvme_reset_work(struct work_struct *work)
2263 struct nvme_dev *dev =
2264 container_of(work, struct nvme_dev, ctrl.reset_work);
2265 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2266 int result = -ENODEV;
2267 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2269 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2273 * If we're called to reset a live controller first shut it down before
2276 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2277 nvme_dev_disable(dev, false);
2280 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2281 * initializing procedure here.
2283 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2284 dev_warn(dev->ctrl.device,
2285 "failed to mark controller CONNECTING\n");
2289 result = nvme_pci_enable(dev);
2293 result = nvme_pci_configure_admin_queue(dev);
2297 result = nvme_alloc_admin_tags(dev);
2302 * Limit the max command size to prevent iod->sg allocations going
2303 * over a single page.
2305 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2306 dev->ctrl.max_segments = NVME_MAX_SEGS;
2308 result = nvme_init_identify(&dev->ctrl);
2312 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2313 if (!dev->ctrl.opal_dev)
2314 dev->ctrl.opal_dev =
2315 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2316 else if (was_suspend)
2317 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2319 free_opal_dev(dev->ctrl.opal_dev);
2320 dev->ctrl.opal_dev = NULL;
2323 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2324 result = nvme_dbbuf_dma_alloc(dev);
2327 "unable to allocate dma for dbbuf\n");
2330 if (dev->ctrl.hmpre) {
2331 result = nvme_setup_host_mem(dev);
2336 result = nvme_setup_io_queues(dev);
2341 * Keep the controller around but remove all namespaces if we don't have
2342 * any working I/O queue.
2344 if (dev->online_queues < 2) {
2345 dev_warn(dev->ctrl.device, "IO queues not created\n");
2346 nvme_kill_queues(&dev->ctrl);
2347 nvme_remove_namespaces(&dev->ctrl);
2348 new_state = NVME_CTRL_ADMIN_ONLY;
2350 nvme_start_queues(&dev->ctrl);
2351 nvme_wait_freeze(&dev->ctrl);
2352 /* hit this only when allocate tagset fails */
2353 if (nvme_dev_add(dev))
2354 new_state = NVME_CTRL_ADMIN_ONLY;
2355 nvme_unfreeze(&dev->ctrl);
2359 * If only admin queue live, keep it to do further investigation or
2362 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2363 dev_warn(dev->ctrl.device,
2364 "failed to mark controller state %d\n", new_state);
2368 nvme_start_ctrl(&dev->ctrl);
2372 nvme_remove_dead_ctrl(dev, result);
2375 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2377 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2378 struct pci_dev *pdev = to_pci_dev(dev->dev);
2380 if (pci_get_drvdata(pdev))
2381 device_release_driver(&pdev->dev);
2382 nvme_put_ctrl(&dev->ctrl);
2385 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2387 *val = readl(to_nvme_dev(ctrl)->bar + off);
2391 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2393 writel(val, to_nvme_dev(ctrl)->bar + off);
2397 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2399 *val = readq(to_nvme_dev(ctrl)->bar + off);
2403 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2405 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2407 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2410 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2412 .module = THIS_MODULE,
2413 .flags = NVME_F_METADATA_SUPPORTED |
2415 .reg_read32 = nvme_pci_reg_read32,
2416 .reg_write32 = nvme_pci_reg_write32,
2417 .reg_read64 = nvme_pci_reg_read64,
2418 .free_ctrl = nvme_pci_free_ctrl,
2419 .submit_async_event = nvme_pci_submit_async_event,
2420 .get_address = nvme_pci_get_address,
2423 static int nvme_dev_map(struct nvme_dev *dev)
2425 struct pci_dev *pdev = to_pci_dev(dev->dev);
2427 if (pci_request_mem_regions(pdev, "nvme"))
2430 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2435 pci_release_mem_regions(pdev);
2439 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2441 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2443 * Several Samsung devices seem to drop off the PCIe bus
2444 * randomly when APST is on and uses the deepest sleep state.
2445 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2446 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2447 * 950 PRO 256GB", but it seems to be restricted to two Dell
2450 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2451 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2452 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2453 return NVME_QUIRK_NO_DEEPEST_PS;
2454 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2456 * Samsung SSD 960 EVO drops off the PCIe bus after system
2457 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2458 * within few minutes after bootup on a Coffee Lake board -
2461 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2462 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2463 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2464 return NVME_QUIRK_NO_APST;
2470 static void nvme_async_probe(void *data, async_cookie_t cookie)
2472 struct nvme_dev *dev = data;
2474 nvme_reset_ctrl_sync(&dev->ctrl);
2475 flush_work(&dev->ctrl.scan_work);
2476 nvme_put_ctrl(&dev->ctrl);
2479 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2481 int node, result = -ENOMEM;
2482 struct nvme_dev *dev;
2483 unsigned long quirks = id->driver_data;
2486 node = dev_to_node(&pdev->dev);
2487 if (node == NUMA_NO_NODE)
2488 set_dev_node(&pdev->dev, first_memory_node);
2490 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2494 dev->queues = kcalloc_node(num_possible_cpus() + 1,
2495 sizeof(struct nvme_queue), GFP_KERNEL, node);
2499 dev->dev = get_device(&pdev->dev);
2500 pci_set_drvdata(pdev, dev);
2502 result = nvme_dev_map(dev);
2506 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2507 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2508 mutex_init(&dev->shutdown_lock);
2509 init_completion(&dev->ioq_wait);
2511 result = nvme_setup_prp_pools(dev);
2515 quirks |= check_vendor_combination_bug(pdev);
2518 * Double check that our mempool alloc size will cover the biggest
2519 * command we support.
2521 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2522 NVME_MAX_SEGS, true);
2523 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2525 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2527 (void *) alloc_size,
2529 if (!dev->iod_mempool) {
2534 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2537 goto release_mempool;
2539 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2541 nvme_get_ctrl(&dev->ctrl);
2542 async_schedule(nvme_async_probe, dev);
2547 mempool_destroy(dev->iod_mempool);
2549 nvme_release_prp_pools(dev);
2551 nvme_dev_unmap(dev);
2553 put_device(dev->dev);
2560 static void nvme_reset_prepare(struct pci_dev *pdev)
2562 struct nvme_dev *dev = pci_get_drvdata(pdev);
2563 nvme_dev_disable(dev, false);
2566 static void nvme_reset_done(struct pci_dev *pdev)
2568 struct nvme_dev *dev = pci_get_drvdata(pdev);
2569 nvme_reset_ctrl_sync(&dev->ctrl);
2572 static void nvme_shutdown(struct pci_dev *pdev)
2574 struct nvme_dev *dev = pci_get_drvdata(pdev);
2575 nvme_dev_disable(dev, true);
2579 * The driver's remove may be called on a device in a partially initialized
2580 * state. This function must not have any dependencies on the device state in
2583 static void nvme_remove(struct pci_dev *pdev)
2585 struct nvme_dev *dev = pci_get_drvdata(pdev);
2587 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2588 pci_set_drvdata(pdev, NULL);
2590 if (!pci_device_is_present(pdev)) {
2591 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2592 nvme_dev_disable(dev, true);
2593 nvme_dev_remove_admin(dev);
2596 flush_work(&dev->ctrl.reset_work);
2597 nvme_stop_ctrl(&dev->ctrl);
2598 nvme_remove_namespaces(&dev->ctrl);
2599 nvme_dev_disable(dev, true);
2600 nvme_release_cmb(dev);
2601 nvme_free_host_mem(dev);
2602 nvme_dev_remove_admin(dev);
2603 nvme_free_queues(dev, 0);
2604 nvme_uninit_ctrl(&dev->ctrl);
2605 nvme_release_prp_pools(dev);
2606 nvme_dev_unmap(dev);
2607 nvme_put_ctrl(&dev->ctrl);
2610 #ifdef CONFIG_PM_SLEEP
2611 static int nvme_suspend(struct device *dev)
2613 struct pci_dev *pdev = to_pci_dev(dev);
2614 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2616 nvme_dev_disable(ndev, true);
2620 static int nvme_resume(struct device *dev)
2622 struct pci_dev *pdev = to_pci_dev(dev);
2623 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2625 nvme_reset_ctrl(&ndev->ctrl);
2630 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2632 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2633 pci_channel_state_t state)
2635 struct nvme_dev *dev = pci_get_drvdata(pdev);
2638 * A frozen channel requires a reset. When detected, this method will
2639 * shutdown the controller to quiesce. The controller will be restarted
2640 * after the slot reset through driver's slot_reset callback.
2643 case pci_channel_io_normal:
2644 return PCI_ERS_RESULT_CAN_RECOVER;
2645 case pci_channel_io_frozen:
2646 dev_warn(dev->ctrl.device,
2647 "frozen state error detected, reset controller\n");
2648 nvme_dev_disable(dev, false);
2649 return PCI_ERS_RESULT_NEED_RESET;
2650 case pci_channel_io_perm_failure:
2651 dev_warn(dev->ctrl.device,
2652 "failure state error detected, request disconnect\n");
2653 return PCI_ERS_RESULT_DISCONNECT;
2655 return PCI_ERS_RESULT_NEED_RESET;
2658 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2660 struct nvme_dev *dev = pci_get_drvdata(pdev);
2662 dev_info(dev->ctrl.device, "restart after slot reset\n");
2663 pci_restore_state(pdev);
2664 nvme_reset_ctrl(&dev->ctrl);
2665 return PCI_ERS_RESULT_RECOVERED;
2668 static void nvme_error_resume(struct pci_dev *pdev)
2670 struct nvme_dev *dev = pci_get_drvdata(pdev);
2672 flush_work(&dev->ctrl.reset_work);
2675 static const struct pci_error_handlers nvme_err_handler = {
2676 .error_detected = nvme_error_detected,
2677 .slot_reset = nvme_slot_reset,
2678 .resume = nvme_error_resume,
2679 .reset_prepare = nvme_reset_prepare,
2680 .reset_done = nvme_reset_done,
2683 static const struct pci_device_id nvme_id_table[] = {
2684 { PCI_VDEVICE(INTEL, 0x0953),
2685 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2686 NVME_QUIRK_DEALLOCATE_ZEROES, },
2687 { PCI_VDEVICE(INTEL, 0x0a53),
2688 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2689 NVME_QUIRK_DEALLOCATE_ZEROES, },
2690 { PCI_VDEVICE(INTEL, 0x0a54),
2691 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2692 NVME_QUIRK_DEALLOCATE_ZEROES, },
2693 { PCI_VDEVICE(INTEL, 0x0a55),
2694 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2695 NVME_QUIRK_DEALLOCATE_ZEROES, },
2696 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2697 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2698 NVME_QUIRK_MEDIUM_PRIO_SQ },
2699 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2700 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2701 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2702 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2703 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2704 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2705 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2706 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2707 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2708 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2709 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2710 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2711 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2712 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2713 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2714 .driver_data = NVME_QUIRK_LIGHTNVM, },
2715 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2716 .driver_data = NVME_QUIRK_LIGHTNVM, },
2717 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2718 .driver_data = NVME_QUIRK_LIGHTNVM, },
2719 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2720 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2721 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2724 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2726 static struct pci_driver nvme_driver = {
2728 .id_table = nvme_id_table,
2729 .probe = nvme_probe,
2730 .remove = nvme_remove,
2731 .shutdown = nvme_shutdown,
2733 .pm = &nvme_dev_pm_ops,
2735 .sriov_configure = pci_sriov_configure_simple,
2736 .err_handler = &nvme_err_handler,
2739 static int __init nvme_init(void)
2741 return pci_register_driver(&nvme_driver);
2744 static void __exit nvme_exit(void)
2746 pci_unregister_driver(&nvme_driver);
2747 flush_workqueue(nvme_wq);
2751 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2752 MODULE_LICENSE("GPL");
2753 MODULE_VERSION("1.0");
2754 module_init(nvme_init);
2755 module_exit(nvme_exit);