drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/aer.h>
   9 #include <linux/async.h>
  10 #include <linux/blkdev.h>
  11 #include <linux/blk-mq.h>
  12 #include <linux/blk-mq-pci.h>
  13 #include <linux/blk-integrity.h>
  14 #include <linux/dmi.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/mm.h>
  19 #include <linux/module.h>
  20 #include <linux/mutex.h>
  21 #include <linux/once.h>
  22 #include <linux/pci.h>
  23 #include <linux/suspend.h>
  24 #include <linux/t10-pi.h>
  25 #include <linux/types.h>
  26 #include <linux/io-64-nonatomic-lo-hi.h>
  27 #include <linux/io-64-nonatomic-hi-lo.h>
  28 #include <linux/sed-opal.h>
  29 #include <linux/pci-p2pdma.h>
  30
  31 #include "trace.h"
  32 #include "nvme.h"
  33
  34 #define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  35 #define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  36
  37 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  38
  39 /*
  40  * These can be higher, but we need to ensure that any command doesn't
  41  * require an sg allocation that needs more than a page of data.
  42  */
  43 #define NVME_MAX_KB_SZ  4096
  44 #define NVME_MAX_SEGS   127
  45
  46 static int use_threaded_interrupts;
  47 module_param(use_threaded_interrupts, int, 0);
  48
  49 static bool use_cmb_sqes = true;
  50 module_param(use_cmb_sqes, bool, 0444);
  51 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  52
  53 static unsigned int max_host_mem_size_mb = 128;
  54 module_param(max_host_mem_size_mb, uint, 0444);
  55 MODULE_PARM_DESC(max_host_mem_size_mb,
  56         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  57
  58 static unsigned int sgl_threshold = SZ_32K;
  59 module_param(sgl_threshold, uint, 0644);
  60 MODULE_PARM_DESC(sgl_threshold,
  61                 "Use SGLs when average request segment size is larger or equal to "
  62                 "this size. Use 0 to disable SGLs.");
  63
  64 #define NVME_PCI_MIN_QUEUE_SIZE 2
  65 #define NVME_PCI_MAX_QUEUE_SIZE 4095
  66 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  67 static const struct kernel_param_ops io_queue_depth_ops = {
  68         .set = io_queue_depth_set,
  69         .get = param_get_uint,
  70 };
  71
  72 static unsigned int io_queue_depth = 1024;
  73 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  74 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
  75
  76 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  77 {
  78         unsigned int n;
  79         int ret;
  80
  81         ret = kstrtouint(val, 10, &n);
  82         if (ret != 0 || n > num_possible_cpus())
  83                 return -EINVAL;
  84         return param_set_uint(val, kp);
  85 }
  86
  87 static const struct kernel_param_ops io_queue_count_ops = {
  88         .set = io_queue_count_set,
  89         .get = param_get_uint,
  90 };
  91
  92 static unsigned int write_queues;
  93 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  94 MODULE_PARM_DESC(write_queues,
  95         "Number of queues to use for writes. If not set, reads and writes "
  96         "will share a queue set.");
  97
  98 static unsigned int poll_queues;
  99 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
 100 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
 101
 102 static bool noacpi;
 103 module_param(noacpi, bool, 0444);
 104 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 105
 106 struct nvme_dev;
 107 struct nvme_queue;
 108
 109 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 110 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
 111
 112 /*
 113  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 114  */
 115 struct nvme_dev {
 116         struct nvme_queue *queues;
 117         struct blk_mq_tag_set tagset;
 118         struct blk_mq_tag_set admin_tagset;
 119         u32 __iomem *dbs;
 120         struct device *dev;
 121         struct dma_pool *prp_page_pool;
 122         struct dma_pool *prp_small_pool;
 123         unsigned online_queues;
 124         unsigned max_qid;
 125         unsigned io_queues[HCTX_MAX_TYPES];
 126         unsigned int num_vecs;
 127         u32 q_depth;
 128         int io_sqes;
 129         u32 db_stride;
 130         void __iomem *bar;
 131         unsigned long bar_mapped_size;
 132         struct work_struct remove_work;
 133         struct mutex shutdown_lock;
 134         bool subsystem;
 135         u64 cmb_size;
 136         bool cmb_use_sqes;
 137         u32 cmbsz;
 138         u32 cmbloc;
 139         struct nvme_ctrl ctrl;
 140         u32 last_ps;
 141         bool hmb;
 142
 143         mempool_t *iod_mempool;
 144
 145         /* shadow doorbell buffer support: */
 146         u32 *dbbuf_dbs;
 147         dma_addr_t dbbuf_dbs_dma_addr;
 148         u32 *dbbuf_eis;
 149         dma_addr_t dbbuf_eis_dma_addr;
 150
 151         /* host memory buffer support: */
 152         u64 host_mem_size;
 153         u32 nr_host_mem_descs;
 154         dma_addr_t host_mem_descs_dma;
 155         struct nvme_host_mem_buf_desc *host_mem_descs;
 156         void **host_mem_desc_bufs;
 157         unsigned int nr_allocated_queues;
 158         unsigned int nr_write_queues;
 159         unsigned int nr_poll_queues;
 160
 161         bool attrs_added;
 162 };
 163
 164 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 165 {
 166         return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
 167                         NVME_PCI_MAX_QUEUE_SIZE);
 168 }
 169
 170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 171 {
 172         return qid * 2 * stride;
 173 }
 174
 175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 176 {
 177         return (qid * 2 + 1) * stride;
 178 }
 179
 180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 181 {
 182         return container_of(ctrl, struct nvme_dev, ctrl);
 183 }
 184
 185 /*
 186  * An NVM Express queue.  Each device has at least two (one for admin
 187  * commands and one for I/O commands).
 188  */
 189 struct nvme_queue {
 190         struct nvme_dev *dev;
 191         spinlock_t sq_lock;
 192         void *sq_cmds;
 193          /* only used for poll queues: */
 194         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 195         struct nvme_completion *cqes;
 196         dma_addr_t sq_dma_addr;
 197         dma_addr_t cq_dma_addr;
 198         u32 __iomem *q_db;
 199         u32 q_depth;
 200         u16 cq_vector;
 201         u16 sq_tail;
 202         u16 last_sq_tail;
 203         u16 cq_head;
 204         u16 qid;
 205         u8 cq_phase;
 206         u8 sqes;
 207         unsigned long flags;
 208 #define NVMEQ_ENABLED           0
 209 #define NVMEQ_SQ_CMB            1
 210 #define NVMEQ_DELETE_ERROR      2
 211 #define NVMEQ_POLLED            3
 212         u32 *dbbuf_sq_db;
 213         u32 *dbbuf_cq_db;
 214         u32 *dbbuf_sq_ei;
 215         u32 *dbbuf_cq_ei;
 216         struct completion delete_done;
 217 };
 218
 219 /*
 220  * The nvme_iod describes the data in an I/O.
 221  *
 222  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 223  * to the actual struct scatterlist.
 224  */
 225 struct nvme_iod {
 226         struct nvme_request req;
 227         struct nvme_command cmd;
 228         struct nvme_queue *nvmeq;
 229         bool use_sgl;
 230         int aborted;
 231         int npages;             /* In the PRP list. 0 means small pool in use */
 232         int nents;              /* Used in scatterlist */
 233         dma_addr_t first_dma;
 234         unsigned int dma_len;   /* length of single DMA segment mapping */
 235         dma_addr_t meta_dma;
 236         struct scatterlist *sg;
 237 };
 238
 239 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 240 {
 241         return dev->nr_allocated_queues * 8 * dev->db_stride;
 242 }
 243
 244 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 245 {
 246         unsigned int mem_size = nvme_dbbuf_size(dev);
 247
 248         if (dev->dbbuf_dbs) {
 249                 /*
 250                  * Clear the dbbuf memory so the driver doesn't observe stale
 251                  * values from the previous instantiation.
 252                  */
 253                 memset(dev->dbbuf_dbs, 0, mem_size);
 254                 memset(dev->dbbuf_eis, 0, mem_size);
 255                 return 0;
 256         }
 257
 258         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 259                                             &dev->dbbuf_dbs_dma_addr,
 260                                             GFP_KERNEL);
 261         if (!dev->dbbuf_dbs)
 262                 return -ENOMEM;
 263         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 264                                             &dev->dbbuf_eis_dma_addr,
 265                                             GFP_KERNEL);
 266         if (!dev->dbbuf_eis) {
 267                 dma_free_coherent(dev->dev, mem_size,
 268                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 269                 dev->dbbuf_dbs = NULL;
 270                 return -ENOMEM;
 271         }
 272
 273         return 0;
 274 }
 275
 276 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 277 {
 278         unsigned int mem_size = nvme_dbbuf_size(dev);
 279
 280         if (dev->dbbuf_dbs) {
 281                 dma_free_coherent(dev->dev, mem_size,
 282                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 283                 dev->dbbuf_dbs = NULL;
 284         }
 285         if (dev->dbbuf_eis) {
 286                 dma_free_coherent(dev->dev, mem_size,
 287                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 288                 dev->dbbuf_eis = NULL;
 289         }
 290 }
 291
 292 static void nvme_dbbuf_init(struct nvme_dev *dev,
 293                             struct nvme_queue *nvmeq, int qid)
 294 {
 295         if (!dev->dbbuf_dbs || !qid)
 296                 return;
 297
 298         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 299         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 300         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 301         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 302 }
 303
 304 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 305 {
 306         if (!nvmeq->qid)
 307                 return;
 308
 309         nvmeq->dbbuf_sq_db = NULL;
 310         nvmeq->dbbuf_cq_db = NULL;
 311         nvmeq->dbbuf_sq_ei = NULL;
 312         nvmeq->dbbuf_cq_ei = NULL;
 313 }
 314
 315 static void nvme_dbbuf_set(struct nvme_dev *dev)
 316 {
 317         struct nvme_command c = { };
 318         unsigned int i;
 319
 320         if (!dev->dbbuf_dbs)
 321                 return;
 322
 323         c.dbbuf.opcode = nvme_admin_dbbuf;
 324         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 325         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 326
 327         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 328                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 329                 /* Free memory and continue on */
 330                 nvme_dbbuf_dma_free(dev);
 331
 332                 for (i = 1; i <= dev->online_queues; i++)
 333                         nvme_dbbuf_free(&dev->queues[i]);
 334         }
 335 }
 336
 337 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 338 {
 339         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 340 }
 341
 342 /* Update dbbuf and return true if an MMIO is required */
 343 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 344                                               volatile u32 *dbbuf_ei)
 345 {
 346         if (dbbuf_db) {
 347                 u16 old_value;
 348
 349                 /*
 350                  * Ensure that the queue is written before updating
 351                  * the doorbell in memory
 352                  */
 353                 wmb();
 354
 355                 old_value = *dbbuf_db;
 356                 *dbbuf_db = value;
 357
 358                 /*
 359                  * Ensure that the doorbell is updated before reading the event
 360                  * index from memory.  The controller needs to provide similar
 361                  * ordering to ensure the envent index is updated before reading
 362                  * the doorbell.
 363                  */
 364                 mb();
 365
 366                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 367                         return false;
 368         }
 369
 370         return true;
 371 }
 372
 373 /*
 374  * Will slightly overestimate the number of pages needed.  This is OK
 375  * as it only leads to a small amount of wasted memory for the lifetime of
 376  * the I/O.
 377  */
 378 static int nvme_pci_npages_prp(void)
 379 {
 380         unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
 381                                       NVME_CTRL_PAGE_SIZE);
 382         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 383 }
 384
 385 /*
 386  * Calculates the number of pages needed for the SGL segments. For example a 4k
 387  * page can accommodate 256 SGL descriptors.
 388  */
 389 static int nvme_pci_npages_sgl(void)
 390 {
 391         return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
 392                         PAGE_SIZE);
 393 }
 394
 395 static size_t nvme_pci_iod_alloc_size(void)
 396 {
 397         size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
 398
 399         return sizeof(__le64 *) * npages +
 400                 sizeof(struct scatterlist) * NVME_MAX_SEGS;
 401 }
 402
 403 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 404                                 unsigned int hctx_idx)
 405 {
 406         struct nvme_dev *dev = data;
 407         struct nvme_queue *nvmeq = &dev->queues[0];
 408
 409         WARN_ON(hctx_idx != 0);
 410         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 411
 412         hctx->driver_data = nvmeq;
 413         return 0;
 414 }
 415
 416 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 417                           unsigned int hctx_idx)
 418 {
 419         struct nvme_dev *dev = data;
 420         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 421
 422         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 423         hctx->driver_data = nvmeq;
 424         return 0;
 425 }
 426
 427 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 428                 unsigned int hctx_idx, unsigned int numa_node)
 429 {
 430         struct nvme_dev *dev = set->driver_data;
 431         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 432         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 433         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 434
 435         BUG_ON(!nvmeq);
 436         iod->nvmeq = nvmeq;
 437
 438         nvme_req(req)->ctrl = &dev->ctrl;
 439         nvme_req(req)->cmd = &iod->cmd;
 440         return 0;
 441 }
 442
 443 static int queue_irq_offset(struct nvme_dev *dev)
 444 {
 445         /* if we have more than 1 vec, admin queue offsets us by 1 */
 446         if (dev->num_vecs > 1)
 447                 return 1;
 448
 449         return 0;
 450 }
 451
 452 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 453 {
 454         struct nvme_dev *dev = set->driver_data;
 455         int i, qoff, offset;
 456
 457         offset = queue_irq_offset(dev);
 458         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 459                 struct blk_mq_queue_map *map = &set->map[i];
 460
 461                 map->nr_queues = dev->io_queues[i];
 462                 if (!map->nr_queues) {
 463                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 464                         continue;
 465                 }
 466
 467                 /*
 468                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 469                  * affinity), so use the regular blk-mq cpu mapping
 470                  */
 471                 map->queue_offset = qoff;
 472                 if (i != HCTX_TYPE_POLL && offset)
 473                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 474                 else
 475                         blk_mq_map_queues(map);
 476                 qoff += map->nr_queues;
 477                 offset += map->nr_queues;
 478         }
 479
 480         return 0;
 481 }
 482
 483 /*
 484  * Write sq tail if we are asked to, or if the next command would wrap.
 485  */
 486 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 487 {
 488         if (!write_sq) {
 489                 u16 next_tail = nvmeq->sq_tail + 1;
 490
 491                 if (next_tail == nvmeq->q_depth)
 492                         next_tail = 0;
 493                 if (next_tail != nvmeq->last_sq_tail)
 494                         return;
 495         }
 496
 497         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 498                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 499                 writel(nvmeq->sq_tail, nvmeq->q_db);
 500         nvmeq->last_sq_tail = nvmeq->sq_tail;
 501 }
 502
 503 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
 504                                     struct nvme_command *cmd)
 505 {
 506         memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 507                 absolute_pointer(cmd), sizeof(*cmd));
 508         if (++nvmeq->sq_tail == nvmeq->q_depth)
 509                 nvmeq->sq_tail = 0;
 510 }
 511
 512 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 513 {
 514         struct nvme_queue *nvmeq = hctx->driver_data;
 515
 516         spin_lock(&nvmeq->sq_lock);
 517         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 518                 nvme_write_sq_db(nvmeq, true);
 519         spin_unlock(&nvmeq->sq_lock);
 520 }
 521
 522 static void **nvme_pci_iod_list(struct request *req)
 523 {
 524         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 525         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 526 }
 527
 528 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 529 {
 530         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 531         int nseg = blk_rq_nr_phys_segments(req);
 532         unsigned int avg_seg_size;
 533
 534         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 535
 536         if (!nvme_ctrl_sgl_supported(&dev->ctrl))
 537                 return false;
 538         if (!iod->nvmeq->qid)
 539                 return false;
 540         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 541                 return false;
 542         return true;
 543 }
 544
 545 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
 546 {
 547         const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 548         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 549         dma_addr_t dma_addr = iod->first_dma;
 550         int i;
 551
 552         for (i = 0; i < iod->npages; i++) {
 553                 __le64 *prp_list = nvme_pci_iod_list(req)[i];
 554                 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 555
 556                 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
 557                 dma_addr = next_dma_addr;
 558         }
 559 }
 560
 561 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
 562 {
 563         const int last_sg = SGES_PER_PAGE - 1;
 564         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 565         dma_addr_t dma_addr = iod->first_dma;
 566         int i;
 567
 568         for (i = 0; i < iod->npages; i++) {
 569                 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
 570                 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
 571
 572                 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
 573                 dma_addr = next_dma_addr;
 574         }
 575 }
 576
 577 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
 578 {
 579         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 580
 581         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 582                 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
 583                                     rq_dma_dir(req));
 584         else
 585                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
 586 }
 587
 588 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 589 {
 590         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 591
 592         if (iod->dma_len) {
 593                 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
 594                                rq_dma_dir(req));
 595                 return;
 596         }
 597
 598         WARN_ON_ONCE(!iod->nents);
 599
 600         nvme_unmap_sg(dev, req);
 601         if (iod->npages == 0)
 602                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 603                               iod->first_dma);
 604         else if (iod->use_sgl)
 605                 nvme_free_sgls(dev, req);
 606         else
 607                 nvme_free_prps(dev, req);
 608         mempool_free(iod->sg, dev->iod_mempool);
 609 }
 610
 611 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 612 {
 613         int i;
 614         struct scatterlist *sg;
 615
 616         for_each_sg(sgl, sg, nents, i) {
 617                 dma_addr_t phys = sg_phys(sg);
 618                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 619                         "dma_address:%pad dma_length:%d\n",
 620                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 621                         sg_dma_len(sg));
 622         }
 623 }
 624
 625 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 626                 struct request *req, struct nvme_rw_command *cmnd)
 627 {
 628         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 629         struct dma_pool *pool;
 630         int length = blk_rq_payload_bytes(req);
 631         struct scatterlist *sg = iod->sg;
 632         int dma_len = sg_dma_len(sg);
 633         u64 dma_addr = sg_dma_address(sg);
 634         int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 635         __le64 *prp_list;
 636         void **list = nvme_pci_iod_list(req);
 637         dma_addr_t prp_dma;
 638         int nprps, i;
 639
 640         length -= (NVME_CTRL_PAGE_SIZE - offset);
 641         if (length <= 0) {
 642                 iod->first_dma = 0;
 643                 goto done;
 644         }
 645
 646         dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 647         if (dma_len) {
 648                 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 649         } else {
 650                 sg = sg_next(sg);
 651                 dma_addr = sg_dma_address(sg);
 652                 dma_len = sg_dma_len(sg);
 653         }
 654
 655         if (length <= NVME_CTRL_PAGE_SIZE) {
 656                 iod->first_dma = dma_addr;
 657                 goto done;
 658         }
 659
 660         nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 661         if (nprps <= (256 / 8)) {
 662                 pool = dev->prp_small_pool;
 663                 iod->npages = 0;
 664         } else {
 665                 pool = dev->prp_page_pool;
 666                 iod->npages = 1;
 667         }
 668
 669         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 670         if (!prp_list) {
 671                 iod->first_dma = dma_addr;
 672                 iod->npages = -1;
 673                 return BLK_STS_RESOURCE;
 674         }
 675         list[0] = prp_list;
 676         iod->first_dma = prp_dma;
 677         i = 0;
 678         for (;;) {
 679                 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 680                         __le64 *old_prp_list = prp_list;
 681                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 682                         if (!prp_list)
 683                                 goto free_prps;
 684                         list[iod->npages++] = prp_list;
 685                         prp_list[0] = old_prp_list[i - 1];
 686                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 687                         i = 1;
 688                 }
 689                 prp_list[i++] = cpu_to_le64(dma_addr);
 690                 dma_len -= NVME_CTRL_PAGE_SIZE;
 691                 dma_addr += NVME_CTRL_PAGE_SIZE;
 692                 length -= NVME_CTRL_PAGE_SIZE;
 693                 if (length <= 0)
 694                         break;
 695                 if (dma_len > 0)
 696                         continue;
 697                 if (unlikely(dma_len < 0))
 698                         goto bad_sgl;
 699                 sg = sg_next(sg);
 700                 dma_addr = sg_dma_address(sg);
 701                 dma_len = sg_dma_len(sg);
 702         }
 703 done:
 704         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 705         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 706         return BLK_STS_OK;
 707 free_prps:
 708         nvme_free_prps(dev, req);
 709         return BLK_STS_RESOURCE;
 710 bad_sgl:
 711         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 712                         "Invalid SGL for payload:%d nents:%d\n",
 713                         blk_rq_payload_bytes(req), iod->nents);
 714         return BLK_STS_IOERR;
 715 }
 716
 717 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 718                 struct scatterlist *sg)
 719 {
 720         sge->addr = cpu_to_le64(sg_dma_address(sg));
 721         sge->length = cpu_to_le32(sg_dma_len(sg));
 722         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 723 }
 724
 725 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 726                 dma_addr_t dma_addr, int entries)
 727 {
 728         sge->addr = cpu_to_le64(dma_addr);
 729         if (entries < SGES_PER_PAGE) {
 730                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 731                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 732         } else {
 733                 sge->length = cpu_to_le32(PAGE_SIZE);
 734                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 735         }
 736 }
 737
 738 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 739                 struct request *req, struct nvme_rw_command *cmd, int entries)
 740 {
 741         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 742         struct dma_pool *pool;
 743         struct nvme_sgl_desc *sg_list;
 744         struct scatterlist *sg = iod->sg;
 745         dma_addr_t sgl_dma;
 746         int i = 0;
 747
 748         /* setting the transfer type as SGL */
 749         cmd->flags = NVME_CMD_SGL_METABUF;
 750
 751         if (entries == 1) {
 752                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 753                 return BLK_STS_OK;
 754         }
 755
 756         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 757                 pool = dev->prp_small_pool;
 758                 iod->npages = 0;
 759         } else {
 760                 pool = dev->prp_page_pool;
 761                 iod->npages = 1;
 762         }
 763
 764         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 765         if (!sg_list) {
 766                 iod->npages = -1;
 767                 return BLK_STS_RESOURCE;
 768         }
 769
 770         nvme_pci_iod_list(req)[0] = sg_list;
 771         iod->first_dma = sgl_dma;
 772
 773         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 774
 775         do {
 776                 if (i == SGES_PER_PAGE) {
 777                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 778                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 779
 780                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 781                         if (!sg_list)
 782                                 goto free_sgls;
 783
 784                         i = 0;
 785                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 786                         sg_list[i++] = *link;
 787                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 788                 }
 789
 790                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 791                 sg = sg_next(sg);
 792         } while (--entries > 0);
 793
 794         return BLK_STS_OK;
 795 free_sgls:
 796         nvme_free_sgls(dev, req);
 797         return BLK_STS_RESOURCE;
 798 }
 799
 800 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 801                 struct request *req, struct nvme_rw_command *cmnd,
 802                 struct bio_vec *bv)
 803 {
 804         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 805         unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 806         unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 807
 808         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 809         if (dma_mapping_error(dev->dev, iod->first_dma))
 810                 return BLK_STS_RESOURCE;
 811         iod->dma_len = bv->bv_len;
 812
 813         cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 814         if (bv->bv_len > first_prp_len)
 815                 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 816         return BLK_STS_OK;
 817 }
 818
 819 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 820                 struct request *req, struct nvme_rw_command *cmnd,
 821                 struct bio_vec *bv)
 822 {
 823         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 824
 825         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 826         if (dma_mapping_error(dev->dev, iod->first_dma))
 827                 return BLK_STS_RESOURCE;
 828         iod->dma_len = bv->bv_len;
 829
 830         cmnd->flags = NVME_CMD_SGL_METABUF;
 831         cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 832         cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 833         cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 834         return BLK_STS_OK;
 835 }
 836
 837 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 838                 struct nvme_command *cmnd)
 839 {
 840         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 841         blk_status_t ret = BLK_STS_RESOURCE;
 842         int nr_mapped;
 843
 844         if (blk_rq_nr_phys_segments(req) == 1) {
 845                 struct bio_vec bv = req_bvec(req);
 846
 847                 if (!is_pci_p2pdma_page(bv.bv_page)) {
 848                         if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 849                                 return nvme_setup_prp_simple(dev, req,
 850                                                              &cmnd->rw, &bv);
 851
 852                         if (iod->nvmeq->qid && sgl_threshold &&
 853                             nvme_ctrl_sgl_supported(&dev->ctrl))
 854                                 return nvme_setup_sgl_simple(dev, req,
 855                                                              &cmnd->rw, &bv);
 856                 }
 857         }
 858
 859         iod->dma_len = 0;
 860         iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 861         if (!iod->sg)
 862                 return BLK_STS_RESOURCE;
 863         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 864         iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
 865         if (!iod->nents)
 866                 goto out_free_sg;
 867
 868         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 869                 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
 870                                 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
 871         else
 872                 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
 873                                              rq_dma_dir(req), DMA_ATTR_NO_WARN);
 874         if (!nr_mapped)
 875                 goto out_free_sg;
 876
 877         iod->use_sgl = nvme_pci_use_sgls(dev, req);
 878         if (iod->use_sgl)
 879                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
 880         else
 881                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 882         if (ret != BLK_STS_OK)
 883                 goto out_unmap_sg;
 884         return BLK_STS_OK;
 885
 886 out_unmap_sg:
 887         nvme_unmap_sg(dev, req);
 888 out_free_sg:
 889         mempool_free(iod->sg, dev->iod_mempool);
 890         return ret;
 891 }
 892
 893 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 894                 struct nvme_command *cmnd)
 895 {
 896         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 897
 898         iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 899                         rq_dma_dir(req), 0);
 900         if (dma_mapping_error(dev->dev, iod->meta_dma))
 901                 return BLK_STS_IOERR;
 902         cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 903         return BLK_STS_OK;
 904 }
 905
 906 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
 907 {
 908         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 909         blk_status_t ret;
 910
 911         iod->aborted = 0;
 912         iod->npages = -1;
 913         iod->nents = 0;
 914
 915         ret = nvme_setup_cmd(req->q->queuedata, req);
 916         if (ret)
 917                 return ret;
 918
 919         if (blk_rq_nr_phys_segments(req)) {
 920                 ret = nvme_map_data(dev, req, &iod->cmd);
 921                 if (ret)
 922                         goto out_free_cmd;
 923         }
 924
 925         if (blk_integrity_rq(req)) {
 926                 ret = nvme_map_metadata(dev, req, &iod->cmd);
 927                 if (ret)
 928                         goto out_unmap_data;
 929         }
 930
 931         blk_mq_start_request(req);
 932         return BLK_STS_OK;
 933 out_unmap_data:
 934         nvme_unmap_data(dev, req);
 935 out_free_cmd:
 936         nvme_cleanup_cmd(req);
 937         return ret;
 938 }
 939
 940 /*
 941  * NOTE: ns is NULL when called on the admin queue.
 942  */
 943 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 944                          const struct blk_mq_queue_data *bd)
 945 {
 946         struct nvme_queue *nvmeq = hctx->driver_data;
 947         struct nvme_dev *dev = nvmeq->dev;
 948         struct request *req = bd->rq;
 949         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 950         blk_status_t ret;
 951
 952         /*
 953          * We should not need to do this, but we're still using this to
 954          * ensure we can drain requests on a dying queue.
 955          */
 956         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 957                 return BLK_STS_IOERR;
 958
 959         if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
 960                 return nvme_fail_nonready_command(&dev->ctrl, req);
 961
 962         ret = nvme_prep_rq(dev, req);
 963         if (unlikely(ret))
 964                 return ret;
 965         spin_lock(&nvmeq->sq_lock);
 966         nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 967         nvme_write_sq_db(nvmeq, bd->last);
 968         spin_unlock(&nvmeq->sq_lock);
 969         return BLK_STS_OK;
 970 }
 971
 972 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
 973 {
 974         spin_lock(&nvmeq->sq_lock);
 975         while (!rq_list_empty(*rqlist)) {
 976                 struct request *req = rq_list_pop(rqlist);
 977                 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 978
 979                 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 980         }
 981         nvme_write_sq_db(nvmeq, true);
 982         spin_unlock(&nvmeq->sq_lock);
 983 }
 984
 985 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
 986 {
 987         /*
 988          * We should not need to do this, but we're still using this to
 989          * ensure we can drain requests on a dying queue.
 990          */
 991         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 992                 return false;
 993         if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
 994                 return false;
 995
 996         req->mq_hctx->tags->rqs[req->tag] = req;
 997         return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
 998 }
 999
1000 static void nvme_queue_rqs(struct request **rqlist)
1001 {
1002         struct request *req, *next, *prev = NULL;
1003         struct request *requeue_list = NULL;
1004
1005         rq_list_for_each_safe(rqlist, req, next) {
1006                 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1007
1008                 if (!nvme_prep_rq_batch(nvmeq, req)) {
1009                         /* detach 'req' and add to remainder list */
1010                         rq_list_move(rqlist, &requeue_list, req, prev);
1011
1012                         req = prev;
1013                         if (!req)
1014                                 continue;
1015                 }
1016
1017                 if (!next || req->mq_hctx != next->mq_hctx) {
1018                         /* detach rest of list, and submit */
1019                         req->rq_next = NULL;
1020                         nvme_submit_cmds(nvmeq, rqlist);
1021                         *rqlist = next;
1022                         prev = NULL;
1023                 } else
1024                         prev = req;
1025         }
1026
1027         *rqlist = requeue_list;
1028 }
1029
1030 static __always_inline void nvme_pci_unmap_rq(struct request *req)
1031 {
1032         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1033         struct nvme_dev *dev = iod->nvmeq->dev;
1034
1035         if (blk_integrity_rq(req))
1036                 dma_unmap_page(dev->dev, iod->meta_dma,
1037                                rq_integrity_vec(req)->bv_len, rq_data_dir(req));
1038         if (blk_rq_nr_phys_segments(req))
1039                 nvme_unmap_data(dev, req);
1040 }
1041
1042 static void nvme_pci_complete_rq(struct request *req)
1043 {
1044         nvme_pci_unmap_rq(req);
1045         nvme_complete_rq(req);
1046 }
1047
1048 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1049 {
1050         nvme_complete_batch(iob, nvme_pci_unmap_rq);
1051 }
1052
1053 /* We read the CQE phase first to check if the rest of the entry is valid */
1054 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
1055 {
1056         struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1057
1058         return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
1059 }
1060
1061 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
1062 {
1063         u16 head = nvmeq->cq_head;
1064
1065         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1066                                               nvmeq->dbbuf_cq_ei))
1067                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1068 }
1069
1070 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1071 {
1072         if (!nvmeq->qid)
1073                 return nvmeq->dev->admin_tagset.tags[0];
1074         return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1075 }
1076
1077 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1078                                    struct io_comp_batch *iob, u16 idx)
1079 {
1080         struct nvme_completion *cqe = &nvmeq->cqes[idx];
1081         __u16 command_id = READ_ONCE(cqe->command_id);
1082         struct request *req;
1083
1084         /*
1085          * AEN requests are special as they don't time out and can
1086          * survive any kind of queue freeze and often don't respond to
1087          * aborts.  We don't even bother to allocate a struct request
1088          * for them but rather special case them here.
1089          */
1090         if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1091                 nvme_complete_async_event(&nvmeq->dev->ctrl,
1092                                 cqe->status, &cqe->result);
1093                 return;
1094         }
1095
1096         req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1097         if (unlikely(!req)) {
1098                 dev_warn(nvmeq->dev->ctrl.device,
1099                         "invalid id %d completed on queue %d\n",
1100                         command_id, le16_to_cpu(cqe->sq_id));
1101                 return;
1102         }
1103
1104         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1105         if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1106             !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1107                                         nvme_pci_complete_batch))
1108                 nvme_pci_complete_rq(req);
1109 }
1110
1111 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1112 {
1113         u32 tmp = nvmeq->cq_head + 1;
1114
1115         if (tmp == nvmeq->q_depth) {
1116                 nvmeq->cq_head = 0;
1117                 nvmeq->cq_phase ^= 1;
1118         } else {
1119                 nvmeq->cq_head = tmp;
1120         }
1121 }
1122
1123 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1124                                struct io_comp_batch *iob)
1125 {
1126         int found = 0;
1127
1128         while (nvme_cqe_pending(nvmeq)) {
1129                 found++;
1130                 /*
1131                  * load-load control dependency between phase and the rest of
1132                  * the cqe requires a full read memory barrier
1133                  */
1134                 dma_rmb();
1135                 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1136                 nvme_update_cq_head(nvmeq);
1137         }
1138
1139         if (found)
1140                 nvme_ring_cq_doorbell(nvmeq);
1141         return found;
1142 }
1143
1144 static irqreturn_t nvme_irq(int irq, void *data)
1145 {
1146         struct nvme_queue *nvmeq = data;
1147         DEFINE_IO_COMP_BATCH(iob);
1148
1149         if (nvme_poll_cq(nvmeq, &iob)) {
1150                 if (!rq_list_empty(iob.req_list))
1151                         nvme_pci_complete_batch(&iob);
1152                 return IRQ_HANDLED;
1153         }
1154         return IRQ_NONE;
1155 }
1156
1157 static irqreturn_t nvme_irq_check(int irq, void *data)
1158 {
1159         struct nvme_queue *nvmeq = data;
1160
1161         if (nvme_cqe_pending(nvmeq))
1162                 return IRQ_WAKE_THREAD;
1163         return IRQ_NONE;
1164 }
1165
1166 /*
1167  * Poll for completions for any interrupt driven queue
1168  * Can be called from any context.
1169  */
1170 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1171 {
1172         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1173
1174         WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1175
1176         disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1177         nvme_poll_cq(nvmeq, NULL);
1178         enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1179 }
1180
1181 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1182 {
1183         struct nvme_queue *nvmeq = hctx->driver_data;
1184         bool found;
1185
1186         if (!nvme_cqe_pending(nvmeq))
1187                 return 0;
1188
1189         spin_lock(&nvmeq->cq_poll_lock);
1190         found = nvme_poll_cq(nvmeq, iob);
1191         spin_unlock(&nvmeq->cq_poll_lock);
1192
1193         return found;
1194 }
1195
1196 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1197 {
1198         struct nvme_dev *dev = to_nvme_dev(ctrl);
1199         struct nvme_queue *nvmeq = &dev->queues[0];
1200         struct nvme_command c = { };
1201
1202         c.common.opcode = nvme_admin_async_event;
1203         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1204
1205         spin_lock(&nvmeq->sq_lock);
1206         nvme_sq_copy_cmd(nvmeq, &c);
1207         nvme_write_sq_db(nvmeq, true);
1208         spin_unlock(&nvmeq->sq_lock);
1209 }
1210
1211 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1212 {
1213         struct nvme_command c = { };
1214
1215         c.delete_queue.opcode = opcode;
1216         c.delete_queue.qid = cpu_to_le16(id);
1217
1218         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1219 }
1220
1221 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1222                 struct nvme_queue *nvmeq, s16 vector)
1223 {
1224         struct nvme_command c = { };
1225         int flags = NVME_QUEUE_PHYS_CONTIG;
1226
1227         if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1228                 flags |= NVME_CQ_IRQ_ENABLED;
1229
1230         /*
1231          * Note: we (ab)use the fact that the prp fields survive if no data
1232          * is attached to the request.
1233          */
1234         c.create_cq.opcode = nvme_admin_create_cq;
1235         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1236         c.create_cq.cqid = cpu_to_le16(qid);
1237         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1238         c.create_cq.cq_flags = cpu_to_le16(flags);
1239         c.create_cq.irq_vector = cpu_to_le16(vector);
1240
1241         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1242 }
1243
1244 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1245                                                 struct nvme_queue *nvmeq)
1246 {
1247         struct nvme_ctrl *ctrl = &dev->ctrl;
1248         struct nvme_command c = { };
1249         int flags = NVME_QUEUE_PHYS_CONTIG;
1250
1251         /*
1252          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1253          * set. Since URGENT priority is zeroes, it makes all queues
1254          * URGENT.
1255          */
1256         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1257                 flags |= NVME_SQ_PRIO_MEDIUM;
1258
1259         /*
1260          * Note: we (ab)use the fact that the prp fields survive if no data
1261          * is attached to the request.
1262          */
1263         c.create_sq.opcode = nvme_admin_create_sq;
1264         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1265         c.create_sq.sqid = cpu_to_le16(qid);
1266         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1267         c.create_sq.sq_flags = cpu_to_le16(flags);
1268         c.create_sq.cqid = cpu_to_le16(qid);
1269
1270         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1271 }
1272
1273 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1274 {
1275         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1276 }
1277
1278 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1279 {
1280         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1281 }
1282
1283 static void abort_endio(struct request *req, blk_status_t error)
1284 {
1285         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1286         struct nvme_queue *nvmeq = iod->nvmeq;
1287
1288         dev_warn(nvmeq->dev->ctrl.device,
1289                  "Abort status: 0x%x", nvme_req(req)->status);
1290         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1291         blk_mq_free_request(req);
1292 }
1293
1294 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1295 {
1296         /* If true, indicates loss of adapter communication, possibly by a
1297          * NVMe Subsystem reset.
1298          */
1299         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1300
1301         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1302         switch (dev->ctrl.state) {
1303         case NVME_CTRL_RESETTING:
1304         case NVME_CTRL_CONNECTING:
1305                 return false;
1306         default:
1307                 break;
1308         }
1309
1310         /* We shouldn't reset unless the controller is on fatal error state
1311          * _or_ if we lost the communication with it.
1312          */
1313         if (!(csts & NVME_CSTS_CFS) && !nssro)
1314                 return false;
1315
1316         return true;
1317 }
1318
1319 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1320 {
1321         /* Read a config register to help see what died. */
1322         u16 pci_status;
1323         int result;
1324
1325         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1326                                       &pci_status);
1327         if (result == PCIBIOS_SUCCESSFUL)
1328                 dev_warn(dev->ctrl.device,
1329                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1330                          csts, pci_status);
1331         else
1332                 dev_warn(dev->ctrl.device,
1333                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1334                          csts, result);
1335 }
1336
1337 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1338 {
1339         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1340         struct nvme_queue *nvmeq = iod->nvmeq;
1341         struct nvme_dev *dev = nvmeq->dev;
1342         struct request *abort_req;
1343         struct nvme_command cmd = { };
1344         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1345
1346         /* If PCI error recovery process is happening, we cannot reset or
1347          * the recovery mechanism will surely fail.
1348          */
1349         mb();
1350         if (pci_channel_offline(to_pci_dev(dev->dev)))
1351                 return BLK_EH_RESET_TIMER;
1352
1353         /*
1354          * Reset immediately if the controller is failed
1355          */
1356         if (nvme_should_reset(dev, csts)) {
1357                 nvme_warn_reset(dev, csts);
1358                 nvme_dev_disable(dev, false);
1359                 nvme_reset_ctrl(&dev->ctrl);
1360                 return BLK_EH_DONE;
1361         }
1362
1363         /*
1364          * Did we miss an interrupt?
1365          */
1366         if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1367                 nvme_poll(req->mq_hctx, NULL);
1368         else
1369                 nvme_poll_irqdisable(nvmeq);
1370
1371         if (blk_mq_request_completed(req)) {
1372                 dev_warn(dev->ctrl.device,
1373                          "I/O %d QID %d timeout, completion polled\n",
1374                          req->tag, nvmeq->qid);
1375                 return BLK_EH_DONE;
1376         }
1377
1378         /*
1379          * Shutdown immediately if controller times out while starting. The
1380          * reset work will see the pci device disabled when it gets the forced
1381          * cancellation error. All outstanding requests are completed on
1382          * shutdown, so we return BLK_EH_DONE.
1383          */
1384         switch (dev->ctrl.state) {
1385         case NVME_CTRL_CONNECTING:
1386                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1387                 fallthrough;
1388         case NVME_CTRL_DELETING:
1389                 dev_warn_ratelimited(dev->ctrl.device,
1390                          "I/O %d QID %d timeout, disable controller\n",
1391                          req->tag, nvmeq->qid);
1392                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1393                 nvme_dev_disable(dev, true);
1394                 return BLK_EH_DONE;
1395         case NVME_CTRL_RESETTING:
1396                 return BLK_EH_RESET_TIMER;
1397         default:
1398                 break;
1399         }
1400
1401         /*
1402          * Shutdown the controller immediately and schedule a reset if the
1403          * command was already aborted once before and still hasn't been
1404          * returned to the driver, or if this is the admin queue.
1405          */
1406         if (!nvmeq->qid || iod->aborted) {
1407                 dev_warn(dev->ctrl.device,
1408                          "I/O %d QID %d timeout, reset controller\n",
1409                          req->tag, nvmeq->qid);
1410                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1411                 nvme_dev_disable(dev, false);
1412                 nvme_reset_ctrl(&dev->ctrl);
1413
1414                 return BLK_EH_DONE;
1415         }
1416
1417         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1418                 atomic_inc(&dev->ctrl.abort_limit);
1419                 return BLK_EH_RESET_TIMER;
1420         }
1421         iod->aborted = 1;
1422
1423         cmd.abort.opcode = nvme_admin_abort_cmd;
1424         cmd.abort.cid = nvme_cid(req);
1425         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1426
1427         dev_warn(nvmeq->dev->ctrl.device,
1428                 "I/O %d QID %d timeout, aborting\n",
1429                  req->tag, nvmeq->qid);
1430
1431         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1432                         BLK_MQ_REQ_NOWAIT);
1433         if (IS_ERR(abort_req)) {
1434                 atomic_inc(&dev->ctrl.abort_limit);
1435                 return BLK_EH_RESET_TIMER;
1436         }
1437
1438         abort_req->end_io_data = NULL;
1439         blk_execute_rq_nowait(abort_req, false, abort_endio);
1440
1441         /*
1442          * The aborted req will be completed on receiving the abort req.
1443          * We enable the timer again. If hit twice, it'll cause a device reset,
1444          * as the device then is in a faulty state.
1445          */
1446         return BLK_EH_RESET_TIMER;
1447 }
1448
1449 static void nvme_free_queue(struct nvme_queue *nvmeq)
1450 {
1451         dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1452                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1453         if (!nvmeq->sq_cmds)
1454                 return;
1455
1456         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1457                 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1458                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1459         } else {
1460                 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1461                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1462         }
1463 }
1464
1465 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1466 {
1467         int i;
1468
1469         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1470                 dev->ctrl.queue_count--;
1471                 nvme_free_queue(&dev->queues[i]);
1472         }
1473 }
1474
1475 /**
1476  * nvme_suspend_queue - put queue into suspended state
1477  * @nvmeq: queue to suspend
1478  */
1479 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1480 {
1481         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1482                 return 1;
1483
1484         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1485         mb();
1486
1487         nvmeq->dev->online_queues--;
1488         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1489                 nvme_stop_admin_queue(&nvmeq->dev->ctrl);
1490         if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1491                 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1492         return 0;
1493 }
1494
1495 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1496 {
1497         int i;
1498
1499         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1500                 nvme_suspend_queue(&dev->queues[i]);
1501 }
1502
1503 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1504 {
1505         struct nvme_queue *nvmeq = &dev->queues[0];
1506
1507         if (shutdown)
1508                 nvme_shutdown_ctrl(&dev->ctrl);
1509         else
1510                 nvme_disable_ctrl(&dev->ctrl);
1511
1512         nvme_poll_irqdisable(nvmeq);
1513 }
1514
1515 /*
1516  * Called only on a device that has been disabled and after all other threads
1517  * that can check this device's completion queues have synced, except
1518  * nvme_poll(). This is the last chance for the driver to see a natural
1519  * completion before nvme_cancel_request() terminates all incomplete requests.
1520  */
1521 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1522 {
1523         int i;
1524
1525         for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1526                 spin_lock(&dev->queues[i].cq_poll_lock);
1527                 nvme_poll_cq(&dev->queues[i], NULL);
1528                 spin_unlock(&dev->queues[i].cq_poll_lock);
1529         }
1530 }
1531
1532 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1533                                 int entry_size)
1534 {
1535         int q_depth = dev->q_depth;
1536         unsigned q_size_aligned = roundup(q_depth * entry_size,
1537                                           NVME_CTRL_PAGE_SIZE);
1538
1539         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1540                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1541
1542                 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1543                 q_depth = div_u64(mem_per_q, entry_size);
1544
1545                 /*
1546                  * Ensure the reduced q_depth is above some threshold where it
1547                  * would be better to map queues in system memory with the
1548                  * original depth
1549                  */
1550                 if (q_depth < 64)
1551                         return -ENOMEM;
1552         }
1553
1554         return q_depth;
1555 }
1556
1557 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1558                                 int qid)
1559 {
1560         struct pci_dev *pdev = to_pci_dev(dev->dev);
1561
1562         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1563                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1564                 if (nvmeq->sq_cmds) {
1565                         nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1566                                                         nvmeq->sq_cmds);
1567                         if (nvmeq->sq_dma_addr) {
1568                                 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1569                                 return 0;
1570                         }
1571
1572                         pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1573                 }
1574         }
1575
1576         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1577                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1578         if (!nvmeq->sq_cmds)
1579                 return -ENOMEM;
1580         return 0;
1581 }
1582
1583 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1584 {
1585         struct nvme_queue *nvmeq = &dev->queues[qid];
1586
1587         if (dev->ctrl.queue_count > qid)
1588                 return 0;
1589
1590         nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1591         nvmeq->q_depth = depth;
1592         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1593                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1594         if (!nvmeq->cqes)
1595                 goto free_nvmeq;
1596
1597         if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1598                 goto free_cqdma;
1599
1600         nvmeq->dev = dev;
1601         spin_lock_init(&nvmeq->sq_lock);
1602         spin_lock_init(&nvmeq->cq_poll_lock);
1603         nvmeq->cq_head = 0;
1604         nvmeq->cq_phase = 1;
1605         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1606         nvmeq->qid = qid;
1607         dev->ctrl.queue_count++;
1608
1609         return 0;
1610
1611  free_cqdma:
1612         dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1613                           nvmeq->cq_dma_addr);
1614  free_nvmeq:
1615         return -ENOMEM;
1616 }
1617
1618 static int queue_request_irq(struct nvme_queue *nvmeq)
1619 {
1620         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1621         int nr = nvmeq->dev->ctrl.instance;
1622
1623         if (use_threaded_interrupts) {
1624                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1625                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1626         } else {
1627                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1628                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1629         }
1630 }
1631
1632 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1633 {
1634         struct nvme_dev *dev = nvmeq->dev;
1635
1636         nvmeq->sq_tail = 0;
1637         nvmeq->last_sq_tail = 0;
1638         nvmeq->cq_head = 0;
1639         nvmeq->cq_phase = 1;
1640         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1641         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1642         nvme_dbbuf_init(dev, nvmeq, qid);
1643         dev->online_queues++;
1644         wmb(); /* ensure the first interrupt sees the initialization */
1645 }
1646
1647 /*
1648  * Try getting shutdown_lock while setting up IO queues.
1649  */
1650 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1651 {
1652         /*
1653          * Give up if the lock is being held by nvme_dev_disable.
1654          */
1655         if (!mutex_trylock(&dev->shutdown_lock))
1656                 return -ENODEV;
1657
1658         /*
1659          * Controller is in wrong state, fail early.
1660          */
1661         if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1662                 mutex_unlock(&dev->shutdown_lock);
1663                 return -ENODEV;
1664         }
1665
1666         return 0;
1667 }
1668
1669 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1670 {
1671         struct nvme_dev *dev = nvmeq->dev;
1672         int result;
1673         u16 vector = 0;
1674
1675         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1676
1677         /*
1678          * A queue's vector matches the queue identifier unless the controller
1679          * has only one vector available.
1680          */
1681         if (!polled)
1682                 vector = dev->num_vecs == 1 ? 0 : qid;
1683         else
1684                 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1685
1686         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1687         if (result)
1688                 return result;
1689
1690         result = adapter_alloc_sq(dev, qid, nvmeq);
1691         if (result < 0)
1692                 return result;
1693         if (result)
1694                 goto release_cq;
1695
1696         nvmeq->cq_vector = vector;
1697
1698         result = nvme_setup_io_queues_trylock(dev);
1699         if (result)
1700                 return result;
1701         nvme_init_queue(nvmeq, qid);
1702         if (!polled) {
1703                 result = queue_request_irq(nvmeq);
1704                 if (result < 0)
1705                         goto release_sq;
1706         }
1707
1708         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1709         mutex_unlock(&dev->shutdown_lock);
1710         return result;
1711
1712 release_sq:
1713         dev->online_queues--;
1714         mutex_unlock(&dev->shutdown_lock);
1715         adapter_delete_sq(dev, qid);
1716 release_cq:
1717         adapter_delete_cq(dev, qid);
1718         return result;
1719 }
1720
1721 static const struct blk_mq_ops nvme_mq_admin_ops = {
1722         .queue_rq       = nvme_queue_rq,
1723         .complete       = nvme_pci_complete_rq,
1724         .init_hctx      = nvme_admin_init_hctx,
1725         .init_request   = nvme_init_request,
1726         .timeout        = nvme_timeout,
1727 };
1728
1729 static const struct blk_mq_ops nvme_mq_ops = {
1730         .queue_rq       = nvme_queue_rq,
1731         .queue_rqs      = nvme_queue_rqs,
1732         .complete       = nvme_pci_complete_rq,
1733         .commit_rqs     = nvme_commit_rqs,
1734         .init_hctx      = nvme_init_hctx,
1735         .init_request   = nvme_init_request,
1736         .map_queues     = nvme_pci_map_queues,
1737         .timeout        = nvme_timeout,
1738         .poll           = nvme_poll,
1739 };
1740
1741 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1742 {
1743         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1744                 /*
1745                  * If the controller was reset during removal, it's possible
1746                  * user requests may be waiting on a stopped queue. Start the
1747                  * queue to flush these to completion.
1748                  */
1749                 nvme_start_admin_queue(&dev->ctrl);
1750                 blk_cleanup_queue(dev->ctrl.admin_q);
1751                 blk_mq_free_tag_set(&dev->admin_tagset);
1752         }
1753 }
1754
1755 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1756 {
1757         if (!dev->ctrl.admin_q) {
1758                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1759                 dev->admin_tagset.nr_hw_queues = 1;
1760
1761                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1762                 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1763                 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1764                 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1765                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1766                 dev->admin_tagset.driver_data = dev;
1767
1768                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1769                         return -ENOMEM;
1770                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1771
1772                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1773                 if (IS_ERR(dev->ctrl.admin_q)) {
1774                         blk_mq_free_tag_set(&dev->admin_tagset);
1775                         return -ENOMEM;
1776                 }
1777                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1778                         nvme_dev_remove_admin(dev);
1779                         dev->ctrl.admin_q = NULL;
1780                         return -ENODEV;
1781                 }
1782         } else
1783                 nvme_start_admin_queue(&dev->ctrl);
1784
1785         return 0;
1786 }
1787
1788 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1789 {
1790         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1791 }
1792
1793 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1794 {
1795         struct pci_dev *pdev = to_pci_dev(dev->dev);
1796
1797         if (size <= dev->bar_mapped_size)
1798                 return 0;
1799         if (size > pci_resource_len(pdev, 0))
1800                 return -ENOMEM;
1801         if (dev->bar)
1802                 iounmap(dev->bar);
1803         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1804         if (!dev->bar) {
1805                 dev->bar_mapped_size = 0;
1806                 return -ENOMEM;
1807         }
1808         dev->bar_mapped_size = size;
1809         dev->dbs = dev->bar + NVME_REG_DBS;
1810
1811         return 0;
1812 }
1813
1814 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1815 {
1816         int result;
1817         u32 aqa;
1818         struct nvme_queue *nvmeq;
1819
1820         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1821         if (result < 0)
1822                 return result;
1823
1824         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1825                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1826
1827         if (dev->subsystem &&
1828             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1829                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1830
1831         result = nvme_disable_ctrl(&dev->ctrl);
1832         if (result < 0)
1833                 return result;
1834
1835         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1836         if (result)
1837                 return result;
1838
1839         dev->ctrl.numa_node = dev_to_node(dev->dev);
1840
1841         nvmeq = &dev->queues[0];
1842         aqa = nvmeq->q_depth - 1;
1843         aqa |= aqa << 16;
1844
1845         writel(aqa, dev->bar + NVME_REG_AQA);
1846         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1847         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1848
1849         result = nvme_enable_ctrl(&dev->ctrl);
1850         if (result)
1851                 return result;
1852
1853         nvmeq->cq_vector = 0;
1854         nvme_init_queue(nvmeq, 0);
1855         result = queue_request_irq(nvmeq);
1856         if (result) {
1857                 dev->online_queues--;
1858                 return result;
1859         }
1860
1861         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1862         return result;
1863 }
1864
1865 static int nvme_create_io_queues(struct nvme_dev *dev)
1866 {
1867         unsigned i, max, rw_queues;
1868         int ret = 0;
1869
1870         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1871                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1872                         ret = -ENOMEM;
1873                         break;
1874                 }
1875         }
1876
1877         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1878         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1879                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1880                                 dev->io_queues[HCTX_TYPE_READ];
1881         } else {
1882                 rw_queues = max;
1883         }
1884
1885         for (i = dev->online_queues; i <= max; i++) {
1886                 bool polled = i > rw_queues;
1887
1888                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1889                 if (ret)
1890                         break;
1891         }
1892
1893         /*
1894          * Ignore failing Create SQ/CQ commands, we can continue with less
1895          * than the desired amount of queues, and even a controller without
1896          * I/O queues can still be used to issue admin commands.  This might
1897          * be useful to upgrade a buggy firmware for example.
1898          */
1899         return ret >= 0 ? 0 : ret;
1900 }
1901
1902 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1903 {
1904         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1905
1906         return 1ULL << (12 + 4 * szu);
1907 }
1908
1909 static u32 nvme_cmb_size(struct nvme_dev *dev)
1910 {
1911         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1912 }
1913
1914 static void nvme_map_cmb(struct nvme_dev *dev)
1915 {
1916         u64 size, offset;
1917         resource_size_t bar_size;
1918         struct pci_dev *pdev = to_pci_dev(dev->dev);
1919         int bar;
1920
1921         if (dev->cmb_size)
1922                 return;
1923
1924         if (NVME_CAP_CMBS(dev->ctrl.cap))
1925                 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1926
1927         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1928         if (!dev->cmbsz)
1929                 return;
1930         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1931
1932         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1933         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1934         bar = NVME_CMB_BIR(dev->cmbloc);
1935         bar_size = pci_resource_len(pdev, bar);
1936
1937         if (offset > bar_size)
1938                 return;
1939
1940         /*
1941          * Tell the controller about the host side address mapping the CMB,
1942          * and enable CMB decoding for the NVMe 1.4+ scheme:
1943          */
1944         if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1945                 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1946                              (pci_bus_address(pdev, bar) + offset),
1947                              dev->bar + NVME_REG_CMBMSC);
1948         }
1949
1950         /*
1951          * Controllers may support a CMB size larger than their BAR,
1952          * for example, due to being behind a bridge. Reduce the CMB to
1953          * the reported size of the BAR
1954          */
1955         if (size > bar_size - offset)
1956                 size = bar_size - offset;
1957
1958         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1959                 dev_warn(dev->ctrl.device,
1960                          "failed to register the CMB\n");
1961                 return;
1962         }
1963
1964         dev->cmb_size = size;
1965         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1966
1967         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1968                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1969                 pci_p2pmem_publish(pdev, true);
1970 }
1971
1972 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1973 {
1974         u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1975         u64 dma_addr = dev->host_mem_descs_dma;
1976         struct nvme_command c = { };
1977         int ret;
1978
1979         c.features.opcode       = nvme_admin_set_features;
1980         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1981         c.features.dword11      = cpu_to_le32(bits);
1982         c.features.dword12      = cpu_to_le32(host_mem_size);
1983         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1984         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1985         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1986
1987         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1988         if (ret) {
1989                 dev_warn(dev->ctrl.device,
1990                          "failed to set host mem (err %d, flags %#x).\n",
1991                          ret, bits);
1992         } else
1993                 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1994
1995         return ret;
1996 }
1997
1998 static void nvme_free_host_mem(struct nvme_dev *dev)
1999 {
2000         int i;
2001
2002         for (i = 0; i < dev->nr_host_mem_descs; i++) {
2003                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
2004                 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
2005
2006                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2007                                le64_to_cpu(desc->addr),
2008                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2009         }
2010
2011         kfree(dev->host_mem_desc_bufs);
2012         dev->host_mem_desc_bufs = NULL;
2013         dma_free_coherent(dev->dev,
2014                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
2015                         dev->host_mem_descs, dev->host_mem_descs_dma);
2016         dev->host_mem_descs = NULL;
2017         dev->nr_host_mem_descs = 0;
2018 }
2019
2020 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
2021                 u32 chunk_size)
2022 {
2023         struct nvme_host_mem_buf_desc *descs;
2024         u32 max_entries, len;
2025         dma_addr_t descs_dma;
2026         int i = 0;
2027         void **bufs;
2028         u64 size, tmp;
2029
2030         tmp = (preferred + chunk_size - 1);
2031         do_div(tmp, chunk_size);
2032         max_entries = tmp;
2033
2034         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2035                 max_entries = dev->ctrl.hmmaxd;
2036
2037         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
2038                                    &descs_dma, GFP_KERNEL);
2039         if (!descs)
2040                 goto out;
2041
2042         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2043         if (!bufs)
2044                 goto out_free_descs;
2045
2046         for (size = 0; size < preferred && i < max_entries; size += len) {
2047                 dma_addr_t dma_addr;
2048
2049                 len = min_t(u64, chunk_size, preferred - size);
2050                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2051                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2052                 if (!bufs[i])
2053                         break;
2054
2055                 descs[i].addr = cpu_to_le64(dma_addr);
2056                 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
2057                 i++;
2058         }
2059
2060         if (!size)
2061                 goto out_free_bufs;
2062
2063         dev->nr_host_mem_descs = i;
2064         dev->host_mem_size = size;
2065         dev->host_mem_descs = descs;
2066         dev->host_mem_descs_dma = descs_dma;
2067         dev->host_mem_desc_bufs = bufs;
2068         return 0;
2069
2070 out_free_bufs:
2071         while (--i >= 0) {
2072                 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
2073
2074                 dma_free_attrs(dev->dev, size, bufs[i],
2075                                le64_to_cpu(descs[i].addr),
2076                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2077         }
2078
2079         kfree(bufs);
2080 out_free_descs:
2081         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2082                         descs_dma);
2083 out:
2084         dev->host_mem_descs = NULL;
2085         return -ENOMEM;
2086 }
2087
2088 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2089 {
2090         u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2091         u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2092         u64 chunk_size;
2093
2094         /* start big and work our way down */
2095         for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2096                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2097                         if (!min || dev->host_mem_size >= min)
2098                                 return 0;
2099                         nvme_free_host_mem(dev);
2100                 }
2101         }
2102
2103         return -ENOMEM;
2104 }
2105
2106 static int nvme_setup_host_mem(struct nvme_dev *dev)
2107 {
2108         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2109         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2110         u64 min = (u64)dev->ctrl.hmmin * 4096;
2111         u32 enable_bits = NVME_HOST_MEM_ENABLE;
2112         int ret;
2113
2114         preferred = min(preferred, max);
2115         if (min > max) {
2116                 dev_warn(dev->ctrl.device,
2117                         "min host memory (%lld MiB) above limit (%d MiB).\n",
2118                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
2119                 nvme_free_host_mem(dev);
2120                 return 0;
2121         }
2122
2123         /*
2124          * If we already have a buffer allocated check if we can reuse it.
2125          */
2126         if (dev->host_mem_descs) {
2127                 if (dev->host_mem_size >= min)
2128                         enable_bits |= NVME_HOST_MEM_RETURN;
2129                 else
2130                         nvme_free_host_mem(dev);
2131         }
2132
2133         if (!dev->host_mem_descs) {
2134                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2135                         dev_warn(dev->ctrl.device,
2136                                 "failed to allocate host memory buffer.\n");
2137                         return 0; /* controller must work without HMB */
2138                 }
2139
2140                 dev_info(dev->ctrl.device,
2141                         "allocated %lld MiB host memory buffer.\n",
2142                         dev->host_mem_size >> ilog2(SZ_1M));
2143         }
2144
2145         ret = nvme_set_host_mem(dev, enable_bits);
2146         if (ret)
2147                 nvme_free_host_mem(dev);
2148         return ret;
2149 }
2150
2151 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2152                 char *buf)
2153 {
2154         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2155
2156         return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz  : x%08x\n",
2157                        ndev->cmbloc, ndev->cmbsz);
2158 }
2159 static DEVICE_ATTR_RO(cmb);
2160
2161 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2162                 char *buf)
2163 {
2164         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2165
2166         return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2167 }
2168 static DEVICE_ATTR_RO(cmbloc);
2169
2170 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2171                 char *buf)
2172 {
2173         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2174
2175         return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2176 }
2177 static DEVICE_ATTR_RO(cmbsz);
2178
2179 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2180                         char *buf)
2181 {
2182         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2183
2184         return sysfs_emit(buf, "%d\n", ndev->hmb);
2185 }
2186
2187 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2188                          const char *buf, size_t count)
2189 {
2190         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2191         bool new;
2192         int ret;
2193
2194         if (strtobool(buf, &new) < 0)
2195                 return -EINVAL;
2196
2197         if (new == ndev->hmb)
2198                 return count;
2199
2200         if (new) {
2201                 ret = nvme_setup_host_mem(ndev);
2202         } else {
2203                 ret = nvme_set_host_mem(ndev, 0);
2204                 if (!ret)
2205                         nvme_free_host_mem(ndev);
2206         }
2207
2208         if (ret < 0)
2209                 return ret;
2210
2211         return count;
2212 }
2213 static DEVICE_ATTR_RW(hmb);
2214
2215 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2216                 struct attribute *a, int n)
2217 {
2218         struct nvme_ctrl *ctrl =
2219                 dev_get_drvdata(container_of(kobj, struct device, kobj));
2220         struct nvme_dev *dev = to_nvme_dev(ctrl);
2221
2222         if (a == &dev_attr_cmb.attr ||
2223             a == &dev_attr_cmbloc.attr ||
2224             a == &dev_attr_cmbsz.attr) {
2225                 if (!dev->cmbsz)
2226                         return 0;
2227         }
2228         if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2229                 return 0;
2230
2231         return a->mode;
2232 }
2233
2234 static struct attribute *nvme_pci_attrs[] = {
2235         &dev_attr_cmb.attr,
2236         &dev_attr_cmbloc.attr,
2237         &dev_attr_cmbsz.attr,
2238         &dev_attr_hmb.attr,
2239         NULL,
2240 };
2241
2242 static const struct attribute_group nvme_pci_attr_group = {
2243         .attrs          = nvme_pci_attrs,
2244         .is_visible     = nvme_pci_attrs_are_visible,
2245 };
2246
2247 /*
2248  * nirqs is the number of interrupts available for write and read
2249  * queues. The core already reserved an interrupt for the admin queue.
2250  */
2251 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2252 {
2253         struct nvme_dev *dev = affd->priv;
2254         unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2255
2256         /*
2257          * If there is no interrupt available for queues, ensure that
2258          * the default queue is set to 1. The affinity set size is
2259          * also set to one, but the irq core ignores it for this case.
2260          *
2261          * If only one interrupt is available or 'write_queue' == 0, combine
2262          * write and read queues.
2263          *
2264          * If 'write_queues' > 0, ensure it leaves room for at least one read
2265          * queue.
2266          */
2267         if (!nrirqs) {
2268                 nrirqs = 1;
2269                 nr_read_queues = 0;
2270         } else if (nrirqs == 1 || !nr_write_queues) {
2271                 nr_read_queues = 0;
2272         } else if (nr_write_queues >= nrirqs) {
2273                 nr_read_queues = 1;
2274         } else {
2275                 nr_read_queues = nrirqs - nr_write_queues;
2276         }
2277
2278         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2279         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2280         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2281         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2282         affd->nr_sets = nr_read_queues ? 2 : 1;
2283 }
2284
2285 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2286 {
2287         struct pci_dev *pdev = to_pci_dev(dev->dev);
2288         struct irq_affinity affd = {
2289                 .pre_vectors    = 1,
2290                 .calc_sets      = nvme_calc_irq_sets,
2291                 .priv           = dev,
2292         };
2293         unsigned int irq_queues, poll_queues;
2294
2295         /*
2296          * Poll queues don't need interrupts, but we need at least one I/O queue
2297          * left over for non-polled I/O.
2298          */
2299         poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2300         dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2301
2302         /*
2303          * Initialize for the single interrupt case, will be updated in
2304          * nvme_calc_irq_sets().
2305          */
2306         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2307         dev->io_queues[HCTX_TYPE_READ] = 0;
2308
2309         /*
2310          * We need interrupts for the admin queue and each non-polled I/O queue,
2311          * but some Apple controllers require all queues to use the first
2312          * vector.
2313          */
2314         irq_queues = 1;
2315         if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2316                 irq_queues += (nr_io_queues - poll_queues);
2317         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2318                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2319 }
2320
2321 static void nvme_disable_io_queues(struct nvme_dev *dev)
2322 {
2323         if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2324                 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2325 }
2326
2327 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2328 {
2329         /*
2330          * If tags are shared with admin queue (Apple bug), then
2331          * make sure we only use one IO queue.
2332          */
2333         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2334                 return 1;
2335         return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2336 }
2337
2338 static int nvme_setup_io_queues(struct nvme_dev *dev)
2339 {
2340         struct nvme_queue *adminq = &dev->queues[0];
2341         struct pci_dev *pdev = to_pci_dev(dev->dev);
2342         unsigned int nr_io_queues;
2343         unsigned long size;
2344         int result;
2345
2346         /*
2347          * Sample the module parameters once at reset time so that we have
2348          * stable values to work with.
2349          */
2350         dev->nr_write_queues = write_queues;
2351         dev->nr_poll_queues = poll_queues;
2352
2353         nr_io_queues = dev->nr_allocated_queues - 1;
2354         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2355         if (result < 0)
2356                 return result;
2357
2358         if (nr_io_queues == 0)
2359                 return 0;
2360
2361         /*
2362          * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2363          * from set to unset. If there is a window to it is truely freed,
2364          * pci_free_irq_vectors() jumping into this window will crash.
2365          * And take lock to avoid racing with pci_free_irq_vectors() in
2366          * nvme_dev_disable() path.
2367          */
2368         result = nvme_setup_io_queues_trylock(dev);
2369         if (result)
2370                 return result;
2371         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2372                 pci_free_irq(pdev, 0, adminq);
2373
2374         if (dev->cmb_use_sqes) {
2375                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2376                                 sizeof(struct nvme_command));
2377                 if (result > 0)
2378                         dev->q_depth = result;
2379                 else
2380                         dev->cmb_use_sqes = false;
2381         }
2382
2383         do {
2384                 size = db_bar_size(dev, nr_io_queues);
2385                 result = nvme_remap_bar(dev, size);
2386                 if (!result)
2387                         break;
2388                 if (!--nr_io_queues) {
2389                         result = -ENOMEM;
2390                         goto out_unlock;
2391                 }
2392         } while (1);
2393         adminq->q_db = dev->dbs;
2394
2395  retry:
2396         /* Deregister the admin queue's interrupt */
2397         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2398                 pci_free_irq(pdev, 0, adminq);
2399
2400         /*
2401          * If we enable msix early due to not intx, disable it again before
2402          * setting up the full range we need.
2403          */
2404         pci_free_irq_vectors(pdev);
2405
2406         result = nvme_setup_irqs(dev, nr_io_queues);
2407         if (result <= 0) {
2408                 result = -EIO;
2409                 goto out_unlock;
2410         }
2411
2412         dev->num_vecs = result;
2413         result = max(result - 1, 1);
2414         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2415
2416         /*
2417          * Should investigate if there's a performance win from allocating
2418          * more queues than interrupt vectors; it might allow the submission
2419          * path to scale better, even if the receive path is limited by the
2420          * number of interrupts.
2421          */
2422         result = queue_request_irq(adminq);
2423         if (result)
2424                 goto out_unlock;
2425         set_bit(NVMEQ_ENABLED, &adminq->flags);
2426         mutex_unlock(&dev->shutdown_lock);
2427
2428         result = nvme_create_io_queues(dev);
2429         if (result || dev->online_queues < 2)
2430                 return result;
2431
2432         if (dev->online_queues - 1 < dev->max_qid) {
2433                 nr_io_queues = dev->online_queues - 1;
2434                 nvme_disable_io_queues(dev);
2435                 result = nvme_setup_io_queues_trylock(dev);
2436                 if (result)
2437                         return result;
2438                 nvme_suspend_io_queues(dev);
2439                 goto retry;
2440         }
2441         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2442                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2443                                         dev->io_queues[HCTX_TYPE_READ],
2444                                         dev->io_queues[HCTX_TYPE_POLL]);
2445         return 0;
2446 out_unlock:
2447         mutex_unlock(&dev->shutdown_lock);
2448         return result;
2449 }
2450
2451 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2452 {
2453         struct nvme_queue *nvmeq = req->end_io_data;
2454
2455         blk_mq_free_request(req);
2456         complete(&nvmeq->delete_done);
2457 }
2458
2459 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2460 {
2461         struct nvme_queue *nvmeq = req->end_io_data;
2462
2463         if (error)
2464                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2465
2466         nvme_del_queue_end(req, error);
2467 }
2468
2469 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2470 {
2471         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2472         struct request *req;
2473         struct nvme_command cmd = { };
2474
2475         cmd.delete_queue.opcode = opcode;
2476         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2477
2478         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
2479         if (IS_ERR(req))
2480                 return PTR_ERR(req);
2481
2482         req->end_io_data = nvmeq;
2483
2484         init_completion(&nvmeq->delete_done);
2485         blk_execute_rq_nowait(req, false, opcode == nvme_admin_delete_cq ?
2486                         nvme_del_cq_end : nvme_del_queue_end);
2487         return 0;
2488 }
2489
2490 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2491 {
2492         int nr_queues = dev->online_queues - 1, sent = 0;
2493         unsigned long timeout;
2494
2495  retry:
2496         timeout = NVME_ADMIN_TIMEOUT;
2497         while (nr_queues > 0) {
2498                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2499                         break;
2500                 nr_queues--;
2501                 sent++;
2502         }
2503         while (sent) {
2504                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2505
2506                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2507                                 timeout);
2508                 if (timeout == 0)
2509                         return false;
2510
2511                 sent--;
2512                 if (nr_queues)
2513                         goto retry;
2514         }
2515         return true;
2516 }
2517
2518 static void nvme_dev_add(struct nvme_dev *dev)
2519 {
2520         int ret;
2521
2522         if (!dev->ctrl.tagset) {
2523                 dev->tagset.ops = &nvme_mq_ops;
2524                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2525                 dev->tagset.nr_maps = 2; /* default + read */
2526                 if (dev->io_queues[HCTX_TYPE_POLL])
2527                         dev->tagset.nr_maps++;
2528                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2529                 dev->tagset.numa_node = dev->ctrl.numa_node;
2530                 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2531                                                 BLK_MQ_MAX_DEPTH) - 1;
2532                 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2533                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2534                 dev->tagset.driver_data = dev;
2535
2536                 /*
2537                  * Some Apple controllers requires tags to be unique
2538                  * across admin and IO queue, so reserve the first 32
2539                  * tags of the IO queue.
2540                  */
2541                 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2542                         dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2543
2544                 ret = blk_mq_alloc_tag_set(&dev->tagset);
2545                 if (ret) {
2546                         dev_warn(dev->ctrl.device,
2547                                 "IO queues tagset allocation failed %d\n", ret);
2548                         return;
2549                 }
2550                 dev->ctrl.tagset = &dev->tagset;
2551         } else {
2552                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2553
2554                 /* Free previously allocated queues that are no longer usable */
2555                 nvme_free_queues(dev, dev->online_queues);
2556         }
2557
2558         nvme_dbbuf_set(dev);
2559 }
2560
2561 static int nvme_pci_enable(struct nvme_dev *dev)
2562 {
2563         int result = -ENOMEM;
2564         struct pci_dev *pdev = to_pci_dev(dev->dev);
2565         int dma_address_bits = 64;
2566
2567         if (pci_enable_device_mem(pdev))
2568                 return result;
2569
2570         pci_set_master(pdev);
2571
2572         if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2573                 dma_address_bits = 48;
2574         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2575                 goto disable;
2576
2577         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2578                 result = -ENODEV;
2579                 goto disable;
2580         }
2581
2582         /*
2583          * Some devices and/or platforms don't advertise or work with INTx
2584          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2585          * adjust this later.
2586          */
2587         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2588         if (result < 0)
2589                 return result;
2590
2591         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2592
2593         dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2594                                 io_queue_depth);
2595         dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2596         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2597         dev->dbs = dev->bar + 4096;
2598
2599         /*
2600          * Some Apple controllers require a non-standard SQE size.
2601          * Interestingly they also seem to ignore the CC:IOSQES register
2602          * so we don't bother updating it here.
2603          */
2604         if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2605                 dev->io_sqes = 7;
2606         else
2607                 dev->io_sqes = NVME_NVM_IOSQES;
2608
2609         /*
2610          * Temporary fix for the Apple controller found in the MacBook8,1 and
2611          * some MacBook7,1 to avoid controller resets and data loss.
2612          */
2613         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2614                 dev->q_depth = 2;
2615                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2616                         "set queue depth=%u to work around controller resets\n",
2617                         dev->q_depth);
2618         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2619                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2620                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2621                 dev->q_depth = 64;
2622                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2623                         "set queue depth=%u\n", dev->q_depth);
2624         }
2625
2626         /*
2627          * Controllers with the shared tags quirk need the IO queue to be
2628          * big enough so that we get 32 tags for the admin queue
2629          */
2630         if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2631             (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2632                 dev->q_depth = NVME_AQ_DEPTH + 2;
2633                 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2634                          dev->q_depth);
2635         }
2636
2637
2638         nvme_map_cmb(dev);
2639
2640         pci_enable_pcie_error_reporting(pdev);
2641         pci_save_state(pdev);
2642         return 0;
2643
2644  disable:
2645         pci_disable_device(pdev);
2646         return result;
2647 }
2648
2649 static void nvme_dev_unmap(struct nvme_dev *dev)
2650 {
2651         if (dev->bar)
2652                 iounmap(dev->bar);
2653         pci_release_mem_regions(to_pci_dev(dev->dev));
2654 }
2655
2656 static void nvme_pci_disable(struct nvme_dev *dev)
2657 {
2658         struct pci_dev *pdev = to_pci_dev(dev->dev);
2659
2660         pci_free_irq_vectors(pdev);
2661
2662         if (pci_is_enabled(pdev)) {
2663                 pci_disable_pcie_error_reporting(pdev);
2664                 pci_disable_device(pdev);
2665         }
2666 }
2667
2668 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2669 {
2670         bool dead = true, freeze = false;
2671         struct pci_dev *pdev = to_pci_dev(dev->dev);
2672
2673         mutex_lock(&dev->shutdown_lock);
2674         if (pci_is_enabled(pdev)) {
2675                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2676
2677                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2678                     dev->ctrl.state == NVME_CTRL_RESETTING) {
2679                         freeze = true;
2680                         nvme_start_freeze(&dev->ctrl);
2681                 }
2682                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2683                         pdev->error_state  != pci_channel_io_normal);
2684         }
2685
2686         /*
2687          * Give the controller a chance to complete all entered requests if
2688          * doing a safe shutdown.
2689          */
2690         if (!dead && shutdown && freeze)
2691                 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2692
2693         nvme_stop_queues(&dev->ctrl);
2694
2695         if (!dead && dev->ctrl.queue_count > 0) {
2696                 nvme_disable_io_queues(dev);
2697                 nvme_disable_admin_queue(dev, shutdown);
2698         }
2699         nvme_suspend_io_queues(dev);
2700         nvme_suspend_queue(&dev->queues[0]);
2701         nvme_pci_disable(dev);
2702         nvme_reap_pending_cqes(dev);
2703
2704         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2705         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2706         blk_mq_tagset_wait_completed_request(&dev->tagset);
2707         blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2708
2709         /*
2710          * The driver will not be starting up queues again if shutting down so
2711          * must flush all entered requests to their failed completion to avoid
2712          * deadlocking blk-mq hot-cpu notifier.
2713          */
2714         if (shutdown) {
2715                 nvme_start_queues(&dev->ctrl);
2716                 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2717                         nvme_start_admin_queue(&dev->ctrl);
2718         }
2719         mutex_unlock(&dev->shutdown_lock);
2720 }
2721
2722 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2723 {
2724         if (!nvme_wait_reset(&dev->ctrl))
2725                 return -EBUSY;
2726         nvme_dev_disable(dev, shutdown);
2727         return 0;
2728 }
2729
2730 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2731 {
2732         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2733                                                 NVME_CTRL_PAGE_SIZE,
2734                                                 NVME_CTRL_PAGE_SIZE, 0);
2735         if (!dev->prp_page_pool)
2736                 return -ENOMEM;
2737
2738         /* Optimisation for I/Os between 4k and 128k */
2739         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2740                                                 256, 256, 0);
2741         if (!dev->prp_small_pool) {
2742                 dma_pool_destroy(dev->prp_page_pool);
2743                 return -ENOMEM;
2744         }
2745         return 0;
2746 }
2747
2748 static void nvme_release_prp_pools(struct nvme_dev *dev)
2749 {
2750         dma_pool_destroy(dev->prp_page_pool);
2751         dma_pool_destroy(dev->prp_small_pool);
2752 }
2753
2754 static void nvme_free_tagset(struct nvme_dev *dev)
2755 {
2756         if (dev->tagset.tags)
2757                 blk_mq_free_tag_set(&dev->tagset);
2758         dev->ctrl.tagset = NULL;
2759 }
2760
2761 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2762 {
2763         struct nvme_dev *dev = to_nvme_dev(ctrl);
2764
2765         nvme_dbbuf_dma_free(dev);
2766         nvme_free_tagset(dev);
2767         if (dev->ctrl.admin_q)
2768                 blk_put_queue(dev->ctrl.admin_q);
2769         free_opal_dev(dev->ctrl.opal_dev);
2770         mempool_destroy(dev->iod_mempool);
2771         put_device(dev->dev);
2772         kfree(dev->queues);
2773         kfree(dev);
2774 }
2775
2776 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2777 {
2778         /*
2779          * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2780          * may be holding this pci_dev's device lock.
2781          */
2782         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2783         nvme_get_ctrl(&dev->ctrl);
2784         nvme_dev_disable(dev, false);
2785         nvme_kill_queues(&dev->ctrl);
2786         if (!queue_work(nvme_wq, &dev->remove_work))
2787                 nvme_put_ctrl(&dev->ctrl);
2788 }
2789
2790 static void nvme_reset_work(struct work_struct *work)
2791 {
2792         struct nvme_dev *dev =
2793                 container_of(work, struct nvme_dev, ctrl.reset_work);
2794         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2795         int result;
2796
2797         if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2798                 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2799                          dev->ctrl.state);
2800                 result = -ENODEV;
2801                 goto out;
2802         }
2803
2804         /*
2805          * If we're called to reset a live controller first shut it down before
2806          * moving on.
2807          */
2808         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2809                 nvme_dev_disable(dev, false);
2810         nvme_sync_queues(&dev->ctrl);
2811
2812         mutex_lock(&dev->shutdown_lock);
2813         result = nvme_pci_enable(dev);
2814         if (result)
2815                 goto out_unlock;
2816
2817         result = nvme_pci_configure_admin_queue(dev);
2818         if (result)
2819                 goto out_unlock;
2820
2821         result = nvme_alloc_admin_tags(dev);
2822         if (result)
2823                 goto out_unlock;
2824
2825         /*
2826          * Limit the max command size to prevent iod->sg allocations going
2827          * over a single page.
2828          */
2829         dev->ctrl.max_hw_sectors = min_t(u32,
2830                 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2831         dev->ctrl.max_segments = NVME_MAX_SEGS;
2832
2833         /*
2834          * Don't limit the IOMMU merged segment size.
2835          */
2836         dma_set_max_seg_size(dev->dev, 0xffffffff);
2837         dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2838
2839         mutex_unlock(&dev->shutdown_lock);
2840
2841         /*
2842          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2843          * initializing procedure here.
2844          */
2845         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2846                 dev_warn(dev->ctrl.device,
2847                         "failed to mark controller CONNECTING\n");
2848                 result = -EBUSY;
2849                 goto out;
2850         }
2851
2852         /*
2853          * We do not support an SGL for metadata (yet), so we are limited to a
2854          * single integrity segment for the separate metadata pointer.
2855          */
2856         dev->ctrl.max_integrity_segments = 1;
2857
2858         result = nvme_init_ctrl_finish(&dev->ctrl);
2859         if (result)
2860                 goto out;
2861
2862         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2863                 if (!dev->ctrl.opal_dev)
2864                         dev->ctrl.opal_dev =
2865                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2866                 else if (was_suspend)
2867                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2868         } else {
2869                 free_opal_dev(dev->ctrl.opal_dev);
2870                 dev->ctrl.opal_dev = NULL;
2871         }
2872
2873         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2874                 result = nvme_dbbuf_dma_alloc(dev);
2875                 if (result)
2876                         dev_warn(dev->dev,
2877                                  "unable to allocate dma for dbbuf\n");
2878         }
2879
2880         if (dev->ctrl.hmpre) {
2881                 result = nvme_setup_host_mem(dev);
2882                 if (result < 0)
2883                         goto out;
2884         }
2885
2886         result = nvme_setup_io_queues(dev);
2887         if (result)
2888                 goto out;
2889
2890         /*
2891          * Keep the controller around but remove all namespaces if we don't have
2892          * any working I/O queue.
2893          */
2894         if (dev->online_queues < 2) {
2895                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2896                 nvme_kill_queues(&dev->ctrl);
2897                 nvme_remove_namespaces(&dev->ctrl);
2898                 nvme_free_tagset(dev);
2899         } else {
2900                 nvme_start_queues(&dev->ctrl);
2901                 nvme_wait_freeze(&dev->ctrl);
2902                 nvme_dev_add(dev);
2903                 nvme_unfreeze(&dev->ctrl);
2904         }
2905
2906         /*
2907          * If only admin queue live, keep it to do further investigation or
2908          * recovery.
2909          */
2910         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2911                 dev_warn(dev->ctrl.device,
2912                         "failed to mark controller live state\n");
2913                 result = -ENODEV;
2914                 goto out;
2915         }
2916
2917         if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2918                         &nvme_pci_attr_group))
2919                 dev->attrs_added = true;
2920
2921         nvme_start_ctrl(&dev->ctrl);
2922         return;
2923
2924  out_unlock:
2925         mutex_unlock(&dev->shutdown_lock);
2926  out:
2927         if (result)
2928                 dev_warn(dev->ctrl.device,
2929                          "Removing after probe failure status: %d\n", result);
2930         nvme_remove_dead_ctrl(dev);
2931 }
2932
2933 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2934 {
2935         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2936         struct pci_dev *pdev = to_pci_dev(dev->dev);
2937
2938         if (pci_get_drvdata(pdev))
2939                 device_release_driver(&pdev->dev);
2940         nvme_put_ctrl(&dev->ctrl);
2941 }
2942
2943 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2944 {
2945         *val = readl(to_nvme_dev(ctrl)->bar + off);
2946         return 0;
2947 }
2948
2949 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2950 {
2951         writel(val, to_nvme_dev(ctrl)->bar + off);
2952         return 0;
2953 }
2954
2955 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2956 {
2957         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2958         return 0;
2959 }
2960
2961 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2962 {
2963         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2964
2965         return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2966 }
2967
2968 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2969         .name                   = "pcie",
2970         .module                 = THIS_MODULE,
2971         .flags                  = NVME_F_METADATA_SUPPORTED |
2972                                   NVME_F_PCI_P2PDMA,
2973         .reg_read32             = nvme_pci_reg_read32,
2974         .reg_write32            = nvme_pci_reg_write32,
2975         .reg_read64             = nvme_pci_reg_read64,
2976         .free_ctrl              = nvme_pci_free_ctrl,
2977         .submit_async_event     = nvme_pci_submit_async_event,
2978         .get_address            = nvme_pci_get_address,
2979 };
2980
2981 static int nvme_dev_map(struct nvme_dev *dev)
2982 {
2983         struct pci_dev *pdev = to_pci_dev(dev->dev);
2984
2985         if (pci_request_mem_regions(pdev, "nvme"))
2986                 return -ENODEV;
2987
2988         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2989                 goto release;
2990
2991         return 0;
2992   release:
2993         pci_release_mem_regions(pdev);
2994         return -ENODEV;
2995 }
2996
2997 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2998 {
2999         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3000                 /*
3001                  * Several Samsung devices seem to drop off the PCIe bus
3002                  * randomly when APST is on and uses the deepest sleep state.
3003                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3004                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3005                  * 950 PRO 256GB", but it seems to be restricted to two Dell
3006                  * laptops.
3007                  */
3008                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3009                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3010                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3011                         return NVME_QUIRK_NO_DEEPEST_PS;
3012         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3013                 /*
3014                  * Samsung SSD 960 EVO drops off the PCIe bus after system
3015                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3016                  * within few minutes after bootup on a Coffee Lake board -
3017                  * ASUS PRIME Z370-A
3018                  */
3019                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
3020                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3021                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
3022                         return NVME_QUIRK_NO_APST;
3023         } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3024                     pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3025                    (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3026                 /*
3027                  * Forcing to use host managed nvme power settings for
3028                  * lowest idle power with quick resume latency on
3029                  * Samsung and Toshiba SSDs based on suspend behavior
3030                  * on Coffee Lake board for LENOVO C640
3031                  */
3032                 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3033                      dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3034                         return NVME_QUIRK_SIMPLE_SUSPEND;
3035         }
3036
3037         return 0;
3038 }
3039
3040 static void nvme_async_probe(void *data, async_cookie_t cookie)
3041 {
3042         struct nvme_dev *dev = data;
3043
3044         flush_work(&dev->ctrl.reset_work);
3045         flush_work(&dev->ctrl.scan_work);
3046         nvme_put_ctrl(&dev->ctrl);
3047 }
3048
3049 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3050 {
3051         int node, result = -ENOMEM;
3052         struct nvme_dev *dev;
3053         unsigned long quirks = id->driver_data;
3054         size_t alloc_size;
3055
3056         node = dev_to_node(&pdev->dev);
3057         if (node == NUMA_NO_NODE)
3058                 set_dev_node(&pdev->dev, first_memory_node);
3059
3060         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3061         if (!dev)
3062                 return -ENOMEM;
3063
3064         dev->nr_write_queues = write_queues;
3065         dev->nr_poll_queues = poll_queues;
3066         dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3067         dev->queues = kcalloc_node(dev->nr_allocated_queues,
3068                         sizeof(struct nvme_queue), GFP_KERNEL, node);
3069         if (!dev->queues)
3070                 goto free;
3071
3072         dev->dev = get_device(&pdev->dev);
3073         pci_set_drvdata(pdev, dev);
3074
3075         result = nvme_dev_map(dev);
3076         if (result)
3077                 goto put_pci;
3078
3079         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
3080         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
3081         mutex_init(&dev->shutdown_lock);
3082
3083         result = nvme_setup_prp_pools(dev);
3084         if (result)
3085                 goto unmap;
3086
3087         quirks |= check_vendor_combination_bug(pdev);
3088
3089         if (!noacpi && acpi_storage_d3(&pdev->dev)) {
3090                 /*
3091                  * Some systems use a bios work around to ask for D3 on
3092                  * platforms that support kernel managed suspend.
3093                  */
3094                 dev_info(&pdev->dev,
3095                          "platform quirk: setting simple suspend\n");
3096                 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3097         }
3098
3099         /*
3100          * Double check that our mempool alloc size will cover the biggest
3101          * command we support.
3102          */
3103         alloc_size = nvme_pci_iod_alloc_size();
3104         WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3105
3106         dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3107                                                 mempool_kfree,
3108                                                 (void *) alloc_size,
3109                                                 GFP_KERNEL, node);
3110         if (!dev->iod_mempool) {
3111                 result = -ENOMEM;
3112                 goto release_pools;
3113         }
3114
3115         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3116                         quirks);
3117         if (result)
3118                 goto release_mempool;
3119
3120         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3121
3122         nvme_reset_ctrl(&dev->ctrl);
3123         async_schedule(nvme_async_probe, dev);
3124
3125         return 0;
3126
3127  release_mempool:
3128         mempool_destroy(dev->iod_mempool);
3129  release_pools:
3130         nvme_release_prp_pools(dev);
3131  unmap:
3132         nvme_dev_unmap(dev);
3133  put_pci:
3134         put_device(dev->dev);
3135  free:
3136         kfree(dev->queues);
3137         kfree(dev);
3138         return result;
3139 }
3140
3141 static void nvme_reset_prepare(struct pci_dev *pdev)
3142 {
3143         struct nvme_dev *dev = pci_get_drvdata(pdev);
3144
3145         /*
3146          * We don't need to check the return value from waiting for the reset
3147          * state as pci_dev device lock is held, making it impossible to race
3148          * with ->remove().
3149          */
3150         nvme_disable_prepare_reset(dev, false);
3151         nvme_sync_queues(&dev->ctrl);
3152 }
3153
3154 static void nvme_reset_done(struct pci_dev *pdev)
3155 {
3156         struct nvme_dev *dev = pci_get_drvdata(pdev);
3157
3158         if (!nvme_try_sched_reset(&dev->ctrl))
3159                 flush_work(&dev->ctrl.reset_work);
3160 }
3161
3162 static void nvme_shutdown(struct pci_dev *pdev)
3163 {
3164         struct nvme_dev *dev = pci_get_drvdata(pdev);
3165
3166         nvme_disable_prepare_reset(dev, true);
3167 }
3168
3169 static void nvme_remove_attrs(struct nvme_dev *dev)
3170 {
3171         if (dev->attrs_added)
3172                 sysfs_remove_group(&dev->ctrl.device->kobj,
3173                                    &nvme_pci_attr_group);
3174 }
3175
3176 /*
3177  * The driver's remove may be called on a device in a partially initialized
3178  * state. This function must not have any dependencies on the device state in
3179  * order to proceed.
3180  */
3181 static void nvme_remove(struct pci_dev *pdev)
3182 {
3183         struct nvme_dev *dev = pci_get_drvdata(pdev);
3184
3185         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3186         pci_set_drvdata(pdev, NULL);
3187
3188         if (!pci_device_is_present(pdev)) {
3189                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3190                 nvme_dev_disable(dev, true);
3191         }
3192
3193         flush_work(&dev->ctrl.reset_work);
3194         nvme_stop_ctrl(&dev->ctrl);
3195         nvme_remove_namespaces(&dev->ctrl);
3196         nvme_dev_disable(dev, true);
3197         nvme_remove_attrs(dev);
3198         nvme_free_host_mem(dev);
3199         nvme_dev_remove_admin(dev);
3200         nvme_free_queues(dev, 0);
3201         nvme_release_prp_pools(dev);
3202         nvme_dev_unmap(dev);
3203         nvme_uninit_ctrl(&dev->ctrl);
3204 }
3205
3206 #ifdef CONFIG_PM_SLEEP
3207 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3208 {
3209         return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3210 }
3211
3212 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3213 {
3214         return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3215 }
3216
3217 static int nvme_resume(struct device *dev)
3218 {
3219         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3220         struct nvme_ctrl *ctrl = &ndev->ctrl;
3221
3222         if (ndev->last_ps == U32_MAX ||
3223             nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3224                 goto reset;
3225         if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3226                 goto reset;
3227
3228         return 0;
3229 reset:
3230         return nvme_try_sched_reset(ctrl);
3231 }
3232
3233 static int nvme_suspend(struct device *dev)
3234 {
3235         struct pci_dev *pdev = to_pci_dev(dev);
3236         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3237         struct nvme_ctrl *ctrl = &ndev->ctrl;
3238         int ret = -EBUSY;
3239
3240         ndev->last_ps = U32_MAX;
3241
3242         /*
3243          * The platform does not remove power for a kernel managed suspend so
3244          * use host managed nvme power settings for lowest idle power if
3245          * possible. This should have quicker resume latency than a full device
3246          * shutdown.  But if the firmware is involved after the suspend or the
3247          * device does not support any non-default power states, shut down the
3248          * device fully.
3249          *
3250          * If ASPM is not enabled for the device, shut down the device and allow
3251          * the PCI bus layer to put it into D3 in order to take the PCIe link
3252          * down, so as to allow the platform to achieve its minimum low-power
3253          * state (which may not be possible if the link is up).
3254          */
3255         if (pm_suspend_via_firmware() || !ctrl->npss ||
3256             !pcie_aspm_enabled(pdev) ||
3257             (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3258                 return nvme_disable_prepare_reset(ndev, true);
3259
3260         nvme_start_freeze(ctrl);
3261         nvme_wait_freeze(ctrl);
3262         nvme_sync_queues(ctrl);
3263
3264         if (ctrl->state != NVME_CTRL_LIVE)
3265                 goto unfreeze;
3266
3267         /*
3268          * Host memory access may not be successful in a system suspend state,
3269          * but the specification allows the controller to access memory in a
3270          * non-operational power state.
3271          */
3272         if (ndev->hmb) {
3273                 ret = nvme_set_host_mem(ndev, 0);
3274                 if (ret < 0)
3275                         goto unfreeze;
3276         }
3277
3278         ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3279         if (ret < 0)
3280                 goto unfreeze;
3281
3282         /*
3283          * A saved state prevents pci pm from generically controlling the
3284          * device's power. If we're using protocol specific settings, we don't
3285          * want pci interfering.
3286          */
3287         pci_save_state(pdev);
3288
3289         ret = nvme_set_power_state(ctrl, ctrl->npss);
3290         if (ret < 0)
3291                 goto unfreeze;
3292
3293         if (ret) {
3294                 /* discard the saved state */
3295                 pci_load_saved_state(pdev, NULL);
3296
3297                 /*
3298                  * Clearing npss forces a controller reset on resume. The
3299                  * correct value will be rediscovered then.
3300                  */
3301                 ret = nvme_disable_prepare_reset(ndev, true);
3302                 ctrl->npss = 0;
3303         }
3304 unfreeze:
3305         nvme_unfreeze(ctrl);
3306         return ret;
3307 }
3308
3309 static int nvme_simple_suspend(struct device *dev)
3310 {
3311         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3312
3313         return nvme_disable_prepare_reset(ndev, true);
3314 }
3315
3316 static int nvme_simple_resume(struct device *dev)
3317 {
3318         struct pci_dev *pdev = to_pci_dev(dev);
3319         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3320
3321         return nvme_try_sched_reset(&ndev->ctrl);
3322 }
3323
3324 static const struct dev_pm_ops nvme_dev_pm_ops = {
3325         .suspend        = nvme_suspend,
3326         .resume         = nvme_resume,
3327         .freeze         = nvme_simple_suspend,
3328         .thaw           = nvme_simple_resume,
3329         .poweroff       = nvme_simple_suspend,
3330         .restore        = nvme_simple_resume,
3331 };
3332 #endif /* CONFIG_PM_SLEEP */
3333
3334 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3335                                                 pci_channel_state_t state)
3336 {
3337         struct nvme_dev *dev = pci_get_drvdata(pdev);
3338
3339         /*
3340          * A frozen channel requires a reset. When detected, this method will
3341          * shutdown the controller to quiesce. The controller will be restarted
3342          * after the slot reset through driver's slot_reset callback.
3343          */
3344         switch (state) {
3345         case pci_channel_io_normal:
3346                 return PCI_ERS_RESULT_CAN_RECOVER;
3347         case pci_channel_io_frozen:
3348                 dev_warn(dev->ctrl.device,
3349                         "frozen state error detected, reset controller\n");
3350                 nvme_dev_disable(dev, false);
3351                 return PCI_ERS_RESULT_NEED_RESET;
3352         case pci_channel_io_perm_failure:
3353                 dev_warn(dev->ctrl.device,
3354                         "failure state error detected, request disconnect\n");
3355                 return PCI_ERS_RESULT_DISCONNECT;
3356         }
3357         return PCI_ERS_RESULT_NEED_RESET;
3358 }
3359
3360 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3361 {
3362         struct nvme_dev *dev = pci_get_drvdata(pdev);
3363
3364         dev_info(dev->ctrl.device, "restart after slot reset\n");
3365         pci_restore_state(pdev);
3366         nvme_reset_ctrl(&dev->ctrl);
3367         return PCI_ERS_RESULT_RECOVERED;
3368 }
3369
3370 static void nvme_error_resume(struct pci_dev *pdev)
3371 {
3372         struct nvme_dev *dev = pci_get_drvdata(pdev);
3373
3374         flush_work(&dev->ctrl.reset_work);
3375 }
3376
3377 static const struct pci_error_handlers nvme_err_handler = {
3378         .error_detected = nvme_error_detected,
3379         .slot_reset     = nvme_slot_reset,
3380         .resume         = nvme_error_resume,
3381         .reset_prepare  = nvme_reset_prepare,
3382         .reset_done     = nvme_reset_done,
3383 };
3384
3385 static const struct pci_device_id nvme_id_table[] = {
3386         { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3387                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3388                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3389         { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3390                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3391                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3392         { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3393                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3394                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3395         { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3396                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3397                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3398         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3399                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3400                                 NVME_QUIRK_MEDIUM_PRIO_SQ |
3401                                 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3402                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3403         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3404                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3405         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3406                 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3407                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3408         { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3409                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3410         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3411                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3412                                 NVME_QUIRK_NO_NS_DESC_LIST, },
3413         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3414                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3415         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3416                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3417         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3418                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3419         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3420                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3421         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3422                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3423                                 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3424                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3425         { PCI_DEVICE(0x1987, 0x5016),   /* Phison E16 */
3426                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3427         { PCI_DEVICE(0x1b4b, 0x1092),   /* Lexar 256 GB SSD */
3428                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3429                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3430         { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3431                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3432         { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3433                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3434                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3435         { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3436                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3437         { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3438                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3439         { PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
3440                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3441         { PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3442                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3443         { PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3444                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3445         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3446                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3447         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3448                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3449         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3450                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3451         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3452                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3453         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3454                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3455         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3456                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3457         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3458                 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3459         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3460         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3461                 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3462                                 NVME_QUIRK_128_BYTES_SQES |
3463                                 NVME_QUIRK_SHARED_TAGS |
3464                                 NVME_QUIRK_SKIP_CID_GEN },
3465
3466         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3467         { 0, }
3468 };
3469 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3470
3471 static struct pci_driver nvme_driver = {
3472         .name           = "nvme",
3473         .id_table       = nvme_id_table,
3474         .probe          = nvme_probe,
3475         .remove         = nvme_remove,
3476         .shutdown       = nvme_shutdown,
3477 #ifdef CONFIG_PM_SLEEP
3478         .driver         = {
3479                 .pm     = &nvme_dev_pm_ops,
3480         },
3481 #endif
3482         .sriov_configure = pci_sriov_configure_simple,
3483         .err_handler    = &nvme_err_handler,
3484 };
3485
3486 static int __init nvme_init(void)
3487 {
3488         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3489         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3490         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3491         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3492
3493         return pci_register_driver(&nvme_driver);
3494 }
3495
3496 static void __exit nvme_exit(void)
3497 {
3498         pci_unregister_driver(&nvme_driver);
3499         flush_workqueue(nvme_wq);
3500 }
3501
3502 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3503 MODULE_LICENSE("GPL");
3504 MODULE_VERSION("1.0");
3505 module_init(nvme_init);
3506 module_exit(nvme_exit);