1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/once.h>
20 #include <linux/pci.h>
21 #include <linux/suspend.h>
22 #include <linux/t10-pi.h>
23 #include <linux/types.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/sed-opal.h>
26 #include <linux/pci-p2pdma.h>
31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
40 #define NVME_MAX_KB_SZ 4096
41 #define NVME_MAX_SEGS 127
43 static int use_threaded_interrupts;
44 module_param(use_threaded_interrupts, int, 0);
46 static bool use_cmb_sqes = true;
47 module_param(use_cmb_sqes, bool, 0444);
48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
50 static unsigned int max_host_mem_size_mb = 128;
51 module_param(max_host_mem_size_mb, uint, 0444);
52 MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
55 static unsigned int sgl_threshold = SZ_32K;
56 module_param(sgl_threshold, uint, 0644);
57 MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62 static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
67 static int io_queue_depth = 1024;
68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
71 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
76 ret = kstrtouint(val, 10, &n);
77 if (ret != 0 || n > num_possible_cpus())
79 return param_set_uint(val, kp);
82 static const struct kernel_param_ops io_queue_count_ops = {
83 .set = io_queue_count_set,
84 .get = param_get_uint,
87 static unsigned int write_queues;
88 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
89 MODULE_PARM_DESC(write_queues,
90 "Number of queues to use for writes. If not set, reads and writes "
91 "will share a queue set.");
93 static unsigned int poll_queues;
94 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
95 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
100 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
101 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
104 * Represents an NVM Express device. Each nvme_dev is a PCI function.
107 struct nvme_queue *queues;
108 struct blk_mq_tag_set tagset;
109 struct blk_mq_tag_set admin_tagset;
112 struct dma_pool *prp_page_pool;
113 struct dma_pool *prp_small_pool;
114 unsigned online_queues;
116 unsigned io_queues[HCTX_MAX_TYPES];
117 unsigned int num_vecs;
122 unsigned long bar_mapped_size;
123 struct work_struct remove_work;
124 struct mutex shutdown_lock;
130 struct nvme_ctrl ctrl;
133 mempool_t *iod_mempool;
135 /* shadow doorbell buffer support: */
137 dma_addr_t dbbuf_dbs_dma_addr;
139 dma_addr_t dbbuf_eis_dma_addr;
141 /* host memory buffer support: */
143 u32 nr_host_mem_descs;
144 dma_addr_t host_mem_descs_dma;
145 struct nvme_host_mem_buf_desc *host_mem_descs;
146 void **host_mem_desc_bufs;
147 unsigned int nr_allocated_queues;
148 unsigned int nr_write_queues;
149 unsigned int nr_poll_queues;
152 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
156 ret = kstrtoint(val, 10, &n);
157 if (ret != 0 || n < 2)
160 return param_set_int(val, kp);
163 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
165 return qid * 2 * stride;
168 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
170 return (qid * 2 + 1) * stride;
173 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
175 return container_of(ctrl, struct nvme_dev, ctrl);
179 * An NVM Express queue. Each device has at least two (one for admin
180 * commands and one for I/O commands).
183 struct nvme_dev *dev;
186 /* only used for poll queues: */
187 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
188 struct nvme_completion *cqes;
189 dma_addr_t sq_dma_addr;
190 dma_addr_t cq_dma_addr;
200 #define NVMEQ_ENABLED 0
201 #define NVMEQ_SQ_CMB 1
202 #define NVMEQ_DELETE_ERROR 2
203 #define NVMEQ_POLLED 3
208 struct completion delete_done;
212 * The nvme_iod describes the data in an I/O.
214 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
215 * to the actual struct scatterlist.
218 struct nvme_request req;
219 struct nvme_queue *nvmeq;
222 int npages; /* In the PRP list. 0 means small pool in use */
223 int nents; /* Used in scatterlist */
224 dma_addr_t first_dma;
225 unsigned int dma_len; /* length of single DMA segment mapping */
227 struct scatterlist *sg;
230 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
232 return dev->nr_allocated_queues * 8 * dev->db_stride;
235 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
237 unsigned int mem_size = nvme_dbbuf_size(dev);
242 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
243 &dev->dbbuf_dbs_dma_addr,
247 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
248 &dev->dbbuf_eis_dma_addr,
250 if (!dev->dbbuf_eis) {
251 dma_free_coherent(dev->dev, mem_size,
252 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
253 dev->dbbuf_dbs = NULL;
260 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
262 unsigned int mem_size = nvme_dbbuf_size(dev);
264 if (dev->dbbuf_dbs) {
265 dma_free_coherent(dev->dev, mem_size,
266 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
267 dev->dbbuf_dbs = NULL;
269 if (dev->dbbuf_eis) {
270 dma_free_coherent(dev->dev, mem_size,
271 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
272 dev->dbbuf_eis = NULL;
276 static void nvme_dbbuf_init(struct nvme_dev *dev,
277 struct nvme_queue *nvmeq, int qid)
279 if (!dev->dbbuf_dbs || !qid)
282 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
283 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
284 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
285 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
288 static void nvme_dbbuf_set(struct nvme_dev *dev)
290 struct nvme_command c;
295 memset(&c, 0, sizeof(c));
296 c.dbbuf.opcode = nvme_admin_dbbuf;
297 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
298 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
300 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
301 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
302 /* Free memory and continue on */
303 nvme_dbbuf_dma_free(dev);
307 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
309 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
312 /* Update dbbuf and return true if an MMIO is required */
313 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
314 volatile u32 *dbbuf_ei)
320 * Ensure that the queue is written before updating
321 * the doorbell in memory
325 old_value = *dbbuf_db;
329 * Ensure that the doorbell is updated before reading the event
330 * index from memory. The controller needs to provide similar
331 * ordering to ensure the envent index is updated before reading
336 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
344 * Will slightly overestimate the number of pages needed. This is OK
345 * as it only leads to a small amount of wasted memory for the lifetime of
348 static int nvme_npages(unsigned size, struct nvme_dev *dev)
350 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
351 dev->ctrl.page_size);
352 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
356 * Calculates the number of pages needed for the SGL segments. For example a 4k
357 * page can accommodate 256 SGL descriptors.
359 static int nvme_pci_npages_sgl(unsigned int num_seg)
361 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
364 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
365 unsigned int size, unsigned int nseg, bool use_sgl)
370 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
372 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
374 return alloc_size + sizeof(struct scatterlist) * nseg;
377 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
378 unsigned int hctx_idx)
380 struct nvme_dev *dev = data;
381 struct nvme_queue *nvmeq = &dev->queues[0];
383 WARN_ON(hctx_idx != 0);
384 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
386 hctx->driver_data = nvmeq;
390 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
391 unsigned int hctx_idx)
393 struct nvme_dev *dev = data;
394 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
396 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
397 hctx->driver_data = nvmeq;
401 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
402 unsigned int hctx_idx, unsigned int numa_node)
404 struct nvme_dev *dev = set->driver_data;
405 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
406 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
407 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
412 nvme_req(req)->ctrl = &dev->ctrl;
416 static int queue_irq_offset(struct nvme_dev *dev)
418 /* if we have more than 1 vec, admin queue offsets us by 1 */
419 if (dev->num_vecs > 1)
425 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
427 struct nvme_dev *dev = set->driver_data;
430 offset = queue_irq_offset(dev);
431 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
432 struct blk_mq_queue_map *map = &set->map[i];
434 map->nr_queues = dev->io_queues[i];
435 if (!map->nr_queues) {
436 BUG_ON(i == HCTX_TYPE_DEFAULT);
441 * The poll queue(s) doesn't have an IRQ (and hence IRQ
442 * affinity), so use the regular blk-mq cpu mapping
444 map->queue_offset = qoff;
445 if (i != HCTX_TYPE_POLL && offset)
446 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
448 blk_mq_map_queues(map);
449 qoff += map->nr_queues;
450 offset += map->nr_queues;
456 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq)
458 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
459 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
460 writel(nvmeq->sq_tail, nvmeq->q_db);
464 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
465 * @nvmeq: The queue to use
466 * @cmd: The command to send
467 * @write_sq: whether to write to the SQ doorbell
469 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
472 spin_lock(&nvmeq->sq_lock);
473 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
475 if (++nvmeq->sq_tail == nvmeq->q_depth)
478 nvme_write_sq_db(nvmeq);
479 spin_unlock(&nvmeq->sq_lock);
482 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
484 struct nvme_queue *nvmeq = hctx->driver_data;
486 spin_lock(&nvmeq->sq_lock);
487 nvme_write_sq_db(nvmeq);
488 spin_unlock(&nvmeq->sq_lock);
491 static void **nvme_pci_iod_list(struct request *req)
493 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
494 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
497 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
499 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
500 int nseg = blk_rq_nr_phys_segments(req);
501 unsigned int avg_seg_size;
506 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
508 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
510 if (!iod->nvmeq->qid)
512 if (!sgl_threshold || avg_seg_size < sgl_threshold)
517 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
519 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
520 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
521 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
525 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
530 WARN_ON_ONCE(!iod->nents);
532 if (is_pci_p2pdma_page(sg_page(iod->sg)))
533 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
536 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
539 if (iod->npages == 0)
540 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
543 for (i = 0; i < iod->npages; i++) {
544 void *addr = nvme_pci_iod_list(req)[i];
547 struct nvme_sgl_desc *sg_list = addr;
550 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
552 __le64 *prp_list = addr;
554 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
557 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
558 dma_addr = next_dma_addr;
561 mempool_free(iod->sg, dev->iod_mempool);
564 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
567 struct scatterlist *sg;
569 for_each_sg(sgl, sg, nents, i) {
570 dma_addr_t phys = sg_phys(sg);
571 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
572 "dma_address:%pad dma_length:%d\n",
573 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
578 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
579 struct request *req, struct nvme_rw_command *cmnd)
581 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
582 struct dma_pool *pool;
583 int length = blk_rq_payload_bytes(req);
584 struct scatterlist *sg = iod->sg;
585 int dma_len = sg_dma_len(sg);
586 u64 dma_addr = sg_dma_address(sg);
587 u32 page_size = dev->ctrl.page_size;
588 int offset = dma_addr & (page_size - 1);
590 void **list = nvme_pci_iod_list(req);
594 length -= (page_size - offset);
600 dma_len -= (page_size - offset);
602 dma_addr += (page_size - offset);
605 dma_addr = sg_dma_address(sg);
606 dma_len = sg_dma_len(sg);
609 if (length <= page_size) {
610 iod->first_dma = dma_addr;
614 nprps = DIV_ROUND_UP(length, page_size);
615 if (nprps <= (256 / 8)) {
616 pool = dev->prp_small_pool;
619 pool = dev->prp_page_pool;
623 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
625 iod->first_dma = dma_addr;
627 return BLK_STS_RESOURCE;
630 iod->first_dma = prp_dma;
633 if (i == page_size >> 3) {
634 __le64 *old_prp_list = prp_list;
635 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
637 return BLK_STS_RESOURCE;
638 list[iod->npages++] = prp_list;
639 prp_list[0] = old_prp_list[i - 1];
640 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
643 prp_list[i++] = cpu_to_le64(dma_addr);
644 dma_len -= page_size;
645 dma_addr += page_size;
651 if (unlikely(dma_len < 0))
654 dma_addr = sg_dma_address(sg);
655 dma_len = sg_dma_len(sg);
659 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
660 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
665 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
666 "Invalid SGL for payload:%d nents:%d\n",
667 blk_rq_payload_bytes(req), iod->nents);
668 return BLK_STS_IOERR;
671 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
672 struct scatterlist *sg)
674 sge->addr = cpu_to_le64(sg_dma_address(sg));
675 sge->length = cpu_to_le32(sg_dma_len(sg));
676 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
679 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
680 dma_addr_t dma_addr, int entries)
682 sge->addr = cpu_to_le64(dma_addr);
683 if (entries < SGES_PER_PAGE) {
684 sge->length = cpu_to_le32(entries * sizeof(*sge));
685 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
687 sge->length = cpu_to_le32(PAGE_SIZE);
688 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
692 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
693 struct request *req, struct nvme_rw_command *cmd, int entries)
695 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
696 struct dma_pool *pool;
697 struct nvme_sgl_desc *sg_list;
698 struct scatterlist *sg = iod->sg;
702 /* setting the transfer type as SGL */
703 cmd->flags = NVME_CMD_SGL_METABUF;
706 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
710 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
711 pool = dev->prp_small_pool;
714 pool = dev->prp_page_pool;
718 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
721 return BLK_STS_RESOURCE;
724 nvme_pci_iod_list(req)[0] = sg_list;
725 iod->first_dma = sgl_dma;
727 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
730 if (i == SGES_PER_PAGE) {
731 struct nvme_sgl_desc *old_sg_desc = sg_list;
732 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
734 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
736 return BLK_STS_RESOURCE;
739 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
740 sg_list[i++] = *link;
741 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
744 nvme_pci_sgl_set_data(&sg_list[i++], sg);
746 } while (--entries > 0);
751 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
752 struct request *req, struct nvme_rw_command *cmnd,
755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
756 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1);
757 unsigned int first_prp_len = dev->ctrl.page_size - offset;
759 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
760 if (dma_mapping_error(dev->dev, iod->first_dma))
761 return BLK_STS_RESOURCE;
762 iod->dma_len = bv->bv_len;
764 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
765 if (bv->bv_len > first_prp_len)
766 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
770 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
771 struct request *req, struct nvme_rw_command *cmnd,
774 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
776 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
777 if (dma_mapping_error(dev->dev, iod->first_dma))
778 return BLK_STS_RESOURCE;
779 iod->dma_len = bv->bv_len;
781 cmnd->flags = NVME_CMD_SGL_METABUF;
782 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
783 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
784 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
788 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
789 struct nvme_command *cmnd)
791 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
792 blk_status_t ret = BLK_STS_RESOURCE;
795 if (blk_rq_nr_phys_segments(req) == 1) {
796 struct bio_vec bv = req_bvec(req);
798 if (!is_pci_p2pdma_page(bv.bv_page)) {
799 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
800 return nvme_setup_prp_simple(dev, req,
803 if (iod->nvmeq->qid &&
804 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
805 return nvme_setup_sgl_simple(dev, req,
811 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
813 return BLK_STS_RESOURCE;
814 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
815 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
819 if (is_pci_p2pdma_page(sg_page(iod->sg)))
820 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
821 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
823 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
824 rq_dma_dir(req), DMA_ATTR_NO_WARN);
828 iod->use_sgl = nvme_pci_use_sgls(dev, req);
830 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
832 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
834 if (ret != BLK_STS_OK)
835 nvme_unmap_data(dev, req);
839 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
840 struct nvme_command *cmnd)
842 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
844 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
846 if (dma_mapping_error(dev->dev, iod->meta_dma))
847 return BLK_STS_IOERR;
848 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
853 * NOTE: ns is NULL when called on the admin queue.
855 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
856 const struct blk_mq_queue_data *bd)
858 struct nvme_ns *ns = hctx->queue->queuedata;
859 struct nvme_queue *nvmeq = hctx->driver_data;
860 struct nvme_dev *dev = nvmeq->dev;
861 struct request *req = bd->rq;
862 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
863 struct nvme_command cmnd;
871 * We should not need to do this, but we're still using this to
872 * ensure we can drain requests on a dying queue.
874 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
875 return BLK_STS_IOERR;
877 ret = nvme_setup_cmd(ns, req, &cmnd);
881 if (blk_rq_nr_phys_segments(req)) {
882 ret = nvme_map_data(dev, req, &cmnd);
887 if (blk_integrity_rq(req)) {
888 ret = nvme_map_metadata(dev, req, &cmnd);
893 blk_mq_start_request(req);
894 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
897 nvme_unmap_data(dev, req);
899 nvme_cleanup_cmd(req);
903 static void nvme_pci_complete_rq(struct request *req)
905 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
906 struct nvme_dev *dev = iod->nvmeq->dev;
908 if (blk_integrity_rq(req))
909 dma_unmap_page(dev->dev, iod->meta_dma,
910 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
911 if (blk_rq_nr_phys_segments(req))
912 nvme_unmap_data(dev, req);
913 nvme_complete_rq(req);
916 /* We read the CQE phase first to check if the rest of the entry is valid */
917 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
919 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
921 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
924 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
926 u16 head = nvmeq->cq_head;
928 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
930 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
933 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
936 return nvmeq->dev->admin_tagset.tags[0];
937 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
940 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
942 struct nvme_completion *cqe = &nvmeq->cqes[idx];
945 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
946 dev_warn(nvmeq->dev->ctrl.device,
947 "invalid id %d completed on queue %d\n",
948 cqe->command_id, le16_to_cpu(cqe->sq_id));
953 * AEN requests are special as they don't time out and can
954 * survive any kind of queue freeze and often don't respond to
955 * aborts. We don't even bother to allocate a struct request
956 * for them but rather special case them here.
958 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
959 nvme_complete_async_event(&nvmeq->dev->ctrl,
960 cqe->status, &cqe->result);
964 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
965 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
966 nvme_end_request(req, cqe->status, cqe->result);
969 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
971 u16 tmp = nvmeq->cq_head + 1;
973 if (tmp == nvmeq->q_depth) {
975 nvmeq->cq_phase ^= 1;
977 nvmeq->cq_head = tmp;
981 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
985 while (nvme_cqe_pending(nvmeq)) {
988 * load-load control dependency between phase and the rest of
989 * the cqe requires a full read memory barrier
992 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
993 nvme_update_cq_head(nvmeq);
997 nvme_ring_cq_doorbell(nvmeq);
1001 static irqreturn_t nvme_irq(int irq, void *data)
1003 struct nvme_queue *nvmeq = data;
1004 irqreturn_t ret = IRQ_NONE;
1007 * The rmb/wmb pair ensures we see all updates from a previous run of
1008 * the irq handler, even if that was on another CPU.
1011 if (nvme_process_cq(nvmeq))
1018 static irqreturn_t nvme_irq_check(int irq, void *data)
1020 struct nvme_queue *nvmeq = data;
1021 if (nvme_cqe_pending(nvmeq))
1022 return IRQ_WAKE_THREAD;
1027 * Poll for completions for any interrupt driven queue
1028 * Can be called from any context.
1030 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1032 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1034 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1036 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1037 nvme_process_cq(nvmeq);
1038 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1041 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1043 struct nvme_queue *nvmeq = hctx->driver_data;
1046 if (!nvme_cqe_pending(nvmeq))
1049 spin_lock(&nvmeq->cq_poll_lock);
1050 found = nvme_process_cq(nvmeq);
1051 spin_unlock(&nvmeq->cq_poll_lock);
1056 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1058 struct nvme_dev *dev = to_nvme_dev(ctrl);
1059 struct nvme_queue *nvmeq = &dev->queues[0];
1060 struct nvme_command c;
1062 memset(&c, 0, sizeof(c));
1063 c.common.opcode = nvme_admin_async_event;
1064 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1065 nvme_submit_cmd(nvmeq, &c, true);
1068 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1070 struct nvme_command c;
1072 memset(&c, 0, sizeof(c));
1073 c.delete_queue.opcode = opcode;
1074 c.delete_queue.qid = cpu_to_le16(id);
1076 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1079 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1080 struct nvme_queue *nvmeq, s16 vector)
1082 struct nvme_command c;
1083 int flags = NVME_QUEUE_PHYS_CONTIG;
1085 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1086 flags |= NVME_CQ_IRQ_ENABLED;
1089 * Note: we (ab)use the fact that the prp fields survive if no data
1090 * is attached to the request.
1092 memset(&c, 0, sizeof(c));
1093 c.create_cq.opcode = nvme_admin_create_cq;
1094 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1095 c.create_cq.cqid = cpu_to_le16(qid);
1096 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1097 c.create_cq.cq_flags = cpu_to_le16(flags);
1098 c.create_cq.irq_vector = cpu_to_le16(vector);
1100 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1103 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1104 struct nvme_queue *nvmeq)
1106 struct nvme_ctrl *ctrl = &dev->ctrl;
1107 struct nvme_command c;
1108 int flags = NVME_QUEUE_PHYS_CONTIG;
1111 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1112 * set. Since URGENT priority is zeroes, it makes all queues
1115 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1116 flags |= NVME_SQ_PRIO_MEDIUM;
1119 * Note: we (ab)use the fact that the prp fields survive if no data
1120 * is attached to the request.
1122 memset(&c, 0, sizeof(c));
1123 c.create_sq.opcode = nvme_admin_create_sq;
1124 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1125 c.create_sq.sqid = cpu_to_le16(qid);
1126 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1127 c.create_sq.sq_flags = cpu_to_le16(flags);
1128 c.create_sq.cqid = cpu_to_le16(qid);
1130 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1133 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1135 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1138 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1140 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1143 static void abort_endio(struct request *req, blk_status_t error)
1145 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1146 struct nvme_queue *nvmeq = iod->nvmeq;
1148 dev_warn(nvmeq->dev->ctrl.device,
1149 "Abort status: 0x%x", nvme_req(req)->status);
1150 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1151 blk_mq_free_request(req);
1154 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1157 /* If true, indicates loss of adapter communication, possibly by a
1158 * NVMe Subsystem reset.
1160 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1162 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1163 switch (dev->ctrl.state) {
1164 case NVME_CTRL_RESETTING:
1165 case NVME_CTRL_CONNECTING:
1171 /* We shouldn't reset unless the controller is on fatal error state
1172 * _or_ if we lost the communication with it.
1174 if (!(csts & NVME_CSTS_CFS) && !nssro)
1180 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1182 /* Read a config register to help see what died. */
1186 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1188 if (result == PCIBIOS_SUCCESSFUL)
1189 dev_warn(dev->ctrl.device,
1190 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1193 dev_warn(dev->ctrl.device,
1194 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1198 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1200 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1201 struct nvme_queue *nvmeq = iod->nvmeq;
1202 struct nvme_dev *dev = nvmeq->dev;
1203 struct request *abort_req;
1204 struct nvme_command cmd;
1205 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1207 /* If PCI error recovery process is happening, we cannot reset or
1208 * the recovery mechanism will surely fail.
1211 if (pci_channel_offline(to_pci_dev(dev->dev)))
1212 return BLK_EH_RESET_TIMER;
1215 * Reset immediately if the controller is failed
1217 if (nvme_should_reset(dev, csts)) {
1218 nvme_warn_reset(dev, csts);
1219 nvme_dev_disable(dev, false);
1220 nvme_reset_ctrl(&dev->ctrl);
1225 * Did we miss an interrupt?
1227 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1228 nvme_poll(req->mq_hctx);
1230 nvme_poll_irqdisable(nvmeq);
1232 if (blk_mq_request_completed(req)) {
1233 dev_warn(dev->ctrl.device,
1234 "I/O %d QID %d timeout, completion polled\n",
1235 req->tag, nvmeq->qid);
1240 * Shutdown immediately if controller times out while starting. The
1241 * reset work will see the pci device disabled when it gets the forced
1242 * cancellation error. All outstanding requests are completed on
1243 * shutdown, so we return BLK_EH_DONE.
1245 switch (dev->ctrl.state) {
1246 case NVME_CTRL_CONNECTING:
1247 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1249 case NVME_CTRL_DELETING:
1250 dev_warn_ratelimited(dev->ctrl.device,
1251 "I/O %d QID %d timeout, disable controller\n",
1252 req->tag, nvmeq->qid);
1253 nvme_dev_disable(dev, true);
1254 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1256 case NVME_CTRL_RESETTING:
1257 return BLK_EH_RESET_TIMER;
1263 * Shutdown the controller immediately and schedule a reset if the
1264 * command was already aborted once before and still hasn't been
1265 * returned to the driver, or if this is the admin queue.
1267 if (!nvmeq->qid || iod->aborted) {
1268 dev_warn(dev->ctrl.device,
1269 "I/O %d QID %d timeout, reset controller\n",
1270 req->tag, nvmeq->qid);
1271 nvme_dev_disable(dev, false);
1272 nvme_reset_ctrl(&dev->ctrl);
1274 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1278 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1279 atomic_inc(&dev->ctrl.abort_limit);
1280 return BLK_EH_RESET_TIMER;
1284 memset(&cmd, 0, sizeof(cmd));
1285 cmd.abort.opcode = nvme_admin_abort_cmd;
1286 cmd.abort.cid = req->tag;
1287 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1289 dev_warn(nvmeq->dev->ctrl.device,
1290 "I/O %d QID %d timeout, aborting\n",
1291 req->tag, nvmeq->qid);
1293 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1294 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1295 if (IS_ERR(abort_req)) {
1296 atomic_inc(&dev->ctrl.abort_limit);
1297 return BLK_EH_RESET_TIMER;
1300 abort_req->timeout = ADMIN_TIMEOUT;
1301 abort_req->end_io_data = NULL;
1302 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1305 * The aborted req will be completed on receiving the abort req.
1306 * We enable the timer again. If hit twice, it'll cause a device reset,
1307 * as the device then is in a faulty state.
1309 return BLK_EH_RESET_TIMER;
1312 static void nvme_free_queue(struct nvme_queue *nvmeq)
1314 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1315 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1316 if (!nvmeq->sq_cmds)
1319 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1320 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1321 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1323 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1324 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1328 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1332 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1333 dev->ctrl.queue_count--;
1334 nvme_free_queue(&dev->queues[i]);
1339 * nvme_suspend_queue - put queue into suspended state
1340 * @nvmeq: queue to suspend
1342 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1344 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1347 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1350 nvmeq->dev->online_queues--;
1351 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1352 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1353 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1354 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1358 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1362 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1363 nvme_suspend_queue(&dev->queues[i]);
1366 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1368 struct nvme_queue *nvmeq = &dev->queues[0];
1371 nvme_shutdown_ctrl(&dev->ctrl);
1373 nvme_disable_ctrl(&dev->ctrl);
1375 nvme_poll_irqdisable(nvmeq);
1379 * Called only on a device that has been disabled and after all other threads
1380 * that can check this device's completion queues have synced, except
1381 * nvme_poll(). This is the last chance for the driver to see a natural
1382 * completion before nvme_cancel_request() terminates all incomplete requests.
1384 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1388 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1389 spin_lock(&dev->queues[i].cq_poll_lock);
1390 nvme_process_cq(&dev->queues[i]);
1391 spin_unlock(&dev->queues[i].cq_poll_lock);
1395 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1398 int q_depth = dev->q_depth;
1399 unsigned q_size_aligned = roundup(q_depth * entry_size,
1400 dev->ctrl.page_size);
1402 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1403 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1404 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1405 q_depth = div_u64(mem_per_q, entry_size);
1408 * Ensure the reduced q_depth is above some threshold where it
1409 * would be better to map queues in system memory with the
1419 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1422 struct pci_dev *pdev = to_pci_dev(dev->dev);
1424 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1425 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1426 if (nvmeq->sq_cmds) {
1427 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1429 if (nvmeq->sq_dma_addr) {
1430 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1434 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1438 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1439 &nvmeq->sq_dma_addr, GFP_KERNEL);
1440 if (!nvmeq->sq_cmds)
1445 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1447 struct nvme_queue *nvmeq = &dev->queues[qid];
1449 if (dev->ctrl.queue_count > qid)
1452 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1453 nvmeq->q_depth = depth;
1454 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1455 &nvmeq->cq_dma_addr, GFP_KERNEL);
1459 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1463 spin_lock_init(&nvmeq->sq_lock);
1464 spin_lock_init(&nvmeq->cq_poll_lock);
1466 nvmeq->cq_phase = 1;
1467 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1469 dev->ctrl.queue_count++;
1474 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1475 nvmeq->cq_dma_addr);
1480 static int queue_request_irq(struct nvme_queue *nvmeq)
1482 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1483 int nr = nvmeq->dev->ctrl.instance;
1485 if (use_threaded_interrupts) {
1486 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1487 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1489 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1490 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1494 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1496 struct nvme_dev *dev = nvmeq->dev;
1500 nvmeq->cq_phase = 1;
1501 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1502 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1503 nvme_dbbuf_init(dev, nvmeq, qid);
1504 dev->online_queues++;
1505 wmb(); /* ensure the first interrupt sees the initialization */
1508 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1510 struct nvme_dev *dev = nvmeq->dev;
1514 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1517 * A queue's vector matches the queue identifier unless the controller
1518 * has only one vector available.
1521 vector = dev->num_vecs == 1 ? 0 : qid;
1523 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1525 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1529 result = adapter_alloc_sq(dev, qid, nvmeq);
1535 nvmeq->cq_vector = vector;
1536 nvme_init_queue(nvmeq, qid);
1539 result = queue_request_irq(nvmeq);
1544 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1548 dev->online_queues--;
1549 adapter_delete_sq(dev, qid);
1551 adapter_delete_cq(dev, qid);
1555 static const struct blk_mq_ops nvme_mq_admin_ops = {
1556 .queue_rq = nvme_queue_rq,
1557 .complete = nvme_pci_complete_rq,
1558 .init_hctx = nvme_admin_init_hctx,
1559 .init_request = nvme_init_request,
1560 .timeout = nvme_timeout,
1563 static const struct blk_mq_ops nvme_mq_ops = {
1564 .queue_rq = nvme_queue_rq,
1565 .complete = nvme_pci_complete_rq,
1566 .commit_rqs = nvme_commit_rqs,
1567 .init_hctx = nvme_init_hctx,
1568 .init_request = nvme_init_request,
1569 .map_queues = nvme_pci_map_queues,
1570 .timeout = nvme_timeout,
1574 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1576 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1578 * If the controller was reset during removal, it's possible
1579 * user requests may be waiting on a stopped queue. Start the
1580 * queue to flush these to completion.
1582 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1583 blk_cleanup_queue(dev->ctrl.admin_q);
1584 blk_mq_free_tag_set(&dev->admin_tagset);
1588 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1590 if (!dev->ctrl.admin_q) {
1591 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1592 dev->admin_tagset.nr_hw_queues = 1;
1594 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1595 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1596 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1597 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1598 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1599 dev->admin_tagset.driver_data = dev;
1601 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1603 dev->ctrl.admin_tagset = &dev->admin_tagset;
1605 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1606 if (IS_ERR(dev->ctrl.admin_q)) {
1607 blk_mq_free_tag_set(&dev->admin_tagset);
1610 if (!blk_get_queue(dev->ctrl.admin_q)) {
1611 nvme_dev_remove_admin(dev);
1612 dev->ctrl.admin_q = NULL;
1616 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1621 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1623 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1626 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1628 struct pci_dev *pdev = to_pci_dev(dev->dev);
1630 if (size <= dev->bar_mapped_size)
1632 if (size > pci_resource_len(pdev, 0))
1636 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1638 dev->bar_mapped_size = 0;
1641 dev->bar_mapped_size = size;
1642 dev->dbs = dev->bar + NVME_REG_DBS;
1647 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1651 struct nvme_queue *nvmeq;
1653 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1657 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1658 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1660 if (dev->subsystem &&
1661 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1662 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1664 result = nvme_disable_ctrl(&dev->ctrl);
1668 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1672 dev->ctrl.numa_node = dev_to_node(dev->dev);
1674 nvmeq = &dev->queues[0];
1675 aqa = nvmeq->q_depth - 1;
1678 writel(aqa, dev->bar + NVME_REG_AQA);
1679 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1680 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1682 result = nvme_enable_ctrl(&dev->ctrl);
1686 nvmeq->cq_vector = 0;
1687 nvme_init_queue(nvmeq, 0);
1688 result = queue_request_irq(nvmeq);
1690 dev->online_queues--;
1694 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1698 static int nvme_create_io_queues(struct nvme_dev *dev)
1700 unsigned i, max, rw_queues;
1703 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1704 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1710 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1711 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1712 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1713 dev->io_queues[HCTX_TYPE_READ];
1718 for (i = dev->online_queues; i <= max; i++) {
1719 bool polled = i > rw_queues;
1721 ret = nvme_create_queue(&dev->queues[i], i, polled);
1727 * Ignore failing Create SQ/CQ commands, we can continue with less
1728 * than the desired amount of queues, and even a controller without
1729 * I/O queues can still be used to issue admin commands. This might
1730 * be useful to upgrade a buggy firmware for example.
1732 return ret >= 0 ? 0 : ret;
1735 static ssize_t nvme_cmb_show(struct device *dev,
1736 struct device_attribute *attr,
1739 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1741 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1742 ndev->cmbloc, ndev->cmbsz);
1744 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1746 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1748 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1750 return 1ULL << (12 + 4 * szu);
1753 static u32 nvme_cmb_size(struct nvme_dev *dev)
1755 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1758 static void nvme_map_cmb(struct nvme_dev *dev)
1761 resource_size_t bar_size;
1762 struct pci_dev *pdev = to_pci_dev(dev->dev);
1768 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1771 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1773 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1774 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1775 bar = NVME_CMB_BIR(dev->cmbloc);
1776 bar_size = pci_resource_len(pdev, bar);
1778 if (offset > bar_size)
1782 * Controllers may support a CMB size larger than their BAR,
1783 * for example, due to being behind a bridge. Reduce the CMB to
1784 * the reported size of the BAR
1786 if (size > bar_size - offset)
1787 size = bar_size - offset;
1789 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1790 dev_warn(dev->ctrl.device,
1791 "failed to register the CMB\n");
1795 dev->cmb_size = size;
1796 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1798 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1799 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1800 pci_p2pmem_publish(pdev, true);
1802 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1803 &dev_attr_cmb.attr, NULL))
1804 dev_warn(dev->ctrl.device,
1805 "failed to add sysfs attribute for CMB\n");
1808 static inline void nvme_release_cmb(struct nvme_dev *dev)
1810 if (dev->cmb_size) {
1811 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1812 &dev_attr_cmb.attr, NULL);
1817 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1819 u64 dma_addr = dev->host_mem_descs_dma;
1820 struct nvme_command c;
1823 memset(&c, 0, sizeof(c));
1824 c.features.opcode = nvme_admin_set_features;
1825 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1826 c.features.dword11 = cpu_to_le32(bits);
1827 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1828 ilog2(dev->ctrl.page_size));
1829 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1830 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1831 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1833 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1835 dev_warn(dev->ctrl.device,
1836 "failed to set host mem (err %d, flags %#x).\n",
1842 static void nvme_free_host_mem(struct nvme_dev *dev)
1846 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1847 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1848 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1850 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1851 le64_to_cpu(desc->addr),
1852 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1855 kfree(dev->host_mem_desc_bufs);
1856 dev->host_mem_desc_bufs = NULL;
1857 dma_free_coherent(dev->dev,
1858 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1859 dev->host_mem_descs, dev->host_mem_descs_dma);
1860 dev->host_mem_descs = NULL;
1861 dev->nr_host_mem_descs = 0;
1864 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1867 struct nvme_host_mem_buf_desc *descs;
1868 u32 max_entries, len;
1869 dma_addr_t descs_dma;
1874 tmp = (preferred + chunk_size - 1);
1875 do_div(tmp, chunk_size);
1878 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1879 max_entries = dev->ctrl.hmmaxd;
1881 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1882 &descs_dma, GFP_KERNEL);
1886 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1888 goto out_free_descs;
1890 for (size = 0; size < preferred && i < max_entries; size += len) {
1891 dma_addr_t dma_addr;
1893 len = min_t(u64, chunk_size, preferred - size);
1894 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1895 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1899 descs[i].addr = cpu_to_le64(dma_addr);
1900 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1907 dev->nr_host_mem_descs = i;
1908 dev->host_mem_size = size;
1909 dev->host_mem_descs = descs;
1910 dev->host_mem_descs_dma = descs_dma;
1911 dev->host_mem_desc_bufs = bufs;
1916 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1918 dma_free_attrs(dev->dev, size, bufs[i],
1919 le64_to_cpu(descs[i].addr),
1920 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1925 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1928 dev->host_mem_descs = NULL;
1932 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1936 /* start big and work our way down */
1937 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1938 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1940 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1941 if (!min || dev->host_mem_size >= min)
1943 nvme_free_host_mem(dev);
1950 static int nvme_setup_host_mem(struct nvme_dev *dev)
1952 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1953 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1954 u64 min = (u64)dev->ctrl.hmmin * 4096;
1955 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1958 preferred = min(preferred, max);
1960 dev_warn(dev->ctrl.device,
1961 "min host memory (%lld MiB) above limit (%d MiB).\n",
1962 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1963 nvme_free_host_mem(dev);
1968 * If we already have a buffer allocated check if we can reuse it.
1970 if (dev->host_mem_descs) {
1971 if (dev->host_mem_size >= min)
1972 enable_bits |= NVME_HOST_MEM_RETURN;
1974 nvme_free_host_mem(dev);
1977 if (!dev->host_mem_descs) {
1978 if (nvme_alloc_host_mem(dev, min, preferred)) {
1979 dev_warn(dev->ctrl.device,
1980 "failed to allocate host memory buffer.\n");
1981 return 0; /* controller must work without HMB */
1984 dev_info(dev->ctrl.device,
1985 "allocated %lld MiB host memory buffer.\n",
1986 dev->host_mem_size >> ilog2(SZ_1M));
1989 ret = nvme_set_host_mem(dev, enable_bits);
1991 nvme_free_host_mem(dev);
1996 * nirqs is the number of interrupts available for write and read
1997 * queues. The core already reserved an interrupt for the admin queue.
1999 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2001 struct nvme_dev *dev = affd->priv;
2002 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2005 * If there is no interupt available for queues, ensure that
2006 * the default queue is set to 1. The affinity set size is
2007 * also set to one, but the irq core ignores it for this case.
2009 * If only one interrupt is available or 'write_queue' == 0, combine
2010 * write and read queues.
2012 * If 'write_queues' > 0, ensure it leaves room for at least one read
2018 } else if (nrirqs == 1 || !nr_write_queues) {
2020 } else if (nr_write_queues >= nrirqs) {
2023 nr_read_queues = nrirqs - nr_write_queues;
2026 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2027 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2028 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2029 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2030 affd->nr_sets = nr_read_queues ? 2 : 1;
2033 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2035 struct pci_dev *pdev = to_pci_dev(dev->dev);
2036 struct irq_affinity affd = {
2038 .calc_sets = nvme_calc_irq_sets,
2041 unsigned int irq_queues, this_p_queues;
2044 * Poll queues don't need interrupts, but we need at least one IO
2045 * queue left over for non-polled IO.
2047 this_p_queues = dev->nr_poll_queues;
2048 if (this_p_queues >= nr_io_queues) {
2049 this_p_queues = nr_io_queues - 1;
2052 irq_queues = nr_io_queues - this_p_queues + 1;
2054 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2056 /* Initialize for the single interrupt case */
2057 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2058 dev->io_queues[HCTX_TYPE_READ] = 0;
2061 * Some Apple controllers require all queues to use the
2064 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2067 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2068 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2071 static void nvme_disable_io_queues(struct nvme_dev *dev)
2073 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2074 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2077 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2079 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2082 static int nvme_setup_io_queues(struct nvme_dev *dev)
2084 struct nvme_queue *adminq = &dev->queues[0];
2085 struct pci_dev *pdev = to_pci_dev(dev->dev);
2086 unsigned int nr_io_queues;
2091 * Sample the module parameters once at reset time so that we have
2092 * stable values to work with.
2094 dev->nr_write_queues = write_queues;
2095 dev->nr_poll_queues = poll_queues;
2098 * If tags are shared with admin queue (Apple bug), then
2099 * make sure we only use one IO queue.
2101 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2104 nr_io_queues = min(nvme_max_io_queues(dev),
2105 dev->nr_allocated_queues - 1);
2107 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2111 if (nr_io_queues == 0)
2114 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2116 if (dev->cmb_use_sqes) {
2117 result = nvme_cmb_qdepth(dev, nr_io_queues,
2118 sizeof(struct nvme_command));
2120 dev->q_depth = result;
2122 dev->cmb_use_sqes = false;
2126 size = db_bar_size(dev, nr_io_queues);
2127 result = nvme_remap_bar(dev, size);
2130 if (!--nr_io_queues)
2133 adminq->q_db = dev->dbs;
2136 /* Deregister the admin queue's interrupt */
2137 pci_free_irq(pdev, 0, adminq);
2140 * If we enable msix early due to not intx, disable it again before
2141 * setting up the full range we need.
2143 pci_free_irq_vectors(pdev);
2145 result = nvme_setup_irqs(dev, nr_io_queues);
2149 dev->num_vecs = result;
2150 result = max(result - 1, 1);
2151 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2154 * Should investigate if there's a performance win from allocating
2155 * more queues than interrupt vectors; it might allow the submission
2156 * path to scale better, even if the receive path is limited by the
2157 * number of interrupts.
2159 result = queue_request_irq(adminq);
2162 set_bit(NVMEQ_ENABLED, &adminq->flags);
2164 result = nvme_create_io_queues(dev);
2165 if (result || dev->online_queues < 2)
2168 if (dev->online_queues - 1 < dev->max_qid) {
2169 nr_io_queues = dev->online_queues - 1;
2170 nvme_disable_io_queues(dev);
2171 nvme_suspend_io_queues(dev);
2174 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2175 dev->io_queues[HCTX_TYPE_DEFAULT],
2176 dev->io_queues[HCTX_TYPE_READ],
2177 dev->io_queues[HCTX_TYPE_POLL]);
2181 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2183 struct nvme_queue *nvmeq = req->end_io_data;
2185 blk_mq_free_request(req);
2186 complete(&nvmeq->delete_done);
2189 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2191 struct nvme_queue *nvmeq = req->end_io_data;
2194 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2196 nvme_del_queue_end(req, error);
2199 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2201 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2202 struct request *req;
2203 struct nvme_command cmd;
2205 memset(&cmd, 0, sizeof(cmd));
2206 cmd.delete_queue.opcode = opcode;
2207 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2209 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2211 return PTR_ERR(req);
2213 req->timeout = ADMIN_TIMEOUT;
2214 req->end_io_data = nvmeq;
2216 init_completion(&nvmeq->delete_done);
2217 blk_execute_rq_nowait(q, NULL, req, false,
2218 opcode == nvme_admin_delete_cq ?
2219 nvme_del_cq_end : nvme_del_queue_end);
2223 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2225 int nr_queues = dev->online_queues - 1, sent = 0;
2226 unsigned long timeout;
2229 timeout = ADMIN_TIMEOUT;
2230 while (nr_queues > 0) {
2231 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2237 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2239 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2251 static void nvme_dev_add(struct nvme_dev *dev)
2255 if (!dev->ctrl.tagset) {
2256 dev->tagset.ops = &nvme_mq_ops;
2257 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2258 dev->tagset.nr_maps = 2; /* default + read */
2259 if (dev->io_queues[HCTX_TYPE_POLL])
2260 dev->tagset.nr_maps++;
2261 dev->tagset.timeout = NVME_IO_TIMEOUT;
2262 dev->tagset.numa_node = dev->ctrl.numa_node;
2263 dev->tagset.queue_depth =
2264 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2265 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2266 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2267 dev->tagset.driver_data = dev;
2270 * Some Apple controllers requires tags to be unique
2271 * across admin and IO queue, so reserve the first 32
2272 * tags of the IO queue.
2274 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2275 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2277 ret = blk_mq_alloc_tag_set(&dev->tagset);
2279 dev_warn(dev->ctrl.device,
2280 "IO queues tagset allocation failed %d\n", ret);
2283 dev->ctrl.tagset = &dev->tagset;
2285 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2287 /* Free previously allocated queues that are no longer usable */
2288 nvme_free_queues(dev, dev->online_queues);
2291 nvme_dbbuf_set(dev);
2294 static int nvme_pci_enable(struct nvme_dev *dev)
2296 int result = -ENOMEM;
2297 struct pci_dev *pdev = to_pci_dev(dev->dev);
2299 if (pci_enable_device_mem(pdev))
2302 pci_set_master(pdev);
2304 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
2307 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2313 * Some devices and/or platforms don't advertise or work with INTx
2314 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2315 * adjust this later.
2317 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2321 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2323 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2325 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2326 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2327 dev->dbs = dev->bar + 4096;
2330 * Some Apple controllers require a non-standard SQE size.
2331 * Interestingly they also seem to ignore the CC:IOSQES register
2332 * so we don't bother updating it here.
2334 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2337 dev->io_sqes = NVME_NVM_IOSQES;
2340 * Temporary fix for the Apple controller found in the MacBook8,1 and
2341 * some MacBook7,1 to avoid controller resets and data loss.
2343 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2345 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2346 "set queue depth=%u to work around controller resets\n",
2348 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2349 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2350 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2352 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2353 "set queue depth=%u\n", dev->q_depth);
2357 * Controllers with the shared tags quirk need the IO queue to be
2358 * big enough so that we get 32 tags for the admin queue
2360 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2361 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2362 dev->q_depth = NVME_AQ_DEPTH + 2;
2363 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2370 pci_enable_pcie_error_reporting(pdev);
2371 pci_save_state(pdev);
2375 pci_disable_device(pdev);
2379 static void nvme_dev_unmap(struct nvme_dev *dev)
2383 pci_release_mem_regions(to_pci_dev(dev->dev));
2386 static void nvme_pci_disable(struct nvme_dev *dev)
2388 struct pci_dev *pdev = to_pci_dev(dev->dev);
2390 pci_free_irq_vectors(pdev);
2392 if (pci_is_enabled(pdev)) {
2393 pci_disable_pcie_error_reporting(pdev);
2394 pci_disable_device(pdev);
2398 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2400 bool dead = true, freeze = false;
2401 struct pci_dev *pdev = to_pci_dev(dev->dev);
2403 mutex_lock(&dev->shutdown_lock);
2404 if (pci_is_enabled(pdev)) {
2405 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2407 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2408 dev->ctrl.state == NVME_CTRL_RESETTING) {
2410 nvme_start_freeze(&dev->ctrl);
2412 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2413 pdev->error_state != pci_channel_io_normal);
2417 * Give the controller a chance to complete all entered requests if
2418 * doing a safe shutdown.
2420 if (!dead && shutdown && freeze)
2421 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2423 nvme_stop_queues(&dev->ctrl);
2425 if (!dead && dev->ctrl.queue_count > 0) {
2426 nvme_disable_io_queues(dev);
2427 nvme_disable_admin_queue(dev, shutdown);
2429 nvme_suspend_io_queues(dev);
2430 nvme_suspend_queue(&dev->queues[0]);
2431 nvme_pci_disable(dev);
2432 nvme_reap_pending_cqes(dev);
2434 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2435 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2436 blk_mq_tagset_wait_completed_request(&dev->tagset);
2437 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2440 * The driver will not be starting up queues again if shutting down so
2441 * must flush all entered requests to their failed completion to avoid
2442 * deadlocking blk-mq hot-cpu notifier.
2445 nvme_start_queues(&dev->ctrl);
2446 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2447 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2449 mutex_unlock(&dev->shutdown_lock);
2452 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2454 if (!nvme_wait_reset(&dev->ctrl))
2456 nvme_dev_disable(dev, shutdown);
2460 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2462 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2463 PAGE_SIZE, PAGE_SIZE, 0);
2464 if (!dev->prp_page_pool)
2467 /* Optimisation for I/Os between 4k and 128k */
2468 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2470 if (!dev->prp_small_pool) {
2471 dma_pool_destroy(dev->prp_page_pool);
2477 static void nvme_release_prp_pools(struct nvme_dev *dev)
2479 dma_pool_destroy(dev->prp_page_pool);
2480 dma_pool_destroy(dev->prp_small_pool);
2483 static void nvme_free_tagset(struct nvme_dev *dev)
2485 if (dev->tagset.tags)
2486 blk_mq_free_tag_set(&dev->tagset);
2487 dev->ctrl.tagset = NULL;
2490 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2492 struct nvme_dev *dev = to_nvme_dev(ctrl);
2494 nvme_dbbuf_dma_free(dev);
2495 nvme_free_tagset(dev);
2496 if (dev->ctrl.admin_q)
2497 blk_put_queue(dev->ctrl.admin_q);
2498 free_opal_dev(dev->ctrl.opal_dev);
2499 mempool_destroy(dev->iod_mempool);
2500 put_device(dev->dev);
2505 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2508 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2509 * may be holding this pci_dev's device lock.
2511 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2512 nvme_get_ctrl(&dev->ctrl);
2513 nvme_dev_disable(dev, false);
2514 nvme_kill_queues(&dev->ctrl);
2515 if (!queue_work(nvme_wq, &dev->remove_work))
2516 nvme_put_ctrl(&dev->ctrl);
2519 static void nvme_reset_work(struct work_struct *work)
2521 struct nvme_dev *dev =
2522 container_of(work, struct nvme_dev, ctrl.reset_work);
2523 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2526 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2532 * If we're called to reset a live controller first shut it down before
2535 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2536 nvme_dev_disable(dev, false);
2537 nvme_sync_queues(&dev->ctrl);
2539 mutex_lock(&dev->shutdown_lock);
2540 result = nvme_pci_enable(dev);
2544 result = nvme_pci_configure_admin_queue(dev);
2548 result = nvme_alloc_admin_tags(dev);
2553 * Limit the max command size to prevent iod->sg allocations going
2554 * over a single page.
2556 dev->ctrl.max_hw_sectors = min_t(u32,
2557 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2558 dev->ctrl.max_segments = NVME_MAX_SEGS;
2561 * Don't limit the IOMMU merged segment size.
2563 dma_set_max_seg_size(dev->dev, 0xffffffff);
2565 mutex_unlock(&dev->shutdown_lock);
2568 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2569 * initializing procedure here.
2571 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2572 dev_warn(dev->ctrl.device,
2573 "failed to mark controller CONNECTING\n");
2579 * We do not support an SGL for metadata (yet), so we are limited to a
2580 * single integrity segment for the separate metadata pointer.
2582 dev->ctrl.max_integrity_segments = 1;
2584 result = nvme_init_identify(&dev->ctrl);
2588 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2589 if (!dev->ctrl.opal_dev)
2590 dev->ctrl.opal_dev =
2591 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2592 else if (was_suspend)
2593 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2595 free_opal_dev(dev->ctrl.opal_dev);
2596 dev->ctrl.opal_dev = NULL;
2599 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2600 result = nvme_dbbuf_dma_alloc(dev);
2603 "unable to allocate dma for dbbuf\n");
2606 if (dev->ctrl.hmpre) {
2607 result = nvme_setup_host_mem(dev);
2612 result = nvme_setup_io_queues(dev);
2617 * Keep the controller around but remove all namespaces if we don't have
2618 * any working I/O queue.
2620 if (dev->online_queues < 2) {
2621 dev_warn(dev->ctrl.device, "IO queues not created\n");
2622 nvme_kill_queues(&dev->ctrl);
2623 nvme_remove_namespaces(&dev->ctrl);
2624 nvme_free_tagset(dev);
2626 nvme_start_queues(&dev->ctrl);
2627 nvme_wait_freeze(&dev->ctrl);
2629 nvme_unfreeze(&dev->ctrl);
2633 * If only admin queue live, keep it to do further investigation or
2636 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2637 dev_warn(dev->ctrl.device,
2638 "failed to mark controller live state\n");
2643 nvme_start_ctrl(&dev->ctrl);
2647 mutex_unlock(&dev->shutdown_lock);
2650 dev_warn(dev->ctrl.device,
2651 "Removing after probe failure status: %d\n", result);
2652 nvme_remove_dead_ctrl(dev);
2655 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2657 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2658 struct pci_dev *pdev = to_pci_dev(dev->dev);
2660 if (pci_get_drvdata(pdev))
2661 device_release_driver(&pdev->dev);
2662 nvme_put_ctrl(&dev->ctrl);
2665 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2667 *val = readl(to_nvme_dev(ctrl)->bar + off);
2671 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2673 writel(val, to_nvme_dev(ctrl)->bar + off);
2677 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2679 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2683 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2685 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2687 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2690 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2692 .module = THIS_MODULE,
2693 .flags = NVME_F_METADATA_SUPPORTED |
2695 .reg_read32 = nvme_pci_reg_read32,
2696 .reg_write32 = nvme_pci_reg_write32,
2697 .reg_read64 = nvme_pci_reg_read64,
2698 .free_ctrl = nvme_pci_free_ctrl,
2699 .submit_async_event = nvme_pci_submit_async_event,
2700 .get_address = nvme_pci_get_address,
2703 static int nvme_dev_map(struct nvme_dev *dev)
2705 struct pci_dev *pdev = to_pci_dev(dev->dev);
2707 if (pci_request_mem_regions(pdev, "nvme"))
2710 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2715 pci_release_mem_regions(pdev);
2719 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2721 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2723 * Several Samsung devices seem to drop off the PCIe bus
2724 * randomly when APST is on and uses the deepest sleep state.
2725 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2726 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2727 * 950 PRO 256GB", but it seems to be restricted to two Dell
2730 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2731 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2732 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2733 return NVME_QUIRK_NO_DEEPEST_PS;
2734 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2736 * Samsung SSD 960 EVO drops off the PCIe bus after system
2737 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2738 * within few minutes after bootup on a Coffee Lake board -
2741 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2742 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2743 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2744 return NVME_QUIRK_NO_APST;
2745 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2746 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2747 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2749 * Forcing to use host managed nvme power settings for
2750 * lowest idle power with quick resume latency on
2751 * Samsung and Toshiba SSDs based on suspend behavior
2752 * on Coffee Lake board for LENOVO C640
2754 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2755 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2756 return NVME_QUIRK_SIMPLE_SUSPEND;
2762 static void nvme_async_probe(void *data, async_cookie_t cookie)
2764 struct nvme_dev *dev = data;
2766 flush_work(&dev->ctrl.reset_work);
2767 flush_work(&dev->ctrl.scan_work);
2768 nvme_put_ctrl(&dev->ctrl);
2771 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2773 int node, result = -ENOMEM;
2774 struct nvme_dev *dev;
2775 unsigned long quirks = id->driver_data;
2778 node = dev_to_node(&pdev->dev);
2779 if (node == NUMA_NO_NODE)
2780 set_dev_node(&pdev->dev, first_memory_node);
2782 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2786 dev->nr_write_queues = write_queues;
2787 dev->nr_poll_queues = poll_queues;
2788 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2789 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2790 sizeof(struct nvme_queue), GFP_KERNEL, node);
2794 dev->dev = get_device(&pdev->dev);
2795 pci_set_drvdata(pdev, dev);
2797 result = nvme_dev_map(dev);
2801 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2802 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2803 mutex_init(&dev->shutdown_lock);
2805 result = nvme_setup_prp_pools(dev);
2809 quirks |= check_vendor_combination_bug(pdev);
2812 * Double check that our mempool alloc size will cover the biggest
2813 * command we support.
2815 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2816 NVME_MAX_SEGS, true);
2817 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2819 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2821 (void *) alloc_size,
2823 if (!dev->iod_mempool) {
2828 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2831 goto release_mempool;
2833 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2835 nvme_reset_ctrl(&dev->ctrl);
2836 async_schedule(nvme_async_probe, dev);
2841 mempool_destroy(dev->iod_mempool);
2843 nvme_release_prp_pools(dev);
2845 nvme_dev_unmap(dev);
2847 put_device(dev->dev);
2854 static void nvme_reset_prepare(struct pci_dev *pdev)
2856 struct nvme_dev *dev = pci_get_drvdata(pdev);
2859 * We don't need to check the return value from waiting for the reset
2860 * state as pci_dev device lock is held, making it impossible to race
2863 nvme_disable_prepare_reset(dev, false);
2864 nvme_sync_queues(&dev->ctrl);
2867 static void nvme_reset_done(struct pci_dev *pdev)
2869 struct nvme_dev *dev = pci_get_drvdata(pdev);
2871 if (!nvme_try_sched_reset(&dev->ctrl))
2872 flush_work(&dev->ctrl.reset_work);
2875 static void nvme_shutdown(struct pci_dev *pdev)
2877 struct nvme_dev *dev = pci_get_drvdata(pdev);
2878 nvme_disable_prepare_reset(dev, true);
2882 * The driver's remove may be called on a device in a partially initialized
2883 * state. This function must not have any dependencies on the device state in
2886 static void nvme_remove(struct pci_dev *pdev)
2888 struct nvme_dev *dev = pci_get_drvdata(pdev);
2890 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2891 pci_set_drvdata(pdev, NULL);
2893 if (!pci_device_is_present(pdev)) {
2894 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2895 nvme_dev_disable(dev, true);
2896 nvme_dev_remove_admin(dev);
2899 flush_work(&dev->ctrl.reset_work);
2900 nvme_stop_ctrl(&dev->ctrl);
2901 nvme_remove_namespaces(&dev->ctrl);
2902 nvme_dev_disable(dev, true);
2903 nvme_release_cmb(dev);
2904 nvme_free_host_mem(dev);
2905 nvme_dev_remove_admin(dev);
2906 nvme_free_queues(dev, 0);
2907 nvme_release_prp_pools(dev);
2908 nvme_dev_unmap(dev);
2909 nvme_uninit_ctrl(&dev->ctrl);
2912 #ifdef CONFIG_PM_SLEEP
2913 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2915 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2918 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2920 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2923 static int nvme_resume(struct device *dev)
2925 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2926 struct nvme_ctrl *ctrl = &ndev->ctrl;
2928 if (ndev->last_ps == U32_MAX ||
2929 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
2930 return nvme_try_sched_reset(&ndev->ctrl);
2934 static int nvme_suspend(struct device *dev)
2936 struct pci_dev *pdev = to_pci_dev(dev);
2937 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2938 struct nvme_ctrl *ctrl = &ndev->ctrl;
2941 ndev->last_ps = U32_MAX;
2944 * The platform does not remove power for a kernel managed suspend so
2945 * use host managed nvme power settings for lowest idle power if
2946 * possible. This should have quicker resume latency than a full device
2947 * shutdown. But if the firmware is involved after the suspend or the
2948 * device does not support any non-default power states, shut down the
2951 * If ASPM is not enabled for the device, shut down the device and allow
2952 * the PCI bus layer to put it into D3 in order to take the PCIe link
2953 * down, so as to allow the platform to achieve its minimum low-power
2954 * state (which may not be possible if the link is up).
2956 * If a host memory buffer is enabled, shut down the device as the NVMe
2957 * specification allows the device to access the host memory buffer in
2958 * host DRAM from all power states, but hosts will fail access to DRAM
2961 if (pm_suspend_via_firmware() || !ctrl->npss ||
2962 !pcie_aspm_enabled(pdev) ||
2963 ndev->nr_host_mem_descs ||
2964 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
2965 return nvme_disable_prepare_reset(ndev, true);
2967 nvme_start_freeze(ctrl);
2968 nvme_wait_freeze(ctrl);
2969 nvme_sync_queues(ctrl);
2971 if (ctrl->state != NVME_CTRL_LIVE)
2974 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2979 * A saved state prevents pci pm from generically controlling the
2980 * device's power. If we're using protocol specific settings, we don't
2981 * want pci interfering.
2983 pci_save_state(pdev);
2985 ret = nvme_set_power_state(ctrl, ctrl->npss);
2990 /* discard the saved state */
2991 pci_load_saved_state(pdev, NULL);
2994 * Clearing npss forces a controller reset on resume. The
2995 * correct value will be rediscovered then.
2997 ret = nvme_disable_prepare_reset(ndev, true);
3001 nvme_unfreeze(ctrl);
3005 static int nvme_simple_suspend(struct device *dev)
3007 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3008 return nvme_disable_prepare_reset(ndev, true);
3011 static int nvme_simple_resume(struct device *dev)
3013 struct pci_dev *pdev = to_pci_dev(dev);
3014 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3016 return nvme_try_sched_reset(&ndev->ctrl);
3019 static const struct dev_pm_ops nvme_dev_pm_ops = {
3020 .suspend = nvme_suspend,
3021 .resume = nvme_resume,
3022 .freeze = nvme_simple_suspend,
3023 .thaw = nvme_simple_resume,
3024 .poweroff = nvme_simple_suspend,
3025 .restore = nvme_simple_resume,
3027 #endif /* CONFIG_PM_SLEEP */
3029 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3030 pci_channel_state_t state)
3032 struct nvme_dev *dev = pci_get_drvdata(pdev);
3035 * A frozen channel requires a reset. When detected, this method will
3036 * shutdown the controller to quiesce. The controller will be restarted
3037 * after the slot reset through driver's slot_reset callback.
3040 case pci_channel_io_normal:
3041 return PCI_ERS_RESULT_CAN_RECOVER;
3042 case pci_channel_io_frozen:
3043 dev_warn(dev->ctrl.device,
3044 "frozen state error detected, reset controller\n");
3045 nvme_dev_disable(dev, false);
3046 return PCI_ERS_RESULT_NEED_RESET;
3047 case pci_channel_io_perm_failure:
3048 dev_warn(dev->ctrl.device,
3049 "failure state error detected, request disconnect\n");
3050 return PCI_ERS_RESULT_DISCONNECT;
3052 return PCI_ERS_RESULT_NEED_RESET;
3055 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3057 struct nvme_dev *dev = pci_get_drvdata(pdev);
3059 dev_info(dev->ctrl.device, "restart after slot reset\n");
3060 pci_restore_state(pdev);
3061 nvme_reset_ctrl(&dev->ctrl);
3062 return PCI_ERS_RESULT_RECOVERED;
3065 static void nvme_error_resume(struct pci_dev *pdev)
3067 struct nvme_dev *dev = pci_get_drvdata(pdev);
3069 flush_work(&dev->ctrl.reset_work);
3072 static const struct pci_error_handlers nvme_err_handler = {
3073 .error_detected = nvme_error_detected,
3074 .slot_reset = nvme_slot_reset,
3075 .resume = nvme_error_resume,
3076 .reset_prepare = nvme_reset_prepare,
3077 .reset_done = nvme_reset_done,
3080 static const struct pci_device_id nvme_id_table[] = {
3081 { PCI_VDEVICE(INTEL, 0x0953),
3082 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3083 NVME_QUIRK_DEALLOCATE_ZEROES, },
3084 { PCI_VDEVICE(INTEL, 0x0a53),
3085 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3086 NVME_QUIRK_DEALLOCATE_ZEROES, },
3087 { PCI_VDEVICE(INTEL, 0x0a54),
3088 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3089 NVME_QUIRK_DEALLOCATE_ZEROES, },
3090 { PCI_VDEVICE(INTEL, 0x0a55),
3091 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3092 NVME_QUIRK_DEALLOCATE_ZEROES, },
3093 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3094 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3095 NVME_QUIRK_MEDIUM_PRIO_SQ |
3096 NVME_QUIRK_NO_TEMP_THRESH_CHANGE },
3097 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3098 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3099 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3100 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3101 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3102 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3103 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3104 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3105 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3106 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3107 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3108 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3109 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3110 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3111 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3112 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3113 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3114 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3115 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3116 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3117 .driver_data = NVME_QUIRK_LIGHTNVM, },
3118 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3119 .driver_data = NVME_QUIRK_LIGHTNVM, },
3120 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3121 .driver_data = NVME_QUIRK_LIGHTNVM, },
3122 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3123 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3124 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3125 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3126 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3127 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3128 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3129 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3130 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3131 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3132 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3133 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3134 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3135 NVME_QUIRK_128_BYTES_SQES |
3136 NVME_QUIRK_SHARED_TAGS },
3139 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3141 static struct pci_driver nvme_driver = {
3143 .id_table = nvme_id_table,
3144 .probe = nvme_probe,
3145 .remove = nvme_remove,
3146 .shutdown = nvme_shutdown,
3147 #ifdef CONFIG_PM_SLEEP
3149 .pm = &nvme_dev_pm_ops,
3152 .sriov_configure = pci_sriov_configure_simple,
3153 .err_handler = &nvme_err_handler,
3156 static int __init nvme_init(void)
3158 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3159 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3160 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3161 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3163 return pci_register_driver(&nvme_driver);
3166 static void __exit nvme_exit(void)
3168 pci_unregister_driver(&nvme_driver);
3169 flush_workqueue(nvme_wq);
3172 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3173 MODULE_LICENSE("GPL");
3174 MODULE_VERSION("1.0");
3175 module_init(nvme_init);
3176 module_exit(nvme_exit);