drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <linux/fs.h>
  23 #include <linux/genhd.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/idr.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kdev_t.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/mutex.h>
  35 #include <linux/pci.h>
  36 #include <linux/poison.h>
  37 #include <linux/ptrace.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/t10-pi.h>
  41 #include <linux/timer.h>
  42 #include <linux/types.h>
  43 #include <linux/io-64-nonatomic-lo-hi.h>
  44 #include <asm/unaligned.h>
  45
  46 #include "nvme.h"
  47
  48 #define NVME_Q_DEPTH            1024
  49 #define NVME_AQ_DEPTH           256
  50 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  51 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  52
  53 /*
  54  * We handle AEN commands ourselves and don't even let the
  55  * block layer know about them.
  56  */
  57 #define NVME_NR_AEN_COMMANDS    1
  58 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  59
  60 static int use_threaded_interrupts;
  61 module_param(use_threaded_interrupts, int, 0);
  62
  63 static bool use_cmb_sqes = true;
  64 module_param(use_cmb_sqes, bool, 0644);
  65 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  66
  67 static struct workqueue_struct *nvme_workq;
  68
  69 struct nvme_dev;
  70 struct nvme_queue;
  71
  72 static int nvme_reset(struct nvme_dev *dev);
  73 static void nvme_process_cq(struct nvme_queue *nvmeq);
  74 static void nvme_remove_dead_ctrl(struct nvme_dev *dev);
  75 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  76
  77 /*
  78  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  79  */
  80 struct nvme_dev {
  81         struct nvme_queue **queues;
  82         struct blk_mq_tag_set tagset;
  83         struct blk_mq_tag_set admin_tagset;
  84         u32 __iomem *dbs;
  85         struct device *dev;
  86         struct dma_pool *prp_page_pool;
  87         struct dma_pool *prp_small_pool;
  88         unsigned queue_count;
  89         unsigned online_queues;
  90         unsigned max_qid;
  91         int q_depth;
  92         u32 db_stride;
  93         struct msix_entry *entry;
  94         void __iomem *bar;
  95         struct work_struct reset_work;
  96         struct work_struct scan_work;
  97         struct work_struct remove_work;
  98         struct work_struct async_work;
  99         struct timer_list watchdog_timer;
 100         struct mutex shutdown_lock;
 101         bool subsystem;
 102         void __iomem *cmb;
 103         dma_addr_t cmb_dma_addr;
 104         u64 cmb_size;
 105         u32 cmbsz;
 106         unsigned long flags;
 107
 108 #define NVME_CTRL_RESETTING    0
 109
 110         struct nvme_ctrl ctrl;
 111         struct completion ioq_wait;
 112 };
 113
 114 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 115 {
 116         return container_of(ctrl, struct nvme_dev, ctrl);
 117 }
 118
 119 /*
 120  * An NVM Express queue.  Each device has at least two (one for admin
 121  * commands and one for I/O commands).
 122  */
 123 struct nvme_queue {
 124         struct device *q_dmadev;
 125         struct nvme_dev *dev;
 126         char irqname[24];       /* nvme4294967295-65535\0 */
 127         spinlock_t q_lock;
 128         struct nvme_command *sq_cmds;
 129         struct nvme_command __iomem *sq_cmds_io;
 130         volatile struct nvme_completion *cqes;
 131         struct blk_mq_tags **tags;
 132         dma_addr_t sq_dma_addr;
 133         dma_addr_t cq_dma_addr;
 134         u32 __iomem *q_db;
 135         u16 q_depth;
 136         s16 cq_vector;
 137         u16 sq_head;
 138         u16 sq_tail;
 139         u16 cq_head;
 140         u16 qid;
 141         u8 cq_phase;
 142         u8 cqe_seen;
 143 };
 144
 145 /*
 146  * The nvme_iod describes the data in an I/O, including the list of PRP
 147  * entries.  You can't see it in this data structure because C doesn't let
 148  * me express that.  Use nvme_init_iod to ensure there's enough space
 149  * allocated to store the PRP list.
 150  */
 151 struct nvme_iod {
 152         struct nvme_queue *nvmeq;
 153         int aborted;
 154         int npages;             /* In the PRP list. 0 means small pool in use */
 155         int nents;              /* Used in scatterlist */
 156         int length;             /* Of data, in bytes */
 157         dma_addr_t first_dma;
 158         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 159         struct scatterlist *sg;
 160         struct scatterlist inline_sg[0];
 161 };
 162
 163 /*
 164  * Check we didin't inadvertently grow the command struct
 165  */
 166 static inline void _nvme_check_size(void)
 167 {
 168         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 169         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 170         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 171         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 172         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 173         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 174         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 175         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 176         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 177         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 178         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 179         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 180 }
 181
 182 /*
 183  * Max size of iod being embedded in the request payload
 184  */
 185 #define NVME_INT_PAGES          2
 186 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 187
 188 /*
 189  * Will slightly overestimate the number of pages needed.  This is OK
 190  * as it only leads to a small amount of wasted memory for the lifetime of
 191  * the I/O.
 192  */
 193 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 194 {
 195         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 196                                       dev->ctrl.page_size);
 197         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 198 }
 199
 200 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 201                 unsigned int size, unsigned int nseg)
 202 {
 203         return sizeof(__le64 *) * nvme_npages(size, dev) +
 204                         sizeof(struct scatterlist) * nseg;
 205 }
 206
 207 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 208 {
 209         return sizeof(struct nvme_iod) +
 210                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 211 }
 212
 213 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 214                                 unsigned int hctx_idx)
 215 {
 216         struct nvme_dev *dev = data;
 217         struct nvme_queue *nvmeq = dev->queues[0];
 218
 219         WARN_ON(hctx_idx != 0);
 220         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 221         WARN_ON(nvmeq->tags);
 222
 223         hctx->driver_data = nvmeq;
 224         nvmeq->tags = &dev->admin_tagset.tags[0];
 225         return 0;
 226 }
 227
 228 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 229 {
 230         struct nvme_queue *nvmeq = hctx->driver_data;
 231
 232         nvmeq->tags = NULL;
 233 }
 234
 235 static int nvme_admin_init_request(void *data, struct request *req,
 236                                 unsigned int hctx_idx, unsigned int rq_idx,
 237                                 unsigned int numa_node)
 238 {
 239         struct nvme_dev *dev = data;
 240         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 241         struct nvme_queue *nvmeq = dev->queues[0];
 242
 243         BUG_ON(!nvmeq);
 244         iod->nvmeq = nvmeq;
 245         return 0;
 246 }
 247
 248 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 249                           unsigned int hctx_idx)
 250 {
 251         struct nvme_dev *dev = data;
 252         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 253
 254         if (!nvmeq->tags)
 255                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 256
 257         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 258         hctx->driver_data = nvmeq;
 259         return 0;
 260 }
 261
 262 static int nvme_init_request(void *data, struct request *req,
 263                                 unsigned int hctx_idx, unsigned int rq_idx,
 264                                 unsigned int numa_node)
 265 {
 266         struct nvme_dev *dev = data;
 267         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 268         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 269
 270         BUG_ON(!nvmeq);
 271         iod->nvmeq = nvmeq;
 272         return 0;
 273 }
 274
 275 static void nvme_complete_async_event(struct nvme_dev *dev,
 276                 struct nvme_completion *cqe)
 277 {
 278         u16 status = le16_to_cpu(cqe->status) >> 1;
 279         u32 result = le32_to_cpu(cqe->result);
 280
 281         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) {
 282                 ++dev->ctrl.event_limit;
 283                 queue_work(nvme_workq, &dev->async_work);
 284         }
 285
 286         if (status != NVME_SC_SUCCESS)
 287                 return;
 288
 289         switch (result & 0xff07) {
 290         case NVME_AER_NOTICE_NS_CHANGED:
 291                 dev_info(dev->ctrl.device, "rescanning\n");
 292                 queue_work(nvme_workq, &dev->scan_work);
 293         default:
 294                 dev_warn(dev->ctrl.device, "async event result %08x\n", result);
 295         }
 296 }
 297
 298 /**
 299  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 300  * @nvmeq: The queue to use
 301  * @cmd: The command to send
 302  *
 303  * Safe to use from interrupt context
 304  */
 305 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 306                                                 struct nvme_command *cmd)
 307 {
 308         u16 tail = nvmeq->sq_tail;
 309
 310         if (nvmeq->sq_cmds_io)
 311                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 312         else
 313                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 314
 315         if (++tail == nvmeq->q_depth)
 316                 tail = 0;
 317         writel(tail, nvmeq->q_db);
 318         nvmeq->sq_tail = tail;
 319 }
 320
 321 static __le64 **iod_list(struct request *req)
 322 {
 323         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 324         return (__le64 **)(iod->sg + req->nr_phys_segments);
 325 }
 326
 327 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 328 {
 329         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 330         int nseg = rq->nr_phys_segments;
 331         unsigned size;
 332
 333         if (rq->cmd_flags & REQ_DISCARD)
 334                 size = sizeof(struct nvme_dsm_range);
 335         else
 336                 size = blk_rq_bytes(rq);
 337
 338         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 339                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 340                 if (!iod->sg)
 341                         return BLK_MQ_RQ_QUEUE_BUSY;
 342         } else {
 343                 iod->sg = iod->inline_sg;
 344         }
 345
 346         iod->aborted = 0;
 347         iod->npages = -1;
 348         iod->nents = 0;
 349         iod->length = size;
 350         return 0;
 351 }
 352
 353 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 354 {
 355         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 356         const int last_prp = dev->ctrl.page_size / 8 - 1;
 357         int i;
 358         __le64 **list = iod_list(req);
 359         dma_addr_t prp_dma = iod->first_dma;
 360
 361         if (iod->npages == 0)
 362                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 363         for (i = 0; i < iod->npages; i++) {
 364                 __le64 *prp_list = list[i];
 365                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 366                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 367                 prp_dma = next_prp_dma;
 368         }
 369
 370         if (iod->sg != iod->inline_sg)
 371                 kfree(iod->sg);
 372 }
 373
 374 #ifdef CONFIG_BLK_DEV_INTEGRITY
 375 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 376 {
 377         if (be32_to_cpu(pi->ref_tag) == v)
 378                 pi->ref_tag = cpu_to_be32(p);
 379 }
 380
 381 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 382 {
 383         if (be32_to_cpu(pi->ref_tag) == p)
 384                 pi->ref_tag = cpu_to_be32(v);
 385 }
 386
 387 /**
 388  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 389  *
 390  * The virtual start sector is the one that was originally submitted by the
 391  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 392  * start sector may be different. Remap protection information to match the
 393  * physical LBA on writes, and back to the original seed on reads.
 394  *
 395  * Type 0 and 3 do not have a ref tag, so no remapping required.
 396  */
 397 static void nvme_dif_remap(struct request *req,
 398                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 399 {
 400         struct nvme_ns *ns = req->rq_disk->private_data;
 401         struct bio_integrity_payload *bip;
 402         struct t10_pi_tuple *pi;
 403         void *p, *pmap;
 404         u32 i, nlb, ts, phys, virt;
 405
 406         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 407                 return;
 408
 409         bip = bio_integrity(req->bio);
 410         if (!bip)
 411                 return;
 412
 413         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 414
 415         p = pmap;
 416         virt = bip_get_seed(bip);
 417         phys = nvme_block_nr(ns, blk_rq_pos(req));
 418         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 419         ts = ns->disk->queue->integrity.tuple_size;
 420
 421         for (i = 0; i < nlb; i++, virt++, phys++) {
 422                 pi = (struct t10_pi_tuple *)p;
 423                 dif_swap(phys, virt, pi);
 424                 p += ts;
 425         }
 426         kunmap_atomic(pmap);
 427 }
 428 #else /* CONFIG_BLK_DEV_INTEGRITY */
 429 static void nvme_dif_remap(struct request *req,
 430                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 431 {
 432 }
 433 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 434 {
 435 }
 436 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 437 {
 438 }
 439 #endif
 440
 441 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
 442                 int total_len)
 443 {
 444         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 445         struct dma_pool *pool;
 446         int length = total_len;
 447         struct scatterlist *sg = iod->sg;
 448         int dma_len = sg_dma_len(sg);
 449         u64 dma_addr = sg_dma_address(sg);
 450         u32 page_size = dev->ctrl.page_size;
 451         int offset = dma_addr & (page_size - 1);
 452         __le64 *prp_list;
 453         __le64 **list = iod_list(req);
 454         dma_addr_t prp_dma;
 455         int nprps, i;
 456
 457         length -= (page_size - offset);
 458         if (length <= 0)
 459                 return true;
 460
 461         dma_len -= (page_size - offset);
 462         if (dma_len) {
 463                 dma_addr += (page_size - offset);
 464         } else {
 465                 sg = sg_next(sg);
 466                 dma_addr = sg_dma_address(sg);
 467                 dma_len = sg_dma_len(sg);
 468         }
 469
 470         if (length <= page_size) {
 471                 iod->first_dma = dma_addr;
 472                 return true;
 473         }
 474
 475         nprps = DIV_ROUND_UP(length, page_size);
 476         if (nprps <= (256 / 8)) {
 477                 pool = dev->prp_small_pool;
 478                 iod->npages = 0;
 479         } else {
 480                 pool = dev->prp_page_pool;
 481                 iod->npages = 1;
 482         }
 483
 484         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 485         if (!prp_list) {
 486                 iod->first_dma = dma_addr;
 487                 iod->npages = -1;
 488                 return false;
 489         }
 490         list[0] = prp_list;
 491         iod->first_dma = prp_dma;
 492         i = 0;
 493         for (;;) {
 494                 if (i == page_size >> 3) {
 495                         __le64 *old_prp_list = prp_list;
 496                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 497                         if (!prp_list)
 498                                 return false;
 499                         list[iod->npages++] = prp_list;
 500                         prp_list[0] = old_prp_list[i - 1];
 501                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 502                         i = 1;
 503                 }
 504                 prp_list[i++] = cpu_to_le64(dma_addr);
 505                 dma_len -= page_size;
 506                 dma_addr += page_size;
 507                 length -= page_size;
 508                 if (length <= 0)
 509                         break;
 510                 if (dma_len > 0)
 511                         continue;
 512                 BUG_ON(dma_len < 0);
 513                 sg = sg_next(sg);
 514                 dma_addr = sg_dma_address(sg);
 515                 dma_len = sg_dma_len(sg);
 516         }
 517
 518         return true;
 519 }
 520
 521 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 522                 struct nvme_command *cmnd)
 523 {
 524         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 525         struct request_queue *q = req->q;
 526         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 527                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 528         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 529
 530         sg_init_table(iod->sg, req->nr_phys_segments);
 531         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 532         if (!iod->nents)
 533                 goto out;
 534
 535         ret = BLK_MQ_RQ_QUEUE_BUSY;
 536         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 537                 goto out;
 538
 539         if (!nvme_setup_prps(dev, req, blk_rq_bytes(req)))
 540                 goto out_unmap;
 541
 542         ret = BLK_MQ_RQ_QUEUE_ERROR;
 543         if (blk_integrity_rq(req)) {
 544                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 545                         goto out_unmap;
 546
 547                 sg_init_table(&iod->meta_sg, 1);
 548                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 549                         goto out_unmap;
 550
 551                 if (rq_data_dir(req))
 552                         nvme_dif_remap(req, nvme_dif_prep);
 553
 554                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 555                         goto out_unmap;
 556         }
 557
 558         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 559         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 560         if (blk_integrity_rq(req))
 561                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 562         return BLK_MQ_RQ_QUEUE_OK;
 563
 564 out_unmap:
 565         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 566 out:
 567         return ret;
 568 }
 569
 570 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 571 {
 572         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 573         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 574                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 575
 576         if (iod->nents) {
 577                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 578                 if (blk_integrity_rq(req)) {
 579                         if (!rq_data_dir(req))
 580                                 nvme_dif_remap(req, nvme_dif_complete);
 581                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 582                 }
 583         }
 584
 585         nvme_free_iod(dev, req);
 586 }
 587
 588 /*
 589  * We reuse the small pool to allocate the 16-byte range here as it is not
 590  * worth having a special pool for these or additional cases to handle freeing
 591  * the iod.
 592  */
 593 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 594                 struct request *req, struct nvme_command *cmnd)
 595 {
 596         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 597         struct nvme_dsm_range *range;
 598
 599         range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
 600                                                 &iod->first_dma);
 601         if (!range)
 602                 return BLK_MQ_RQ_QUEUE_BUSY;
 603         iod_list(req)[0] = (__le64 *)range;
 604         iod->npages = 0;
 605
 606         range->cattr = cpu_to_le32(0);
 607         range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
 608         range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
 609
 610         memset(cmnd, 0, sizeof(*cmnd));
 611         cmnd->dsm.opcode = nvme_cmd_dsm;
 612         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
 613         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
 614         cmnd->dsm.nr = 0;
 615         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
 616         return BLK_MQ_RQ_QUEUE_OK;
 617 }
 618
 619 /*
 620  * NOTE: ns is NULL when called on the admin queue.
 621  */
 622 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 623                          const struct blk_mq_queue_data *bd)
 624 {
 625         struct nvme_ns *ns = hctx->queue->queuedata;
 626         struct nvme_queue *nvmeq = hctx->driver_data;
 627         struct nvme_dev *dev = nvmeq->dev;
 628         struct request *req = bd->rq;
 629         struct nvme_command cmnd;
 630         int ret = BLK_MQ_RQ_QUEUE_OK;
 631
 632         /*
 633          * If formated with metadata, require the block layer provide a buffer
 634          * unless this namespace is formated such that the metadata can be
 635          * stripped/generated by the controller with PRACT=1.
 636          */
 637         if (ns && ns->ms && !blk_integrity_rq(req)) {
 638                 if (!(ns->pi_type && ns->ms == 8) &&
 639                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 640                         blk_mq_end_request(req, -EFAULT);
 641                         return BLK_MQ_RQ_QUEUE_OK;
 642                 }
 643         }
 644
 645         ret = nvme_init_iod(req, dev);
 646         if (ret)
 647                 return ret;
 648
 649         if (req->cmd_flags & REQ_DISCARD) {
 650                 ret = nvme_setup_discard(nvmeq, ns, req, &cmnd);
 651         } else {
 652                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 653                         memcpy(&cmnd, req->cmd, sizeof(cmnd));
 654                 else if (req->cmd_flags & REQ_FLUSH)
 655                         nvme_setup_flush(ns, &cmnd);
 656                 else
 657                         nvme_setup_rw(ns, req, &cmnd);
 658
 659                 if (req->nr_phys_segments)
 660                         ret = nvme_map_data(dev, req, &cmnd);
 661         }
 662
 663         if (ret)
 664                 goto out;
 665
 666         cmnd.common.command_id = req->tag;
 667         blk_mq_start_request(req);
 668
 669         spin_lock_irq(&nvmeq->q_lock);
 670         __nvme_submit_cmd(nvmeq, &cmnd);
 671         nvme_process_cq(nvmeq);
 672         spin_unlock_irq(&nvmeq->q_lock);
 673         return BLK_MQ_RQ_QUEUE_OK;
 674 out:
 675         nvme_free_iod(dev, req);
 676         return ret;
 677 }
 678
 679 static void nvme_complete_rq(struct request *req)
 680 {
 681         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 682         struct nvme_dev *dev = iod->nvmeq->dev;
 683         int error = 0;
 684
 685         nvme_unmap_data(dev, req);
 686
 687         if (unlikely(req->errors)) {
 688                 if (nvme_req_needs_retry(req, req->errors)) {
 689                         nvme_requeue_req(req);
 690                         return;
 691                 }
 692
 693                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 694                         error = req->errors;
 695                 else
 696                         error = nvme_error_status(req->errors);
 697         }
 698
 699         if (unlikely(iod->aborted)) {
 700                 dev_warn(dev->ctrl.device,
 701                         "completing aborted command with status: %04x\n",
 702                         req->errors);
 703         }
 704
 705         blk_mq_end_request(req, error);
 706 }
 707
 708 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 709 {
 710         u16 head, phase;
 711
 712         head = nvmeq->cq_head;
 713         phase = nvmeq->cq_phase;
 714
 715         for (;;) {
 716                 struct nvme_completion cqe = nvmeq->cqes[head];
 717                 u16 status = le16_to_cpu(cqe.status);
 718                 struct request *req;
 719
 720                 if ((status & 1) != phase)
 721                         break;
 722                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 723                 if (++head == nvmeq->q_depth) {
 724                         head = 0;
 725                         phase = !phase;
 726                 }
 727
 728                 if (tag && *tag == cqe.command_id)
 729                         *tag = -1;
 730
 731                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 732                         dev_warn(nvmeq->dev->ctrl.device,
 733                                 "invalid id %d completed on queue %d\n",
 734                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 735                         continue;
 736                 }
 737
 738                 /*
 739                  * AEN requests are special as they don't time out and can
 740                  * survive any kind of queue freeze and often don't respond to
 741                  * aborts.  We don't even bother to allocate a struct request
 742                  * for them but rather special case them here.
 743                  */
 744                 if (unlikely(nvmeq->qid == 0 &&
 745                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 746                         nvme_complete_async_event(nvmeq->dev, &cqe);
 747                         continue;
 748                 }
 749
 750                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 751                 if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special)
 752                         memcpy(req->special, &cqe, sizeof(cqe));
 753                 blk_mq_complete_request(req, status >> 1);
 754
 755         }
 756
 757         /* If the controller ignores the cq head doorbell and continuously
 758          * writes to the queue, it is theoretically possible to wrap around
 759          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 760          * requires that 0.1% of your interrupts are handled, so this isn't
 761          * a big problem.
 762          */
 763         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 764                 return;
 765
 766         if (likely(nvmeq->cq_vector >= 0))
 767                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 768         nvmeq->cq_head = head;
 769         nvmeq->cq_phase = phase;
 770
 771         nvmeq->cqe_seen = 1;
 772 }
 773
 774 static void nvme_process_cq(struct nvme_queue *nvmeq)
 775 {
 776         __nvme_process_cq(nvmeq, NULL);
 777 }
 778
 779 static irqreturn_t nvme_irq(int irq, void *data)
 780 {
 781         irqreturn_t result;
 782         struct nvme_queue *nvmeq = data;
 783         spin_lock(&nvmeq->q_lock);
 784         nvme_process_cq(nvmeq);
 785         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 786         nvmeq->cqe_seen = 0;
 787         spin_unlock(&nvmeq->q_lock);
 788         return result;
 789 }
 790
 791 static irqreturn_t nvme_irq_check(int irq, void *data)
 792 {
 793         struct nvme_queue *nvmeq = data;
 794         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 795         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 796                 return IRQ_NONE;
 797         return IRQ_WAKE_THREAD;
 798 }
 799
 800 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 801 {
 802         struct nvme_queue *nvmeq = hctx->driver_data;
 803
 804         if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
 805             nvmeq->cq_phase) {
 806                 spin_lock_irq(&nvmeq->q_lock);
 807                 __nvme_process_cq(nvmeq, &tag);
 808                 spin_unlock_irq(&nvmeq->q_lock);
 809
 810                 if (tag == -1)
 811                         return 1;
 812         }
 813
 814         return 0;
 815 }
 816
 817 static void nvme_async_event_work(struct work_struct *work)
 818 {
 819         struct nvme_dev *dev = container_of(work, struct nvme_dev, async_work);
 820         struct nvme_queue *nvmeq = dev->queues[0];
 821         struct nvme_command c;
 822
 823         memset(&c, 0, sizeof(c));
 824         c.common.opcode = nvme_admin_async_event;
 825
 826         spin_lock_irq(&nvmeq->q_lock);
 827         while (dev->ctrl.event_limit > 0) {
 828                 c.common.command_id = NVME_AQ_BLKMQ_DEPTH +
 829                         --dev->ctrl.event_limit;
 830                 __nvme_submit_cmd(nvmeq, &c);
 831         }
 832         spin_unlock_irq(&nvmeq->q_lock);
 833 }
 834
 835 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 836 {
 837         struct nvme_command c;
 838
 839         memset(&c, 0, sizeof(c));
 840         c.delete_queue.opcode = opcode;
 841         c.delete_queue.qid = cpu_to_le16(id);
 842
 843         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 844 }
 845
 846 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 847                                                 struct nvme_queue *nvmeq)
 848 {
 849         struct nvme_command c;
 850         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 851
 852         /*
 853          * Note: we (ab)use the fact the the prp fields survive if no data
 854          * is attached to the request.
 855          */
 856         memset(&c, 0, sizeof(c));
 857         c.create_cq.opcode = nvme_admin_create_cq;
 858         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 859         c.create_cq.cqid = cpu_to_le16(qid);
 860         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 861         c.create_cq.cq_flags = cpu_to_le16(flags);
 862         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 863
 864         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 865 }
 866
 867 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 868                                                 struct nvme_queue *nvmeq)
 869 {
 870         struct nvme_command c;
 871         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 872
 873         /*
 874          * Note: we (ab)use the fact the the prp fields survive if no data
 875          * is attached to the request.
 876          */
 877         memset(&c, 0, sizeof(c));
 878         c.create_sq.opcode = nvme_admin_create_sq;
 879         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 880         c.create_sq.sqid = cpu_to_le16(qid);
 881         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 882         c.create_sq.sq_flags = cpu_to_le16(flags);
 883         c.create_sq.cqid = cpu_to_le16(qid);
 884
 885         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 886 }
 887
 888 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 889 {
 890         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 891 }
 892
 893 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 894 {
 895         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 896 }
 897
 898 static void abort_endio(struct request *req, int error)
 899 {
 900         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 901         struct nvme_queue *nvmeq = iod->nvmeq;
 902         u16 status = req->errors;
 903
 904         dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
 905         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 906         blk_mq_free_request(req);
 907 }
 908
 909 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 910 {
 911         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 912         struct nvme_queue *nvmeq = iod->nvmeq;
 913         struct nvme_dev *dev = nvmeq->dev;
 914         struct request *abort_req;
 915         struct nvme_command cmd;
 916
 917         /*
 918          * Shutdown immediately if controller times out while starting. The
 919          * reset work will see the pci device disabled when it gets the forced
 920          * cancellation error. All outstanding requests are completed on
 921          * shutdown, so we return BLK_EH_HANDLED.
 922          */
 923         if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) {
 924                 dev_warn(dev->ctrl.device,
 925                          "I/O %d QID %d timeout, disable controller\n",
 926                          req->tag, nvmeq->qid);
 927                 nvme_dev_disable(dev, false);
 928                 req->errors = NVME_SC_CANCELLED;
 929                 return BLK_EH_HANDLED;
 930         }
 931
 932         /*
 933          * Shutdown the controller immediately and schedule a reset if the
 934          * command was already aborted once before and still hasn't been
 935          * returned to the driver, or if this is the admin queue.
 936          */
 937         if (!nvmeq->qid || iod->aborted) {
 938                 dev_warn(dev->ctrl.device,
 939                          "I/O %d QID %d timeout, reset controller\n",
 940                          req->tag, nvmeq->qid);
 941                 nvme_dev_disable(dev, false);
 942                 queue_work(nvme_workq, &dev->reset_work);
 943
 944                 /*
 945                  * Mark the request as handled, since the inline shutdown
 946                  * forces all outstanding requests to complete.
 947                  */
 948                 req->errors = NVME_SC_CANCELLED;
 949                 return BLK_EH_HANDLED;
 950         }
 951
 952         iod->aborted = 1;
 953
 954         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 955                 atomic_inc(&dev->ctrl.abort_limit);
 956                 return BLK_EH_RESET_TIMER;
 957         }
 958
 959         memset(&cmd, 0, sizeof(cmd));
 960         cmd.abort.opcode = nvme_admin_abort_cmd;
 961         cmd.abort.cid = req->tag;
 962         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 963
 964         dev_warn(nvmeq->dev->ctrl.device,
 965                 "I/O %d QID %d timeout, aborting\n",
 966                  req->tag, nvmeq->qid);
 967
 968         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 969                         BLK_MQ_REQ_NOWAIT);
 970         if (IS_ERR(abort_req)) {
 971                 atomic_inc(&dev->ctrl.abort_limit);
 972                 return BLK_EH_RESET_TIMER;
 973         }
 974
 975         abort_req->timeout = ADMIN_TIMEOUT;
 976         abort_req->end_io_data = NULL;
 977         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 978
 979         /*
 980          * The aborted req will be completed on receiving the abort req.
 981          * We enable the timer again. If hit twice, it'll cause a device reset,
 982          * as the device then is in a faulty state.
 983          */
 984         return BLK_EH_RESET_TIMER;
 985 }
 986
 987 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
 988 {
 989         struct nvme_queue *nvmeq = data;
 990         int status;
 991
 992         if (!blk_mq_request_started(req))
 993                 return;
 994
 995         dev_warn(nvmeq->dev->ctrl.device,
 996                  "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid);
 997
 998         status = NVME_SC_ABORT_REQ;
 999         if (blk_queue_dying(req->q))
1000                 status |= NVME_SC_DNR;
1001         blk_mq_complete_request(req, status);
1002 }
1003
1004 static void nvme_free_queue(struct nvme_queue *nvmeq)
1005 {
1006         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1007                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1008         if (nvmeq->sq_cmds)
1009                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1010                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1011         kfree(nvmeq);
1012 }
1013
1014 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1015 {
1016         int i;
1017
1018         for (i = dev->queue_count - 1; i >= lowest; i--) {
1019                 struct nvme_queue *nvmeq = dev->queues[i];
1020                 dev->queue_count--;
1021                 dev->queues[i] = NULL;
1022                 nvme_free_queue(nvmeq);
1023         }
1024 }
1025
1026 /**
1027  * nvme_suspend_queue - put queue into suspended state
1028  * @nvmeq - queue to suspend
1029  */
1030 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1031 {
1032         int vector;
1033
1034         spin_lock_irq(&nvmeq->q_lock);
1035         if (nvmeq->cq_vector == -1) {
1036                 spin_unlock_irq(&nvmeq->q_lock);
1037                 return 1;
1038         }
1039         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1040         nvmeq->dev->online_queues--;
1041         nvmeq->cq_vector = -1;
1042         spin_unlock_irq(&nvmeq->q_lock);
1043
1044         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1045                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1046
1047         irq_set_affinity_hint(vector, NULL);
1048         free_irq(vector, nvmeq);
1049
1050         return 0;
1051 }
1052
1053 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1054 {
1055         spin_lock_irq(&nvmeq->q_lock);
1056         if (nvmeq->tags && *nvmeq->tags)
1057                 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1058         spin_unlock_irq(&nvmeq->q_lock);
1059 }
1060
1061 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1062 {
1063         struct nvme_queue *nvmeq = dev->queues[0];
1064
1065         if (!nvmeq)
1066                 return;
1067         if (nvme_suspend_queue(nvmeq))
1068                 return;
1069
1070         if (shutdown)
1071                 nvme_shutdown_ctrl(&dev->ctrl);
1072         else
1073                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1074                                                 dev->bar + NVME_REG_CAP));
1075
1076         spin_lock_irq(&nvmeq->q_lock);
1077         nvme_process_cq(nvmeq);
1078         spin_unlock_irq(&nvmeq->q_lock);
1079 }
1080
1081 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1082                                 int entry_size)
1083 {
1084         int q_depth = dev->q_depth;
1085         unsigned q_size_aligned = roundup(q_depth * entry_size,
1086                                           dev->ctrl.page_size);
1087
1088         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1089                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1090                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1091                 q_depth = div_u64(mem_per_q, entry_size);
1092
1093                 /*
1094                  * Ensure the reduced q_depth is above some threshold where it
1095                  * would be better to map queues in system memory with the
1096                  * original depth
1097                  */
1098                 if (q_depth < 64)
1099                         return -ENOMEM;
1100         }
1101
1102         return q_depth;
1103 }
1104
1105 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1106                                 int qid, int depth)
1107 {
1108         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1109                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1110                                                       dev->ctrl.page_size);
1111                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1112                 nvmeq->sq_cmds_io = dev->cmb + offset;
1113         } else {
1114                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1115                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1116                 if (!nvmeq->sq_cmds)
1117                         return -ENOMEM;
1118         }
1119
1120         return 0;
1121 }
1122
1123 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1124                                                         int depth)
1125 {
1126         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1127         if (!nvmeq)
1128                 return NULL;
1129
1130         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1131                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1132         if (!nvmeq->cqes)
1133                 goto free_nvmeq;
1134
1135         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1136                 goto free_cqdma;
1137
1138         nvmeq->q_dmadev = dev->dev;
1139         nvmeq->dev = dev;
1140         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1141                         dev->ctrl.instance, qid);
1142         spin_lock_init(&nvmeq->q_lock);
1143         nvmeq->cq_head = 0;
1144         nvmeq->cq_phase = 1;
1145         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1146         nvmeq->q_depth = depth;
1147         nvmeq->qid = qid;
1148         nvmeq->cq_vector = -1;
1149         dev->queues[qid] = nvmeq;
1150         dev->queue_count++;
1151
1152         return nvmeq;
1153
1154  free_cqdma:
1155         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1156                                                         nvmeq->cq_dma_addr);
1157  free_nvmeq:
1158         kfree(nvmeq);
1159         return NULL;
1160 }
1161
1162 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1163                                                         const char *name)
1164 {
1165         if (use_threaded_interrupts)
1166                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1167                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1168                                         name, nvmeq);
1169         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1170                                 IRQF_SHARED, name, nvmeq);
1171 }
1172
1173 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1174 {
1175         struct nvme_dev *dev = nvmeq->dev;
1176
1177         spin_lock_irq(&nvmeq->q_lock);
1178         nvmeq->sq_tail = 0;
1179         nvmeq->cq_head = 0;
1180         nvmeq->cq_phase = 1;
1181         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1182         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1183         dev->online_queues++;
1184         spin_unlock_irq(&nvmeq->q_lock);
1185 }
1186
1187 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1188 {
1189         struct nvme_dev *dev = nvmeq->dev;
1190         int result;
1191
1192         nvmeq->cq_vector = qid - 1;
1193         result = adapter_alloc_cq(dev, qid, nvmeq);
1194         if (result < 0)
1195                 return result;
1196
1197         result = adapter_alloc_sq(dev, qid, nvmeq);
1198         if (result < 0)
1199                 goto release_cq;
1200
1201         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1202         if (result < 0)
1203                 goto release_sq;
1204
1205         nvme_init_queue(nvmeq, qid);
1206         return result;
1207
1208  release_sq:
1209         adapter_delete_sq(dev, qid);
1210  release_cq:
1211         adapter_delete_cq(dev, qid);
1212         return result;
1213 }
1214
1215 static struct blk_mq_ops nvme_mq_admin_ops = {
1216         .queue_rq       = nvme_queue_rq,
1217         .complete       = nvme_complete_rq,
1218         .map_queue      = blk_mq_map_queue,
1219         .init_hctx      = nvme_admin_init_hctx,
1220         .exit_hctx      = nvme_admin_exit_hctx,
1221         .init_request   = nvme_admin_init_request,
1222         .timeout        = nvme_timeout,
1223 };
1224
1225 static struct blk_mq_ops nvme_mq_ops = {
1226         .queue_rq       = nvme_queue_rq,
1227         .complete       = nvme_complete_rq,
1228         .map_queue      = blk_mq_map_queue,
1229         .init_hctx      = nvme_init_hctx,
1230         .init_request   = nvme_init_request,
1231         .timeout        = nvme_timeout,
1232         .poll           = nvme_poll,
1233 };
1234
1235 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1236 {
1237         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1238                 blk_cleanup_queue(dev->ctrl.admin_q);
1239                 blk_mq_free_tag_set(&dev->admin_tagset);
1240         }
1241 }
1242
1243 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1244 {
1245         if (!dev->ctrl.admin_q) {
1246                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1247                 dev->admin_tagset.nr_hw_queues = 1;
1248
1249                 /*
1250                  * Subtract one to leave an empty queue entry for 'Full Queue'
1251                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1252                  */
1253                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1254                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1255                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1256                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1257                 dev->admin_tagset.driver_data = dev;
1258
1259                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1260                         return -ENOMEM;
1261
1262                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1263                 if (IS_ERR(dev->ctrl.admin_q)) {
1264                         blk_mq_free_tag_set(&dev->admin_tagset);
1265                         return -ENOMEM;
1266                 }
1267                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1268                         nvme_dev_remove_admin(dev);
1269                         dev->ctrl.admin_q = NULL;
1270                         return -ENODEV;
1271                 }
1272         } else
1273                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1274
1275         return 0;
1276 }
1277
1278 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1279 {
1280         int result;
1281         u32 aqa;
1282         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1283         struct nvme_queue *nvmeq;
1284
1285         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1286                                                 NVME_CAP_NSSRC(cap) : 0;
1287
1288         if (dev->subsystem &&
1289             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1290                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1291
1292         result = nvme_disable_ctrl(&dev->ctrl, cap);
1293         if (result < 0)
1294                 return result;
1295
1296         nvmeq = dev->queues[0];
1297         if (!nvmeq) {
1298                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1299                 if (!nvmeq)
1300                         return -ENOMEM;
1301         }
1302
1303         aqa = nvmeq->q_depth - 1;
1304         aqa |= aqa << 16;
1305
1306         writel(aqa, dev->bar + NVME_REG_AQA);
1307         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1308         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1309
1310         result = nvme_enable_ctrl(&dev->ctrl, cap);
1311         if (result)
1312                 goto free_nvmeq;
1313
1314         nvmeq->cq_vector = 0;
1315         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1316         if (result) {
1317                 nvmeq->cq_vector = -1;
1318                 goto free_nvmeq;
1319         }
1320
1321         return result;
1322
1323  free_nvmeq:
1324         nvme_free_queues(dev, 0);
1325         return result;
1326 }
1327
1328 static void nvme_watchdog_timer(unsigned long data)
1329 {
1330         struct nvme_dev *dev = (struct nvme_dev *)data;
1331         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1332
1333         /*
1334          * Skip controllers currently under reset.
1335          */
1336         if (!work_pending(&dev->reset_work) && !work_busy(&dev->reset_work) &&
1337             ((csts & NVME_CSTS_CFS) ||
1338              (dev->subsystem && (csts & NVME_CSTS_NSSRO)))) {
1339                 if (queue_work(nvme_workq, &dev->reset_work)) {
1340                         dev_warn(dev->dev,
1341                                 "Failed status: 0x%x, reset controller.\n",
1342                                 csts);
1343                 }
1344                 return;
1345         }
1346
1347         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1348 }
1349
1350 static int nvme_create_io_queues(struct nvme_dev *dev)
1351 {
1352         unsigned i, max;
1353         int ret = 0;
1354
1355         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1356                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1357                         ret = -ENOMEM;
1358                         break;
1359                 }
1360         }
1361
1362         max = min(dev->max_qid, dev->queue_count - 1);
1363         for (i = dev->online_queues; i <= max; i++) {
1364                 ret = nvme_create_queue(dev->queues[i], i);
1365                 if (ret) {
1366                         nvme_free_queues(dev, i);
1367                         break;
1368                 }
1369         }
1370
1371         /*
1372          * Ignore failing Create SQ/CQ commands, we can continue with less
1373          * than the desired aount of queues, and even a controller without
1374          * I/O queues an still be used to issue admin commands.  This might
1375          * be useful to upgrade a buggy firmware for example.
1376          */
1377         return ret >= 0 ? 0 : ret;
1378 }
1379
1380 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1381 {
1382         u64 szu, size, offset;
1383         u32 cmbloc;
1384         resource_size_t bar_size;
1385         struct pci_dev *pdev = to_pci_dev(dev->dev);
1386         void __iomem *cmb;
1387         dma_addr_t dma_addr;
1388
1389         if (!use_cmb_sqes)
1390                 return NULL;
1391
1392         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1393         if (!(NVME_CMB_SZ(dev->cmbsz)))
1394                 return NULL;
1395
1396         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1397
1398         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1399         size = szu * NVME_CMB_SZ(dev->cmbsz);
1400         offset = szu * NVME_CMB_OFST(cmbloc);
1401         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1402
1403         if (offset > bar_size)
1404                 return NULL;
1405
1406         /*
1407          * Controllers may support a CMB size larger than their BAR,
1408          * for example, due to being behind a bridge. Reduce the CMB to
1409          * the reported size of the BAR
1410          */
1411         if (size > bar_size - offset)
1412                 size = bar_size - offset;
1413
1414         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1415         cmb = ioremap_wc(dma_addr, size);
1416         if (!cmb)
1417                 return NULL;
1418
1419         dev->cmb_dma_addr = dma_addr;
1420         dev->cmb_size = size;
1421         return cmb;
1422 }
1423
1424 static inline void nvme_release_cmb(struct nvme_dev *dev)
1425 {
1426         if (dev->cmb) {
1427                 iounmap(dev->cmb);
1428                 dev->cmb = NULL;
1429         }
1430 }
1431
1432 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1433 {
1434         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1435 }
1436
1437 static int nvme_setup_io_queues(struct nvme_dev *dev)
1438 {
1439         struct nvme_queue *adminq = dev->queues[0];
1440         struct pci_dev *pdev = to_pci_dev(dev->dev);
1441         int result, i, vecs, nr_io_queues, size;
1442
1443         nr_io_queues = num_possible_cpus();
1444         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1445         if (result < 0)
1446                 return result;
1447
1448         /*
1449          * Degraded controllers might return an error when setting the queue
1450          * count.  We still want to be able to bring them online and offer
1451          * access to the admin queue, as that might be only way to fix them up.
1452          */
1453         if (result > 0) {
1454                 dev_err(dev->ctrl.device,
1455                         "Could not set queue count (%d)\n", result);
1456                 nr_io_queues = 0;
1457                 result = 0;
1458         }
1459
1460         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1461                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1462                                 sizeof(struct nvme_command));
1463                 if (result > 0)
1464                         dev->q_depth = result;
1465                 else
1466                         nvme_release_cmb(dev);
1467         }
1468
1469         size = db_bar_size(dev, nr_io_queues);
1470         if (size > 8192) {
1471                 iounmap(dev->bar);
1472                 do {
1473                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1474                         if (dev->bar)
1475                                 break;
1476                         if (!--nr_io_queues)
1477                                 return -ENOMEM;
1478                         size = db_bar_size(dev, nr_io_queues);
1479                 } while (1);
1480                 dev->dbs = dev->bar + 4096;
1481                 adminq->q_db = dev->dbs;
1482         }
1483
1484         /* Deregister the admin queue's interrupt */
1485         free_irq(dev->entry[0].vector, adminq);
1486
1487         /*
1488          * If we enable msix early due to not intx, disable it again before
1489          * setting up the full range we need.
1490          */
1491         if (!pdev->irq)
1492                 pci_disable_msix(pdev);
1493
1494         for (i = 0; i < nr_io_queues; i++)
1495                 dev->entry[i].entry = i;
1496         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1497         if (vecs < 0) {
1498                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1499                 if (vecs < 0) {
1500                         vecs = 1;
1501                 } else {
1502                         for (i = 0; i < vecs; i++)
1503                                 dev->entry[i].vector = i + pdev->irq;
1504                 }
1505         }
1506
1507         /*
1508          * Should investigate if there's a performance win from allocating
1509          * more queues than interrupt vectors; it might allow the submission
1510          * path to scale better, even if the receive path is limited by the
1511          * number of interrupts.
1512          */
1513         nr_io_queues = vecs;
1514         dev->max_qid = nr_io_queues;
1515
1516         result = queue_request_irq(dev, adminq, adminq->irqname);
1517         if (result) {
1518                 adminq->cq_vector = -1;
1519                 goto free_queues;
1520         }
1521         return nvme_create_io_queues(dev);
1522
1523  free_queues:
1524         nvme_free_queues(dev, 1);
1525         return result;
1526 }
1527
1528 static void nvme_set_irq_hints(struct nvme_dev *dev)
1529 {
1530         struct nvme_queue *nvmeq;
1531         int i;
1532
1533         for (i = 0; i < dev->online_queues; i++) {
1534                 nvmeq = dev->queues[i];
1535
1536                 if (!nvmeq->tags || !(*nvmeq->tags))
1537                         continue;
1538
1539                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1540                                         blk_mq_tags_cpumask(*nvmeq->tags));
1541         }
1542 }
1543
1544 static void nvme_dev_scan(struct work_struct *work)
1545 {
1546         struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1547
1548         if (!dev->tagset.tags)
1549                 return;
1550         nvme_scan_namespaces(&dev->ctrl);
1551         nvme_set_irq_hints(dev);
1552 }
1553
1554 static void nvme_del_queue_end(struct request *req, int error)
1555 {
1556         struct nvme_queue *nvmeq = req->end_io_data;
1557
1558         blk_mq_free_request(req);
1559         complete(&nvmeq->dev->ioq_wait);
1560 }
1561
1562 static void nvme_del_cq_end(struct request *req, int error)
1563 {
1564         struct nvme_queue *nvmeq = req->end_io_data;
1565
1566         if (!error) {
1567                 unsigned long flags;
1568
1569                 spin_lock_irqsave(&nvmeq->q_lock, flags);
1570                 nvme_process_cq(nvmeq);
1571                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1572         }
1573
1574         nvme_del_queue_end(req, error);
1575 }
1576
1577 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1578 {
1579         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1580         struct request *req;
1581         struct nvme_command cmd;
1582
1583         memset(&cmd, 0, sizeof(cmd));
1584         cmd.delete_queue.opcode = opcode;
1585         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1586
1587         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
1588         if (IS_ERR(req))
1589                 return PTR_ERR(req);
1590
1591         req->timeout = ADMIN_TIMEOUT;
1592         req->end_io_data = nvmeq;
1593
1594         blk_execute_rq_nowait(q, NULL, req, false,
1595                         opcode == nvme_admin_delete_cq ?
1596                                 nvme_del_cq_end : nvme_del_queue_end);
1597         return 0;
1598 }
1599
1600 static void nvme_disable_io_queues(struct nvme_dev *dev)
1601 {
1602         int pass;
1603         unsigned long timeout;
1604         u8 opcode = nvme_admin_delete_sq;
1605
1606         for (pass = 0; pass < 2; pass++) {
1607                 int sent = 0, i = dev->queue_count - 1;
1608
1609                 reinit_completion(&dev->ioq_wait);
1610  retry:
1611                 timeout = ADMIN_TIMEOUT;
1612                 for (; i > 0; i--) {
1613                         struct nvme_queue *nvmeq = dev->queues[i];
1614
1615                         if (!pass)
1616                                 nvme_suspend_queue(nvmeq);
1617                         if (nvme_delete_queue(nvmeq, opcode))
1618                                 break;
1619                         ++sent;
1620                 }
1621                 while (sent--) {
1622                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1623                         if (timeout == 0)
1624                                 return;
1625                         if (i)
1626                                 goto retry;
1627                 }
1628                 opcode = nvme_admin_delete_cq;
1629         }
1630 }
1631
1632 /*
1633  * Return: error value if an error occurred setting up the queues or calling
1634  * Identify Device.  0 if these succeeded, even if adding some of the
1635  * namespaces failed.  At the moment, these failures are silent.  TBD which
1636  * failures should be reported.
1637  */
1638 static int nvme_dev_add(struct nvme_dev *dev)
1639 {
1640         if (!dev->ctrl.tagset) {
1641                 dev->tagset.ops = &nvme_mq_ops;
1642                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1643                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1644                 dev->tagset.numa_node = dev_to_node(dev->dev);
1645                 dev->tagset.queue_depth =
1646                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1647                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1648                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1649                 dev->tagset.driver_data = dev;
1650
1651                 if (blk_mq_alloc_tag_set(&dev->tagset))
1652                         return 0;
1653                 dev->ctrl.tagset = &dev->tagset;
1654         } else {
1655                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1656
1657                 /* Free previously allocated queues that are no longer usable */
1658                 nvme_free_queues(dev, dev->online_queues);
1659         }
1660
1661         queue_work(nvme_workq, &dev->scan_work);
1662         return 0;
1663 }
1664
1665 static int nvme_dev_map(struct nvme_dev *dev)
1666 {
1667         u64 cap;
1668         int bars, result = -ENOMEM;
1669         struct pci_dev *pdev = to_pci_dev(dev->dev);
1670
1671         if (pci_enable_device_mem(pdev))
1672                 return result;
1673
1674         dev->entry[0].vector = pdev->irq;
1675         pci_set_master(pdev);
1676         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1677         if (!bars)
1678                 goto disable_pci;
1679
1680         if (pci_request_selected_regions(pdev, bars, "nvme"))
1681                 goto disable_pci;
1682
1683         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1684             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1685                 goto disable;
1686
1687         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1688         if (!dev->bar)
1689                 goto disable;
1690
1691         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1692                 result = -ENODEV;
1693                 goto unmap;
1694         }
1695
1696         /*
1697          * Some devices don't advertse INTx interrupts, pre-enable a single
1698          * MSIX vec for setup. We'll adjust this later.
1699          */
1700         if (!pdev->irq) {
1701                 result = pci_enable_msix(pdev, dev->entry, 1);
1702                 if (result < 0)
1703                         goto unmap;
1704         }
1705
1706         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1707
1708         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1709         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1710         dev->dbs = dev->bar + 4096;
1711
1712         /*
1713          * Temporary fix for the Apple controller found in the MacBook8,1 and
1714          * some MacBook7,1 to avoid controller resets and data loss.
1715          */
1716         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1717                 dev->q_depth = 2;
1718                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1719                         "queue depth=%u to work around controller resets\n",
1720                         dev->q_depth);
1721         }
1722
1723         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1724                 dev->cmb = nvme_map_cmb(dev);
1725
1726         pci_enable_pcie_error_reporting(pdev);
1727         pci_save_state(pdev);
1728         return 0;
1729
1730  unmap:
1731         iounmap(dev->bar);
1732         dev->bar = NULL;
1733  disable:
1734         pci_release_regions(pdev);
1735  disable_pci:
1736         pci_disable_device(pdev);
1737         return result;
1738 }
1739
1740 static void nvme_dev_unmap(struct nvme_dev *dev)
1741 {
1742         struct pci_dev *pdev = to_pci_dev(dev->dev);
1743
1744         if (pdev->msi_enabled)
1745                 pci_disable_msi(pdev);
1746         else if (pdev->msix_enabled)
1747                 pci_disable_msix(pdev);
1748
1749         if (dev->bar) {
1750                 iounmap(dev->bar);
1751                 dev->bar = NULL;
1752                 pci_release_regions(pdev);
1753         }
1754
1755         if (pci_is_enabled(pdev)) {
1756                 pci_disable_pcie_error_reporting(pdev);
1757                 pci_disable_device(pdev);
1758         }
1759 }
1760
1761 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1762 {
1763         int i;
1764         u32 csts = -1;
1765
1766         del_timer_sync(&dev->watchdog_timer);
1767
1768         mutex_lock(&dev->shutdown_lock);
1769         if (dev->bar) {
1770                 nvme_stop_queues(&dev->ctrl);
1771                 csts = readl(dev->bar + NVME_REG_CSTS);
1772         }
1773         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1774                 for (i = dev->queue_count - 1; i >= 0; i--) {
1775                         struct nvme_queue *nvmeq = dev->queues[i];
1776                         nvme_suspend_queue(nvmeq);
1777                 }
1778         } else {
1779                 nvme_disable_io_queues(dev);
1780                 nvme_disable_admin_queue(dev, shutdown);
1781         }
1782         nvme_dev_unmap(dev);
1783
1784         for (i = dev->queue_count - 1; i >= 0; i--)
1785                 nvme_clear_queue(dev->queues[i]);
1786         mutex_unlock(&dev->shutdown_lock);
1787 }
1788
1789 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1790 {
1791         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1792                                                 PAGE_SIZE, PAGE_SIZE, 0);
1793         if (!dev->prp_page_pool)
1794                 return -ENOMEM;
1795
1796         /* Optimisation for I/Os between 4k and 128k */
1797         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1798                                                 256, 256, 0);
1799         if (!dev->prp_small_pool) {
1800                 dma_pool_destroy(dev->prp_page_pool);
1801                 return -ENOMEM;
1802         }
1803         return 0;
1804 }
1805
1806 static void nvme_release_prp_pools(struct nvme_dev *dev)
1807 {
1808         dma_pool_destroy(dev->prp_page_pool);
1809         dma_pool_destroy(dev->prp_small_pool);
1810 }
1811
1812 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1813 {
1814         struct nvme_dev *dev = to_nvme_dev(ctrl);
1815
1816         put_device(dev->dev);
1817         if (dev->tagset.tags)
1818                 blk_mq_free_tag_set(&dev->tagset);
1819         if (dev->ctrl.admin_q)
1820                 blk_put_queue(dev->ctrl.admin_q);
1821         kfree(dev->queues);
1822         kfree(dev->entry);
1823         kfree(dev);
1824 }
1825
1826 static void nvme_reset_work(struct work_struct *work)
1827 {
1828         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1829         int result;
1830
1831         if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags)))
1832                 goto out;
1833
1834         /*
1835          * If we're called to reset a live controller first shut it down before
1836          * moving on.
1837          */
1838         if (dev->bar)
1839                 nvme_dev_disable(dev, false);
1840
1841         set_bit(NVME_CTRL_RESETTING, &dev->flags);
1842
1843         result = nvme_dev_map(dev);
1844         if (result)
1845                 goto out;
1846
1847         result = nvme_configure_admin_queue(dev);
1848         if (result)
1849                 goto unmap;
1850
1851         nvme_init_queue(dev->queues[0], 0);
1852         result = nvme_alloc_admin_tags(dev);
1853         if (result)
1854                 goto disable;
1855
1856         result = nvme_init_identify(&dev->ctrl);
1857         if (result)
1858                 goto free_tags;
1859
1860         result = nvme_setup_io_queues(dev);
1861         if (result)
1862                 goto free_tags;
1863
1864         dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS;
1865         queue_work(nvme_workq, &dev->async_work);
1866
1867         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1868
1869         /*
1870          * Keep the controller around but remove all namespaces if we don't have
1871          * any working I/O queue.
1872          */
1873         if (dev->online_queues < 2) {
1874                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1875                 nvme_remove_namespaces(&dev->ctrl);
1876         } else {
1877                 nvme_start_queues(&dev->ctrl);
1878                 nvme_dev_add(dev);
1879         }
1880
1881         clear_bit(NVME_CTRL_RESETTING, &dev->flags);
1882         return;
1883
1884  free_tags:
1885         nvme_dev_remove_admin(dev);
1886         blk_put_queue(dev->ctrl.admin_q);
1887         dev->ctrl.admin_q = NULL;
1888         dev->queues[0]->tags = NULL;
1889  disable:
1890         nvme_disable_admin_queue(dev, false);
1891  unmap:
1892         nvme_dev_unmap(dev);
1893  out:
1894         nvme_remove_dead_ctrl(dev);
1895 }
1896
1897 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1898 {
1899         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1900         struct pci_dev *pdev = to_pci_dev(dev->dev);
1901
1902         if (pci_get_drvdata(pdev))
1903                 pci_stop_and_remove_bus_device_locked(pdev);
1904         nvme_put_ctrl(&dev->ctrl);
1905 }
1906
1907 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
1908 {
1909         dev_warn(dev->ctrl.device, "Removing after probe failure\n");
1910         kref_get(&dev->ctrl.kref);
1911         if (!schedule_work(&dev->remove_work))
1912                 nvme_put_ctrl(&dev->ctrl);
1913 }
1914
1915 static int nvme_reset(struct nvme_dev *dev)
1916 {
1917         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1918                 return -ENODEV;
1919
1920         if (!queue_work(nvme_workq, &dev->reset_work))
1921                 return -EBUSY;
1922
1923         flush_work(&dev->reset_work);
1924         return 0;
1925 }
1926
1927 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1928 {
1929         *val = readl(to_nvme_dev(ctrl)->bar + off);
1930         return 0;
1931 }
1932
1933 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1934 {
1935         writel(val, to_nvme_dev(ctrl)->bar + off);
1936         return 0;
1937 }
1938
1939 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1940 {
1941         *val = readq(to_nvme_dev(ctrl)->bar + off);
1942         return 0;
1943 }
1944
1945 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl)
1946 {
1947         struct nvme_dev *dev = to_nvme_dev(ctrl);
1948
1949         return !dev->bar || dev->online_queues < 2;
1950 }
1951
1952 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1953 {
1954         return nvme_reset(to_nvme_dev(ctrl));
1955 }
1956
1957 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1958         .module                 = THIS_MODULE,
1959         .reg_read32             = nvme_pci_reg_read32,
1960         .reg_write32            = nvme_pci_reg_write32,
1961         .reg_read64             = nvme_pci_reg_read64,
1962         .io_incapable           = nvme_pci_io_incapable,
1963         .reset_ctrl             = nvme_pci_reset_ctrl,
1964         .free_ctrl              = nvme_pci_free_ctrl,
1965 };
1966
1967 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1968 {
1969         int node, result = -ENOMEM;
1970         struct nvme_dev *dev;
1971
1972         node = dev_to_node(&pdev->dev);
1973         if (node == NUMA_NO_NODE)
1974                 set_dev_node(&pdev->dev, 0);
1975
1976         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1977         if (!dev)
1978                 return -ENOMEM;
1979         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
1980                                                         GFP_KERNEL, node);
1981         if (!dev->entry)
1982                 goto free;
1983         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1984                                                         GFP_KERNEL, node);
1985         if (!dev->queues)
1986                 goto free;
1987
1988         dev->dev = get_device(&pdev->dev);
1989         pci_set_drvdata(pdev, dev);
1990
1991         INIT_WORK(&dev->scan_work, nvme_dev_scan);
1992         INIT_WORK(&dev->reset_work, nvme_reset_work);
1993         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1994         INIT_WORK(&dev->async_work, nvme_async_event_work);
1995         setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1996                 (unsigned long)dev);
1997         mutex_init(&dev->shutdown_lock);
1998         init_completion(&dev->ioq_wait);
1999
2000         result = nvme_setup_prp_pools(dev);
2001         if (result)
2002                 goto put_pci;
2003
2004         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2005                         id->driver_data);
2006         if (result)
2007                 goto release_pools;
2008
2009         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2010
2011         queue_work(nvme_workq, &dev->reset_work);
2012         return 0;
2013
2014  release_pools:
2015         nvme_release_prp_pools(dev);
2016  put_pci:
2017         put_device(dev->dev);
2018  free:
2019         kfree(dev->queues);
2020         kfree(dev->entry);
2021         kfree(dev);
2022         return result;
2023 }
2024
2025 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2026 {
2027         struct nvme_dev *dev = pci_get_drvdata(pdev);
2028
2029         if (prepare)
2030                 nvme_dev_disable(dev, false);
2031         else
2032                 queue_work(nvme_workq, &dev->reset_work);
2033 }
2034
2035 static void nvme_shutdown(struct pci_dev *pdev)
2036 {
2037         struct nvme_dev *dev = pci_get_drvdata(pdev);
2038         nvme_dev_disable(dev, true);
2039 }
2040
2041 static void nvme_remove(struct pci_dev *pdev)
2042 {
2043         struct nvme_dev *dev = pci_get_drvdata(pdev);
2044
2045         del_timer_sync(&dev->watchdog_timer);
2046
2047         pci_set_drvdata(pdev, NULL);
2048         flush_work(&dev->async_work);
2049         flush_work(&dev->reset_work);
2050         flush_work(&dev->scan_work);
2051         nvme_remove_namespaces(&dev->ctrl);
2052         nvme_uninit_ctrl(&dev->ctrl);
2053         nvme_dev_disable(dev, true);
2054         nvme_dev_remove_admin(dev);
2055         nvme_free_queues(dev, 0);
2056         nvme_release_cmb(dev);
2057         nvme_release_prp_pools(dev);
2058         nvme_put_ctrl(&dev->ctrl);
2059 }
2060
2061 #ifdef CONFIG_PM_SLEEP
2062 static int nvme_suspend(struct device *dev)
2063 {
2064         struct pci_dev *pdev = to_pci_dev(dev);
2065         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2066
2067         nvme_dev_disable(ndev, true);
2068         return 0;
2069 }
2070
2071 static int nvme_resume(struct device *dev)
2072 {
2073         struct pci_dev *pdev = to_pci_dev(dev);
2074         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2075
2076         queue_work(nvme_workq, &ndev->reset_work);
2077         return 0;
2078 }
2079 #endif
2080
2081 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2082
2083 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2084                                                 pci_channel_state_t state)
2085 {
2086         struct nvme_dev *dev = pci_get_drvdata(pdev);
2087
2088         /*
2089          * A frozen channel requires a reset. When detected, this method will
2090          * shutdown the controller to quiesce. The controller will be restarted
2091          * after the slot reset through driver's slot_reset callback.
2092          */
2093         dev_warn(dev->ctrl.device, "error detected: state:%d\n", state);
2094         switch (state) {
2095         case pci_channel_io_normal:
2096                 return PCI_ERS_RESULT_CAN_RECOVER;
2097         case pci_channel_io_frozen:
2098                 nvme_dev_disable(dev, false);
2099                 return PCI_ERS_RESULT_NEED_RESET;
2100         case pci_channel_io_perm_failure:
2101                 return PCI_ERS_RESULT_DISCONNECT;
2102         }
2103         return PCI_ERS_RESULT_NEED_RESET;
2104 }
2105
2106 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2107 {
2108         struct nvme_dev *dev = pci_get_drvdata(pdev);
2109
2110         dev_info(dev->ctrl.device, "restart after slot reset\n");
2111         pci_restore_state(pdev);
2112         queue_work(nvme_workq, &dev->reset_work);
2113         return PCI_ERS_RESULT_RECOVERED;
2114 }
2115
2116 static void nvme_error_resume(struct pci_dev *pdev)
2117 {
2118         pci_cleanup_aer_uncorrect_error_status(pdev);
2119 }
2120
2121 static const struct pci_error_handlers nvme_err_handler = {
2122         .error_detected = nvme_error_detected,
2123         .slot_reset     = nvme_slot_reset,
2124         .resume         = nvme_error_resume,
2125         .reset_notify   = nvme_reset_notify,
2126 };
2127
2128 /* Move to pci_ids.h later */
2129 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2130
2131 static const struct pci_device_id nvme_id_table[] = {
2132         { PCI_VDEVICE(INTEL, 0x0953),
2133                 .driver_data = NVME_QUIRK_STRIPE_SIZE, },
2134         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2135                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2136         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2137         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2138         { 0, }
2139 };
2140 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2141
2142 static struct pci_driver nvme_driver = {
2143         .name           = "nvme",
2144         .id_table       = nvme_id_table,
2145         .probe          = nvme_probe,
2146         .remove         = nvme_remove,
2147         .shutdown       = nvme_shutdown,
2148         .driver         = {
2149                 .pm     = &nvme_dev_pm_ops,
2150         },
2151         .err_handler    = &nvme_err_handler,
2152 };
2153
2154 static int __init nvme_init(void)
2155 {
2156         int result;
2157
2158         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2159         if (!nvme_workq)
2160                 return -ENOMEM;
2161
2162         result = pci_register_driver(&nvme_driver);
2163         if (result)
2164                 destroy_workqueue(nvme_workq);
2165         return result;
2166 }
2167
2168 static void __exit nvme_exit(void)
2169 {
2170         pci_unregister_driver(&nvme_driver);
2171         destroy_workqueue(nvme_workq);
2172         _nvme_check_size();
2173 }
2174
2175 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2176 MODULE_LICENSE("GPL");
2177 MODULE_VERSION("1.0");
2178 module_init(nvme_init);
2179 module_exit(nvme_exit);