2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/pci.h>
28 #include <linux/poison.h>
29 #include <linux/t10-pi.h>
30 #include <linux/timer.h>
31 #include <linux/types.h>
32 #include <linux/io-64-nonatomic-lo-hi.h>
33 #include <asm/unaligned.h>
34 #include <linux/sed-opal.h>
38 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
39 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
42 * We handle AEN commands ourselves and don't even let the
43 * block layer know about them.
45 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
47 static int use_threaded_interrupts;
48 module_param(use_threaded_interrupts, int, 0);
50 static bool use_cmb_sqes = true;
51 module_param(use_cmb_sqes, bool, 0644);
52 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54 static unsigned int max_host_mem_size_mb = 128;
55 module_param(max_host_mem_size_mb, uint, 0444);
56 MODULE_PARM_DESC(max_host_mem_size_mb,
57 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
59 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
60 static const struct kernel_param_ops io_queue_depth_ops = {
61 .set = io_queue_depth_set,
65 static int io_queue_depth = 1024;
66 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
67 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
72 static void nvme_process_cq(struct nvme_queue *nvmeq);
73 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
76 * Represents an NVM Express device. Each nvme_dev is a PCI function.
79 struct nvme_queue **queues;
80 struct blk_mq_tag_set tagset;
81 struct blk_mq_tag_set admin_tagset;
84 struct dma_pool *prp_page_pool;
85 struct dma_pool *prp_small_pool;
86 unsigned online_queues;
91 unsigned long bar_mapped_size;
92 struct work_struct remove_work;
93 struct mutex shutdown_lock;
96 dma_addr_t cmb_dma_addr;
100 struct nvme_ctrl ctrl;
101 struct completion ioq_wait;
103 /* shadow doorbell buffer support: */
105 dma_addr_t dbbuf_dbs_dma_addr;
107 dma_addr_t dbbuf_eis_dma_addr;
109 /* host memory buffer support: */
111 u32 nr_host_mem_descs;
112 struct nvme_host_mem_buf_desc *host_mem_descs;
113 void **host_mem_desc_bufs;
116 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
120 ret = kstrtoint(val, 10, &n);
121 if (ret != 0 || n < 2)
124 return param_set_int(val, kp);
127 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
129 return qid * 2 * stride;
132 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
134 return (qid * 2 + 1) * stride;
137 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
139 return container_of(ctrl, struct nvme_dev, ctrl);
143 * An NVM Express queue. Each device has at least two (one for admin
144 * commands and one for I/O commands).
147 struct device *q_dmadev;
148 struct nvme_dev *dev;
150 struct nvme_command *sq_cmds;
151 struct nvme_command __iomem *sq_cmds_io;
152 volatile struct nvme_completion *cqes;
153 struct blk_mq_tags **tags;
154 dma_addr_t sq_dma_addr;
155 dma_addr_t cq_dma_addr;
171 * The nvme_iod describes the data in an I/O, including the list of PRP
172 * entries. You can't see it in this data structure because C doesn't let
173 * me express that. Use nvme_init_iod to ensure there's enough space
174 * allocated to store the PRP list.
177 struct nvme_request req;
178 struct nvme_queue *nvmeq;
180 int npages; /* In the PRP list. 0 means small pool in use */
181 int nents; /* Used in scatterlist */
182 int length; /* Of data, in bytes */
183 dma_addr_t first_dma;
184 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
185 struct scatterlist *sg;
186 struct scatterlist inline_sg[0];
190 * Check we didin't inadvertently grow the command struct
192 static inline void _nvme_check_size(void)
194 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
195 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
203 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
204 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
205 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
206 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
209 static inline unsigned int nvme_dbbuf_size(u32 stride)
211 return ((num_possible_cpus() + 1) * 8 * stride);
214 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
216 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
221 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
222 &dev->dbbuf_dbs_dma_addr,
226 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
227 &dev->dbbuf_eis_dma_addr,
229 if (!dev->dbbuf_eis) {
230 dma_free_coherent(dev->dev, mem_size,
231 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
232 dev->dbbuf_dbs = NULL;
239 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
241 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
243 if (dev->dbbuf_dbs) {
244 dma_free_coherent(dev->dev, mem_size,
245 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
246 dev->dbbuf_dbs = NULL;
248 if (dev->dbbuf_eis) {
249 dma_free_coherent(dev->dev, mem_size,
250 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
251 dev->dbbuf_eis = NULL;
255 static void nvme_dbbuf_init(struct nvme_dev *dev,
256 struct nvme_queue *nvmeq, int qid)
258 if (!dev->dbbuf_dbs || !qid)
261 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
262 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
263 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
264 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
267 static void nvme_dbbuf_set(struct nvme_dev *dev)
269 struct nvme_command c;
274 memset(&c, 0, sizeof(c));
275 c.dbbuf.opcode = nvme_admin_dbbuf;
276 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
277 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
279 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
280 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
281 /* Free memory and continue on */
282 nvme_dbbuf_dma_free(dev);
286 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
288 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
291 /* Update dbbuf and return true if an MMIO is required */
292 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
293 volatile u32 *dbbuf_ei)
299 * Ensure that the queue is written before updating
300 * the doorbell in memory
304 old_value = *dbbuf_db;
307 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
315 * Max size of iod being embedded in the request payload
317 #define NVME_INT_PAGES 2
318 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
321 * Will slightly overestimate the number of pages needed. This is OK
322 * as it only leads to a small amount of wasted memory for the lifetime of
325 static int nvme_npages(unsigned size, struct nvme_dev *dev)
327 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
328 dev->ctrl.page_size);
329 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
332 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
333 unsigned int size, unsigned int nseg)
335 return sizeof(__le64 *) * nvme_npages(size, dev) +
336 sizeof(struct scatterlist) * nseg;
339 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
341 return sizeof(struct nvme_iod) +
342 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
345 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
346 unsigned int hctx_idx)
348 struct nvme_dev *dev = data;
349 struct nvme_queue *nvmeq = dev->queues[0];
351 WARN_ON(hctx_idx != 0);
352 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
353 WARN_ON(nvmeq->tags);
355 hctx->driver_data = nvmeq;
356 nvmeq->tags = &dev->admin_tagset.tags[0];
360 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
362 struct nvme_queue *nvmeq = hctx->driver_data;
367 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
368 unsigned int hctx_idx)
370 struct nvme_dev *dev = data;
371 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
374 nvmeq->tags = &dev->tagset.tags[hctx_idx];
376 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
377 hctx->driver_data = nvmeq;
381 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
382 unsigned int hctx_idx, unsigned int numa_node)
384 struct nvme_dev *dev = set->driver_data;
385 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
386 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
387 struct nvme_queue *nvmeq = dev->queues[queue_idx];
394 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
396 struct nvme_dev *dev = set->driver_data;
398 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
402 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
403 * @nvmeq: The queue to use
404 * @cmd: The command to send
406 * Safe to use from interrupt context
408 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
409 struct nvme_command *cmd)
411 u16 tail = nvmeq->sq_tail;
413 if (nvmeq->sq_cmds_io)
414 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
416 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
418 if (++tail == nvmeq->q_depth)
420 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
422 writel(tail, nvmeq->q_db);
423 nvmeq->sq_tail = tail;
426 static __le64 **iod_list(struct request *req)
428 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
429 return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
432 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
434 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
435 int nseg = blk_rq_nr_phys_segments(rq);
436 unsigned int size = blk_rq_payload_bytes(rq);
438 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
439 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
441 return BLK_STS_RESOURCE;
443 iod->sg = iod->inline_sg;
454 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
456 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
457 const int last_prp = dev->ctrl.page_size / 8 - 1;
459 __le64 **list = iod_list(req);
460 dma_addr_t prp_dma = iod->first_dma;
462 if (iod->npages == 0)
463 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
464 for (i = 0; i < iod->npages; i++) {
465 __le64 *prp_list = list[i];
466 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
467 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
468 prp_dma = next_prp_dma;
471 if (iod->sg != iod->inline_sg)
475 #ifdef CONFIG_BLK_DEV_INTEGRITY
476 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
478 if (be32_to_cpu(pi->ref_tag) == v)
479 pi->ref_tag = cpu_to_be32(p);
482 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
484 if (be32_to_cpu(pi->ref_tag) == p)
485 pi->ref_tag = cpu_to_be32(v);
489 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
491 * The virtual start sector is the one that was originally submitted by the
492 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
493 * start sector may be different. Remap protection information to match the
494 * physical LBA on writes, and back to the original seed on reads.
496 * Type 0 and 3 do not have a ref tag, so no remapping required.
498 static void nvme_dif_remap(struct request *req,
499 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
501 struct nvme_ns *ns = req->rq_disk->private_data;
502 struct bio_integrity_payload *bip;
503 struct t10_pi_tuple *pi;
505 u32 i, nlb, ts, phys, virt;
507 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
510 bip = bio_integrity(req->bio);
514 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
517 virt = bip_get_seed(bip);
518 phys = nvme_block_nr(ns, blk_rq_pos(req));
519 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
520 ts = ns->disk->queue->integrity.tuple_size;
522 for (i = 0; i < nlb; i++, virt++, phys++) {
523 pi = (struct t10_pi_tuple *)p;
524 dif_swap(phys, virt, pi);
529 #else /* CONFIG_BLK_DEV_INTEGRITY */
530 static void nvme_dif_remap(struct request *req,
531 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
534 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
537 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
542 static blk_status_t nvme_setup_prps(struct nvme_dev *dev, struct request *req)
544 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
545 struct dma_pool *pool;
546 int length = blk_rq_payload_bytes(req);
547 struct scatterlist *sg = iod->sg;
548 int dma_len = sg_dma_len(sg);
549 u64 dma_addr = sg_dma_address(sg);
550 u32 page_size = dev->ctrl.page_size;
551 int offset = dma_addr & (page_size - 1);
553 __le64 **list = iod_list(req);
557 length -= (page_size - offset);
561 dma_len -= (page_size - offset);
563 dma_addr += (page_size - offset);
566 dma_addr = sg_dma_address(sg);
567 dma_len = sg_dma_len(sg);
570 if (length <= page_size) {
571 iod->first_dma = dma_addr;
575 nprps = DIV_ROUND_UP(length, page_size);
576 if (nprps <= (256 / 8)) {
577 pool = dev->prp_small_pool;
580 pool = dev->prp_page_pool;
584 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
586 iod->first_dma = dma_addr;
588 return BLK_STS_RESOURCE;
591 iod->first_dma = prp_dma;
594 if (i == page_size >> 3) {
595 __le64 *old_prp_list = prp_list;
596 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
598 return BLK_STS_RESOURCE;
599 list[iod->npages++] = prp_list;
600 prp_list[0] = old_prp_list[i - 1];
601 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
604 prp_list[i++] = cpu_to_le64(dma_addr);
605 dma_len -= page_size;
606 dma_addr += page_size;
612 if (unlikely(dma_len < 0))
615 dma_addr = sg_dma_address(sg);
616 dma_len = sg_dma_len(sg);
622 if (WARN_ONCE(1, "Invalid SGL for payload:%d nents:%d\n",
623 blk_rq_payload_bytes(req), iod->nents)) {
624 for_each_sg(iod->sg, sg, iod->nents, i) {
625 dma_addr_t phys = sg_phys(sg);
626 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
627 "dma_address:%pad dma_length:%d\n", i, &phys,
628 sg->offset, sg->length,
633 return BLK_STS_IOERR;
637 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
638 struct nvme_command *cmnd)
640 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
641 struct request_queue *q = req->q;
642 enum dma_data_direction dma_dir = rq_data_dir(req) ?
643 DMA_TO_DEVICE : DMA_FROM_DEVICE;
644 blk_status_t ret = BLK_STS_IOERR;
646 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
647 iod->nents = blk_rq_map_sg(q, req, iod->sg);
651 ret = BLK_STS_RESOURCE;
652 if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
656 ret = nvme_setup_prps(dev, req);
657 if (ret != BLK_STS_OK)
661 if (blk_integrity_rq(req)) {
662 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
665 sg_init_table(&iod->meta_sg, 1);
666 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
669 if (rq_data_dir(req))
670 nvme_dif_remap(req, nvme_dif_prep);
672 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
676 cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
677 cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
678 if (blk_integrity_rq(req))
679 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
683 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
688 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
690 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
691 enum dma_data_direction dma_dir = rq_data_dir(req) ?
692 DMA_TO_DEVICE : DMA_FROM_DEVICE;
695 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
696 if (blk_integrity_rq(req)) {
697 if (!rq_data_dir(req))
698 nvme_dif_remap(req, nvme_dif_complete);
699 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
703 nvme_cleanup_cmd(req);
704 nvme_free_iod(dev, req);
708 * NOTE: ns is NULL when called on the admin queue.
710 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
711 const struct blk_mq_queue_data *bd)
713 struct nvme_ns *ns = hctx->queue->queuedata;
714 struct nvme_queue *nvmeq = hctx->driver_data;
715 struct nvme_dev *dev = nvmeq->dev;
716 struct request *req = bd->rq;
717 struct nvme_command cmnd;
720 ret = nvme_setup_cmd(ns, req, &cmnd);
724 ret = nvme_init_iod(req, dev);
728 if (blk_rq_nr_phys_segments(req)) {
729 ret = nvme_map_data(dev, req, &cmnd);
731 goto out_cleanup_iod;
734 blk_mq_start_request(req);
736 spin_lock_irq(&nvmeq->q_lock);
737 if (unlikely(nvmeq->cq_vector < 0)) {
739 spin_unlock_irq(&nvmeq->q_lock);
740 goto out_cleanup_iod;
742 __nvme_submit_cmd(nvmeq, &cmnd);
743 nvme_process_cq(nvmeq);
744 spin_unlock_irq(&nvmeq->q_lock);
747 nvme_free_iod(dev, req);
749 nvme_cleanup_cmd(req);
753 static void nvme_pci_complete_rq(struct request *req)
755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
757 nvme_unmap_data(iod->nvmeq->dev, req);
758 nvme_complete_rq(req);
761 /* We read the CQE phase first to check if the rest of the entry is valid */
762 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
765 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
768 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
770 u16 head = nvmeq->cq_head;
772 if (likely(nvmeq->cq_vector >= 0)) {
773 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
775 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
779 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
780 struct nvme_completion *cqe)
784 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
785 dev_warn(nvmeq->dev->ctrl.device,
786 "invalid id %d completed on queue %d\n",
787 cqe->command_id, le16_to_cpu(cqe->sq_id));
792 * AEN requests are special as they don't time out and can
793 * survive any kind of queue freeze and often don't respond to
794 * aborts. We don't even bother to allocate a struct request
795 * for them but rather special case them here.
797 if (unlikely(nvmeq->qid == 0 &&
798 cqe->command_id >= NVME_AQ_BLKMQ_DEPTH)) {
799 nvme_complete_async_event(&nvmeq->dev->ctrl,
800 cqe->status, &cqe->result);
804 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
805 nvme_end_request(req, cqe->status, cqe->result);
808 static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
809 struct nvme_completion *cqe)
811 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
812 *cqe = nvmeq->cqes[nvmeq->cq_head];
814 if (++nvmeq->cq_head == nvmeq->q_depth) {
816 nvmeq->cq_phase = !nvmeq->cq_phase;
823 static void nvme_process_cq(struct nvme_queue *nvmeq)
825 struct nvme_completion cqe;
828 while (nvme_read_cqe(nvmeq, &cqe)) {
829 nvme_handle_cqe(nvmeq, &cqe);
834 nvme_ring_cq_doorbell(nvmeq);
839 static irqreturn_t nvme_irq(int irq, void *data)
842 struct nvme_queue *nvmeq = data;
843 spin_lock(&nvmeq->q_lock);
844 nvme_process_cq(nvmeq);
845 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
847 spin_unlock(&nvmeq->q_lock);
851 static irqreturn_t nvme_irq_check(int irq, void *data)
853 struct nvme_queue *nvmeq = data;
854 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
855 return IRQ_WAKE_THREAD;
859 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
861 struct nvme_completion cqe;
862 int found = 0, consumed = 0;
864 if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
867 spin_lock_irq(&nvmeq->q_lock);
868 while (nvme_read_cqe(nvmeq, &cqe)) {
869 nvme_handle_cqe(nvmeq, &cqe);
872 if (tag == cqe.command_id) {
879 nvme_ring_cq_doorbell(nvmeq);
880 spin_unlock_irq(&nvmeq->q_lock);
885 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
887 struct nvme_queue *nvmeq = hctx->driver_data;
889 return __nvme_poll(nvmeq, tag);
892 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
894 struct nvme_dev *dev = to_nvme_dev(ctrl);
895 struct nvme_queue *nvmeq = dev->queues[0];
896 struct nvme_command c;
898 memset(&c, 0, sizeof(c));
899 c.common.opcode = nvme_admin_async_event;
900 c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
902 spin_lock_irq(&nvmeq->q_lock);
903 __nvme_submit_cmd(nvmeq, &c);
904 spin_unlock_irq(&nvmeq->q_lock);
907 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
909 struct nvme_command c;
911 memset(&c, 0, sizeof(c));
912 c.delete_queue.opcode = opcode;
913 c.delete_queue.qid = cpu_to_le16(id);
915 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
918 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
919 struct nvme_queue *nvmeq)
921 struct nvme_command c;
922 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
925 * Note: we (ab)use the fact the the prp fields survive if no data
926 * is attached to the request.
928 memset(&c, 0, sizeof(c));
929 c.create_cq.opcode = nvme_admin_create_cq;
930 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
931 c.create_cq.cqid = cpu_to_le16(qid);
932 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
933 c.create_cq.cq_flags = cpu_to_le16(flags);
934 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
936 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
939 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
940 struct nvme_queue *nvmeq)
942 struct nvme_command c;
943 int flags = NVME_QUEUE_PHYS_CONTIG;
946 * Note: we (ab)use the fact the the prp fields survive if no data
947 * is attached to the request.
949 memset(&c, 0, sizeof(c));
950 c.create_sq.opcode = nvme_admin_create_sq;
951 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
952 c.create_sq.sqid = cpu_to_le16(qid);
953 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
954 c.create_sq.sq_flags = cpu_to_le16(flags);
955 c.create_sq.cqid = cpu_to_le16(qid);
957 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
960 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
962 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
965 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
967 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
970 static void abort_endio(struct request *req, blk_status_t error)
972 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
973 struct nvme_queue *nvmeq = iod->nvmeq;
975 dev_warn(nvmeq->dev->ctrl.device,
976 "Abort status: 0x%x", nvme_req(req)->status);
977 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
978 blk_mq_free_request(req);
981 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
984 /* If true, indicates loss of adapter communication, possibly by a
985 * NVMe Subsystem reset.
987 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
989 /* If there is a reset ongoing, we shouldn't reset again. */
990 if (dev->ctrl.state == NVME_CTRL_RESETTING)
993 /* We shouldn't reset unless the controller is on fatal error state
994 * _or_ if we lost the communication with it.
996 if (!(csts & NVME_CSTS_CFS) && !nssro)
999 /* If PCI error recovery process is happening, we cannot reset or
1000 * the recovery mechanism will surely fail.
1002 if (pci_channel_offline(to_pci_dev(dev->dev)))
1008 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1010 /* Read a config register to help see what died. */
1014 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1016 if (result == PCIBIOS_SUCCESSFUL)
1017 dev_warn(dev->ctrl.device,
1018 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1021 dev_warn(dev->ctrl.device,
1022 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1026 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1028 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1029 struct nvme_queue *nvmeq = iod->nvmeq;
1030 struct nvme_dev *dev = nvmeq->dev;
1031 struct request *abort_req;
1032 struct nvme_command cmd;
1033 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1036 * Reset immediately if the controller is failed
1038 if (nvme_should_reset(dev, csts)) {
1039 nvme_warn_reset(dev, csts);
1040 nvme_dev_disable(dev, false);
1041 nvme_reset_ctrl(&dev->ctrl);
1042 return BLK_EH_HANDLED;
1046 * Did we miss an interrupt?
1048 if (__nvme_poll(nvmeq, req->tag)) {
1049 dev_warn(dev->ctrl.device,
1050 "I/O %d QID %d timeout, completion polled\n",
1051 req->tag, nvmeq->qid);
1052 return BLK_EH_HANDLED;
1056 * Shutdown immediately if controller times out while starting. The
1057 * reset work will see the pci device disabled when it gets the forced
1058 * cancellation error. All outstanding requests are completed on
1059 * shutdown, so we return BLK_EH_HANDLED.
1061 if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1062 dev_warn(dev->ctrl.device,
1063 "I/O %d QID %d timeout, disable controller\n",
1064 req->tag, nvmeq->qid);
1065 nvme_dev_disable(dev, false);
1066 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1067 return BLK_EH_HANDLED;
1071 * Shutdown the controller immediately and schedule a reset if the
1072 * command was already aborted once before and still hasn't been
1073 * returned to the driver, or if this is the admin queue.
1075 if (!nvmeq->qid || iod->aborted) {
1076 dev_warn(dev->ctrl.device,
1077 "I/O %d QID %d timeout, reset controller\n",
1078 req->tag, nvmeq->qid);
1079 nvme_dev_disable(dev, false);
1080 nvme_reset_ctrl(&dev->ctrl);
1083 * Mark the request as handled, since the inline shutdown
1084 * forces all outstanding requests to complete.
1086 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1087 return BLK_EH_HANDLED;
1090 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1091 atomic_inc(&dev->ctrl.abort_limit);
1092 return BLK_EH_RESET_TIMER;
1096 memset(&cmd, 0, sizeof(cmd));
1097 cmd.abort.opcode = nvme_admin_abort_cmd;
1098 cmd.abort.cid = req->tag;
1099 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1101 dev_warn(nvmeq->dev->ctrl.device,
1102 "I/O %d QID %d timeout, aborting\n",
1103 req->tag, nvmeq->qid);
1105 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1106 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1107 if (IS_ERR(abort_req)) {
1108 atomic_inc(&dev->ctrl.abort_limit);
1109 return BLK_EH_RESET_TIMER;
1112 abort_req->timeout = ADMIN_TIMEOUT;
1113 abort_req->end_io_data = NULL;
1114 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1117 * The aborted req will be completed on receiving the abort req.
1118 * We enable the timer again. If hit twice, it'll cause a device reset,
1119 * as the device then is in a faulty state.
1121 return BLK_EH_RESET_TIMER;
1124 static void nvme_free_queue(struct nvme_queue *nvmeq)
1126 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1127 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1129 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1130 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1134 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1138 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1139 struct nvme_queue *nvmeq = dev->queues[i];
1140 dev->ctrl.queue_count--;
1141 dev->queues[i] = NULL;
1142 nvme_free_queue(nvmeq);
1147 * nvme_suspend_queue - put queue into suspended state
1148 * @nvmeq - queue to suspend
1150 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1154 spin_lock_irq(&nvmeq->q_lock);
1155 if (nvmeq->cq_vector == -1) {
1156 spin_unlock_irq(&nvmeq->q_lock);
1159 vector = nvmeq->cq_vector;
1160 nvmeq->dev->online_queues--;
1161 nvmeq->cq_vector = -1;
1162 spin_unlock_irq(&nvmeq->q_lock);
1164 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1165 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1167 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1172 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1174 struct nvme_queue *nvmeq = dev->queues[0];
1178 if (nvme_suspend_queue(nvmeq))
1182 nvme_shutdown_ctrl(&dev->ctrl);
1184 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1186 spin_lock_irq(&nvmeq->q_lock);
1187 nvme_process_cq(nvmeq);
1188 spin_unlock_irq(&nvmeq->q_lock);
1191 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1194 int q_depth = dev->q_depth;
1195 unsigned q_size_aligned = roundup(q_depth * entry_size,
1196 dev->ctrl.page_size);
1198 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1199 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1200 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1201 q_depth = div_u64(mem_per_q, entry_size);
1204 * Ensure the reduced q_depth is above some threshold where it
1205 * would be better to map queues in system memory with the
1215 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1218 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1219 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1220 dev->ctrl.page_size);
1221 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1222 nvmeq->sq_cmds_io = dev->cmb + offset;
1224 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1225 &nvmeq->sq_dma_addr, GFP_KERNEL);
1226 if (!nvmeq->sq_cmds)
1233 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1234 int depth, int node)
1236 struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1241 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1242 &nvmeq->cq_dma_addr, GFP_KERNEL);
1246 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1249 nvmeq->q_dmadev = dev->dev;
1251 spin_lock_init(&nvmeq->q_lock);
1253 nvmeq->cq_phase = 1;
1254 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1255 nvmeq->q_depth = depth;
1257 nvmeq->cq_vector = -1;
1258 dev->queues[qid] = nvmeq;
1259 dev->ctrl.queue_count++;
1264 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1265 nvmeq->cq_dma_addr);
1271 static int queue_request_irq(struct nvme_queue *nvmeq)
1273 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1274 int nr = nvmeq->dev->ctrl.instance;
1276 if (use_threaded_interrupts) {
1277 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1278 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1280 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1281 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1285 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1287 struct nvme_dev *dev = nvmeq->dev;
1289 spin_lock_irq(&nvmeq->q_lock);
1292 nvmeq->cq_phase = 1;
1293 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1294 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1295 nvme_dbbuf_init(dev, nvmeq, qid);
1296 dev->online_queues++;
1297 spin_unlock_irq(&nvmeq->q_lock);
1300 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1302 struct nvme_dev *dev = nvmeq->dev;
1305 nvmeq->cq_vector = qid - 1;
1306 result = adapter_alloc_cq(dev, qid, nvmeq);
1310 result = adapter_alloc_sq(dev, qid, nvmeq);
1314 result = queue_request_irq(nvmeq);
1318 nvme_init_queue(nvmeq, qid);
1322 adapter_delete_sq(dev, qid);
1324 adapter_delete_cq(dev, qid);
1328 static const struct blk_mq_ops nvme_mq_admin_ops = {
1329 .queue_rq = nvme_queue_rq,
1330 .complete = nvme_pci_complete_rq,
1331 .init_hctx = nvme_admin_init_hctx,
1332 .exit_hctx = nvme_admin_exit_hctx,
1333 .init_request = nvme_init_request,
1334 .timeout = nvme_timeout,
1337 static const struct blk_mq_ops nvme_mq_ops = {
1338 .queue_rq = nvme_queue_rq,
1339 .complete = nvme_pci_complete_rq,
1340 .init_hctx = nvme_init_hctx,
1341 .init_request = nvme_init_request,
1342 .map_queues = nvme_pci_map_queues,
1343 .timeout = nvme_timeout,
1347 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1349 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1351 * If the controller was reset during removal, it's possible
1352 * user requests may be waiting on a stopped queue. Start the
1353 * queue to flush these to completion.
1355 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1356 blk_cleanup_queue(dev->ctrl.admin_q);
1357 blk_mq_free_tag_set(&dev->admin_tagset);
1361 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1363 if (!dev->ctrl.admin_q) {
1364 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1365 dev->admin_tagset.nr_hw_queues = 1;
1368 * Subtract one to leave an empty queue entry for 'Full Queue'
1369 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1371 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1372 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1373 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1374 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1375 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1376 dev->admin_tagset.driver_data = dev;
1378 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1381 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1382 if (IS_ERR(dev->ctrl.admin_q)) {
1383 blk_mq_free_tag_set(&dev->admin_tagset);
1386 if (!blk_get_queue(dev->ctrl.admin_q)) {
1387 nvme_dev_remove_admin(dev);
1388 dev->ctrl.admin_q = NULL;
1392 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1397 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1399 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1402 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1404 struct pci_dev *pdev = to_pci_dev(dev->dev);
1406 if (size <= dev->bar_mapped_size)
1408 if (size > pci_resource_len(pdev, 0))
1412 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1414 dev->bar_mapped_size = 0;
1417 dev->bar_mapped_size = size;
1418 dev->dbs = dev->bar + NVME_REG_DBS;
1423 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1427 struct nvme_queue *nvmeq;
1429 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1433 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1434 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1436 if (dev->subsystem &&
1437 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1438 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1440 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1444 nvmeq = dev->queues[0];
1446 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1447 dev_to_node(dev->dev));
1452 aqa = nvmeq->q_depth - 1;
1455 writel(aqa, dev->bar + NVME_REG_AQA);
1456 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1457 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1459 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1463 nvmeq->cq_vector = 0;
1464 result = queue_request_irq(nvmeq);
1466 nvmeq->cq_vector = -1;
1473 static int nvme_create_io_queues(struct nvme_dev *dev)
1478 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1479 /* vector == qid - 1, match nvme_create_queue */
1480 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1481 pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1487 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1488 for (i = dev->online_queues; i <= max; i++) {
1489 ret = nvme_create_queue(dev->queues[i], i);
1495 * Ignore failing Create SQ/CQ commands, we can continue with less
1496 * than the desired aount of queues, and even a controller without
1497 * I/O queues an still be used to issue admin commands. This might
1498 * be useful to upgrade a buggy firmware for example.
1500 return ret >= 0 ? 0 : ret;
1503 static ssize_t nvme_cmb_show(struct device *dev,
1504 struct device_attribute *attr,
1507 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1509 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1510 ndev->cmbloc, ndev->cmbsz);
1512 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1514 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1516 u64 szu, size, offset;
1517 resource_size_t bar_size;
1518 struct pci_dev *pdev = to_pci_dev(dev->dev);
1520 dma_addr_t dma_addr;
1522 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1523 if (!(NVME_CMB_SZ(dev->cmbsz)))
1525 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1530 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1531 size = szu * NVME_CMB_SZ(dev->cmbsz);
1532 offset = szu * NVME_CMB_OFST(dev->cmbloc);
1533 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1535 if (offset > bar_size)
1539 * Controllers may support a CMB size larger than their BAR,
1540 * for example, due to being behind a bridge. Reduce the CMB to
1541 * the reported size of the BAR
1543 if (size > bar_size - offset)
1544 size = bar_size - offset;
1546 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1547 cmb = ioremap_wc(dma_addr, size);
1551 dev->cmb_dma_addr = dma_addr;
1552 dev->cmb_size = size;
1556 static inline void nvme_release_cmb(struct nvme_dev *dev)
1562 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1563 &dev_attr_cmb.attr, NULL);
1569 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1571 size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs);
1572 struct nvme_command c;
1576 dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len,
1578 if (dma_mapping_error(dev->dev, dma_addr))
1581 memset(&c, 0, sizeof(c));
1582 c.features.opcode = nvme_admin_set_features;
1583 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1584 c.features.dword11 = cpu_to_le32(bits);
1585 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1586 ilog2(dev->ctrl.page_size));
1587 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1588 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1589 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1591 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1593 dev_warn(dev->ctrl.device,
1594 "failed to set host mem (err %d, flags %#x).\n",
1597 dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE);
1601 static void nvme_free_host_mem(struct nvme_dev *dev)
1605 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1606 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1607 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1609 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1610 le64_to_cpu(desc->addr));
1613 kfree(dev->host_mem_desc_bufs);
1614 dev->host_mem_desc_bufs = NULL;
1615 kfree(dev->host_mem_descs);
1616 dev->host_mem_descs = NULL;
1619 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1621 struct nvme_host_mem_buf_desc *descs;
1622 u32 chunk_size, max_entries, len;
1627 /* start big and work our way down */
1628 chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER);
1630 tmp = (preferred + chunk_size - 1);
1631 do_div(tmp, chunk_size);
1633 descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL);
1637 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1639 goto out_free_descs;
1641 for (size = 0; size < preferred; size += len) {
1642 dma_addr_t dma_addr;
1644 len = min_t(u64, chunk_size, preferred - size);
1645 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1646 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1650 descs[i].addr = cpu_to_le64(dma_addr);
1651 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1655 if (!size || (min && size < min)) {
1656 dev_warn(dev->ctrl.device,
1657 "failed to allocate host memory buffer.\n");
1661 dev_info(dev->ctrl.device,
1662 "allocated %lld MiB host memory buffer.\n",
1663 size >> ilog2(SZ_1M));
1664 dev->nr_host_mem_descs = i;
1665 dev->host_mem_size = size;
1666 dev->host_mem_descs = descs;
1667 dev->host_mem_desc_bufs = bufs;
1672 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1674 dma_free_coherent(dev->dev, size, bufs[i],
1675 le64_to_cpu(descs[i].addr));
1682 /* try a smaller chunk size if we failed early */
1683 if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) {
1687 dev->host_mem_descs = NULL;
1691 static void nvme_setup_host_mem(struct nvme_dev *dev)
1693 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1694 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1695 u64 min = (u64)dev->ctrl.hmmin * 4096;
1696 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1698 preferred = min(preferred, max);
1700 dev_warn(dev->ctrl.device,
1701 "min host memory (%lld MiB) above limit (%d MiB).\n",
1702 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1703 nvme_free_host_mem(dev);
1708 * If we already have a buffer allocated check if we can reuse it.
1710 if (dev->host_mem_descs) {
1711 if (dev->host_mem_size >= min)
1712 enable_bits |= NVME_HOST_MEM_RETURN;
1714 nvme_free_host_mem(dev);
1717 if (!dev->host_mem_descs) {
1718 if (nvme_alloc_host_mem(dev, min, preferred))
1722 if (nvme_set_host_mem(dev, enable_bits))
1723 nvme_free_host_mem(dev);
1726 static int nvme_setup_io_queues(struct nvme_dev *dev)
1728 struct nvme_queue *adminq = dev->queues[0];
1729 struct pci_dev *pdev = to_pci_dev(dev->dev);
1730 int result, nr_io_queues;
1733 nr_io_queues = num_present_cpus();
1734 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1738 if (nr_io_queues == 0)
1741 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1742 result = nvme_cmb_qdepth(dev, nr_io_queues,
1743 sizeof(struct nvme_command));
1745 dev->q_depth = result;
1747 nvme_release_cmb(dev);
1751 size = db_bar_size(dev, nr_io_queues);
1752 result = nvme_remap_bar(dev, size);
1755 if (!--nr_io_queues)
1758 adminq->q_db = dev->dbs;
1760 /* Deregister the admin queue's interrupt */
1761 pci_free_irq(pdev, 0, adminq);
1764 * If we enable msix early due to not intx, disable it again before
1765 * setting up the full range we need.
1767 pci_free_irq_vectors(pdev);
1768 nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1769 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1770 if (nr_io_queues <= 0)
1772 dev->max_qid = nr_io_queues;
1775 * Should investigate if there's a performance win from allocating
1776 * more queues than interrupt vectors; it might allow the submission
1777 * path to scale better, even if the receive path is limited by the
1778 * number of interrupts.
1781 result = queue_request_irq(adminq);
1783 adminq->cq_vector = -1;
1786 return nvme_create_io_queues(dev);
1789 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1791 struct nvme_queue *nvmeq = req->end_io_data;
1793 blk_mq_free_request(req);
1794 complete(&nvmeq->dev->ioq_wait);
1797 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1799 struct nvme_queue *nvmeq = req->end_io_data;
1802 unsigned long flags;
1805 * We might be called with the AQ q_lock held
1806 * and the I/O queue q_lock should always
1807 * nest inside the AQ one.
1809 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1810 SINGLE_DEPTH_NESTING);
1811 nvme_process_cq(nvmeq);
1812 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1815 nvme_del_queue_end(req, error);
1818 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1820 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1821 struct request *req;
1822 struct nvme_command cmd;
1824 memset(&cmd, 0, sizeof(cmd));
1825 cmd.delete_queue.opcode = opcode;
1826 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1828 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1830 return PTR_ERR(req);
1832 req->timeout = ADMIN_TIMEOUT;
1833 req->end_io_data = nvmeq;
1835 blk_execute_rq_nowait(q, NULL, req, false,
1836 opcode == nvme_admin_delete_cq ?
1837 nvme_del_cq_end : nvme_del_queue_end);
1841 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1844 unsigned long timeout;
1845 u8 opcode = nvme_admin_delete_sq;
1847 for (pass = 0; pass < 2; pass++) {
1848 int sent = 0, i = queues;
1850 reinit_completion(&dev->ioq_wait);
1852 timeout = ADMIN_TIMEOUT;
1853 for (; i > 0; i--, sent++)
1854 if (nvme_delete_queue(dev->queues[i], opcode))
1858 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1864 opcode = nvme_admin_delete_cq;
1869 * Return: error value if an error occurred setting up the queues or calling
1870 * Identify Device. 0 if these succeeded, even if adding some of the
1871 * namespaces failed. At the moment, these failures are silent. TBD which
1872 * failures should be reported.
1874 static int nvme_dev_add(struct nvme_dev *dev)
1876 if (!dev->ctrl.tagset) {
1877 dev->tagset.ops = &nvme_mq_ops;
1878 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1879 dev->tagset.timeout = NVME_IO_TIMEOUT;
1880 dev->tagset.numa_node = dev_to_node(dev->dev);
1881 dev->tagset.queue_depth =
1882 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1883 dev->tagset.cmd_size = nvme_cmd_size(dev);
1884 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1885 dev->tagset.driver_data = dev;
1887 if (blk_mq_alloc_tag_set(&dev->tagset))
1889 dev->ctrl.tagset = &dev->tagset;
1891 nvme_dbbuf_set(dev);
1893 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1895 /* Free previously allocated queues that are no longer usable */
1896 nvme_free_queues(dev, dev->online_queues);
1902 static int nvme_pci_enable(struct nvme_dev *dev)
1904 int result = -ENOMEM;
1905 struct pci_dev *pdev = to_pci_dev(dev->dev);
1907 if (pci_enable_device_mem(pdev))
1910 pci_set_master(pdev);
1912 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1913 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1916 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1922 * Some devices and/or platforms don't advertise or work with INTx
1923 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1924 * adjust this later.
1926 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1930 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1932 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
1934 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
1935 dev->dbs = dev->bar + 4096;
1938 * Temporary fix for the Apple controller found in the MacBook8,1 and
1939 * some MacBook7,1 to avoid controller resets and data loss.
1941 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1943 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
1944 "set queue depth=%u to work around controller resets\n",
1946 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
1947 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
1948 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
1950 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
1951 "set queue depth=%u\n", dev->q_depth);
1955 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1956 * populate sysfs if a CMB is implemented. Note that we add the
1957 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1958 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1959 * NULL as final argument to sysfs_add_file_to_group.
1962 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1963 dev->cmb = nvme_map_cmb(dev);
1966 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1967 &dev_attr_cmb.attr, NULL))
1968 dev_warn(dev->ctrl.device,
1969 "failed to add sysfs attribute for CMB\n");
1973 pci_enable_pcie_error_reporting(pdev);
1974 pci_save_state(pdev);
1978 pci_disable_device(pdev);
1982 static void nvme_dev_unmap(struct nvme_dev *dev)
1986 pci_release_mem_regions(to_pci_dev(dev->dev));
1989 static void nvme_pci_disable(struct nvme_dev *dev)
1991 struct pci_dev *pdev = to_pci_dev(dev->dev);
1993 nvme_release_cmb(dev);
1994 pci_free_irq_vectors(pdev);
1996 if (pci_is_enabled(pdev)) {
1997 pci_disable_pcie_error_reporting(pdev);
1998 pci_disable_device(pdev);
2002 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2006 struct pci_dev *pdev = to_pci_dev(dev->dev);
2008 mutex_lock(&dev->shutdown_lock);
2009 if (pci_is_enabled(pdev)) {
2010 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2012 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2013 dev->ctrl.state == NVME_CTRL_RESETTING)
2014 nvme_start_freeze(&dev->ctrl);
2015 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2016 pdev->error_state != pci_channel_io_normal);
2020 * Give the controller a chance to complete all entered requests if
2021 * doing a safe shutdown.
2025 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2028 * If the controller is still alive tell it to stop using the
2029 * host memory buffer. In theory the shutdown / reset should
2030 * make sure that it doesn't access the host memoery anymore,
2031 * but I'd rather be safe than sorry..
2033 if (dev->host_mem_descs)
2034 nvme_set_host_mem(dev, 0);
2037 nvme_stop_queues(&dev->ctrl);
2039 queues = dev->online_queues - 1;
2040 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
2041 nvme_suspend_queue(dev->queues[i]);
2044 /* A device might become IO incapable very soon during
2045 * probe, before the admin queue is configured. Thus,
2046 * queue_count can be 0 here.
2048 if (dev->ctrl.queue_count)
2049 nvme_suspend_queue(dev->queues[0]);
2051 nvme_disable_io_queues(dev, queues);
2052 nvme_disable_admin_queue(dev, shutdown);
2054 nvme_pci_disable(dev);
2056 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2057 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2060 * The driver will not be starting up queues again if shutting down so
2061 * must flush all entered requests to their failed completion to avoid
2062 * deadlocking blk-mq hot-cpu notifier.
2065 nvme_start_queues(&dev->ctrl);
2066 mutex_unlock(&dev->shutdown_lock);
2069 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2071 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2072 PAGE_SIZE, PAGE_SIZE, 0);
2073 if (!dev->prp_page_pool)
2076 /* Optimisation for I/Os between 4k and 128k */
2077 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2079 if (!dev->prp_small_pool) {
2080 dma_pool_destroy(dev->prp_page_pool);
2086 static void nvme_release_prp_pools(struct nvme_dev *dev)
2088 dma_pool_destroy(dev->prp_page_pool);
2089 dma_pool_destroy(dev->prp_small_pool);
2092 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2094 struct nvme_dev *dev = to_nvme_dev(ctrl);
2096 nvme_dbbuf_dma_free(dev);
2097 put_device(dev->dev);
2098 if (dev->tagset.tags)
2099 blk_mq_free_tag_set(&dev->tagset);
2100 if (dev->ctrl.admin_q)
2101 blk_put_queue(dev->ctrl.admin_q);
2103 free_opal_dev(dev->ctrl.opal_dev);
2107 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2109 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2111 kref_get(&dev->ctrl.kref);
2112 nvme_dev_disable(dev, false);
2113 if (!schedule_work(&dev->remove_work))
2114 nvme_put_ctrl(&dev->ctrl);
2117 static void nvme_reset_work(struct work_struct *work)
2119 struct nvme_dev *dev =
2120 container_of(work, struct nvme_dev, ctrl.reset_work);
2121 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2122 int result = -ENODEV;
2124 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2128 * If we're called to reset a live controller first shut it down before
2131 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2132 nvme_dev_disable(dev, false);
2134 result = nvme_pci_enable(dev);
2138 result = nvme_pci_configure_admin_queue(dev);
2142 nvme_init_queue(dev->queues[0], 0);
2143 result = nvme_alloc_admin_tags(dev);
2147 result = nvme_init_identify(&dev->ctrl);
2151 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2152 if (!dev->ctrl.opal_dev)
2153 dev->ctrl.opal_dev =
2154 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2155 else if (was_suspend)
2156 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2158 free_opal_dev(dev->ctrl.opal_dev);
2159 dev->ctrl.opal_dev = NULL;
2162 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2163 result = nvme_dbbuf_dma_alloc(dev);
2166 "unable to allocate dma for dbbuf\n");
2169 if (dev->ctrl.hmpre)
2170 nvme_setup_host_mem(dev);
2172 result = nvme_setup_io_queues(dev);
2177 * Keep the controller around but remove all namespaces if we don't have
2178 * any working I/O queue.
2180 if (dev->online_queues < 2) {
2181 dev_warn(dev->ctrl.device, "IO queues not created\n");
2182 nvme_kill_queues(&dev->ctrl);
2183 nvme_remove_namespaces(&dev->ctrl);
2185 nvme_start_queues(&dev->ctrl);
2186 nvme_wait_freeze(&dev->ctrl);
2188 nvme_unfreeze(&dev->ctrl);
2191 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2192 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
2196 nvme_start_ctrl(&dev->ctrl);
2200 nvme_remove_dead_ctrl(dev, result);
2203 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2205 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2206 struct pci_dev *pdev = to_pci_dev(dev->dev);
2208 nvme_kill_queues(&dev->ctrl);
2209 if (pci_get_drvdata(pdev))
2210 device_release_driver(&pdev->dev);
2211 nvme_put_ctrl(&dev->ctrl);
2214 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2216 *val = readl(to_nvme_dev(ctrl)->bar + off);
2220 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2222 writel(val, to_nvme_dev(ctrl)->bar + off);
2226 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2228 *val = readq(to_nvme_dev(ctrl)->bar + off);
2232 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2234 .module = THIS_MODULE,
2235 .flags = NVME_F_METADATA_SUPPORTED,
2236 .reg_read32 = nvme_pci_reg_read32,
2237 .reg_write32 = nvme_pci_reg_write32,
2238 .reg_read64 = nvme_pci_reg_read64,
2239 .free_ctrl = nvme_pci_free_ctrl,
2240 .submit_async_event = nvme_pci_submit_async_event,
2243 static int nvme_dev_map(struct nvme_dev *dev)
2245 struct pci_dev *pdev = to_pci_dev(dev->dev);
2247 if (pci_request_mem_regions(pdev, "nvme"))
2250 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2255 pci_release_mem_regions(pdev);
2259 static unsigned long check_dell_samsung_bug(struct pci_dev *pdev)
2261 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2263 * Several Samsung devices seem to drop off the PCIe bus
2264 * randomly when APST is on and uses the deepest sleep state.
2265 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2266 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2267 * 950 PRO 256GB", but it seems to be restricted to two Dell
2270 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2271 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2272 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2273 return NVME_QUIRK_NO_DEEPEST_PS;
2279 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2281 int node, result = -ENOMEM;
2282 struct nvme_dev *dev;
2283 unsigned long quirks = id->driver_data;
2285 node = dev_to_node(&pdev->dev);
2286 if (node == NUMA_NO_NODE)
2287 set_dev_node(&pdev->dev, first_memory_node);
2289 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2292 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2297 dev->dev = get_device(&pdev->dev);
2298 pci_set_drvdata(pdev, dev);
2300 result = nvme_dev_map(dev);
2304 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2305 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2306 mutex_init(&dev->shutdown_lock);
2307 init_completion(&dev->ioq_wait);
2309 result = nvme_setup_prp_pools(dev);
2313 quirks |= check_dell_samsung_bug(pdev);
2315 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2320 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
2321 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2323 queue_work(nvme_wq, &dev->ctrl.reset_work);
2327 nvme_release_prp_pools(dev);
2329 nvme_dev_unmap(dev);
2331 put_device(dev->dev);
2338 static void nvme_reset_prepare(struct pci_dev *pdev)
2340 struct nvme_dev *dev = pci_get_drvdata(pdev);
2341 nvme_dev_disable(dev, false);
2344 static void nvme_reset_done(struct pci_dev *pdev)
2346 struct nvme_dev *dev = pci_get_drvdata(pdev);
2347 nvme_reset_ctrl(&dev->ctrl);
2350 static void nvme_shutdown(struct pci_dev *pdev)
2352 struct nvme_dev *dev = pci_get_drvdata(pdev);
2353 nvme_dev_disable(dev, true);
2357 * The driver's remove may be called on a device in a partially initialized
2358 * state. This function must not have any dependencies on the device state in
2361 static void nvme_remove(struct pci_dev *pdev)
2363 struct nvme_dev *dev = pci_get_drvdata(pdev);
2365 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2367 cancel_work_sync(&dev->ctrl.reset_work);
2368 pci_set_drvdata(pdev, NULL);
2370 if (!pci_device_is_present(pdev)) {
2371 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2372 nvme_dev_disable(dev, false);
2375 flush_work(&dev->ctrl.reset_work);
2376 nvme_stop_ctrl(&dev->ctrl);
2377 nvme_remove_namespaces(&dev->ctrl);
2378 nvme_dev_disable(dev, true);
2379 nvme_free_host_mem(dev);
2380 nvme_dev_remove_admin(dev);
2381 nvme_free_queues(dev, 0);
2382 nvme_uninit_ctrl(&dev->ctrl);
2383 nvme_release_prp_pools(dev);
2384 nvme_dev_unmap(dev);
2385 nvme_put_ctrl(&dev->ctrl);
2388 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2393 if (pci_vfs_assigned(pdev)) {
2394 dev_warn(&pdev->dev,
2395 "Cannot disable SR-IOV VFs while assigned\n");
2398 pci_disable_sriov(pdev);
2402 ret = pci_enable_sriov(pdev, numvfs);
2403 return ret ? ret : numvfs;
2406 #ifdef CONFIG_PM_SLEEP
2407 static int nvme_suspend(struct device *dev)
2409 struct pci_dev *pdev = to_pci_dev(dev);
2410 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2412 nvme_dev_disable(ndev, true);
2416 static int nvme_resume(struct device *dev)
2418 struct pci_dev *pdev = to_pci_dev(dev);
2419 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2421 nvme_reset_ctrl(&ndev->ctrl);
2426 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2428 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2429 pci_channel_state_t state)
2431 struct nvme_dev *dev = pci_get_drvdata(pdev);
2434 * A frozen channel requires a reset. When detected, this method will
2435 * shutdown the controller to quiesce. The controller will be restarted
2436 * after the slot reset through driver's slot_reset callback.
2439 case pci_channel_io_normal:
2440 return PCI_ERS_RESULT_CAN_RECOVER;
2441 case pci_channel_io_frozen:
2442 dev_warn(dev->ctrl.device,
2443 "frozen state error detected, reset controller\n");
2444 nvme_dev_disable(dev, false);
2445 return PCI_ERS_RESULT_NEED_RESET;
2446 case pci_channel_io_perm_failure:
2447 dev_warn(dev->ctrl.device,
2448 "failure state error detected, request disconnect\n");
2449 return PCI_ERS_RESULT_DISCONNECT;
2451 return PCI_ERS_RESULT_NEED_RESET;
2454 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2456 struct nvme_dev *dev = pci_get_drvdata(pdev);
2458 dev_info(dev->ctrl.device, "restart after slot reset\n");
2459 pci_restore_state(pdev);
2460 nvme_reset_ctrl(&dev->ctrl);
2461 return PCI_ERS_RESULT_RECOVERED;
2464 static void nvme_error_resume(struct pci_dev *pdev)
2466 pci_cleanup_aer_uncorrect_error_status(pdev);
2469 static const struct pci_error_handlers nvme_err_handler = {
2470 .error_detected = nvme_error_detected,
2471 .slot_reset = nvme_slot_reset,
2472 .resume = nvme_error_resume,
2473 .reset_prepare = nvme_reset_prepare,
2474 .reset_done = nvme_reset_done,
2477 static const struct pci_device_id nvme_id_table[] = {
2478 { PCI_VDEVICE(INTEL, 0x0953),
2479 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2480 NVME_QUIRK_DEALLOCATE_ZEROES, },
2481 { PCI_VDEVICE(INTEL, 0x0a53),
2482 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2483 NVME_QUIRK_DEALLOCATE_ZEROES, },
2484 { PCI_VDEVICE(INTEL, 0x0a54),
2485 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2486 NVME_QUIRK_DEALLOCATE_ZEROES, },
2487 { PCI_VDEVICE(INTEL, 0x0a55),
2488 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2489 NVME_QUIRK_DEALLOCATE_ZEROES, },
2490 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2491 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
2492 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2493 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2494 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2495 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2496 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2497 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2498 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2499 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2500 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2501 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2502 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2503 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2504 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2507 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2509 static struct pci_driver nvme_driver = {
2511 .id_table = nvme_id_table,
2512 .probe = nvme_probe,
2513 .remove = nvme_remove,
2514 .shutdown = nvme_shutdown,
2516 .pm = &nvme_dev_pm_ops,
2518 .sriov_configure = nvme_pci_sriov_configure,
2519 .err_handler = &nvme_err_handler,
2522 static int __init nvme_init(void)
2524 return pci_register_driver(&nvme_driver);
2527 static void __exit nvme_exit(void)
2529 pci_unregister_driver(&nvme_driver);
2533 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2534 MODULE_LICENSE("GPL");
2535 MODULE_VERSION("1.0");
2536 module_init(nvme_init);
2537 module_exit(nvme_exit);