1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/once.h>
20 #include <linux/pci.h>
21 #include <linux/suspend.h>
22 #include <linux/t10-pi.h>
23 #include <linux/types.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/sed-opal.h>
26 #include <linux/pci-p2pdma.h>
31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
40 #define NVME_MAX_KB_SZ 4096
41 #define NVME_MAX_SEGS 127
43 static int use_threaded_interrupts;
44 module_param(use_threaded_interrupts, int, 0);
46 static bool use_cmb_sqes = true;
47 module_param(use_cmb_sqes, bool, 0444);
48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
50 static unsigned int max_host_mem_size_mb = 128;
51 module_param(max_host_mem_size_mb, uint, 0444);
52 MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
55 static unsigned int sgl_threshold = SZ_32K;
56 module_param(sgl_threshold, uint, 0644);
57 MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62 static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
64 .get = param_get_uint,
67 static unsigned int io_queue_depth = 1024;
68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
71 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
76 ret = kstrtouint(val, 10, &n);
77 if (ret != 0 || n > num_possible_cpus())
79 return param_set_uint(val, kp);
82 static const struct kernel_param_ops io_queue_count_ops = {
83 .set = io_queue_count_set,
84 .get = param_get_uint,
87 static unsigned int write_queues;
88 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
89 MODULE_PARM_DESC(write_queues,
90 "Number of queues to use for writes. If not set, reads and writes "
91 "will share a queue set.");
93 static unsigned int poll_queues;
94 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
95 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
100 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
101 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
104 * Represents an NVM Express device. Each nvme_dev is a PCI function.
107 struct nvme_queue *queues;
108 struct blk_mq_tag_set tagset;
109 struct blk_mq_tag_set admin_tagset;
112 struct dma_pool *prp_page_pool;
113 struct dma_pool *prp_small_pool;
114 unsigned online_queues;
116 unsigned io_queues[HCTX_MAX_TYPES];
117 unsigned int num_vecs;
122 unsigned long bar_mapped_size;
123 struct work_struct remove_work;
124 struct mutex shutdown_lock;
130 struct nvme_ctrl ctrl;
133 mempool_t *iod_mempool;
135 /* shadow doorbell buffer support: */
137 dma_addr_t dbbuf_dbs_dma_addr;
139 dma_addr_t dbbuf_eis_dma_addr;
141 /* host memory buffer support: */
143 u32 nr_host_mem_descs;
144 dma_addr_t host_mem_descs_dma;
145 struct nvme_host_mem_buf_desc *host_mem_descs;
146 void **host_mem_desc_bufs;
147 unsigned int nr_allocated_queues;
148 unsigned int nr_write_queues;
149 unsigned int nr_poll_queues;
152 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
157 ret = kstrtou16(val, 10, &n);
158 if (ret != 0 || n < 2)
161 return param_set_ushort(val, kp);
164 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
166 return qid * 2 * stride;
169 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
171 return (qid * 2 + 1) * stride;
174 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
176 return container_of(ctrl, struct nvme_dev, ctrl);
180 * An NVM Express queue. Each device has at least two (one for admin
181 * commands and one for I/O commands).
184 struct nvme_dev *dev;
187 /* only used for poll queues: */
188 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
189 struct nvme_completion *cqes;
190 dma_addr_t sq_dma_addr;
191 dma_addr_t cq_dma_addr;
201 #define NVMEQ_ENABLED 0
202 #define NVMEQ_SQ_CMB 1
203 #define NVMEQ_DELETE_ERROR 2
204 #define NVMEQ_POLLED 3
209 struct completion delete_done;
213 * The nvme_iod describes the data in an I/O.
215 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
216 * to the actual struct scatterlist.
219 struct nvme_request req;
220 struct nvme_queue *nvmeq;
223 int npages; /* In the PRP list. 0 means small pool in use */
224 int nents; /* Used in scatterlist */
225 dma_addr_t first_dma;
226 unsigned int dma_len; /* length of single DMA segment mapping */
228 struct scatterlist *sg;
231 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
233 return dev->nr_allocated_queues * 8 * dev->db_stride;
236 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
238 unsigned int mem_size = nvme_dbbuf_size(dev);
243 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
244 &dev->dbbuf_dbs_dma_addr,
248 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
249 &dev->dbbuf_eis_dma_addr,
251 if (!dev->dbbuf_eis) {
252 dma_free_coherent(dev->dev, mem_size,
253 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
254 dev->dbbuf_dbs = NULL;
261 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
263 unsigned int mem_size = nvme_dbbuf_size(dev);
265 if (dev->dbbuf_dbs) {
266 dma_free_coherent(dev->dev, mem_size,
267 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
268 dev->dbbuf_dbs = NULL;
270 if (dev->dbbuf_eis) {
271 dma_free_coherent(dev->dev, mem_size,
272 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
273 dev->dbbuf_eis = NULL;
277 static void nvme_dbbuf_init(struct nvme_dev *dev,
278 struct nvme_queue *nvmeq, int qid)
280 if (!dev->dbbuf_dbs || !qid)
283 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
284 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
285 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
286 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
289 static void nvme_dbbuf_set(struct nvme_dev *dev)
291 struct nvme_command c;
296 memset(&c, 0, sizeof(c));
297 c.dbbuf.opcode = nvme_admin_dbbuf;
298 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
299 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
301 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
302 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
303 /* Free memory and continue on */
304 nvme_dbbuf_dma_free(dev);
308 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
310 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
313 /* Update dbbuf and return true if an MMIO is required */
314 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
315 volatile u32 *dbbuf_ei)
321 * Ensure that the queue is written before updating
322 * the doorbell in memory
326 old_value = *dbbuf_db;
330 * Ensure that the doorbell is updated before reading the event
331 * index from memory. The controller needs to provide similar
332 * ordering to ensure the envent index is updated before reading
337 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
345 * Will slightly overestimate the number of pages needed. This is OK
346 * as it only leads to a small amount of wasted memory for the lifetime of
349 static int nvme_npages(unsigned size, struct nvme_dev *dev)
351 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
352 dev->ctrl.page_size);
353 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
357 * Calculates the number of pages needed for the SGL segments. For example a 4k
358 * page can accommodate 256 SGL descriptors.
360 static int nvme_pci_npages_sgl(unsigned int num_seg)
362 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
365 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
366 unsigned int size, unsigned int nseg, bool use_sgl)
371 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
373 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
375 return alloc_size + sizeof(struct scatterlist) * nseg;
378 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
379 unsigned int hctx_idx)
381 struct nvme_dev *dev = data;
382 struct nvme_queue *nvmeq = &dev->queues[0];
384 WARN_ON(hctx_idx != 0);
385 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
387 hctx->driver_data = nvmeq;
391 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
392 unsigned int hctx_idx)
394 struct nvme_dev *dev = data;
395 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
397 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
398 hctx->driver_data = nvmeq;
402 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
403 unsigned int hctx_idx, unsigned int numa_node)
405 struct nvme_dev *dev = set->driver_data;
406 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
407 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
408 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
413 nvme_req(req)->ctrl = &dev->ctrl;
417 static int queue_irq_offset(struct nvme_dev *dev)
419 /* if we have more than 1 vec, admin queue offsets us by 1 */
420 if (dev->num_vecs > 1)
426 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
428 struct nvme_dev *dev = set->driver_data;
431 offset = queue_irq_offset(dev);
432 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
433 struct blk_mq_queue_map *map = &set->map[i];
435 map->nr_queues = dev->io_queues[i];
436 if (!map->nr_queues) {
437 BUG_ON(i == HCTX_TYPE_DEFAULT);
442 * The poll queue(s) doesn't have an IRQ (and hence IRQ
443 * affinity), so use the regular blk-mq cpu mapping
445 map->queue_offset = qoff;
446 if (i != HCTX_TYPE_POLL && offset)
447 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
449 blk_mq_map_queues(map);
450 qoff += map->nr_queues;
451 offset += map->nr_queues;
457 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq)
459 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
460 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
461 writel(nvmeq->sq_tail, nvmeq->q_db);
465 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
466 * @nvmeq: The queue to use
467 * @cmd: The command to send
468 * @write_sq: whether to write to the SQ doorbell
470 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
473 spin_lock(&nvmeq->sq_lock);
474 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
476 if (++nvmeq->sq_tail == nvmeq->q_depth)
479 nvme_write_sq_db(nvmeq);
480 spin_unlock(&nvmeq->sq_lock);
483 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
485 struct nvme_queue *nvmeq = hctx->driver_data;
487 spin_lock(&nvmeq->sq_lock);
488 nvme_write_sq_db(nvmeq);
489 spin_unlock(&nvmeq->sq_lock);
492 static void **nvme_pci_iod_list(struct request *req)
494 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
495 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
498 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
500 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
501 int nseg = blk_rq_nr_phys_segments(req);
502 unsigned int avg_seg_size;
504 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
506 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
508 if (!iod->nvmeq->qid)
510 if (!sgl_threshold || avg_seg_size < sgl_threshold)
515 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
517 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
518 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
519 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
523 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
528 WARN_ON_ONCE(!iod->nents);
530 if (is_pci_p2pdma_page(sg_page(iod->sg)))
531 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
534 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
537 if (iod->npages == 0)
538 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
541 for (i = 0; i < iod->npages; i++) {
542 void *addr = nvme_pci_iod_list(req)[i];
545 struct nvme_sgl_desc *sg_list = addr;
548 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
550 __le64 *prp_list = addr;
552 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
555 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
556 dma_addr = next_dma_addr;
559 mempool_free(iod->sg, dev->iod_mempool);
562 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
565 struct scatterlist *sg;
567 for_each_sg(sgl, sg, nents, i) {
568 dma_addr_t phys = sg_phys(sg);
569 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
570 "dma_address:%pad dma_length:%d\n",
571 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
576 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
577 struct request *req, struct nvme_rw_command *cmnd)
579 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
580 struct dma_pool *pool;
581 int length = blk_rq_payload_bytes(req);
582 struct scatterlist *sg = iod->sg;
583 int dma_len = sg_dma_len(sg);
584 u64 dma_addr = sg_dma_address(sg);
585 u32 page_size = dev->ctrl.page_size;
586 int offset = dma_addr & (page_size - 1);
588 void **list = nvme_pci_iod_list(req);
592 length -= (page_size - offset);
598 dma_len -= (page_size - offset);
600 dma_addr += (page_size - offset);
603 dma_addr = sg_dma_address(sg);
604 dma_len = sg_dma_len(sg);
607 if (length <= page_size) {
608 iod->first_dma = dma_addr;
612 nprps = DIV_ROUND_UP(length, page_size);
613 if (nprps <= (256 / 8)) {
614 pool = dev->prp_small_pool;
617 pool = dev->prp_page_pool;
621 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
623 iod->first_dma = dma_addr;
625 return BLK_STS_RESOURCE;
628 iod->first_dma = prp_dma;
631 if (i == page_size >> 3) {
632 __le64 *old_prp_list = prp_list;
633 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
635 return BLK_STS_RESOURCE;
636 list[iod->npages++] = prp_list;
637 prp_list[0] = old_prp_list[i - 1];
638 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
641 prp_list[i++] = cpu_to_le64(dma_addr);
642 dma_len -= page_size;
643 dma_addr += page_size;
649 if (unlikely(dma_len < 0))
652 dma_addr = sg_dma_address(sg);
653 dma_len = sg_dma_len(sg);
657 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
658 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
663 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
664 "Invalid SGL for payload:%d nents:%d\n",
665 blk_rq_payload_bytes(req), iod->nents);
666 return BLK_STS_IOERR;
669 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
670 struct scatterlist *sg)
672 sge->addr = cpu_to_le64(sg_dma_address(sg));
673 sge->length = cpu_to_le32(sg_dma_len(sg));
674 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
677 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
678 dma_addr_t dma_addr, int entries)
680 sge->addr = cpu_to_le64(dma_addr);
681 if (entries < SGES_PER_PAGE) {
682 sge->length = cpu_to_le32(entries * sizeof(*sge));
683 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
685 sge->length = cpu_to_le32(PAGE_SIZE);
686 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
690 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
691 struct request *req, struct nvme_rw_command *cmd, int entries)
693 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
694 struct dma_pool *pool;
695 struct nvme_sgl_desc *sg_list;
696 struct scatterlist *sg = iod->sg;
700 /* setting the transfer type as SGL */
701 cmd->flags = NVME_CMD_SGL_METABUF;
704 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
708 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
709 pool = dev->prp_small_pool;
712 pool = dev->prp_page_pool;
716 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
719 return BLK_STS_RESOURCE;
722 nvme_pci_iod_list(req)[0] = sg_list;
723 iod->first_dma = sgl_dma;
725 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
728 if (i == SGES_PER_PAGE) {
729 struct nvme_sgl_desc *old_sg_desc = sg_list;
730 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
732 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
734 return BLK_STS_RESOURCE;
737 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
738 sg_list[i++] = *link;
739 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
742 nvme_pci_sgl_set_data(&sg_list[i++], sg);
744 } while (--entries > 0);
749 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
750 struct request *req, struct nvme_rw_command *cmnd,
753 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
754 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1);
755 unsigned int first_prp_len = dev->ctrl.page_size - offset;
757 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
758 if (dma_mapping_error(dev->dev, iod->first_dma))
759 return BLK_STS_RESOURCE;
760 iod->dma_len = bv->bv_len;
762 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
763 if (bv->bv_len > first_prp_len)
764 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
768 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
769 struct request *req, struct nvme_rw_command *cmnd,
772 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
774 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
775 if (dma_mapping_error(dev->dev, iod->first_dma))
776 return BLK_STS_RESOURCE;
777 iod->dma_len = bv->bv_len;
779 cmnd->flags = NVME_CMD_SGL_METABUF;
780 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
781 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
782 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
786 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
787 struct nvme_command *cmnd)
789 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
790 blk_status_t ret = BLK_STS_RESOURCE;
793 if (blk_rq_nr_phys_segments(req) == 1) {
794 struct bio_vec bv = req_bvec(req);
796 if (!is_pci_p2pdma_page(bv.bv_page)) {
797 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
798 return nvme_setup_prp_simple(dev, req,
801 if (iod->nvmeq->qid &&
802 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
803 return nvme_setup_sgl_simple(dev, req,
809 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
811 return BLK_STS_RESOURCE;
812 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
813 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
817 if (is_pci_p2pdma_page(sg_page(iod->sg)))
818 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
819 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
821 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
822 rq_dma_dir(req), DMA_ATTR_NO_WARN);
826 iod->use_sgl = nvme_pci_use_sgls(dev, req);
828 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
830 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
832 if (ret != BLK_STS_OK)
833 nvme_unmap_data(dev, req);
837 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
838 struct nvme_command *cmnd)
840 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
842 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
844 if (dma_mapping_error(dev->dev, iod->meta_dma))
845 return BLK_STS_IOERR;
846 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
851 * NOTE: ns is NULL when called on the admin queue.
853 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
854 const struct blk_mq_queue_data *bd)
856 struct nvme_ns *ns = hctx->queue->queuedata;
857 struct nvme_queue *nvmeq = hctx->driver_data;
858 struct nvme_dev *dev = nvmeq->dev;
859 struct request *req = bd->rq;
860 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
861 struct nvme_command cmnd;
869 * We should not need to do this, but we're still using this to
870 * ensure we can drain requests on a dying queue.
872 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
873 return BLK_STS_IOERR;
875 ret = nvme_setup_cmd(ns, req, &cmnd);
879 if (blk_rq_nr_phys_segments(req)) {
880 ret = nvme_map_data(dev, req, &cmnd);
885 if (blk_integrity_rq(req)) {
886 ret = nvme_map_metadata(dev, req, &cmnd);
891 blk_mq_start_request(req);
892 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
895 nvme_unmap_data(dev, req);
897 nvme_cleanup_cmd(req);
901 static void nvme_pci_complete_rq(struct request *req)
903 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
904 struct nvme_dev *dev = iod->nvmeq->dev;
906 if (blk_integrity_rq(req))
907 dma_unmap_page(dev->dev, iod->meta_dma,
908 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
909 if (blk_rq_nr_phys_segments(req))
910 nvme_unmap_data(dev, req);
911 nvme_complete_rq(req);
914 /* We read the CQE phase first to check if the rest of the entry is valid */
915 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
917 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
919 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
922 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
924 u16 head = nvmeq->cq_head;
926 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
928 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
931 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
934 return nvmeq->dev->admin_tagset.tags[0];
935 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
938 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
940 struct nvme_completion *cqe = &nvmeq->cqes[idx];
943 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
944 dev_warn(nvmeq->dev->ctrl.device,
945 "invalid id %d completed on queue %d\n",
946 cqe->command_id, le16_to_cpu(cqe->sq_id));
951 * AEN requests are special as they don't time out and can
952 * survive any kind of queue freeze and often don't respond to
953 * aborts. We don't even bother to allocate a struct request
954 * for them but rather special case them here.
956 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
957 nvme_complete_async_event(&nvmeq->dev->ctrl,
958 cqe->status, &cqe->result);
962 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
963 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
964 if (!nvme_end_request(req, cqe->status, cqe->result))
965 nvme_pci_complete_rq(req);
968 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
970 u16 tmp = nvmeq->cq_head + 1;
972 if (tmp == nvmeq->q_depth) {
974 nvmeq->cq_phase ^= 1;
976 nvmeq->cq_head = tmp;
980 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
984 while (nvme_cqe_pending(nvmeq)) {
987 * load-load control dependency between phase and the rest of
988 * the cqe requires a full read memory barrier
991 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
992 nvme_update_cq_head(nvmeq);
996 nvme_ring_cq_doorbell(nvmeq);
1000 static irqreturn_t nvme_irq(int irq, void *data)
1002 struct nvme_queue *nvmeq = data;
1003 irqreturn_t ret = IRQ_NONE;
1006 * The rmb/wmb pair ensures we see all updates from a previous run of
1007 * the irq handler, even if that was on another CPU.
1010 if (nvme_process_cq(nvmeq))
1017 static irqreturn_t nvme_irq_check(int irq, void *data)
1019 struct nvme_queue *nvmeq = data;
1020 if (nvme_cqe_pending(nvmeq))
1021 return IRQ_WAKE_THREAD;
1026 * Poll for completions for any interrupt driven queue
1027 * Can be called from any context.
1029 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1031 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1033 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1035 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1036 nvme_process_cq(nvmeq);
1037 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1040 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1042 struct nvme_queue *nvmeq = hctx->driver_data;
1045 if (!nvme_cqe_pending(nvmeq))
1048 spin_lock(&nvmeq->cq_poll_lock);
1049 found = nvme_process_cq(nvmeq);
1050 spin_unlock(&nvmeq->cq_poll_lock);
1055 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1057 struct nvme_dev *dev = to_nvme_dev(ctrl);
1058 struct nvme_queue *nvmeq = &dev->queues[0];
1059 struct nvme_command c;
1061 memset(&c, 0, sizeof(c));
1062 c.common.opcode = nvme_admin_async_event;
1063 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1064 nvme_submit_cmd(nvmeq, &c, true);
1067 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1069 struct nvme_command c;
1071 memset(&c, 0, sizeof(c));
1072 c.delete_queue.opcode = opcode;
1073 c.delete_queue.qid = cpu_to_le16(id);
1075 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1078 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1079 struct nvme_queue *nvmeq, s16 vector)
1081 struct nvme_command c;
1082 int flags = NVME_QUEUE_PHYS_CONTIG;
1084 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1085 flags |= NVME_CQ_IRQ_ENABLED;
1088 * Note: we (ab)use the fact that the prp fields survive if no data
1089 * is attached to the request.
1091 memset(&c, 0, sizeof(c));
1092 c.create_cq.opcode = nvme_admin_create_cq;
1093 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1094 c.create_cq.cqid = cpu_to_le16(qid);
1095 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1096 c.create_cq.cq_flags = cpu_to_le16(flags);
1097 c.create_cq.irq_vector = cpu_to_le16(vector);
1099 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1102 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1103 struct nvme_queue *nvmeq)
1105 struct nvme_ctrl *ctrl = &dev->ctrl;
1106 struct nvme_command c;
1107 int flags = NVME_QUEUE_PHYS_CONTIG;
1110 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1111 * set. Since URGENT priority is zeroes, it makes all queues
1114 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1115 flags |= NVME_SQ_PRIO_MEDIUM;
1118 * Note: we (ab)use the fact that the prp fields survive if no data
1119 * is attached to the request.
1121 memset(&c, 0, sizeof(c));
1122 c.create_sq.opcode = nvme_admin_create_sq;
1123 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1124 c.create_sq.sqid = cpu_to_le16(qid);
1125 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1126 c.create_sq.sq_flags = cpu_to_le16(flags);
1127 c.create_sq.cqid = cpu_to_le16(qid);
1129 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1132 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1134 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1137 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1139 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1142 static void abort_endio(struct request *req, blk_status_t error)
1144 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1145 struct nvme_queue *nvmeq = iod->nvmeq;
1147 dev_warn(nvmeq->dev->ctrl.device,
1148 "Abort status: 0x%x", nvme_req(req)->status);
1149 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1150 blk_mq_free_request(req);
1153 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1155 /* If true, indicates loss of adapter communication, possibly by a
1156 * NVMe Subsystem reset.
1158 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1160 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1161 switch (dev->ctrl.state) {
1162 case NVME_CTRL_RESETTING:
1163 case NVME_CTRL_CONNECTING:
1169 /* We shouldn't reset unless the controller is on fatal error state
1170 * _or_ if we lost the communication with it.
1172 if (!(csts & NVME_CSTS_CFS) && !nssro)
1178 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1180 /* Read a config register to help see what died. */
1184 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1186 if (result == PCIBIOS_SUCCESSFUL)
1187 dev_warn(dev->ctrl.device,
1188 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1191 dev_warn(dev->ctrl.device,
1192 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1196 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1198 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1199 struct nvme_queue *nvmeq = iod->nvmeq;
1200 struct nvme_dev *dev = nvmeq->dev;
1201 struct request *abort_req;
1202 struct nvme_command cmd;
1203 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1205 /* If PCI error recovery process is happening, we cannot reset or
1206 * the recovery mechanism will surely fail.
1209 if (pci_channel_offline(to_pci_dev(dev->dev)))
1210 return BLK_EH_RESET_TIMER;
1213 * Reset immediately if the controller is failed
1215 if (nvme_should_reset(dev, csts)) {
1216 nvme_warn_reset(dev, csts);
1217 nvme_dev_disable(dev, false);
1218 nvme_reset_ctrl(&dev->ctrl);
1223 * Did we miss an interrupt?
1225 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1226 nvme_poll(req->mq_hctx);
1228 nvme_poll_irqdisable(nvmeq);
1230 if (blk_mq_request_completed(req)) {
1231 dev_warn(dev->ctrl.device,
1232 "I/O %d QID %d timeout, completion polled\n",
1233 req->tag, nvmeq->qid);
1238 * Shutdown immediately if controller times out while starting. The
1239 * reset work will see the pci device disabled when it gets the forced
1240 * cancellation error. All outstanding requests are completed on
1241 * shutdown, so we return BLK_EH_DONE.
1243 switch (dev->ctrl.state) {
1244 case NVME_CTRL_CONNECTING:
1245 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1247 case NVME_CTRL_DELETING:
1248 dev_warn_ratelimited(dev->ctrl.device,
1249 "I/O %d QID %d timeout, disable controller\n",
1250 req->tag, nvmeq->qid);
1251 nvme_dev_disable(dev, true);
1252 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1254 case NVME_CTRL_RESETTING:
1255 return BLK_EH_RESET_TIMER;
1261 * Shutdown the controller immediately and schedule a reset if the
1262 * command was already aborted once before and still hasn't been
1263 * returned to the driver, or if this is the admin queue.
1265 if (!nvmeq->qid || iod->aborted) {
1266 dev_warn(dev->ctrl.device,
1267 "I/O %d QID %d timeout, reset controller\n",
1268 req->tag, nvmeq->qid);
1269 nvme_dev_disable(dev, false);
1270 nvme_reset_ctrl(&dev->ctrl);
1272 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1276 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1277 atomic_inc(&dev->ctrl.abort_limit);
1278 return BLK_EH_RESET_TIMER;
1282 memset(&cmd, 0, sizeof(cmd));
1283 cmd.abort.opcode = nvme_admin_abort_cmd;
1284 cmd.abort.cid = req->tag;
1285 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1287 dev_warn(nvmeq->dev->ctrl.device,
1288 "I/O %d QID %d timeout, aborting\n",
1289 req->tag, nvmeq->qid);
1291 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1292 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1293 if (IS_ERR(abort_req)) {
1294 atomic_inc(&dev->ctrl.abort_limit);
1295 return BLK_EH_RESET_TIMER;
1298 abort_req->timeout = ADMIN_TIMEOUT;
1299 abort_req->end_io_data = NULL;
1300 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1303 * The aborted req will be completed on receiving the abort req.
1304 * We enable the timer again. If hit twice, it'll cause a device reset,
1305 * as the device then is in a faulty state.
1307 return BLK_EH_RESET_TIMER;
1310 static void nvme_free_queue(struct nvme_queue *nvmeq)
1312 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1313 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1314 if (!nvmeq->sq_cmds)
1317 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1318 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1319 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1321 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1322 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1326 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1330 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1331 dev->ctrl.queue_count--;
1332 nvme_free_queue(&dev->queues[i]);
1337 * nvme_suspend_queue - put queue into suspended state
1338 * @nvmeq: queue to suspend
1340 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1342 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1345 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1348 nvmeq->dev->online_queues--;
1349 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1350 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1351 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1352 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1356 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1360 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1361 nvme_suspend_queue(&dev->queues[i]);
1364 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1366 struct nvme_queue *nvmeq = &dev->queues[0];
1369 nvme_shutdown_ctrl(&dev->ctrl);
1371 nvme_disable_ctrl(&dev->ctrl);
1373 nvme_poll_irqdisable(nvmeq);
1377 * Called only on a device that has been disabled and after all other threads
1378 * that can check this device's completion queues have synced, except
1379 * nvme_poll(). This is the last chance for the driver to see a natural
1380 * completion before nvme_cancel_request() terminates all incomplete requests.
1382 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1386 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1387 spin_lock(&dev->queues[i].cq_poll_lock);
1388 nvme_process_cq(&dev->queues[i]);
1389 spin_unlock(&dev->queues[i].cq_poll_lock);
1393 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1396 int q_depth = dev->q_depth;
1397 unsigned q_size_aligned = roundup(q_depth * entry_size,
1398 dev->ctrl.page_size);
1400 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1401 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1402 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1403 q_depth = div_u64(mem_per_q, entry_size);
1406 * Ensure the reduced q_depth is above some threshold where it
1407 * would be better to map queues in system memory with the
1417 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1420 struct pci_dev *pdev = to_pci_dev(dev->dev);
1422 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1423 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1424 if (nvmeq->sq_cmds) {
1425 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1427 if (nvmeq->sq_dma_addr) {
1428 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1432 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1436 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1437 &nvmeq->sq_dma_addr, GFP_KERNEL);
1438 if (!nvmeq->sq_cmds)
1443 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1445 struct nvme_queue *nvmeq = &dev->queues[qid];
1447 if (dev->ctrl.queue_count > qid)
1450 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1451 nvmeq->q_depth = depth;
1452 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1453 &nvmeq->cq_dma_addr, GFP_KERNEL);
1457 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1461 spin_lock_init(&nvmeq->sq_lock);
1462 spin_lock_init(&nvmeq->cq_poll_lock);
1464 nvmeq->cq_phase = 1;
1465 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1467 dev->ctrl.queue_count++;
1472 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1473 nvmeq->cq_dma_addr);
1478 static int queue_request_irq(struct nvme_queue *nvmeq)
1480 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1481 int nr = nvmeq->dev->ctrl.instance;
1483 if (use_threaded_interrupts) {
1484 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1485 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1487 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1488 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1492 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1494 struct nvme_dev *dev = nvmeq->dev;
1498 nvmeq->cq_phase = 1;
1499 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1500 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1501 nvme_dbbuf_init(dev, nvmeq, qid);
1502 dev->online_queues++;
1503 wmb(); /* ensure the first interrupt sees the initialization */
1506 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1508 struct nvme_dev *dev = nvmeq->dev;
1512 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1515 * A queue's vector matches the queue identifier unless the controller
1516 * has only one vector available.
1519 vector = dev->num_vecs == 1 ? 0 : qid;
1521 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1523 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1527 result = adapter_alloc_sq(dev, qid, nvmeq);
1533 nvmeq->cq_vector = vector;
1534 nvme_init_queue(nvmeq, qid);
1537 result = queue_request_irq(nvmeq);
1542 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1546 dev->online_queues--;
1547 adapter_delete_sq(dev, qid);
1549 adapter_delete_cq(dev, qid);
1553 static const struct blk_mq_ops nvme_mq_admin_ops = {
1554 .queue_rq = nvme_queue_rq,
1555 .complete = nvme_pci_complete_rq,
1556 .init_hctx = nvme_admin_init_hctx,
1557 .init_request = nvme_init_request,
1558 .timeout = nvme_timeout,
1561 static const struct blk_mq_ops nvme_mq_ops = {
1562 .queue_rq = nvme_queue_rq,
1563 .complete = nvme_pci_complete_rq,
1564 .commit_rqs = nvme_commit_rqs,
1565 .init_hctx = nvme_init_hctx,
1566 .init_request = nvme_init_request,
1567 .map_queues = nvme_pci_map_queues,
1568 .timeout = nvme_timeout,
1572 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1574 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1576 * If the controller was reset during removal, it's possible
1577 * user requests may be waiting on a stopped queue. Start the
1578 * queue to flush these to completion.
1580 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1581 blk_cleanup_queue(dev->ctrl.admin_q);
1582 blk_mq_free_tag_set(&dev->admin_tagset);
1586 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1588 if (!dev->ctrl.admin_q) {
1589 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1590 dev->admin_tagset.nr_hw_queues = 1;
1592 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1593 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1594 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1595 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1596 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1597 dev->admin_tagset.driver_data = dev;
1599 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1601 dev->ctrl.admin_tagset = &dev->admin_tagset;
1603 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1604 if (IS_ERR(dev->ctrl.admin_q)) {
1605 blk_mq_free_tag_set(&dev->admin_tagset);
1608 if (!blk_get_queue(dev->ctrl.admin_q)) {
1609 nvme_dev_remove_admin(dev);
1610 dev->ctrl.admin_q = NULL;
1614 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1619 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1621 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1624 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1626 struct pci_dev *pdev = to_pci_dev(dev->dev);
1628 if (size <= dev->bar_mapped_size)
1630 if (size > pci_resource_len(pdev, 0))
1634 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1636 dev->bar_mapped_size = 0;
1639 dev->bar_mapped_size = size;
1640 dev->dbs = dev->bar + NVME_REG_DBS;
1645 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1649 struct nvme_queue *nvmeq;
1651 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1655 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1656 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1658 if (dev->subsystem &&
1659 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1660 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1662 result = nvme_disable_ctrl(&dev->ctrl);
1666 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1670 dev->ctrl.numa_node = dev_to_node(dev->dev);
1672 nvmeq = &dev->queues[0];
1673 aqa = nvmeq->q_depth - 1;
1676 writel(aqa, dev->bar + NVME_REG_AQA);
1677 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1678 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1680 result = nvme_enable_ctrl(&dev->ctrl);
1684 nvmeq->cq_vector = 0;
1685 nvme_init_queue(nvmeq, 0);
1686 result = queue_request_irq(nvmeq);
1688 dev->online_queues--;
1692 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1696 static int nvme_create_io_queues(struct nvme_dev *dev)
1698 unsigned i, max, rw_queues;
1701 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1702 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1708 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1709 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1710 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1711 dev->io_queues[HCTX_TYPE_READ];
1716 for (i = dev->online_queues; i <= max; i++) {
1717 bool polled = i > rw_queues;
1719 ret = nvme_create_queue(&dev->queues[i], i, polled);
1725 * Ignore failing Create SQ/CQ commands, we can continue with less
1726 * than the desired amount of queues, and even a controller without
1727 * I/O queues can still be used to issue admin commands. This might
1728 * be useful to upgrade a buggy firmware for example.
1730 return ret >= 0 ? 0 : ret;
1733 static ssize_t nvme_cmb_show(struct device *dev,
1734 struct device_attribute *attr,
1737 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1739 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1740 ndev->cmbloc, ndev->cmbsz);
1742 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1744 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1746 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1748 return 1ULL << (12 + 4 * szu);
1751 static u32 nvme_cmb_size(struct nvme_dev *dev)
1753 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1756 static void nvme_map_cmb(struct nvme_dev *dev)
1759 resource_size_t bar_size;
1760 struct pci_dev *pdev = to_pci_dev(dev->dev);
1766 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1769 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1771 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1772 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1773 bar = NVME_CMB_BIR(dev->cmbloc);
1774 bar_size = pci_resource_len(pdev, bar);
1776 if (offset > bar_size)
1780 * Controllers may support a CMB size larger than their BAR,
1781 * for example, due to being behind a bridge. Reduce the CMB to
1782 * the reported size of the BAR
1784 if (size > bar_size - offset)
1785 size = bar_size - offset;
1787 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1788 dev_warn(dev->ctrl.device,
1789 "failed to register the CMB\n");
1793 dev->cmb_size = size;
1794 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1796 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1797 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1798 pci_p2pmem_publish(pdev, true);
1800 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1801 &dev_attr_cmb.attr, NULL))
1802 dev_warn(dev->ctrl.device,
1803 "failed to add sysfs attribute for CMB\n");
1806 static inline void nvme_release_cmb(struct nvme_dev *dev)
1808 if (dev->cmb_size) {
1809 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1810 &dev_attr_cmb.attr, NULL);
1815 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1817 u64 dma_addr = dev->host_mem_descs_dma;
1818 struct nvme_command c;
1821 memset(&c, 0, sizeof(c));
1822 c.features.opcode = nvme_admin_set_features;
1823 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1824 c.features.dword11 = cpu_to_le32(bits);
1825 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1826 ilog2(dev->ctrl.page_size));
1827 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1828 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1829 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1831 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1833 dev_warn(dev->ctrl.device,
1834 "failed to set host mem (err %d, flags %#x).\n",
1840 static void nvme_free_host_mem(struct nvme_dev *dev)
1844 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1845 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1846 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1848 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1849 le64_to_cpu(desc->addr),
1850 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1853 kfree(dev->host_mem_desc_bufs);
1854 dev->host_mem_desc_bufs = NULL;
1855 dma_free_coherent(dev->dev,
1856 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1857 dev->host_mem_descs, dev->host_mem_descs_dma);
1858 dev->host_mem_descs = NULL;
1859 dev->nr_host_mem_descs = 0;
1862 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1865 struct nvme_host_mem_buf_desc *descs;
1866 u32 max_entries, len;
1867 dma_addr_t descs_dma;
1872 tmp = (preferred + chunk_size - 1);
1873 do_div(tmp, chunk_size);
1876 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1877 max_entries = dev->ctrl.hmmaxd;
1879 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1880 &descs_dma, GFP_KERNEL);
1884 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1886 goto out_free_descs;
1888 for (size = 0; size < preferred && i < max_entries; size += len) {
1889 dma_addr_t dma_addr;
1891 len = min_t(u64, chunk_size, preferred - size);
1892 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1893 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1897 descs[i].addr = cpu_to_le64(dma_addr);
1898 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1905 dev->nr_host_mem_descs = i;
1906 dev->host_mem_size = size;
1907 dev->host_mem_descs = descs;
1908 dev->host_mem_descs_dma = descs_dma;
1909 dev->host_mem_desc_bufs = bufs;
1914 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1916 dma_free_attrs(dev->dev, size, bufs[i],
1917 le64_to_cpu(descs[i].addr),
1918 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1923 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1926 dev->host_mem_descs = NULL;
1930 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1932 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1933 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1936 /* start big and work our way down */
1937 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
1938 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1939 if (!min || dev->host_mem_size >= min)
1941 nvme_free_host_mem(dev);
1948 static int nvme_setup_host_mem(struct nvme_dev *dev)
1950 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1951 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1952 u64 min = (u64)dev->ctrl.hmmin * 4096;
1953 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1956 preferred = min(preferred, max);
1958 dev_warn(dev->ctrl.device,
1959 "min host memory (%lld MiB) above limit (%d MiB).\n",
1960 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1961 nvme_free_host_mem(dev);
1966 * If we already have a buffer allocated check if we can reuse it.
1968 if (dev->host_mem_descs) {
1969 if (dev->host_mem_size >= min)
1970 enable_bits |= NVME_HOST_MEM_RETURN;
1972 nvme_free_host_mem(dev);
1975 if (!dev->host_mem_descs) {
1976 if (nvme_alloc_host_mem(dev, min, preferred)) {
1977 dev_warn(dev->ctrl.device,
1978 "failed to allocate host memory buffer.\n");
1979 return 0; /* controller must work without HMB */
1982 dev_info(dev->ctrl.device,
1983 "allocated %lld MiB host memory buffer.\n",
1984 dev->host_mem_size >> ilog2(SZ_1M));
1987 ret = nvme_set_host_mem(dev, enable_bits);
1989 nvme_free_host_mem(dev);
1994 * nirqs is the number of interrupts available for write and read
1995 * queues. The core already reserved an interrupt for the admin queue.
1997 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
1999 struct nvme_dev *dev = affd->priv;
2000 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2003 * If there is no interrupt available for queues, ensure that
2004 * the default queue is set to 1. The affinity set size is
2005 * also set to one, but the irq core ignores it for this case.
2007 * If only one interrupt is available or 'write_queue' == 0, combine
2008 * write and read queues.
2010 * If 'write_queues' > 0, ensure it leaves room for at least one read
2016 } else if (nrirqs == 1 || !nr_write_queues) {
2018 } else if (nr_write_queues >= nrirqs) {
2021 nr_read_queues = nrirqs - nr_write_queues;
2024 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2025 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2026 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2027 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2028 affd->nr_sets = nr_read_queues ? 2 : 1;
2031 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2033 struct pci_dev *pdev = to_pci_dev(dev->dev);
2034 struct irq_affinity affd = {
2036 .calc_sets = nvme_calc_irq_sets,
2039 unsigned int irq_queues, this_p_queues;
2042 * Poll queues don't need interrupts, but we need at least one IO
2043 * queue left over for non-polled IO.
2045 this_p_queues = dev->nr_poll_queues;
2046 if (this_p_queues >= nr_io_queues) {
2047 this_p_queues = nr_io_queues - 1;
2050 irq_queues = nr_io_queues - this_p_queues + 1;
2052 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2054 /* Initialize for the single interrupt case */
2055 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2056 dev->io_queues[HCTX_TYPE_READ] = 0;
2059 * Some Apple controllers require all queues to use the
2062 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2065 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2066 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2069 static void nvme_disable_io_queues(struct nvme_dev *dev)
2071 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2072 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2075 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2077 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2080 static int nvme_setup_io_queues(struct nvme_dev *dev)
2082 struct nvme_queue *adminq = &dev->queues[0];
2083 struct pci_dev *pdev = to_pci_dev(dev->dev);
2084 unsigned int nr_io_queues;
2089 * Sample the module parameters once at reset time so that we have
2090 * stable values to work with.
2092 dev->nr_write_queues = write_queues;
2093 dev->nr_poll_queues = poll_queues;
2096 * If tags are shared with admin queue (Apple bug), then
2097 * make sure we only use one IO queue.
2099 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2102 nr_io_queues = min(nvme_max_io_queues(dev),
2103 dev->nr_allocated_queues - 1);
2105 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2109 if (nr_io_queues == 0)
2112 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2114 if (dev->cmb_use_sqes) {
2115 result = nvme_cmb_qdepth(dev, nr_io_queues,
2116 sizeof(struct nvme_command));
2118 dev->q_depth = result;
2120 dev->cmb_use_sqes = false;
2124 size = db_bar_size(dev, nr_io_queues);
2125 result = nvme_remap_bar(dev, size);
2128 if (!--nr_io_queues)
2131 adminq->q_db = dev->dbs;
2134 /* Deregister the admin queue's interrupt */
2135 pci_free_irq(pdev, 0, adminq);
2138 * If we enable msix early due to not intx, disable it again before
2139 * setting up the full range we need.
2141 pci_free_irq_vectors(pdev);
2143 result = nvme_setup_irqs(dev, nr_io_queues);
2147 dev->num_vecs = result;
2148 result = max(result - 1, 1);
2149 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2152 * Should investigate if there's a performance win from allocating
2153 * more queues than interrupt vectors; it might allow the submission
2154 * path to scale better, even if the receive path is limited by the
2155 * number of interrupts.
2157 result = queue_request_irq(adminq);
2160 set_bit(NVMEQ_ENABLED, &adminq->flags);
2162 result = nvme_create_io_queues(dev);
2163 if (result || dev->online_queues < 2)
2166 if (dev->online_queues - 1 < dev->max_qid) {
2167 nr_io_queues = dev->online_queues - 1;
2168 nvme_disable_io_queues(dev);
2169 nvme_suspend_io_queues(dev);
2172 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2173 dev->io_queues[HCTX_TYPE_DEFAULT],
2174 dev->io_queues[HCTX_TYPE_READ],
2175 dev->io_queues[HCTX_TYPE_POLL]);
2179 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2181 struct nvme_queue *nvmeq = req->end_io_data;
2183 blk_mq_free_request(req);
2184 complete(&nvmeq->delete_done);
2187 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2189 struct nvme_queue *nvmeq = req->end_io_data;
2192 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2194 nvme_del_queue_end(req, error);
2197 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2199 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2200 struct request *req;
2201 struct nvme_command cmd;
2203 memset(&cmd, 0, sizeof(cmd));
2204 cmd.delete_queue.opcode = opcode;
2205 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2207 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2209 return PTR_ERR(req);
2211 req->timeout = ADMIN_TIMEOUT;
2212 req->end_io_data = nvmeq;
2214 init_completion(&nvmeq->delete_done);
2215 blk_execute_rq_nowait(q, NULL, req, false,
2216 opcode == nvme_admin_delete_cq ?
2217 nvme_del_cq_end : nvme_del_queue_end);
2221 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2223 int nr_queues = dev->online_queues - 1, sent = 0;
2224 unsigned long timeout;
2227 timeout = ADMIN_TIMEOUT;
2228 while (nr_queues > 0) {
2229 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2235 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2237 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2249 static void nvme_dev_add(struct nvme_dev *dev)
2253 if (!dev->ctrl.tagset) {
2254 dev->tagset.ops = &nvme_mq_ops;
2255 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2256 dev->tagset.nr_maps = 2; /* default + read */
2257 if (dev->io_queues[HCTX_TYPE_POLL])
2258 dev->tagset.nr_maps++;
2259 dev->tagset.timeout = NVME_IO_TIMEOUT;
2260 dev->tagset.numa_node = dev->ctrl.numa_node;
2261 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2262 BLK_MQ_MAX_DEPTH) - 1;
2263 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2264 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2265 dev->tagset.driver_data = dev;
2268 * Some Apple controllers requires tags to be unique
2269 * across admin and IO queue, so reserve the first 32
2270 * tags of the IO queue.
2272 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2273 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2275 ret = blk_mq_alloc_tag_set(&dev->tagset);
2277 dev_warn(dev->ctrl.device,
2278 "IO queues tagset allocation failed %d\n", ret);
2281 dev->ctrl.tagset = &dev->tagset;
2283 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2285 /* Free previously allocated queues that are no longer usable */
2286 nvme_free_queues(dev, dev->online_queues);
2289 nvme_dbbuf_set(dev);
2292 static int nvme_pci_enable(struct nvme_dev *dev)
2294 int result = -ENOMEM;
2295 struct pci_dev *pdev = to_pci_dev(dev->dev);
2297 if (pci_enable_device_mem(pdev))
2300 pci_set_master(pdev);
2302 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
2305 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2311 * Some devices and/or platforms don't advertise or work with INTx
2312 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2313 * adjust this later.
2315 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2319 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2321 dev->q_depth = min_t(u16, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2323 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2324 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2325 dev->dbs = dev->bar + 4096;
2328 * Some Apple controllers require a non-standard SQE size.
2329 * Interestingly they also seem to ignore the CC:IOSQES register
2330 * so we don't bother updating it here.
2332 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2335 dev->io_sqes = NVME_NVM_IOSQES;
2338 * Temporary fix for the Apple controller found in the MacBook8,1 and
2339 * some MacBook7,1 to avoid controller resets and data loss.
2341 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2343 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2344 "set queue depth=%u to work around controller resets\n",
2346 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2347 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2348 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2350 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2351 "set queue depth=%u\n", dev->q_depth);
2355 * Controllers with the shared tags quirk need the IO queue to be
2356 * big enough so that we get 32 tags for the admin queue
2358 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2359 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2360 dev->q_depth = NVME_AQ_DEPTH + 2;
2361 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2368 pci_enable_pcie_error_reporting(pdev);
2369 pci_save_state(pdev);
2373 pci_disable_device(pdev);
2377 static void nvme_dev_unmap(struct nvme_dev *dev)
2381 pci_release_mem_regions(to_pci_dev(dev->dev));
2384 static void nvme_pci_disable(struct nvme_dev *dev)
2386 struct pci_dev *pdev = to_pci_dev(dev->dev);
2388 pci_free_irq_vectors(pdev);
2390 if (pci_is_enabled(pdev)) {
2391 pci_disable_pcie_error_reporting(pdev);
2392 pci_disable_device(pdev);
2396 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2398 bool dead = true, freeze = false;
2399 struct pci_dev *pdev = to_pci_dev(dev->dev);
2401 mutex_lock(&dev->shutdown_lock);
2402 if (pci_is_enabled(pdev)) {
2403 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2405 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2406 dev->ctrl.state == NVME_CTRL_RESETTING) {
2408 nvme_start_freeze(&dev->ctrl);
2410 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2411 pdev->error_state != pci_channel_io_normal);
2415 * Give the controller a chance to complete all entered requests if
2416 * doing a safe shutdown.
2418 if (!dead && shutdown && freeze)
2419 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2421 nvme_stop_queues(&dev->ctrl);
2423 if (!dead && dev->ctrl.queue_count > 0) {
2424 nvme_disable_io_queues(dev);
2425 nvme_disable_admin_queue(dev, shutdown);
2427 nvme_suspend_io_queues(dev);
2428 nvme_suspend_queue(&dev->queues[0]);
2429 nvme_pci_disable(dev);
2430 nvme_reap_pending_cqes(dev);
2432 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2433 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2434 blk_mq_tagset_wait_completed_request(&dev->tagset);
2435 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2438 * The driver will not be starting up queues again if shutting down so
2439 * must flush all entered requests to their failed completion to avoid
2440 * deadlocking blk-mq hot-cpu notifier.
2443 nvme_start_queues(&dev->ctrl);
2444 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2445 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2447 mutex_unlock(&dev->shutdown_lock);
2450 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2452 if (!nvme_wait_reset(&dev->ctrl))
2454 nvme_dev_disable(dev, shutdown);
2458 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2460 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2461 PAGE_SIZE, PAGE_SIZE, 0);
2462 if (!dev->prp_page_pool)
2465 /* Optimisation for I/Os between 4k and 128k */
2466 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2468 if (!dev->prp_small_pool) {
2469 dma_pool_destroy(dev->prp_page_pool);
2475 static void nvme_release_prp_pools(struct nvme_dev *dev)
2477 dma_pool_destroy(dev->prp_page_pool);
2478 dma_pool_destroy(dev->prp_small_pool);
2481 static void nvme_free_tagset(struct nvme_dev *dev)
2483 if (dev->tagset.tags)
2484 blk_mq_free_tag_set(&dev->tagset);
2485 dev->ctrl.tagset = NULL;
2488 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2490 struct nvme_dev *dev = to_nvme_dev(ctrl);
2492 nvme_dbbuf_dma_free(dev);
2493 nvme_free_tagset(dev);
2494 if (dev->ctrl.admin_q)
2495 blk_put_queue(dev->ctrl.admin_q);
2496 free_opal_dev(dev->ctrl.opal_dev);
2497 mempool_destroy(dev->iod_mempool);
2498 put_device(dev->dev);
2503 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2506 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2507 * may be holding this pci_dev's device lock.
2509 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2510 nvme_get_ctrl(&dev->ctrl);
2511 nvme_dev_disable(dev, false);
2512 nvme_kill_queues(&dev->ctrl);
2513 if (!queue_work(nvme_wq, &dev->remove_work))
2514 nvme_put_ctrl(&dev->ctrl);
2517 static void nvme_reset_work(struct work_struct *work)
2519 struct nvme_dev *dev =
2520 container_of(work, struct nvme_dev, ctrl.reset_work);
2521 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2524 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2530 * If we're called to reset a live controller first shut it down before
2533 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2534 nvme_dev_disable(dev, false);
2535 nvme_sync_queues(&dev->ctrl);
2537 mutex_lock(&dev->shutdown_lock);
2538 result = nvme_pci_enable(dev);
2542 result = nvme_pci_configure_admin_queue(dev);
2546 result = nvme_alloc_admin_tags(dev);
2551 * Limit the max command size to prevent iod->sg allocations going
2552 * over a single page.
2554 dev->ctrl.max_hw_sectors = min_t(u32,
2555 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2556 dev->ctrl.max_segments = NVME_MAX_SEGS;
2559 * Don't limit the IOMMU merged segment size.
2561 dma_set_max_seg_size(dev->dev, 0xffffffff);
2563 mutex_unlock(&dev->shutdown_lock);
2566 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2567 * initializing procedure here.
2569 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2570 dev_warn(dev->ctrl.device,
2571 "failed to mark controller CONNECTING\n");
2577 * We do not support an SGL for metadata (yet), so we are limited to a
2578 * single integrity segment for the separate metadata pointer.
2580 dev->ctrl.max_integrity_segments = 1;
2582 result = nvme_init_identify(&dev->ctrl);
2586 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2587 if (!dev->ctrl.opal_dev)
2588 dev->ctrl.opal_dev =
2589 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2590 else if (was_suspend)
2591 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2593 free_opal_dev(dev->ctrl.opal_dev);
2594 dev->ctrl.opal_dev = NULL;
2597 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2598 result = nvme_dbbuf_dma_alloc(dev);
2601 "unable to allocate dma for dbbuf\n");
2604 if (dev->ctrl.hmpre) {
2605 result = nvme_setup_host_mem(dev);
2610 result = nvme_setup_io_queues(dev);
2615 * Keep the controller around but remove all namespaces if we don't have
2616 * any working I/O queue.
2618 if (dev->online_queues < 2) {
2619 dev_warn(dev->ctrl.device, "IO queues not created\n");
2620 nvme_kill_queues(&dev->ctrl);
2621 nvme_remove_namespaces(&dev->ctrl);
2622 nvme_free_tagset(dev);
2624 nvme_start_queues(&dev->ctrl);
2625 nvme_wait_freeze(&dev->ctrl);
2627 nvme_unfreeze(&dev->ctrl);
2631 * If only admin queue live, keep it to do further investigation or
2634 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2635 dev_warn(dev->ctrl.device,
2636 "failed to mark controller live state\n");
2641 nvme_start_ctrl(&dev->ctrl);
2645 mutex_unlock(&dev->shutdown_lock);
2648 dev_warn(dev->ctrl.device,
2649 "Removing after probe failure status: %d\n", result);
2650 nvme_remove_dead_ctrl(dev);
2653 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2655 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2656 struct pci_dev *pdev = to_pci_dev(dev->dev);
2658 if (pci_get_drvdata(pdev))
2659 device_release_driver(&pdev->dev);
2660 nvme_put_ctrl(&dev->ctrl);
2663 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2665 *val = readl(to_nvme_dev(ctrl)->bar + off);
2669 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2671 writel(val, to_nvme_dev(ctrl)->bar + off);
2675 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2677 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2681 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2683 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2685 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2688 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2690 .module = THIS_MODULE,
2691 .flags = NVME_F_METADATA_SUPPORTED |
2693 .reg_read32 = nvme_pci_reg_read32,
2694 .reg_write32 = nvme_pci_reg_write32,
2695 .reg_read64 = nvme_pci_reg_read64,
2696 .free_ctrl = nvme_pci_free_ctrl,
2697 .submit_async_event = nvme_pci_submit_async_event,
2698 .get_address = nvme_pci_get_address,
2701 static int nvme_dev_map(struct nvme_dev *dev)
2703 struct pci_dev *pdev = to_pci_dev(dev->dev);
2705 if (pci_request_mem_regions(pdev, "nvme"))
2708 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2713 pci_release_mem_regions(pdev);
2717 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2719 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2721 * Several Samsung devices seem to drop off the PCIe bus
2722 * randomly when APST is on and uses the deepest sleep state.
2723 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2724 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2725 * 950 PRO 256GB", but it seems to be restricted to two Dell
2728 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2729 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2730 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2731 return NVME_QUIRK_NO_DEEPEST_PS;
2732 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2734 * Samsung SSD 960 EVO drops off the PCIe bus after system
2735 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2736 * within few minutes after bootup on a Coffee Lake board -
2739 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2740 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2741 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2742 return NVME_QUIRK_NO_APST;
2743 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2744 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2745 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2747 * Forcing to use host managed nvme power settings for
2748 * lowest idle power with quick resume latency on
2749 * Samsung and Toshiba SSDs based on suspend behavior
2750 * on Coffee Lake board for LENOVO C640
2752 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2753 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2754 return NVME_QUIRK_SIMPLE_SUSPEND;
2760 static void nvme_async_probe(void *data, async_cookie_t cookie)
2762 struct nvme_dev *dev = data;
2764 flush_work(&dev->ctrl.reset_work);
2765 flush_work(&dev->ctrl.scan_work);
2766 nvme_put_ctrl(&dev->ctrl);
2769 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2771 int node, result = -ENOMEM;
2772 struct nvme_dev *dev;
2773 unsigned long quirks = id->driver_data;
2776 node = dev_to_node(&pdev->dev);
2777 if (node == NUMA_NO_NODE)
2778 set_dev_node(&pdev->dev, first_memory_node);
2780 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2784 dev->nr_write_queues = write_queues;
2785 dev->nr_poll_queues = poll_queues;
2786 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2787 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2788 sizeof(struct nvme_queue), GFP_KERNEL, node);
2792 dev->dev = get_device(&pdev->dev);
2793 pci_set_drvdata(pdev, dev);
2795 result = nvme_dev_map(dev);
2799 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2800 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2801 mutex_init(&dev->shutdown_lock);
2803 result = nvme_setup_prp_pools(dev);
2807 quirks |= check_vendor_combination_bug(pdev);
2810 * Double check that our mempool alloc size will cover the biggest
2811 * command we support.
2813 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2814 NVME_MAX_SEGS, true);
2815 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2817 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2819 (void *) alloc_size,
2821 if (!dev->iod_mempool) {
2826 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2829 goto release_mempool;
2831 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2833 nvme_reset_ctrl(&dev->ctrl);
2834 async_schedule(nvme_async_probe, dev);
2839 mempool_destroy(dev->iod_mempool);
2841 nvme_release_prp_pools(dev);
2843 nvme_dev_unmap(dev);
2845 put_device(dev->dev);
2852 static void nvme_reset_prepare(struct pci_dev *pdev)
2854 struct nvme_dev *dev = pci_get_drvdata(pdev);
2857 * We don't need to check the return value from waiting for the reset
2858 * state as pci_dev device lock is held, making it impossible to race
2861 nvme_disable_prepare_reset(dev, false);
2862 nvme_sync_queues(&dev->ctrl);
2865 static void nvme_reset_done(struct pci_dev *pdev)
2867 struct nvme_dev *dev = pci_get_drvdata(pdev);
2869 if (!nvme_try_sched_reset(&dev->ctrl))
2870 flush_work(&dev->ctrl.reset_work);
2873 static void nvme_shutdown(struct pci_dev *pdev)
2875 struct nvme_dev *dev = pci_get_drvdata(pdev);
2876 nvme_disable_prepare_reset(dev, true);
2880 * The driver's remove may be called on a device in a partially initialized
2881 * state. This function must not have any dependencies on the device state in
2884 static void nvme_remove(struct pci_dev *pdev)
2886 struct nvme_dev *dev = pci_get_drvdata(pdev);
2888 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2889 pci_set_drvdata(pdev, NULL);
2891 if (!pci_device_is_present(pdev)) {
2892 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2893 nvme_dev_disable(dev, true);
2894 nvme_dev_remove_admin(dev);
2897 flush_work(&dev->ctrl.reset_work);
2898 nvme_stop_ctrl(&dev->ctrl);
2899 nvme_remove_namespaces(&dev->ctrl);
2900 nvme_dev_disable(dev, true);
2901 nvme_release_cmb(dev);
2902 nvme_free_host_mem(dev);
2903 nvme_dev_remove_admin(dev);
2904 nvme_free_queues(dev, 0);
2905 nvme_release_prp_pools(dev);
2906 nvme_dev_unmap(dev);
2907 nvme_uninit_ctrl(&dev->ctrl);
2910 #ifdef CONFIG_PM_SLEEP
2911 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2913 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2916 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2918 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2921 static int nvme_resume(struct device *dev)
2923 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2924 struct nvme_ctrl *ctrl = &ndev->ctrl;
2926 if (ndev->last_ps == U32_MAX ||
2927 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
2928 return nvme_try_sched_reset(&ndev->ctrl);
2932 static int nvme_suspend(struct device *dev)
2934 struct pci_dev *pdev = to_pci_dev(dev);
2935 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2936 struct nvme_ctrl *ctrl = &ndev->ctrl;
2939 ndev->last_ps = U32_MAX;
2942 * The platform does not remove power for a kernel managed suspend so
2943 * use host managed nvme power settings for lowest idle power if
2944 * possible. This should have quicker resume latency than a full device
2945 * shutdown. But if the firmware is involved after the suspend or the
2946 * device does not support any non-default power states, shut down the
2949 * If ASPM is not enabled for the device, shut down the device and allow
2950 * the PCI bus layer to put it into D3 in order to take the PCIe link
2951 * down, so as to allow the platform to achieve its minimum low-power
2952 * state (which may not be possible if the link is up).
2954 * If a host memory buffer is enabled, shut down the device as the NVMe
2955 * specification allows the device to access the host memory buffer in
2956 * host DRAM from all power states, but hosts will fail access to DRAM
2959 if (pm_suspend_via_firmware() || !ctrl->npss ||
2960 !pcie_aspm_enabled(pdev) ||
2961 ndev->nr_host_mem_descs ||
2962 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
2963 return nvme_disable_prepare_reset(ndev, true);
2965 nvme_start_freeze(ctrl);
2966 nvme_wait_freeze(ctrl);
2967 nvme_sync_queues(ctrl);
2969 if (ctrl->state != NVME_CTRL_LIVE)
2972 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2977 * A saved state prevents pci pm from generically controlling the
2978 * device's power. If we're using protocol specific settings, we don't
2979 * want pci interfering.
2981 pci_save_state(pdev);
2983 ret = nvme_set_power_state(ctrl, ctrl->npss);
2988 /* discard the saved state */
2989 pci_load_saved_state(pdev, NULL);
2992 * Clearing npss forces a controller reset on resume. The
2993 * correct value will be rediscovered then.
2995 ret = nvme_disable_prepare_reset(ndev, true);
2999 nvme_unfreeze(ctrl);
3003 static int nvme_simple_suspend(struct device *dev)
3005 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3006 return nvme_disable_prepare_reset(ndev, true);
3009 static int nvme_simple_resume(struct device *dev)
3011 struct pci_dev *pdev = to_pci_dev(dev);
3012 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3014 return nvme_try_sched_reset(&ndev->ctrl);
3017 static const struct dev_pm_ops nvme_dev_pm_ops = {
3018 .suspend = nvme_suspend,
3019 .resume = nvme_resume,
3020 .freeze = nvme_simple_suspend,
3021 .thaw = nvme_simple_resume,
3022 .poweroff = nvme_simple_suspend,
3023 .restore = nvme_simple_resume,
3025 #endif /* CONFIG_PM_SLEEP */
3027 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3028 pci_channel_state_t state)
3030 struct nvme_dev *dev = pci_get_drvdata(pdev);
3033 * A frozen channel requires a reset. When detected, this method will
3034 * shutdown the controller to quiesce. The controller will be restarted
3035 * after the slot reset through driver's slot_reset callback.
3038 case pci_channel_io_normal:
3039 return PCI_ERS_RESULT_CAN_RECOVER;
3040 case pci_channel_io_frozen:
3041 dev_warn(dev->ctrl.device,
3042 "frozen state error detected, reset controller\n");
3043 nvme_dev_disable(dev, false);
3044 return PCI_ERS_RESULT_NEED_RESET;
3045 case pci_channel_io_perm_failure:
3046 dev_warn(dev->ctrl.device,
3047 "failure state error detected, request disconnect\n");
3048 return PCI_ERS_RESULT_DISCONNECT;
3050 return PCI_ERS_RESULT_NEED_RESET;
3053 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3055 struct nvme_dev *dev = pci_get_drvdata(pdev);
3057 dev_info(dev->ctrl.device, "restart after slot reset\n");
3058 pci_restore_state(pdev);
3059 nvme_reset_ctrl(&dev->ctrl);
3060 return PCI_ERS_RESULT_RECOVERED;
3063 static void nvme_error_resume(struct pci_dev *pdev)
3065 struct nvme_dev *dev = pci_get_drvdata(pdev);
3067 flush_work(&dev->ctrl.reset_work);
3070 static const struct pci_error_handlers nvme_err_handler = {
3071 .error_detected = nvme_error_detected,
3072 .slot_reset = nvme_slot_reset,
3073 .resume = nvme_error_resume,
3074 .reset_prepare = nvme_reset_prepare,
3075 .reset_done = nvme_reset_done,
3078 static const struct pci_device_id nvme_id_table[] = {
3079 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3080 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3081 NVME_QUIRK_DEALLOCATE_ZEROES, },
3082 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
3083 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3084 NVME_QUIRK_DEALLOCATE_ZEROES, },
3085 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
3086 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3087 NVME_QUIRK_DEALLOCATE_ZEROES, },
3088 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
3089 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3090 NVME_QUIRK_DEALLOCATE_ZEROES, },
3091 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3092 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3093 NVME_QUIRK_MEDIUM_PRIO_SQ |
3094 NVME_QUIRK_NO_TEMP_THRESH_CHANGE },
3095 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3096 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3097 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3098 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3099 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3100 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3101 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3102 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3103 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3104 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3105 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3106 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3107 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3108 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3109 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3110 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3111 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3112 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3113 .driver_data = NVME_QUIRK_LIGHTNVM, },
3114 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3115 .driver_data = NVME_QUIRK_LIGHTNVM, },
3116 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3117 .driver_data = NVME_QUIRK_LIGHTNVM, },
3118 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3119 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3120 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3121 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3122 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3123 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3124 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3125 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3126 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3127 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3128 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3129 NVME_QUIRK_128_BYTES_SQES |
3130 NVME_QUIRK_SHARED_TAGS },
3133 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3135 static struct pci_driver nvme_driver = {
3137 .id_table = nvme_id_table,
3138 .probe = nvme_probe,
3139 .remove = nvme_remove,
3140 .shutdown = nvme_shutdown,
3141 #ifdef CONFIG_PM_SLEEP
3143 .pm = &nvme_dev_pm_ops,
3146 .sriov_configure = pci_sriov_configure_simple,
3147 .err_handler = &nvme_err_handler,
3150 static int __init nvme_init(void)
3152 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3153 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3154 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3155 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3157 return pci_register_driver(&nvme_driver);
3160 static void __exit nvme_exit(void)
3162 pci_unregister_driver(&nvme_driver);
3163 flush_workqueue(nvme_wq);
3166 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3167 MODULE_LICENSE("GPL");
3168 MODULE_VERSION("1.0");
3169 module_init(nvme_init);
3170 module_exit(nvme_exit);