drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/aer.h>
   9 #include <linux/async.h>
  10 #include <linux/blkdev.h>
  11 #include <linux/blk-mq.h>
  12 #include <linux/blk-mq-pci.h>
  13 #include <linux/blk-integrity.h>
  14 #include <linux/dmi.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/memremap.h>
  19 #include <linux/mm.h>
  20 #include <linux/module.h>
  21 #include <linux/mutex.h>
  22 #include <linux/once.h>
  23 #include <linux/pci.h>
  24 #include <linux/suspend.h>
  25 #include <linux/t10-pi.h>
  26 #include <linux/types.h>
  27 #include <linux/io-64-nonatomic-lo-hi.h>
  28 #include <linux/io-64-nonatomic-hi-lo.h>
  29 #include <linux/sed-opal.h>
  30 #include <linux/pci-p2pdma.h>
  31
  32 #include "trace.h"
  33 #include "nvme.h"
  34
  35 #define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  36 #define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  37
  38 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  39
  40 /*
  41  * These can be higher, but we need to ensure that any command doesn't
  42  * require an sg allocation that needs more than a page of data.
  43  */
  44 #define NVME_MAX_KB_SZ  4096
  45 #define NVME_MAX_SEGS   127
  46
  47 static int use_threaded_interrupts;
  48 module_param(use_threaded_interrupts, int, 0444);
  49
  50 static bool use_cmb_sqes = true;
  51 module_param(use_cmb_sqes, bool, 0444);
  52 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  53
  54 static unsigned int max_host_mem_size_mb = 128;
  55 module_param(max_host_mem_size_mb, uint, 0444);
  56 MODULE_PARM_DESC(max_host_mem_size_mb,
  57         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  58
  59 static unsigned int sgl_threshold = SZ_32K;
  60 module_param(sgl_threshold, uint, 0644);
  61 MODULE_PARM_DESC(sgl_threshold,
  62                 "Use SGLs when average request segment size is larger or equal to "
  63                 "this size. Use 0 to disable SGLs.");
  64
  65 #define NVME_PCI_MIN_QUEUE_SIZE 2
  66 #define NVME_PCI_MAX_QUEUE_SIZE 4095
  67 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  68 static const struct kernel_param_ops io_queue_depth_ops = {
  69         .set = io_queue_depth_set,
  70         .get = param_get_uint,
  71 };
  72
  73 static unsigned int io_queue_depth = 1024;
  74 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  75 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
  76
  77 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  78 {
  79         unsigned int n;
  80         int ret;
  81
  82         ret = kstrtouint(val, 10, &n);
  83         if (ret != 0 || n > num_possible_cpus())
  84                 return -EINVAL;
  85         return param_set_uint(val, kp);
  86 }
  87
  88 static const struct kernel_param_ops io_queue_count_ops = {
  89         .set = io_queue_count_set,
  90         .get = param_get_uint,
  91 };
  92
  93 static unsigned int write_queues;
  94 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  95 MODULE_PARM_DESC(write_queues,
  96         "Number of queues to use for writes. If not set, reads and writes "
  97         "will share a queue set.");
  98
  99 static unsigned int poll_queues;
 100 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
 101 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
 102
 103 static bool noacpi;
 104 module_param(noacpi, bool, 0444);
 105 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 106
 107 struct nvme_dev;
 108 struct nvme_queue;
 109
 110 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 111 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
 112
 113 /*
 114  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 115  */
 116 struct nvme_dev {
 117         struct nvme_queue *queues;
 118         struct blk_mq_tag_set tagset;
 119         struct blk_mq_tag_set admin_tagset;
 120         u32 __iomem *dbs;
 121         struct device *dev;
 122         struct dma_pool *prp_page_pool;
 123         struct dma_pool *prp_small_pool;
 124         unsigned online_queues;
 125         unsigned max_qid;
 126         unsigned io_queues[HCTX_MAX_TYPES];
 127         unsigned int num_vecs;
 128         u32 q_depth;
 129         int io_sqes;
 130         u32 db_stride;
 131         void __iomem *bar;
 132         unsigned long bar_mapped_size;
 133         struct work_struct remove_work;
 134         struct mutex shutdown_lock;
 135         bool subsystem;
 136         u64 cmb_size;
 137         bool cmb_use_sqes;
 138         u32 cmbsz;
 139         u32 cmbloc;
 140         struct nvme_ctrl ctrl;
 141         u32 last_ps;
 142         bool hmb;
 143
 144         mempool_t *iod_mempool;
 145
 146         /* shadow doorbell buffer support: */
 147         u32 *dbbuf_dbs;
 148         dma_addr_t dbbuf_dbs_dma_addr;
 149         u32 *dbbuf_eis;
 150         dma_addr_t dbbuf_eis_dma_addr;
 151
 152         /* host memory buffer support: */
 153         u64 host_mem_size;
 154         u32 nr_host_mem_descs;
 155         dma_addr_t host_mem_descs_dma;
 156         struct nvme_host_mem_buf_desc *host_mem_descs;
 157         void **host_mem_desc_bufs;
 158         unsigned int nr_allocated_queues;
 159         unsigned int nr_write_queues;
 160         unsigned int nr_poll_queues;
 161
 162         bool attrs_added;
 163 };
 164
 165 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 166 {
 167         return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
 168                         NVME_PCI_MAX_QUEUE_SIZE);
 169 }
 170
 171 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 172 {
 173         return qid * 2 * stride;
 174 }
 175
 176 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 177 {
 178         return (qid * 2 + 1) * stride;
 179 }
 180
 181 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 182 {
 183         return container_of(ctrl, struct nvme_dev, ctrl);
 184 }
 185
 186 /*
 187  * An NVM Express queue.  Each device has at least two (one for admin
 188  * commands and one for I/O commands).
 189  */
 190 struct nvme_queue {
 191         struct nvme_dev *dev;
 192         spinlock_t sq_lock;
 193         void *sq_cmds;
 194          /* only used for poll queues: */
 195         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 196         struct nvme_completion *cqes;
 197         dma_addr_t sq_dma_addr;
 198         dma_addr_t cq_dma_addr;
 199         u32 __iomem *q_db;
 200         u32 q_depth;
 201         u16 cq_vector;
 202         u16 sq_tail;
 203         u16 last_sq_tail;
 204         u16 cq_head;
 205         u16 qid;
 206         u8 cq_phase;
 207         u8 sqes;
 208         unsigned long flags;
 209 #define NVMEQ_ENABLED           0
 210 #define NVMEQ_SQ_CMB            1
 211 #define NVMEQ_DELETE_ERROR      2
 212 #define NVMEQ_POLLED            3
 213         u32 *dbbuf_sq_db;
 214         u32 *dbbuf_cq_db;
 215         u32 *dbbuf_sq_ei;
 216         u32 *dbbuf_cq_ei;
 217         struct completion delete_done;
 218 };
 219
 220 /*
 221  * The nvme_iod describes the data in an I/O.
 222  *
 223  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 224  * to the actual struct scatterlist.
 225  */
 226 struct nvme_iod {
 227         struct nvme_request req;
 228         struct nvme_command cmd;
 229         struct nvme_queue *nvmeq;
 230         bool use_sgl;
 231         int aborted;
 232         int npages;             /* In the PRP list. 0 means small pool in use */
 233         int nents;              /* Used in scatterlist */
 234         dma_addr_t first_dma;
 235         unsigned int dma_len;   /* length of single DMA segment mapping */
 236         dma_addr_t meta_dma;
 237         struct scatterlist *sg;
 238 };
 239
 240 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 241 {
 242         return dev->nr_allocated_queues * 8 * dev->db_stride;
 243 }
 244
 245 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 246 {
 247         unsigned int mem_size = nvme_dbbuf_size(dev);
 248
 249         if (dev->dbbuf_dbs) {
 250                 /*
 251                  * Clear the dbbuf memory so the driver doesn't observe stale
 252                  * values from the previous instantiation.
 253                  */
 254                 memset(dev->dbbuf_dbs, 0, mem_size);
 255                 memset(dev->dbbuf_eis, 0, mem_size);
 256                 return 0;
 257         }
 258
 259         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 260                                             &dev->dbbuf_dbs_dma_addr,
 261                                             GFP_KERNEL);
 262         if (!dev->dbbuf_dbs)
 263                 return -ENOMEM;
 264         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 265                                             &dev->dbbuf_eis_dma_addr,
 266                                             GFP_KERNEL);
 267         if (!dev->dbbuf_eis) {
 268                 dma_free_coherent(dev->dev, mem_size,
 269                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 270                 dev->dbbuf_dbs = NULL;
 271                 return -ENOMEM;
 272         }
 273
 274         return 0;
 275 }
 276
 277 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 278 {
 279         unsigned int mem_size = nvme_dbbuf_size(dev);
 280
 281         if (dev->dbbuf_dbs) {
 282                 dma_free_coherent(dev->dev, mem_size,
 283                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 284                 dev->dbbuf_dbs = NULL;
 285         }
 286         if (dev->dbbuf_eis) {
 287                 dma_free_coherent(dev->dev, mem_size,
 288                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 289                 dev->dbbuf_eis = NULL;
 290         }
 291 }
 292
 293 static void nvme_dbbuf_init(struct nvme_dev *dev,
 294                             struct nvme_queue *nvmeq, int qid)
 295 {
 296         if (!dev->dbbuf_dbs || !qid)
 297                 return;
 298
 299         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 300         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 301         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 302         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 303 }
 304
 305 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 306 {
 307         if (!nvmeq->qid)
 308                 return;
 309
 310         nvmeq->dbbuf_sq_db = NULL;
 311         nvmeq->dbbuf_cq_db = NULL;
 312         nvmeq->dbbuf_sq_ei = NULL;
 313         nvmeq->dbbuf_cq_ei = NULL;
 314 }
 315
 316 static void nvme_dbbuf_set(struct nvme_dev *dev)
 317 {
 318         struct nvme_command c = { };
 319         unsigned int i;
 320
 321         if (!dev->dbbuf_dbs)
 322                 return;
 323
 324         c.dbbuf.opcode = nvme_admin_dbbuf;
 325         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 326         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 327
 328         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 329                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 330                 /* Free memory and continue on */
 331                 nvme_dbbuf_dma_free(dev);
 332
 333                 for (i = 1; i <= dev->online_queues; i++)
 334                         nvme_dbbuf_free(&dev->queues[i]);
 335         }
 336 }
 337
 338 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 339 {
 340         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 341 }
 342
 343 /* Update dbbuf and return true if an MMIO is required */
 344 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 345                                               volatile u32 *dbbuf_ei)
 346 {
 347         if (dbbuf_db) {
 348                 u16 old_value;
 349
 350                 /*
 351                  * Ensure that the queue is written before updating
 352                  * the doorbell in memory
 353                  */
 354                 wmb();
 355
 356                 old_value = *dbbuf_db;
 357                 *dbbuf_db = value;
 358
 359                 /*
 360                  * Ensure that the doorbell is updated before reading the event
 361                  * index from memory.  The controller needs to provide similar
 362                  * ordering to ensure the envent index is updated before reading
 363                  * the doorbell.
 364                  */
 365                 mb();
 366
 367                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 368                         return false;
 369         }
 370
 371         return true;
 372 }
 373
 374 /*
 375  * Will slightly overestimate the number of pages needed.  This is OK
 376  * as it only leads to a small amount of wasted memory for the lifetime of
 377  * the I/O.
 378  */
 379 static int nvme_pci_npages_prp(void)
 380 {
 381         unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
 382                                       NVME_CTRL_PAGE_SIZE);
 383         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 384 }
 385
 386 /*
 387  * Calculates the number of pages needed for the SGL segments. For example a 4k
 388  * page can accommodate 256 SGL descriptors.
 389  */
 390 static int nvme_pci_npages_sgl(void)
 391 {
 392         return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
 393                         PAGE_SIZE);
 394 }
 395
 396 static size_t nvme_pci_iod_alloc_size(void)
 397 {
 398         size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
 399
 400         return sizeof(__le64 *) * npages +
 401                 sizeof(struct scatterlist) * NVME_MAX_SEGS;
 402 }
 403
 404 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 405                                 unsigned int hctx_idx)
 406 {
 407         struct nvme_dev *dev = data;
 408         struct nvme_queue *nvmeq = &dev->queues[0];
 409
 410         WARN_ON(hctx_idx != 0);
 411         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 412
 413         hctx->driver_data = nvmeq;
 414         return 0;
 415 }
 416
 417 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 418                           unsigned int hctx_idx)
 419 {
 420         struct nvme_dev *dev = data;
 421         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 422
 423         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 424         hctx->driver_data = nvmeq;
 425         return 0;
 426 }
 427
 428 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
 429                 struct request *req, unsigned int hctx_idx,
 430                 unsigned int numa_node)
 431 {
 432         struct nvme_dev *dev = set->driver_data;
 433         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 434         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 435         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 436
 437         BUG_ON(!nvmeq);
 438         iod->nvmeq = nvmeq;
 439
 440         nvme_req(req)->ctrl = &dev->ctrl;
 441         nvme_req(req)->cmd = &iod->cmd;
 442         return 0;
 443 }
 444
 445 static int queue_irq_offset(struct nvme_dev *dev)
 446 {
 447         /* if we have more than 1 vec, admin queue offsets us by 1 */
 448         if (dev->num_vecs > 1)
 449                 return 1;
 450
 451         return 0;
 452 }
 453
 454 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 455 {
 456         struct nvme_dev *dev = set->driver_data;
 457         int i, qoff, offset;
 458
 459         offset = queue_irq_offset(dev);
 460         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 461                 struct blk_mq_queue_map *map = &set->map[i];
 462
 463                 map->nr_queues = dev->io_queues[i];
 464                 if (!map->nr_queues) {
 465                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 466                         continue;
 467                 }
 468
 469                 /*
 470                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 471                  * affinity), so use the regular blk-mq cpu mapping
 472                  */
 473                 map->queue_offset = qoff;
 474                 if (i != HCTX_TYPE_POLL && offset)
 475                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 476                 else
 477                         blk_mq_map_queues(map);
 478                 qoff += map->nr_queues;
 479                 offset += map->nr_queues;
 480         }
 481
 482         return 0;
 483 }
 484
 485 /*
 486  * Write sq tail if we are asked to, or if the next command would wrap.
 487  */
 488 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 489 {
 490         if (!write_sq) {
 491                 u16 next_tail = nvmeq->sq_tail + 1;
 492
 493                 if (next_tail == nvmeq->q_depth)
 494                         next_tail = 0;
 495                 if (next_tail != nvmeq->last_sq_tail)
 496                         return;
 497         }
 498
 499         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 500                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 501                 writel(nvmeq->sq_tail, nvmeq->q_db);
 502         nvmeq->last_sq_tail = nvmeq->sq_tail;
 503 }
 504
 505 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
 506                                     struct nvme_command *cmd)
 507 {
 508         memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 509                 absolute_pointer(cmd), sizeof(*cmd));
 510         if (++nvmeq->sq_tail == nvmeq->q_depth)
 511                 nvmeq->sq_tail = 0;
 512 }
 513
 514 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 515 {
 516         struct nvme_queue *nvmeq = hctx->driver_data;
 517
 518         spin_lock(&nvmeq->sq_lock);
 519         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 520                 nvme_write_sq_db(nvmeq, true);
 521         spin_unlock(&nvmeq->sq_lock);
 522 }
 523
 524 static void **nvme_pci_iod_list(struct request *req)
 525 {
 526         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 527         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 528 }
 529
 530 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 531 {
 532         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 533         int nseg = blk_rq_nr_phys_segments(req);
 534         unsigned int avg_seg_size;
 535
 536         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 537
 538         if (!nvme_ctrl_sgl_supported(&dev->ctrl))
 539                 return false;
 540         if (!iod->nvmeq->qid)
 541                 return false;
 542         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 543                 return false;
 544         return true;
 545 }
 546
 547 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
 548 {
 549         const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 550         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 551         dma_addr_t dma_addr = iod->first_dma;
 552         int i;
 553
 554         for (i = 0; i < iod->npages; i++) {
 555                 __le64 *prp_list = nvme_pci_iod_list(req)[i];
 556                 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 557
 558                 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
 559                 dma_addr = next_dma_addr;
 560         }
 561 }
 562
 563 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
 564 {
 565         const int last_sg = SGES_PER_PAGE - 1;
 566         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 567         dma_addr_t dma_addr = iod->first_dma;
 568         int i;
 569
 570         for (i = 0; i < iod->npages; i++) {
 571                 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
 572                 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
 573
 574                 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
 575                 dma_addr = next_dma_addr;
 576         }
 577 }
 578
 579 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
 580 {
 581         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 582
 583         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 584                 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
 585                                     rq_dma_dir(req));
 586         else
 587                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
 588 }
 589
 590 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 591 {
 592         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 593
 594         if (iod->dma_len) {
 595                 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
 596                                rq_dma_dir(req));
 597                 return;
 598         }
 599
 600         WARN_ON_ONCE(!iod->nents);
 601
 602         nvme_unmap_sg(dev, req);
 603         if (iod->npages == 0)
 604                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 605                               iod->first_dma);
 606         else if (iod->use_sgl)
 607                 nvme_free_sgls(dev, req);
 608         else
 609                 nvme_free_prps(dev, req);
 610         mempool_free(iod->sg, dev->iod_mempool);
 611 }
 612
 613 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 614 {
 615         int i;
 616         struct scatterlist *sg;
 617
 618         for_each_sg(sgl, sg, nents, i) {
 619                 dma_addr_t phys = sg_phys(sg);
 620                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 621                         "dma_address:%pad dma_length:%d\n",
 622                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 623                         sg_dma_len(sg));
 624         }
 625 }
 626
 627 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 628                 struct request *req, struct nvme_rw_command *cmnd)
 629 {
 630         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 631         struct dma_pool *pool;
 632         int length = blk_rq_payload_bytes(req);
 633         struct scatterlist *sg = iod->sg;
 634         int dma_len = sg_dma_len(sg);
 635         u64 dma_addr = sg_dma_address(sg);
 636         int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 637         __le64 *prp_list;
 638         void **list = nvme_pci_iod_list(req);
 639         dma_addr_t prp_dma;
 640         int nprps, i;
 641
 642         length -= (NVME_CTRL_PAGE_SIZE - offset);
 643         if (length <= 0) {
 644                 iod->first_dma = 0;
 645                 goto done;
 646         }
 647
 648         dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 649         if (dma_len) {
 650                 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 651         } else {
 652                 sg = sg_next(sg);
 653                 dma_addr = sg_dma_address(sg);
 654                 dma_len = sg_dma_len(sg);
 655         }
 656
 657         if (length <= NVME_CTRL_PAGE_SIZE) {
 658                 iod->first_dma = dma_addr;
 659                 goto done;
 660         }
 661
 662         nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 663         if (nprps <= (256 / 8)) {
 664                 pool = dev->prp_small_pool;
 665                 iod->npages = 0;
 666         } else {
 667                 pool = dev->prp_page_pool;
 668                 iod->npages = 1;
 669         }
 670
 671         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 672         if (!prp_list) {
 673                 iod->first_dma = dma_addr;
 674                 iod->npages = -1;
 675                 return BLK_STS_RESOURCE;
 676         }
 677         list[0] = prp_list;
 678         iod->first_dma = prp_dma;
 679         i = 0;
 680         for (;;) {
 681                 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 682                         __le64 *old_prp_list = prp_list;
 683                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 684                         if (!prp_list)
 685                                 goto free_prps;
 686                         list[iod->npages++] = prp_list;
 687                         prp_list[0] = old_prp_list[i - 1];
 688                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 689                         i = 1;
 690                 }
 691                 prp_list[i++] = cpu_to_le64(dma_addr);
 692                 dma_len -= NVME_CTRL_PAGE_SIZE;
 693                 dma_addr += NVME_CTRL_PAGE_SIZE;
 694                 length -= NVME_CTRL_PAGE_SIZE;
 695                 if (length <= 0)
 696                         break;
 697                 if (dma_len > 0)
 698                         continue;
 699                 if (unlikely(dma_len < 0))
 700                         goto bad_sgl;
 701                 sg = sg_next(sg);
 702                 dma_addr = sg_dma_address(sg);
 703                 dma_len = sg_dma_len(sg);
 704         }
 705 done:
 706         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 707         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 708         return BLK_STS_OK;
 709 free_prps:
 710         nvme_free_prps(dev, req);
 711         return BLK_STS_RESOURCE;
 712 bad_sgl:
 713         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 714                         "Invalid SGL for payload:%d nents:%d\n",
 715                         blk_rq_payload_bytes(req), iod->nents);
 716         return BLK_STS_IOERR;
 717 }
 718
 719 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 720                 struct scatterlist *sg)
 721 {
 722         sge->addr = cpu_to_le64(sg_dma_address(sg));
 723         sge->length = cpu_to_le32(sg_dma_len(sg));
 724         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 725 }
 726
 727 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 728                 dma_addr_t dma_addr, int entries)
 729 {
 730         sge->addr = cpu_to_le64(dma_addr);
 731         if (entries < SGES_PER_PAGE) {
 732                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 733                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 734         } else {
 735                 sge->length = cpu_to_le32(PAGE_SIZE);
 736                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 737         }
 738 }
 739
 740 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 741                 struct request *req, struct nvme_rw_command *cmd, int entries)
 742 {
 743         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 744         struct dma_pool *pool;
 745         struct nvme_sgl_desc *sg_list;
 746         struct scatterlist *sg = iod->sg;
 747         dma_addr_t sgl_dma;
 748         int i = 0;
 749
 750         /* setting the transfer type as SGL */
 751         cmd->flags = NVME_CMD_SGL_METABUF;
 752
 753         if (entries == 1) {
 754                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 755                 return BLK_STS_OK;
 756         }
 757
 758         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 759                 pool = dev->prp_small_pool;
 760                 iod->npages = 0;
 761         } else {
 762                 pool = dev->prp_page_pool;
 763                 iod->npages = 1;
 764         }
 765
 766         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 767         if (!sg_list) {
 768                 iod->npages = -1;
 769                 return BLK_STS_RESOURCE;
 770         }
 771
 772         nvme_pci_iod_list(req)[0] = sg_list;
 773         iod->first_dma = sgl_dma;
 774
 775         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 776
 777         do {
 778                 if (i == SGES_PER_PAGE) {
 779                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 780                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 781
 782                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 783                         if (!sg_list)
 784                                 goto free_sgls;
 785
 786                         i = 0;
 787                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 788                         sg_list[i++] = *link;
 789                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 790                 }
 791
 792                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 793                 sg = sg_next(sg);
 794         } while (--entries > 0);
 795
 796         return BLK_STS_OK;
 797 free_sgls:
 798         nvme_free_sgls(dev, req);
 799         return BLK_STS_RESOURCE;
 800 }
 801
 802 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 803                 struct request *req, struct nvme_rw_command *cmnd,
 804                 struct bio_vec *bv)
 805 {
 806         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 807         unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 808         unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 809
 810         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 811         if (dma_mapping_error(dev->dev, iod->first_dma))
 812                 return BLK_STS_RESOURCE;
 813         iod->dma_len = bv->bv_len;
 814
 815         cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 816         if (bv->bv_len > first_prp_len)
 817                 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 818         return BLK_STS_OK;
 819 }
 820
 821 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 822                 struct request *req, struct nvme_rw_command *cmnd,
 823                 struct bio_vec *bv)
 824 {
 825         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 826
 827         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 828         if (dma_mapping_error(dev->dev, iod->first_dma))
 829                 return BLK_STS_RESOURCE;
 830         iod->dma_len = bv->bv_len;
 831
 832         cmnd->flags = NVME_CMD_SGL_METABUF;
 833         cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 834         cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 835         cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 836         return BLK_STS_OK;
 837 }
 838
 839 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 840                 struct nvme_command *cmnd)
 841 {
 842         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 843         blk_status_t ret = BLK_STS_RESOURCE;
 844         int nr_mapped;
 845
 846         if (blk_rq_nr_phys_segments(req) == 1) {
 847                 struct bio_vec bv = req_bvec(req);
 848
 849                 if (!is_pci_p2pdma_page(bv.bv_page)) {
 850                         if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 851                                 return nvme_setup_prp_simple(dev, req,
 852                                                              &cmnd->rw, &bv);
 853
 854                         if (iod->nvmeq->qid && sgl_threshold &&
 855                             nvme_ctrl_sgl_supported(&dev->ctrl))
 856                                 return nvme_setup_sgl_simple(dev, req,
 857                                                              &cmnd->rw, &bv);
 858                 }
 859         }
 860
 861         iod->dma_len = 0;
 862         iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 863         if (!iod->sg)
 864                 return BLK_STS_RESOURCE;
 865         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 866         iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
 867         if (!iod->nents)
 868                 goto out_free_sg;
 869
 870         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 871                 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
 872                                 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
 873         else
 874                 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
 875                                              rq_dma_dir(req), DMA_ATTR_NO_WARN);
 876         if (!nr_mapped)
 877                 goto out_free_sg;
 878
 879         iod->use_sgl = nvme_pci_use_sgls(dev, req);
 880         if (iod->use_sgl)
 881                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
 882         else
 883                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 884         if (ret != BLK_STS_OK)
 885                 goto out_unmap_sg;
 886         return BLK_STS_OK;
 887
 888 out_unmap_sg:
 889         nvme_unmap_sg(dev, req);
 890 out_free_sg:
 891         mempool_free(iod->sg, dev->iod_mempool);
 892         return ret;
 893 }
 894
 895 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 896                 struct nvme_command *cmnd)
 897 {
 898         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 899
 900         iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 901                         rq_dma_dir(req), 0);
 902         if (dma_mapping_error(dev->dev, iod->meta_dma))
 903                 return BLK_STS_IOERR;
 904         cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 905         return BLK_STS_OK;
 906 }
 907
 908 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
 909 {
 910         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 911         blk_status_t ret;
 912
 913         iod->aborted = 0;
 914         iod->npages = -1;
 915         iod->nents = 0;
 916
 917         ret = nvme_setup_cmd(req->q->queuedata, req);
 918         if (ret)
 919                 return ret;
 920
 921         if (blk_rq_nr_phys_segments(req)) {
 922                 ret = nvme_map_data(dev, req, &iod->cmd);
 923                 if (ret)
 924                         goto out_free_cmd;
 925         }
 926
 927         if (blk_integrity_rq(req)) {
 928                 ret = nvme_map_metadata(dev, req, &iod->cmd);
 929                 if (ret)
 930                         goto out_unmap_data;
 931         }
 932
 933         blk_mq_start_request(req);
 934         return BLK_STS_OK;
 935 out_unmap_data:
 936         nvme_unmap_data(dev, req);
 937 out_free_cmd:
 938         nvme_cleanup_cmd(req);
 939         return ret;
 940 }
 941
 942 /*
 943  * NOTE: ns is NULL when called on the admin queue.
 944  */
 945 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 946                          const struct blk_mq_queue_data *bd)
 947 {
 948         struct nvme_queue *nvmeq = hctx->driver_data;
 949         struct nvme_dev *dev = nvmeq->dev;
 950         struct request *req = bd->rq;
 951         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 952         blk_status_t ret;
 953
 954         /*
 955          * We should not need to do this, but we're still using this to
 956          * ensure we can drain requests on a dying queue.
 957          */
 958         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 959                 return BLK_STS_IOERR;
 960
 961         if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
 962                 return nvme_fail_nonready_command(&dev->ctrl, req);
 963
 964         ret = nvme_prep_rq(dev, req);
 965         if (unlikely(ret))
 966                 return ret;
 967         spin_lock(&nvmeq->sq_lock);
 968         nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 969         nvme_write_sq_db(nvmeq, bd->last);
 970         spin_unlock(&nvmeq->sq_lock);
 971         return BLK_STS_OK;
 972 }
 973
 974 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
 975 {
 976         spin_lock(&nvmeq->sq_lock);
 977         while (!rq_list_empty(*rqlist)) {
 978                 struct request *req = rq_list_pop(rqlist);
 979                 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 980
 981                 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 982         }
 983         nvme_write_sq_db(nvmeq, true);
 984         spin_unlock(&nvmeq->sq_lock);
 985 }
 986
 987 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
 988 {
 989         /*
 990          * We should not need to do this, but we're still using this to
 991          * ensure we can drain requests on a dying queue.
 992          */
 993         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 994                 return false;
 995         if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
 996                 return false;
 997
 998         req->mq_hctx->tags->rqs[req->tag] = req;
 999         return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
1000 }
1001
1002 static void nvme_queue_rqs(struct request **rqlist)
1003 {
1004         struct request *req, *next, *prev = NULL;
1005         struct request *requeue_list = NULL;
1006
1007         rq_list_for_each_safe(rqlist, req, next) {
1008                 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1009
1010                 if (!nvme_prep_rq_batch(nvmeq, req)) {
1011                         /* detach 'req' and add to remainder list */
1012                         rq_list_move(rqlist, &requeue_list, req, prev);
1013
1014                         req = prev;
1015                         if (!req)
1016                                 continue;
1017                 }
1018
1019                 if (!next || req->mq_hctx != next->mq_hctx) {
1020                         /* detach rest of list, and submit */
1021                         req->rq_next = NULL;
1022                         nvme_submit_cmds(nvmeq, rqlist);
1023                         *rqlist = next;
1024                         prev = NULL;
1025                 } else
1026                         prev = req;
1027         }
1028
1029         *rqlist = requeue_list;
1030 }
1031
1032 static __always_inline void nvme_pci_unmap_rq(struct request *req)
1033 {
1034         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1035         struct nvme_dev *dev = iod->nvmeq->dev;
1036
1037         if (blk_integrity_rq(req))
1038                 dma_unmap_page(dev->dev, iod->meta_dma,
1039                                rq_integrity_vec(req)->bv_len, rq_data_dir(req));
1040         if (blk_rq_nr_phys_segments(req))
1041                 nvme_unmap_data(dev, req);
1042 }
1043
1044 static void nvme_pci_complete_rq(struct request *req)
1045 {
1046         nvme_pci_unmap_rq(req);
1047         nvme_complete_rq(req);
1048 }
1049
1050 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1051 {
1052         nvme_complete_batch(iob, nvme_pci_unmap_rq);
1053 }
1054
1055 /* We read the CQE phase first to check if the rest of the entry is valid */
1056 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
1057 {
1058         struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1059
1060         return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
1061 }
1062
1063 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
1064 {
1065         u16 head = nvmeq->cq_head;
1066
1067         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1068                                               nvmeq->dbbuf_cq_ei))
1069                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1070 }
1071
1072 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1073 {
1074         if (!nvmeq->qid)
1075                 return nvmeq->dev->admin_tagset.tags[0];
1076         return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1077 }
1078
1079 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1080                                    struct io_comp_batch *iob, u16 idx)
1081 {
1082         struct nvme_completion *cqe = &nvmeq->cqes[idx];
1083         __u16 command_id = READ_ONCE(cqe->command_id);
1084         struct request *req;
1085
1086         /*
1087          * AEN requests are special as they don't time out and can
1088          * survive any kind of queue freeze and often don't respond to
1089          * aborts.  We don't even bother to allocate a struct request
1090          * for them but rather special case them here.
1091          */
1092         if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1093                 nvme_complete_async_event(&nvmeq->dev->ctrl,
1094                                 cqe->status, &cqe->result);
1095                 return;
1096         }
1097
1098         req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1099         if (unlikely(!req)) {
1100                 dev_warn(nvmeq->dev->ctrl.device,
1101                         "invalid id %d completed on queue %d\n",
1102                         command_id, le16_to_cpu(cqe->sq_id));
1103                 return;
1104         }
1105
1106         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1107         if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1108             !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1109                                         nvme_pci_complete_batch))
1110                 nvme_pci_complete_rq(req);
1111 }
1112
1113 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1114 {
1115         u32 tmp = nvmeq->cq_head + 1;
1116
1117         if (tmp == nvmeq->q_depth) {
1118                 nvmeq->cq_head = 0;
1119                 nvmeq->cq_phase ^= 1;
1120         } else {
1121                 nvmeq->cq_head = tmp;
1122         }
1123 }
1124
1125 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1126                                struct io_comp_batch *iob)
1127 {
1128         int found = 0;
1129
1130         while (nvme_cqe_pending(nvmeq)) {
1131                 found++;
1132                 /*
1133                  * load-load control dependency between phase and the rest of
1134                  * the cqe requires a full read memory barrier
1135                  */
1136                 dma_rmb();
1137                 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1138                 nvme_update_cq_head(nvmeq);
1139         }
1140
1141         if (found)
1142                 nvme_ring_cq_doorbell(nvmeq);
1143         return found;
1144 }
1145
1146 static irqreturn_t nvme_irq(int irq, void *data)
1147 {
1148         struct nvme_queue *nvmeq = data;
1149         DEFINE_IO_COMP_BATCH(iob);
1150
1151         if (nvme_poll_cq(nvmeq, &iob)) {
1152                 if (!rq_list_empty(iob.req_list))
1153                         nvme_pci_complete_batch(&iob);
1154                 return IRQ_HANDLED;
1155         }
1156         return IRQ_NONE;
1157 }
1158
1159 static irqreturn_t nvme_irq_check(int irq, void *data)
1160 {
1161         struct nvme_queue *nvmeq = data;
1162
1163         if (nvme_cqe_pending(nvmeq))
1164                 return IRQ_WAKE_THREAD;
1165         return IRQ_NONE;
1166 }
1167
1168 /*
1169  * Poll for completions for any interrupt driven queue
1170  * Can be called from any context.
1171  */
1172 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1173 {
1174         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1175
1176         WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1177
1178         disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1179         nvme_poll_cq(nvmeq, NULL);
1180         enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1181 }
1182
1183 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1184 {
1185         struct nvme_queue *nvmeq = hctx->driver_data;
1186         bool found;
1187
1188         if (!nvme_cqe_pending(nvmeq))
1189                 return 0;
1190
1191         spin_lock(&nvmeq->cq_poll_lock);
1192         found = nvme_poll_cq(nvmeq, iob);
1193         spin_unlock(&nvmeq->cq_poll_lock);
1194
1195         return found;
1196 }
1197
1198 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1199 {
1200         struct nvme_dev *dev = to_nvme_dev(ctrl);
1201         struct nvme_queue *nvmeq = &dev->queues[0];
1202         struct nvme_command c = { };
1203
1204         c.common.opcode = nvme_admin_async_event;
1205         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1206
1207         spin_lock(&nvmeq->sq_lock);
1208         nvme_sq_copy_cmd(nvmeq, &c);
1209         nvme_write_sq_db(nvmeq, true);
1210         spin_unlock(&nvmeq->sq_lock);
1211 }
1212
1213 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1214 {
1215         struct nvme_command c = { };
1216
1217         c.delete_queue.opcode = opcode;
1218         c.delete_queue.qid = cpu_to_le16(id);
1219
1220         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1221 }
1222
1223 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1224                 struct nvme_queue *nvmeq, s16 vector)
1225 {
1226         struct nvme_command c = { };
1227         int flags = NVME_QUEUE_PHYS_CONTIG;
1228
1229         if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1230                 flags |= NVME_CQ_IRQ_ENABLED;
1231
1232         /*
1233          * Note: we (ab)use the fact that the prp fields survive if no data
1234          * is attached to the request.
1235          */
1236         c.create_cq.opcode = nvme_admin_create_cq;
1237         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1238         c.create_cq.cqid = cpu_to_le16(qid);
1239         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1240         c.create_cq.cq_flags = cpu_to_le16(flags);
1241         c.create_cq.irq_vector = cpu_to_le16(vector);
1242
1243         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1244 }
1245
1246 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1247                                                 struct nvme_queue *nvmeq)
1248 {
1249         struct nvme_ctrl *ctrl = &dev->ctrl;
1250         struct nvme_command c = { };
1251         int flags = NVME_QUEUE_PHYS_CONTIG;
1252
1253         /*
1254          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1255          * set. Since URGENT priority is zeroes, it makes all queues
1256          * URGENT.
1257          */
1258         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1259                 flags |= NVME_SQ_PRIO_MEDIUM;
1260
1261         /*
1262          * Note: we (ab)use the fact that the prp fields survive if no data
1263          * is attached to the request.
1264          */
1265         c.create_sq.opcode = nvme_admin_create_sq;
1266         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1267         c.create_sq.sqid = cpu_to_le16(qid);
1268         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1269         c.create_sq.sq_flags = cpu_to_le16(flags);
1270         c.create_sq.cqid = cpu_to_le16(qid);
1271
1272         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1273 }
1274
1275 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1276 {
1277         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1278 }
1279
1280 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1281 {
1282         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1283 }
1284
1285 static void abort_endio(struct request *req, blk_status_t error)
1286 {
1287         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1288         struct nvme_queue *nvmeq = iod->nvmeq;
1289
1290         dev_warn(nvmeq->dev->ctrl.device,
1291                  "Abort status: 0x%x", nvme_req(req)->status);
1292         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1293         blk_mq_free_request(req);
1294 }
1295
1296 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1297 {
1298         /* If true, indicates loss of adapter communication, possibly by a
1299          * NVMe Subsystem reset.
1300          */
1301         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1302
1303         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1304         switch (dev->ctrl.state) {
1305         case NVME_CTRL_RESETTING:
1306         case NVME_CTRL_CONNECTING:
1307                 return false;
1308         default:
1309                 break;
1310         }
1311
1312         /* We shouldn't reset unless the controller is on fatal error state
1313          * _or_ if we lost the communication with it.
1314          */
1315         if (!(csts & NVME_CSTS_CFS) && !nssro)
1316                 return false;
1317
1318         return true;
1319 }
1320
1321 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1322 {
1323         /* Read a config register to help see what died. */
1324         u16 pci_status;
1325         int result;
1326
1327         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1328                                       &pci_status);
1329         if (result == PCIBIOS_SUCCESSFUL)
1330                 dev_warn(dev->ctrl.device,
1331                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1332                          csts, pci_status);
1333         else
1334                 dev_warn(dev->ctrl.device,
1335                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1336                          csts, result);
1337 }
1338
1339 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1340 {
1341         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1342         struct nvme_queue *nvmeq = iod->nvmeq;
1343         struct nvme_dev *dev = nvmeq->dev;
1344         struct request *abort_req;
1345         struct nvme_command cmd = { };
1346         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1347
1348         /* If PCI error recovery process is happening, we cannot reset or
1349          * the recovery mechanism will surely fail.
1350          */
1351         mb();
1352         if (pci_channel_offline(to_pci_dev(dev->dev)))
1353                 return BLK_EH_RESET_TIMER;
1354
1355         /*
1356          * Reset immediately if the controller is failed
1357          */
1358         if (nvme_should_reset(dev, csts)) {
1359                 nvme_warn_reset(dev, csts);
1360                 nvme_dev_disable(dev, false);
1361                 nvme_reset_ctrl(&dev->ctrl);
1362                 return BLK_EH_DONE;
1363         }
1364
1365         /*
1366          * Did we miss an interrupt?
1367          */
1368         if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1369                 nvme_poll(req->mq_hctx, NULL);
1370         else
1371                 nvme_poll_irqdisable(nvmeq);
1372
1373         if (blk_mq_request_completed(req)) {
1374                 dev_warn(dev->ctrl.device,
1375                          "I/O %d QID %d timeout, completion polled\n",
1376                          req->tag, nvmeq->qid);
1377                 return BLK_EH_DONE;
1378         }
1379
1380         /*
1381          * Shutdown immediately if controller times out while starting. The
1382          * reset work will see the pci device disabled when it gets the forced
1383          * cancellation error. All outstanding requests are completed on
1384          * shutdown, so we return BLK_EH_DONE.
1385          */
1386         switch (dev->ctrl.state) {
1387         case NVME_CTRL_CONNECTING:
1388                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1389                 fallthrough;
1390         case NVME_CTRL_DELETING:
1391                 dev_warn_ratelimited(dev->ctrl.device,
1392                          "I/O %d QID %d timeout, disable controller\n",
1393                          req->tag, nvmeq->qid);
1394                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1395                 nvme_dev_disable(dev, true);
1396                 return BLK_EH_DONE;
1397         case NVME_CTRL_RESETTING:
1398                 return BLK_EH_RESET_TIMER;
1399         default:
1400                 break;
1401         }
1402
1403         /*
1404          * Shutdown the controller immediately and schedule a reset if the
1405          * command was already aborted once before and still hasn't been
1406          * returned to the driver, or if this is the admin queue.
1407          */
1408         if (!nvmeq->qid || iod->aborted) {
1409                 dev_warn(dev->ctrl.device,
1410                          "I/O %d QID %d timeout, reset controller\n",
1411                          req->tag, nvmeq->qid);
1412                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1413                 nvme_dev_disable(dev, false);
1414                 nvme_reset_ctrl(&dev->ctrl);
1415
1416                 return BLK_EH_DONE;
1417         }
1418
1419         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1420                 atomic_inc(&dev->ctrl.abort_limit);
1421                 return BLK_EH_RESET_TIMER;
1422         }
1423         iod->aborted = 1;
1424
1425         cmd.abort.opcode = nvme_admin_abort_cmd;
1426         cmd.abort.cid = nvme_cid(req);
1427         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1428
1429         dev_warn(nvmeq->dev->ctrl.device,
1430                 "I/O %d QID %d timeout, aborting\n",
1431                  req->tag, nvmeq->qid);
1432
1433         abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1434                                          BLK_MQ_REQ_NOWAIT);
1435         if (IS_ERR(abort_req)) {
1436                 atomic_inc(&dev->ctrl.abort_limit);
1437                 return BLK_EH_RESET_TIMER;
1438         }
1439         nvme_init_request(abort_req, &cmd);
1440
1441         abort_req->end_io = abort_endio;
1442         abort_req->end_io_data = NULL;
1443         abort_req->rq_flags |= RQF_QUIET;
1444         blk_execute_rq_nowait(abort_req, false);
1445
1446         /*
1447          * The aborted req will be completed on receiving the abort req.
1448          * We enable the timer again. If hit twice, it'll cause a device reset,
1449          * as the device then is in a faulty state.
1450          */
1451         return BLK_EH_RESET_TIMER;
1452 }
1453
1454 static void nvme_free_queue(struct nvme_queue *nvmeq)
1455 {
1456         dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1457                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1458         if (!nvmeq->sq_cmds)
1459                 return;
1460
1461         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1462                 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1463                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1464         } else {
1465                 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1466                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1467         }
1468 }
1469
1470 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1471 {
1472         int i;
1473
1474         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1475                 dev->ctrl.queue_count--;
1476                 nvme_free_queue(&dev->queues[i]);
1477         }
1478 }
1479
1480 /**
1481  * nvme_suspend_queue - put queue into suspended state
1482  * @nvmeq: queue to suspend
1483  */
1484 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1485 {
1486         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1487                 return 1;
1488
1489         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1490         mb();
1491
1492         nvmeq->dev->online_queues--;
1493         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1494                 nvme_stop_admin_queue(&nvmeq->dev->ctrl);
1495         if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1496                 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1497         return 0;
1498 }
1499
1500 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1501 {
1502         int i;
1503
1504         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1505                 nvme_suspend_queue(&dev->queues[i]);
1506 }
1507
1508 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1509 {
1510         struct nvme_queue *nvmeq = &dev->queues[0];
1511
1512         if (shutdown)
1513                 nvme_shutdown_ctrl(&dev->ctrl);
1514         else
1515                 nvme_disable_ctrl(&dev->ctrl);
1516
1517         nvme_poll_irqdisable(nvmeq);
1518 }
1519
1520 /*
1521  * Called only on a device that has been disabled and after all other threads
1522  * that can check this device's completion queues have synced, except
1523  * nvme_poll(). This is the last chance for the driver to see a natural
1524  * completion before nvme_cancel_request() terminates all incomplete requests.
1525  */
1526 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1527 {
1528         int i;
1529
1530         for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1531                 spin_lock(&dev->queues[i].cq_poll_lock);
1532                 nvme_poll_cq(&dev->queues[i], NULL);
1533                 spin_unlock(&dev->queues[i].cq_poll_lock);
1534         }
1535 }
1536
1537 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1538                                 int entry_size)
1539 {
1540         int q_depth = dev->q_depth;
1541         unsigned q_size_aligned = roundup(q_depth * entry_size,
1542                                           NVME_CTRL_PAGE_SIZE);
1543
1544         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1545                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1546
1547                 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1548                 q_depth = div_u64(mem_per_q, entry_size);
1549
1550                 /*
1551                  * Ensure the reduced q_depth is above some threshold where it
1552                  * would be better to map queues in system memory with the
1553                  * original depth
1554                  */
1555                 if (q_depth < 64)
1556                         return -ENOMEM;
1557         }
1558
1559         return q_depth;
1560 }
1561
1562 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1563                                 int qid)
1564 {
1565         struct pci_dev *pdev = to_pci_dev(dev->dev);
1566
1567         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1568                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1569                 if (nvmeq->sq_cmds) {
1570                         nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1571                                                         nvmeq->sq_cmds);
1572                         if (nvmeq->sq_dma_addr) {
1573                                 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1574                                 return 0;
1575                         }
1576
1577                         pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1578                 }
1579         }
1580
1581         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1582                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1583         if (!nvmeq->sq_cmds)
1584                 return -ENOMEM;
1585         return 0;
1586 }
1587
1588 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1589 {
1590         struct nvme_queue *nvmeq = &dev->queues[qid];
1591
1592         if (dev->ctrl.queue_count > qid)
1593                 return 0;
1594
1595         nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1596         nvmeq->q_depth = depth;
1597         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1598                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1599         if (!nvmeq->cqes)
1600                 goto free_nvmeq;
1601
1602         if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1603                 goto free_cqdma;
1604
1605         nvmeq->dev = dev;
1606         spin_lock_init(&nvmeq->sq_lock);
1607         spin_lock_init(&nvmeq->cq_poll_lock);
1608         nvmeq->cq_head = 0;
1609         nvmeq->cq_phase = 1;
1610         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1611         nvmeq->qid = qid;
1612         dev->ctrl.queue_count++;
1613
1614         return 0;
1615
1616  free_cqdma:
1617         dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1618                           nvmeq->cq_dma_addr);
1619  free_nvmeq:
1620         return -ENOMEM;
1621 }
1622
1623 static int queue_request_irq(struct nvme_queue *nvmeq)
1624 {
1625         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1626         int nr = nvmeq->dev->ctrl.instance;
1627
1628         if (use_threaded_interrupts) {
1629                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1630                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1631         } else {
1632                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1633                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1634         }
1635 }
1636
1637 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1638 {
1639         struct nvme_dev *dev = nvmeq->dev;
1640
1641         nvmeq->sq_tail = 0;
1642         nvmeq->last_sq_tail = 0;
1643         nvmeq->cq_head = 0;
1644         nvmeq->cq_phase = 1;
1645         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1646         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1647         nvme_dbbuf_init(dev, nvmeq, qid);
1648         dev->online_queues++;
1649         wmb(); /* ensure the first interrupt sees the initialization */
1650 }
1651
1652 /*
1653  * Try getting shutdown_lock while setting up IO queues.
1654  */
1655 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1656 {
1657         /*
1658          * Give up if the lock is being held by nvme_dev_disable.
1659          */
1660         if (!mutex_trylock(&dev->shutdown_lock))
1661                 return -ENODEV;
1662
1663         /*
1664          * Controller is in wrong state, fail early.
1665          */
1666         if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1667                 mutex_unlock(&dev->shutdown_lock);
1668                 return -ENODEV;
1669         }
1670
1671         return 0;
1672 }
1673
1674 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1675 {
1676         struct nvme_dev *dev = nvmeq->dev;
1677         int result;
1678         u16 vector = 0;
1679
1680         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1681
1682         /*
1683          * A queue's vector matches the queue identifier unless the controller
1684          * has only one vector available.
1685          */
1686         if (!polled)
1687                 vector = dev->num_vecs == 1 ? 0 : qid;
1688         else
1689                 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1690
1691         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1692         if (result)
1693                 return result;
1694
1695         result = adapter_alloc_sq(dev, qid, nvmeq);
1696         if (result < 0)
1697                 return result;
1698         if (result)
1699                 goto release_cq;
1700
1701         nvmeq->cq_vector = vector;
1702
1703         result = nvme_setup_io_queues_trylock(dev);
1704         if (result)
1705                 return result;
1706         nvme_init_queue(nvmeq, qid);
1707         if (!polled) {
1708                 result = queue_request_irq(nvmeq);
1709                 if (result < 0)
1710                         goto release_sq;
1711         }
1712
1713         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1714         mutex_unlock(&dev->shutdown_lock);
1715         return result;
1716
1717 release_sq:
1718         dev->online_queues--;
1719         mutex_unlock(&dev->shutdown_lock);
1720         adapter_delete_sq(dev, qid);
1721 release_cq:
1722         adapter_delete_cq(dev, qid);
1723         return result;
1724 }
1725
1726 static const struct blk_mq_ops nvme_mq_admin_ops = {
1727         .queue_rq       = nvme_queue_rq,
1728         .complete       = nvme_pci_complete_rq,
1729         .init_hctx      = nvme_admin_init_hctx,
1730         .init_request   = nvme_pci_init_request,
1731         .timeout        = nvme_timeout,
1732 };
1733
1734 static const struct blk_mq_ops nvme_mq_ops = {
1735         .queue_rq       = nvme_queue_rq,
1736         .queue_rqs      = nvme_queue_rqs,
1737         .complete       = nvme_pci_complete_rq,
1738         .commit_rqs     = nvme_commit_rqs,
1739         .init_hctx      = nvme_init_hctx,
1740         .init_request   = nvme_pci_init_request,
1741         .map_queues     = nvme_pci_map_queues,
1742         .timeout        = nvme_timeout,
1743         .poll           = nvme_poll,
1744 };
1745
1746 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1747 {
1748         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1749                 /*
1750                  * If the controller was reset during removal, it's possible
1751                  * user requests may be waiting on a stopped queue. Start the
1752                  * queue to flush these to completion.
1753                  */
1754                 nvme_start_admin_queue(&dev->ctrl);
1755                 blk_cleanup_queue(dev->ctrl.admin_q);
1756                 blk_mq_free_tag_set(&dev->admin_tagset);
1757         }
1758 }
1759
1760 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1761 {
1762         if (!dev->ctrl.admin_q) {
1763                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1764                 dev->admin_tagset.nr_hw_queues = 1;
1765
1766                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1767                 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1768                 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1769                 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1770                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1771                 dev->admin_tagset.driver_data = dev;
1772
1773                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1774                         return -ENOMEM;
1775                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1776
1777                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1778                 if (IS_ERR(dev->ctrl.admin_q)) {
1779                         blk_mq_free_tag_set(&dev->admin_tagset);
1780                         dev->ctrl.admin_q = NULL;
1781                         return -ENOMEM;
1782                 }
1783                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1784                         nvme_dev_remove_admin(dev);
1785                         dev->ctrl.admin_q = NULL;
1786                         return -ENODEV;
1787                 }
1788         } else
1789                 nvme_start_admin_queue(&dev->ctrl);
1790
1791         return 0;
1792 }
1793
1794 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1795 {
1796         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1797 }
1798
1799 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1800 {
1801         struct pci_dev *pdev = to_pci_dev(dev->dev);
1802
1803         if (size <= dev->bar_mapped_size)
1804                 return 0;
1805         if (size > pci_resource_len(pdev, 0))
1806                 return -ENOMEM;
1807         if (dev->bar)
1808                 iounmap(dev->bar);
1809         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1810         if (!dev->bar) {
1811                 dev->bar_mapped_size = 0;
1812                 return -ENOMEM;
1813         }
1814         dev->bar_mapped_size = size;
1815         dev->dbs = dev->bar + NVME_REG_DBS;
1816
1817         return 0;
1818 }
1819
1820 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1821 {
1822         int result;
1823         u32 aqa;
1824         struct nvme_queue *nvmeq;
1825
1826         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1827         if (result < 0)
1828                 return result;
1829
1830         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1831                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1832
1833         if (dev->subsystem &&
1834             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1835                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1836
1837         result = nvme_disable_ctrl(&dev->ctrl);
1838         if (result < 0)
1839                 return result;
1840
1841         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1842         if (result)
1843                 return result;
1844
1845         dev->ctrl.numa_node = dev_to_node(dev->dev);
1846
1847         nvmeq = &dev->queues[0];
1848         aqa = nvmeq->q_depth - 1;
1849         aqa |= aqa << 16;
1850
1851         writel(aqa, dev->bar + NVME_REG_AQA);
1852         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1853         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1854
1855         result = nvme_enable_ctrl(&dev->ctrl);
1856         if (result)
1857                 return result;
1858
1859         nvmeq->cq_vector = 0;
1860         nvme_init_queue(nvmeq, 0);
1861         result = queue_request_irq(nvmeq);
1862         if (result) {
1863                 dev->online_queues--;
1864                 return result;
1865         }
1866
1867         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1868         return result;
1869 }
1870
1871 static int nvme_create_io_queues(struct nvme_dev *dev)
1872 {
1873         unsigned i, max, rw_queues;
1874         int ret = 0;
1875
1876         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1877                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1878                         ret = -ENOMEM;
1879                         break;
1880                 }
1881         }
1882
1883         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1884         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1885                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1886                                 dev->io_queues[HCTX_TYPE_READ];
1887         } else {
1888                 rw_queues = max;
1889         }
1890
1891         for (i = dev->online_queues; i <= max; i++) {
1892                 bool polled = i > rw_queues;
1893
1894                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1895                 if (ret)
1896                         break;
1897         }
1898
1899         /*
1900          * Ignore failing Create SQ/CQ commands, we can continue with less
1901          * than the desired amount of queues, and even a controller without
1902          * I/O queues can still be used to issue admin commands.  This might
1903          * be useful to upgrade a buggy firmware for example.
1904          */
1905         return ret >= 0 ? 0 : ret;
1906 }
1907
1908 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1909 {
1910         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1911
1912         return 1ULL << (12 + 4 * szu);
1913 }
1914
1915 static u32 nvme_cmb_size(struct nvme_dev *dev)
1916 {
1917         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1918 }
1919
1920 static void nvme_map_cmb(struct nvme_dev *dev)
1921 {
1922         u64 size, offset;
1923         resource_size_t bar_size;
1924         struct pci_dev *pdev = to_pci_dev(dev->dev);
1925         int bar;
1926
1927         if (dev->cmb_size)
1928                 return;
1929
1930         if (NVME_CAP_CMBS(dev->ctrl.cap))
1931                 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1932
1933         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1934         if (!dev->cmbsz)
1935                 return;
1936         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1937
1938         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1939         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1940         bar = NVME_CMB_BIR(dev->cmbloc);
1941         bar_size = pci_resource_len(pdev, bar);
1942
1943         if (offset > bar_size)
1944                 return;
1945
1946         /*
1947          * Tell the controller about the host side address mapping the CMB,
1948          * and enable CMB decoding for the NVMe 1.4+ scheme:
1949          */
1950         if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1951                 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1952                              (pci_bus_address(pdev, bar) + offset),
1953                              dev->bar + NVME_REG_CMBMSC);
1954         }
1955
1956         /*
1957          * Controllers may support a CMB size larger than their BAR,
1958          * for example, due to being behind a bridge. Reduce the CMB to
1959          * the reported size of the BAR
1960          */
1961         if (size > bar_size - offset)
1962                 size = bar_size - offset;
1963
1964         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1965                 dev_warn(dev->ctrl.device,
1966                          "failed to register the CMB\n");
1967                 return;
1968         }
1969
1970         dev->cmb_size = size;
1971         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1972
1973         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1974                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1975                 pci_p2pmem_publish(pdev, true);
1976 }
1977
1978 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1979 {
1980         u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1981         u64 dma_addr = dev->host_mem_descs_dma;
1982         struct nvme_command c = { };
1983         int ret;
1984
1985         c.features.opcode       = nvme_admin_set_features;
1986         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1987         c.features.dword11      = cpu_to_le32(bits);
1988         c.features.dword12      = cpu_to_le32(host_mem_size);
1989         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1990         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1991         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1992
1993         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1994         if (ret) {
1995                 dev_warn(dev->ctrl.device,
1996                          "failed to set host mem (err %d, flags %#x).\n",
1997                          ret, bits);
1998         } else
1999                 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
2000
2001         return ret;
2002 }
2003
2004 static void nvme_free_host_mem(struct nvme_dev *dev)
2005 {
2006         int i;
2007
2008         for (i = 0; i < dev->nr_host_mem_descs; i++) {
2009                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
2010                 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
2011
2012                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2013                                le64_to_cpu(desc->addr),
2014                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2015         }
2016
2017         kfree(dev->host_mem_desc_bufs);
2018         dev->host_mem_desc_bufs = NULL;
2019         dma_free_coherent(dev->dev,
2020                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
2021                         dev->host_mem_descs, dev->host_mem_descs_dma);
2022         dev->host_mem_descs = NULL;
2023         dev->nr_host_mem_descs = 0;
2024 }
2025
2026 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
2027                 u32 chunk_size)
2028 {
2029         struct nvme_host_mem_buf_desc *descs;
2030         u32 max_entries, len;
2031         dma_addr_t descs_dma;
2032         int i = 0;
2033         void **bufs;
2034         u64 size, tmp;
2035
2036         tmp = (preferred + chunk_size - 1);
2037         do_div(tmp, chunk_size);
2038         max_entries = tmp;
2039
2040         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2041                 max_entries = dev->ctrl.hmmaxd;
2042
2043         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
2044                                    &descs_dma, GFP_KERNEL);
2045         if (!descs)
2046                 goto out;
2047
2048         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2049         if (!bufs)
2050                 goto out_free_descs;
2051
2052         for (size = 0; size < preferred && i < max_entries; size += len) {
2053                 dma_addr_t dma_addr;
2054
2055                 len = min_t(u64, chunk_size, preferred - size);
2056                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2057                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2058                 if (!bufs[i])
2059                         break;
2060
2061                 descs[i].addr = cpu_to_le64(dma_addr);
2062                 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
2063                 i++;
2064         }
2065
2066         if (!size)
2067                 goto out_free_bufs;
2068
2069         dev->nr_host_mem_descs = i;
2070         dev->host_mem_size = size;
2071         dev->host_mem_descs = descs;
2072         dev->host_mem_descs_dma = descs_dma;
2073         dev->host_mem_desc_bufs = bufs;
2074         return 0;
2075
2076 out_free_bufs:
2077         while (--i >= 0) {
2078                 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
2079
2080                 dma_free_attrs(dev->dev, size, bufs[i],
2081                                le64_to_cpu(descs[i].addr),
2082                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2083         }
2084
2085         kfree(bufs);
2086 out_free_descs:
2087         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2088                         descs_dma);
2089 out:
2090         dev->host_mem_descs = NULL;
2091         return -ENOMEM;
2092 }
2093
2094 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2095 {
2096         u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2097         u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2098         u64 chunk_size;
2099
2100         /* start big and work our way down */
2101         for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2102                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2103                         if (!min || dev->host_mem_size >= min)
2104                                 return 0;
2105                         nvme_free_host_mem(dev);
2106                 }
2107         }
2108
2109         return -ENOMEM;
2110 }
2111
2112 static int nvme_setup_host_mem(struct nvme_dev *dev)
2113 {
2114         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2115         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2116         u64 min = (u64)dev->ctrl.hmmin * 4096;
2117         u32 enable_bits = NVME_HOST_MEM_ENABLE;
2118         int ret;
2119
2120         preferred = min(preferred, max);
2121         if (min > max) {
2122                 dev_warn(dev->ctrl.device,
2123                         "min host memory (%lld MiB) above limit (%d MiB).\n",
2124                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
2125                 nvme_free_host_mem(dev);
2126                 return 0;
2127         }
2128
2129         /*
2130          * If we already have a buffer allocated check if we can reuse it.
2131          */
2132         if (dev->host_mem_descs) {
2133                 if (dev->host_mem_size >= min)
2134                         enable_bits |= NVME_HOST_MEM_RETURN;
2135                 else
2136                         nvme_free_host_mem(dev);
2137         }
2138
2139         if (!dev->host_mem_descs) {
2140                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2141                         dev_warn(dev->ctrl.device,
2142                                 "failed to allocate host memory buffer.\n");
2143                         return 0; /* controller must work without HMB */
2144                 }
2145
2146                 dev_info(dev->ctrl.device,
2147                         "allocated %lld MiB host memory buffer.\n",
2148                         dev->host_mem_size >> ilog2(SZ_1M));
2149         }
2150
2151         ret = nvme_set_host_mem(dev, enable_bits);
2152         if (ret)
2153                 nvme_free_host_mem(dev);
2154         return ret;
2155 }
2156
2157 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2158                 char *buf)
2159 {
2160         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2161
2162         return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz  : x%08x\n",
2163                        ndev->cmbloc, ndev->cmbsz);
2164 }
2165 static DEVICE_ATTR_RO(cmb);
2166
2167 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2168                 char *buf)
2169 {
2170         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2171
2172         return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2173 }
2174 static DEVICE_ATTR_RO(cmbloc);
2175
2176 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2177                 char *buf)
2178 {
2179         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2180
2181         return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2182 }
2183 static DEVICE_ATTR_RO(cmbsz);
2184
2185 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2186                         char *buf)
2187 {
2188         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2189
2190         return sysfs_emit(buf, "%d\n", ndev->hmb);
2191 }
2192
2193 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2194                          const char *buf, size_t count)
2195 {
2196         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2197         bool new;
2198         int ret;
2199
2200         if (strtobool(buf, &new) < 0)
2201                 return -EINVAL;
2202
2203         if (new == ndev->hmb)
2204                 return count;
2205
2206         if (new) {
2207                 ret = nvme_setup_host_mem(ndev);
2208         } else {
2209                 ret = nvme_set_host_mem(ndev, 0);
2210                 if (!ret)
2211                         nvme_free_host_mem(ndev);
2212         }
2213
2214         if (ret < 0)
2215                 return ret;
2216
2217         return count;
2218 }
2219 static DEVICE_ATTR_RW(hmb);
2220
2221 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2222                 struct attribute *a, int n)
2223 {
2224         struct nvme_ctrl *ctrl =
2225                 dev_get_drvdata(container_of(kobj, struct device, kobj));
2226         struct nvme_dev *dev = to_nvme_dev(ctrl);
2227
2228         if (a == &dev_attr_cmb.attr ||
2229             a == &dev_attr_cmbloc.attr ||
2230             a == &dev_attr_cmbsz.attr) {
2231                 if (!dev->cmbsz)
2232                         return 0;
2233         }
2234         if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2235                 return 0;
2236
2237         return a->mode;
2238 }
2239
2240 static struct attribute *nvme_pci_attrs[] = {
2241         &dev_attr_cmb.attr,
2242         &dev_attr_cmbloc.attr,
2243         &dev_attr_cmbsz.attr,
2244         &dev_attr_hmb.attr,
2245         NULL,
2246 };
2247
2248 static const struct attribute_group nvme_pci_attr_group = {
2249         .attrs          = nvme_pci_attrs,
2250         .is_visible     = nvme_pci_attrs_are_visible,
2251 };
2252
2253 /*
2254  * nirqs is the number of interrupts available for write and read
2255  * queues. The core already reserved an interrupt for the admin queue.
2256  */
2257 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2258 {
2259         struct nvme_dev *dev = affd->priv;
2260         unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2261
2262         /*
2263          * If there is no interrupt available for queues, ensure that
2264          * the default queue is set to 1. The affinity set size is
2265          * also set to one, but the irq core ignores it for this case.
2266          *
2267          * If only one interrupt is available or 'write_queue' == 0, combine
2268          * write and read queues.
2269          *
2270          * If 'write_queues' > 0, ensure it leaves room for at least one read
2271          * queue.
2272          */
2273         if (!nrirqs) {
2274                 nrirqs = 1;
2275                 nr_read_queues = 0;
2276         } else if (nrirqs == 1 || !nr_write_queues) {
2277                 nr_read_queues = 0;
2278         } else if (nr_write_queues >= nrirqs) {
2279                 nr_read_queues = 1;
2280         } else {
2281                 nr_read_queues = nrirqs - nr_write_queues;
2282         }
2283
2284         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2285         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2286         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2287         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2288         affd->nr_sets = nr_read_queues ? 2 : 1;
2289 }
2290
2291 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2292 {
2293         struct pci_dev *pdev = to_pci_dev(dev->dev);
2294         struct irq_affinity affd = {
2295                 .pre_vectors    = 1,
2296                 .calc_sets      = nvme_calc_irq_sets,
2297                 .priv           = dev,
2298         };
2299         unsigned int irq_queues, poll_queues;
2300
2301         /*
2302          * Poll queues don't need interrupts, but we need at least one I/O queue
2303          * left over for non-polled I/O.
2304          */
2305         poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2306         dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2307
2308         /*
2309          * Initialize for the single interrupt case, will be updated in
2310          * nvme_calc_irq_sets().
2311          */
2312         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2313         dev->io_queues[HCTX_TYPE_READ] = 0;
2314
2315         /*
2316          * We need interrupts for the admin queue and each non-polled I/O queue,
2317          * but some Apple controllers require all queues to use the first
2318          * vector.
2319          */
2320         irq_queues = 1;
2321         if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2322                 irq_queues += (nr_io_queues - poll_queues);
2323         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2324                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2325 }
2326
2327 static void nvme_disable_io_queues(struct nvme_dev *dev)
2328 {
2329         if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2330                 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2331 }
2332
2333 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2334 {
2335         /*
2336          * If tags are shared with admin queue (Apple bug), then
2337          * make sure we only use one IO queue.
2338          */
2339         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2340                 return 1;
2341         return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2342 }
2343
2344 static int nvme_setup_io_queues(struct nvme_dev *dev)
2345 {
2346         struct nvme_queue *adminq = &dev->queues[0];
2347         struct pci_dev *pdev = to_pci_dev(dev->dev);
2348         unsigned int nr_io_queues;
2349         unsigned long size;
2350         int result;
2351
2352         /*
2353          * Sample the module parameters once at reset time so that we have
2354          * stable values to work with.
2355          */
2356         dev->nr_write_queues = write_queues;
2357         dev->nr_poll_queues = poll_queues;
2358
2359         nr_io_queues = dev->nr_allocated_queues - 1;
2360         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2361         if (result < 0)
2362                 return result;
2363
2364         if (nr_io_queues == 0)
2365                 return 0;
2366
2367         /*
2368          * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2369          * from set to unset. If there is a window to it is truely freed,
2370          * pci_free_irq_vectors() jumping into this window will crash.
2371          * And take lock to avoid racing with pci_free_irq_vectors() in
2372          * nvme_dev_disable() path.
2373          */
2374         result = nvme_setup_io_queues_trylock(dev);
2375         if (result)
2376                 return result;
2377         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2378                 pci_free_irq(pdev, 0, adminq);
2379
2380         if (dev->cmb_use_sqes) {
2381                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2382                                 sizeof(struct nvme_command));
2383                 if (result > 0)
2384                         dev->q_depth = result;
2385                 else
2386                         dev->cmb_use_sqes = false;
2387         }
2388
2389         do {
2390                 size = db_bar_size(dev, nr_io_queues);
2391                 result = nvme_remap_bar(dev, size);
2392                 if (!result)
2393                         break;
2394                 if (!--nr_io_queues) {
2395                         result = -ENOMEM;
2396                         goto out_unlock;
2397                 }
2398         } while (1);
2399         adminq->q_db = dev->dbs;
2400
2401  retry:
2402         /* Deregister the admin queue's interrupt */
2403         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2404                 pci_free_irq(pdev, 0, adminq);
2405
2406         /*
2407          * If we enable msix early due to not intx, disable it again before
2408          * setting up the full range we need.
2409          */
2410         pci_free_irq_vectors(pdev);
2411
2412         result = nvme_setup_irqs(dev, nr_io_queues);
2413         if (result <= 0) {
2414                 result = -EIO;
2415                 goto out_unlock;
2416         }
2417
2418         dev->num_vecs = result;
2419         result = max(result - 1, 1);
2420         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2421
2422         /*
2423          * Should investigate if there's a performance win from allocating
2424          * more queues than interrupt vectors; it might allow the submission
2425          * path to scale better, even if the receive path is limited by the
2426          * number of interrupts.
2427          */
2428         result = queue_request_irq(adminq);
2429         if (result)
2430                 goto out_unlock;
2431         set_bit(NVMEQ_ENABLED, &adminq->flags);
2432         mutex_unlock(&dev->shutdown_lock);
2433
2434         result = nvme_create_io_queues(dev);
2435         if (result || dev->online_queues < 2)
2436                 return result;
2437
2438         if (dev->online_queues - 1 < dev->max_qid) {
2439                 nr_io_queues = dev->online_queues - 1;
2440                 nvme_disable_io_queues(dev);
2441                 result = nvme_setup_io_queues_trylock(dev);
2442                 if (result)
2443                         return result;
2444                 nvme_suspend_io_queues(dev);
2445                 goto retry;
2446         }
2447         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2448                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2449                                         dev->io_queues[HCTX_TYPE_READ],
2450                                         dev->io_queues[HCTX_TYPE_POLL]);
2451         return 0;
2452 out_unlock:
2453         mutex_unlock(&dev->shutdown_lock);
2454         return result;
2455 }
2456
2457 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2458 {
2459         struct nvme_queue *nvmeq = req->end_io_data;
2460
2461         blk_mq_free_request(req);
2462         complete(&nvmeq->delete_done);
2463 }
2464
2465 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2466 {
2467         struct nvme_queue *nvmeq = req->end_io_data;
2468
2469         if (error)
2470                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2471
2472         nvme_del_queue_end(req, error);
2473 }
2474
2475 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2476 {
2477         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2478         struct request *req;
2479         struct nvme_command cmd = { };
2480
2481         cmd.delete_queue.opcode = opcode;
2482         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2483
2484         req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2485         if (IS_ERR(req))
2486                 return PTR_ERR(req);
2487         nvme_init_request(req, &cmd);
2488
2489         if (opcode == nvme_admin_delete_cq)
2490                 req->end_io = nvme_del_cq_end;
2491         else
2492                 req->end_io = nvme_del_queue_end;
2493         req->end_io_data = nvmeq;
2494
2495         init_completion(&nvmeq->delete_done);
2496         req->rq_flags |= RQF_QUIET;
2497         blk_execute_rq_nowait(req, false);
2498         return 0;
2499 }
2500
2501 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2502 {
2503         int nr_queues = dev->online_queues - 1, sent = 0;
2504         unsigned long timeout;
2505
2506  retry:
2507         timeout = NVME_ADMIN_TIMEOUT;
2508         while (nr_queues > 0) {
2509                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2510                         break;
2511                 nr_queues--;
2512                 sent++;
2513         }
2514         while (sent) {
2515                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2516
2517                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2518                                 timeout);
2519                 if (timeout == 0)
2520                         return false;
2521
2522                 sent--;
2523                 if (nr_queues)
2524                         goto retry;
2525         }
2526         return true;
2527 }
2528
2529 static void nvme_dev_add(struct nvme_dev *dev)
2530 {
2531         int ret;
2532
2533         if (!dev->ctrl.tagset) {
2534                 dev->tagset.ops = &nvme_mq_ops;
2535                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2536                 dev->tagset.nr_maps = 2; /* default + read */
2537                 if (dev->io_queues[HCTX_TYPE_POLL])
2538                         dev->tagset.nr_maps++;
2539                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2540                 dev->tagset.numa_node = dev->ctrl.numa_node;
2541                 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2542                                                 BLK_MQ_MAX_DEPTH) - 1;
2543                 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2544                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2545                 dev->tagset.driver_data = dev;
2546
2547                 /*
2548                  * Some Apple controllers requires tags to be unique
2549                  * across admin and IO queue, so reserve the first 32
2550                  * tags of the IO queue.
2551                  */
2552                 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2553                         dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2554
2555                 ret = blk_mq_alloc_tag_set(&dev->tagset);
2556                 if (ret) {
2557                         dev_warn(dev->ctrl.device,
2558                                 "IO queues tagset allocation failed %d\n", ret);
2559                         return;
2560                 }
2561                 dev->ctrl.tagset = &dev->tagset;
2562         } else {
2563                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2564
2565                 /* Free previously allocated queues that are no longer usable */
2566                 nvme_free_queues(dev, dev->online_queues);
2567         }
2568
2569         nvme_dbbuf_set(dev);
2570 }
2571
2572 static int nvme_pci_enable(struct nvme_dev *dev)
2573 {
2574         int result = -ENOMEM;
2575         struct pci_dev *pdev = to_pci_dev(dev->dev);
2576         int dma_address_bits = 64;
2577
2578         if (pci_enable_device_mem(pdev))
2579                 return result;
2580
2581         pci_set_master(pdev);
2582
2583         if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2584                 dma_address_bits = 48;
2585         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2586                 goto disable;
2587
2588         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2589                 result = -ENODEV;
2590                 goto disable;
2591         }
2592
2593         /*
2594          * Some devices and/or platforms don't advertise or work with INTx
2595          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2596          * adjust this later.
2597          */
2598         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2599         if (result < 0)
2600                 return result;
2601
2602         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2603
2604         dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2605                                 io_queue_depth);
2606         dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2607         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2608         dev->dbs = dev->bar + 4096;
2609
2610         /*
2611          * Some Apple controllers require a non-standard SQE size.
2612          * Interestingly they also seem to ignore the CC:IOSQES register
2613          * so we don't bother updating it here.
2614          */
2615         if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2616                 dev->io_sqes = 7;
2617         else
2618                 dev->io_sqes = NVME_NVM_IOSQES;
2619
2620         /*
2621          * Temporary fix for the Apple controller found in the MacBook8,1 and
2622          * some MacBook7,1 to avoid controller resets and data loss.
2623          */
2624         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2625                 dev->q_depth = 2;
2626                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2627                         "set queue depth=%u to work around controller resets\n",
2628                         dev->q_depth);
2629         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2630                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2631                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2632                 dev->q_depth = 64;
2633                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2634                         "set queue depth=%u\n", dev->q_depth);
2635         }
2636
2637         /*
2638          * Controllers with the shared tags quirk need the IO queue to be
2639          * big enough so that we get 32 tags for the admin queue
2640          */
2641         if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2642             (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2643                 dev->q_depth = NVME_AQ_DEPTH + 2;
2644                 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2645                          dev->q_depth);
2646         }
2647
2648
2649         nvme_map_cmb(dev);
2650
2651         pci_enable_pcie_error_reporting(pdev);
2652         pci_save_state(pdev);
2653         return 0;
2654
2655  disable:
2656         pci_disable_device(pdev);
2657         return result;
2658 }
2659
2660 static void nvme_dev_unmap(struct nvme_dev *dev)
2661 {
2662         if (dev->bar)
2663                 iounmap(dev->bar);
2664         pci_release_mem_regions(to_pci_dev(dev->dev));
2665 }
2666
2667 static void nvme_pci_disable(struct nvme_dev *dev)
2668 {
2669         struct pci_dev *pdev = to_pci_dev(dev->dev);
2670
2671         pci_free_irq_vectors(pdev);
2672
2673         if (pci_is_enabled(pdev)) {
2674                 pci_disable_pcie_error_reporting(pdev);
2675                 pci_disable_device(pdev);
2676         }
2677 }
2678
2679 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2680 {
2681         bool dead = true, freeze = false;
2682         struct pci_dev *pdev = to_pci_dev(dev->dev);
2683
2684         mutex_lock(&dev->shutdown_lock);
2685         if (pci_device_is_present(pdev) && pci_is_enabled(pdev)) {
2686                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2687
2688                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2689                     dev->ctrl.state == NVME_CTRL_RESETTING) {
2690                         freeze = true;
2691                         nvme_start_freeze(&dev->ctrl);
2692                 }
2693                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2694                         pdev->error_state  != pci_channel_io_normal);
2695         }
2696
2697         /*
2698          * Give the controller a chance to complete all entered requests if
2699          * doing a safe shutdown.
2700          */
2701         if (!dead && shutdown && freeze)
2702                 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2703
2704         nvme_stop_queues(&dev->ctrl);
2705
2706         if (!dead && dev->ctrl.queue_count > 0) {
2707                 nvme_disable_io_queues(dev);
2708                 nvme_disable_admin_queue(dev, shutdown);
2709         }
2710         nvme_suspend_io_queues(dev);
2711         nvme_suspend_queue(&dev->queues[0]);
2712         nvme_pci_disable(dev);
2713         nvme_reap_pending_cqes(dev);
2714
2715         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2716         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2717         blk_mq_tagset_wait_completed_request(&dev->tagset);
2718         blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2719
2720         /*
2721          * The driver will not be starting up queues again if shutting down so
2722          * must flush all entered requests to their failed completion to avoid
2723          * deadlocking blk-mq hot-cpu notifier.
2724          */
2725         if (shutdown) {
2726                 nvme_start_queues(&dev->ctrl);
2727                 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2728                         nvme_start_admin_queue(&dev->ctrl);
2729         }
2730         mutex_unlock(&dev->shutdown_lock);
2731 }
2732
2733 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2734 {
2735         if (!nvme_wait_reset(&dev->ctrl))
2736                 return -EBUSY;
2737         nvme_dev_disable(dev, shutdown);
2738         return 0;
2739 }
2740
2741 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2742 {
2743         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2744                                                 NVME_CTRL_PAGE_SIZE,
2745                                                 NVME_CTRL_PAGE_SIZE, 0);
2746         if (!dev->prp_page_pool)
2747                 return -ENOMEM;
2748
2749         /* Optimisation for I/Os between 4k and 128k */
2750         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2751                                                 256, 256, 0);
2752         if (!dev->prp_small_pool) {
2753                 dma_pool_destroy(dev->prp_page_pool);
2754                 return -ENOMEM;
2755         }
2756         return 0;
2757 }
2758
2759 static void nvme_release_prp_pools(struct nvme_dev *dev)
2760 {
2761         dma_pool_destroy(dev->prp_page_pool);
2762         dma_pool_destroy(dev->prp_small_pool);
2763 }
2764
2765 static void nvme_free_tagset(struct nvme_dev *dev)
2766 {
2767         if (dev->tagset.tags)
2768                 blk_mq_free_tag_set(&dev->tagset);
2769         dev->ctrl.tagset = NULL;
2770 }
2771
2772 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2773 {
2774         struct nvme_dev *dev = to_nvme_dev(ctrl);
2775
2776         nvme_dbbuf_dma_free(dev);
2777         nvme_free_tagset(dev);
2778         if (dev->ctrl.admin_q)
2779                 blk_put_queue(dev->ctrl.admin_q);
2780         free_opal_dev(dev->ctrl.opal_dev);
2781         mempool_destroy(dev->iod_mempool);
2782         put_device(dev->dev);
2783         kfree(dev->queues);
2784         kfree(dev);
2785 }
2786
2787 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2788 {
2789         /*
2790          * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2791          * may be holding this pci_dev's device lock.
2792          */
2793         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2794         nvme_get_ctrl(&dev->ctrl);
2795         nvme_dev_disable(dev, false);
2796         nvme_kill_queues(&dev->ctrl);
2797         if (!queue_work(nvme_wq, &dev->remove_work))
2798                 nvme_put_ctrl(&dev->ctrl);
2799 }
2800
2801 static void nvme_reset_work(struct work_struct *work)
2802 {
2803         struct nvme_dev *dev =
2804                 container_of(work, struct nvme_dev, ctrl.reset_work);
2805         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2806         int result;
2807
2808         if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2809                 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2810                          dev->ctrl.state);
2811                 result = -ENODEV;
2812                 goto out;
2813         }
2814
2815         /*
2816          * If we're called to reset a live controller first shut it down before
2817          * moving on.
2818          */
2819         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2820                 nvme_dev_disable(dev, false);
2821         nvme_sync_queues(&dev->ctrl);
2822
2823         mutex_lock(&dev->shutdown_lock);
2824         result = nvme_pci_enable(dev);
2825         if (result)
2826                 goto out_unlock;
2827
2828         result = nvme_pci_configure_admin_queue(dev);
2829         if (result)
2830                 goto out_unlock;
2831
2832         result = nvme_alloc_admin_tags(dev);
2833         if (result)
2834                 goto out_unlock;
2835
2836         /*
2837          * Limit the max command size to prevent iod->sg allocations going
2838          * over a single page.
2839          */
2840         dev->ctrl.max_hw_sectors = min_t(u32,
2841                 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2842         dev->ctrl.max_segments = NVME_MAX_SEGS;
2843
2844         /*
2845          * Don't limit the IOMMU merged segment size.
2846          */
2847         dma_set_max_seg_size(dev->dev, 0xffffffff);
2848         dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2849
2850         mutex_unlock(&dev->shutdown_lock);
2851
2852         /*
2853          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2854          * initializing procedure here.
2855          */
2856         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2857                 dev_warn(dev->ctrl.device,
2858                         "failed to mark controller CONNECTING\n");
2859                 result = -EBUSY;
2860                 goto out;
2861         }
2862
2863         /*
2864          * We do not support an SGL for metadata (yet), so we are limited to a
2865          * single integrity segment for the separate metadata pointer.
2866          */
2867         dev->ctrl.max_integrity_segments = 1;
2868
2869         result = nvme_init_ctrl_finish(&dev->ctrl);
2870         if (result)
2871                 goto out;
2872
2873         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2874                 if (!dev->ctrl.opal_dev)
2875                         dev->ctrl.opal_dev =
2876                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2877                 else if (was_suspend)
2878                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2879         } else {
2880                 free_opal_dev(dev->ctrl.opal_dev);
2881                 dev->ctrl.opal_dev = NULL;
2882         }
2883
2884         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2885                 result = nvme_dbbuf_dma_alloc(dev);
2886                 if (result)
2887                         dev_warn(dev->dev,
2888                                  "unable to allocate dma for dbbuf\n");
2889         }
2890
2891         if (dev->ctrl.hmpre) {
2892                 result = nvme_setup_host_mem(dev);
2893                 if (result < 0)
2894                         goto out;
2895         }
2896
2897         result = nvme_setup_io_queues(dev);
2898         if (result)
2899                 goto out;
2900
2901         /*
2902          * Keep the controller around but remove all namespaces if we don't have
2903          * any working I/O queue.
2904          */
2905         if (dev->online_queues < 2) {
2906                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2907                 nvme_kill_queues(&dev->ctrl);
2908                 nvme_remove_namespaces(&dev->ctrl);
2909                 nvme_free_tagset(dev);
2910         } else {
2911                 nvme_start_queues(&dev->ctrl);
2912                 nvme_wait_freeze(&dev->ctrl);
2913                 nvme_dev_add(dev);
2914                 nvme_unfreeze(&dev->ctrl);
2915         }
2916
2917         /*
2918          * If only admin queue live, keep it to do further investigation or
2919          * recovery.
2920          */
2921         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2922                 dev_warn(dev->ctrl.device,
2923                         "failed to mark controller live state\n");
2924                 result = -ENODEV;
2925                 goto out;
2926         }
2927
2928         if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2929                         &nvme_pci_attr_group))
2930                 dev->attrs_added = true;
2931
2932         nvme_start_ctrl(&dev->ctrl);
2933         return;
2934
2935  out_unlock:
2936         mutex_unlock(&dev->shutdown_lock);
2937  out:
2938         if (result)
2939                 dev_warn(dev->ctrl.device,
2940                          "Removing after probe failure status: %d\n", result);
2941         nvme_remove_dead_ctrl(dev);
2942 }
2943
2944 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2945 {
2946         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2947         struct pci_dev *pdev = to_pci_dev(dev->dev);
2948
2949         if (pci_get_drvdata(pdev))
2950                 device_release_driver(&pdev->dev);
2951         nvme_put_ctrl(&dev->ctrl);
2952 }
2953
2954 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2955 {
2956         *val = readl(to_nvme_dev(ctrl)->bar + off);
2957         return 0;
2958 }
2959
2960 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2961 {
2962         writel(val, to_nvme_dev(ctrl)->bar + off);
2963         return 0;
2964 }
2965
2966 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2967 {
2968         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2969         return 0;
2970 }
2971
2972 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2973 {
2974         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2975
2976         return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2977 }
2978
2979
2980 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2981 {
2982         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2983         struct nvme_subsystem *subsys = ctrl->subsys;
2984
2985         dev_err(ctrl->device,
2986                 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2987                 pdev->vendor, pdev->device,
2988                 nvme_strlen(subsys->model, sizeof(subsys->model)),
2989                 subsys->model, nvme_strlen(subsys->firmware_rev,
2990                                            sizeof(subsys->firmware_rev)),
2991                 subsys->firmware_rev);
2992 }
2993
2994 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2995         .name                   = "pcie",
2996         .module                 = THIS_MODULE,
2997         .flags                  = NVME_F_METADATA_SUPPORTED |
2998                                   NVME_F_PCI_P2PDMA,
2999         .reg_read32             = nvme_pci_reg_read32,
3000         .reg_write32            = nvme_pci_reg_write32,
3001         .reg_read64             = nvme_pci_reg_read64,
3002         .free_ctrl              = nvme_pci_free_ctrl,
3003         .submit_async_event     = nvme_pci_submit_async_event,
3004         .get_address            = nvme_pci_get_address,
3005         .print_device_info      = nvme_pci_print_device_info,
3006 };
3007
3008 static int nvme_dev_map(struct nvme_dev *dev)
3009 {
3010         struct pci_dev *pdev = to_pci_dev(dev->dev);
3011
3012         if (pci_request_mem_regions(pdev, "nvme"))
3013                 return -ENODEV;
3014
3015         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
3016                 goto release;
3017
3018         return 0;
3019   release:
3020         pci_release_mem_regions(pdev);
3021         return -ENODEV;
3022 }
3023
3024 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
3025 {
3026         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3027                 /*
3028                  * Several Samsung devices seem to drop off the PCIe bus
3029                  * randomly when APST is on and uses the deepest sleep state.
3030                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3031                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3032                  * 950 PRO 256GB", but it seems to be restricted to two Dell
3033                  * laptops.
3034                  */
3035                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3036                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3037                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3038                         return NVME_QUIRK_NO_DEEPEST_PS;
3039         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3040                 /*
3041                  * Samsung SSD 960 EVO drops off the PCIe bus after system
3042                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3043                  * within few minutes after bootup on a Coffee Lake board -
3044                  * ASUS PRIME Z370-A
3045                  */
3046                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
3047                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3048                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
3049                         return NVME_QUIRK_NO_APST;
3050         } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3051                     pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3052                    (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3053                 /*
3054                  * Forcing to use host managed nvme power settings for
3055                  * lowest idle power with quick resume latency on
3056                  * Samsung and Toshiba SSDs based on suspend behavior
3057                  * on Coffee Lake board for LENOVO C640
3058                  */
3059                 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3060                      dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3061                         return NVME_QUIRK_SIMPLE_SUSPEND;
3062         }
3063
3064         return 0;
3065 }
3066
3067 static void nvme_async_probe(void *data, async_cookie_t cookie)
3068 {
3069         struct nvme_dev *dev = data;
3070
3071         flush_work(&dev->ctrl.reset_work);
3072         flush_work(&dev->ctrl.scan_work);
3073         nvme_put_ctrl(&dev->ctrl);
3074 }
3075
3076 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3077 {
3078         int node, result = -ENOMEM;
3079         struct nvme_dev *dev;
3080         unsigned long quirks = id->driver_data;
3081         size_t alloc_size;
3082
3083         node = dev_to_node(&pdev->dev);
3084         if (node == NUMA_NO_NODE)
3085                 set_dev_node(&pdev->dev, first_memory_node);
3086
3087         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3088         if (!dev)
3089                 return -ENOMEM;
3090
3091         dev->nr_write_queues = write_queues;
3092         dev->nr_poll_queues = poll_queues;
3093         dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3094         dev->queues = kcalloc_node(dev->nr_allocated_queues,
3095                         sizeof(struct nvme_queue), GFP_KERNEL, node);
3096         if (!dev->queues)
3097                 goto free;
3098
3099         dev->dev = get_device(&pdev->dev);
3100         pci_set_drvdata(pdev, dev);
3101
3102         result = nvme_dev_map(dev);
3103         if (result)
3104                 goto put_pci;
3105
3106         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
3107         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
3108         mutex_init(&dev->shutdown_lock);
3109
3110         result = nvme_setup_prp_pools(dev);
3111         if (result)
3112                 goto unmap;
3113
3114         quirks |= check_vendor_combination_bug(pdev);
3115
3116         if (!noacpi && acpi_storage_d3(&pdev->dev)) {
3117                 /*
3118                  * Some systems use a bios work around to ask for D3 on
3119                  * platforms that support kernel managed suspend.
3120                  */
3121                 dev_info(&pdev->dev,
3122                          "platform quirk: setting simple suspend\n");
3123                 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3124         }
3125
3126         /*
3127          * Double check that our mempool alloc size will cover the biggest
3128          * command we support.
3129          */
3130         alloc_size = nvme_pci_iod_alloc_size();
3131         WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3132
3133         dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3134                                                 mempool_kfree,
3135                                                 (void *) alloc_size,
3136                                                 GFP_KERNEL, node);
3137         if (!dev->iod_mempool) {
3138                 result = -ENOMEM;
3139                 goto release_pools;
3140         }
3141
3142         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3143                         quirks);
3144         if (result)
3145                 goto release_mempool;
3146
3147         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3148
3149         nvme_reset_ctrl(&dev->ctrl);
3150         async_schedule(nvme_async_probe, dev);
3151
3152         return 0;
3153
3154  release_mempool:
3155         mempool_destroy(dev->iod_mempool);
3156  release_pools:
3157         nvme_release_prp_pools(dev);
3158  unmap:
3159         nvme_dev_unmap(dev);
3160  put_pci:
3161         put_device(dev->dev);
3162  free:
3163         kfree(dev->queues);
3164         kfree(dev);
3165         return result;
3166 }
3167
3168 static void nvme_reset_prepare(struct pci_dev *pdev)
3169 {
3170         struct nvme_dev *dev = pci_get_drvdata(pdev);
3171
3172         /*
3173          * We don't need to check the return value from waiting for the reset
3174          * state as pci_dev device lock is held, making it impossible to race
3175          * with ->remove().
3176          */
3177         nvme_disable_prepare_reset(dev, false);
3178         nvme_sync_queues(&dev->ctrl);
3179 }
3180
3181 static void nvme_reset_done(struct pci_dev *pdev)
3182 {
3183         struct nvme_dev *dev = pci_get_drvdata(pdev);
3184
3185         if (!nvme_try_sched_reset(&dev->ctrl))
3186                 flush_work(&dev->ctrl.reset_work);
3187 }
3188
3189 static void nvme_shutdown(struct pci_dev *pdev)
3190 {
3191         struct nvme_dev *dev = pci_get_drvdata(pdev);
3192
3193         nvme_disable_prepare_reset(dev, true);
3194 }
3195
3196 static void nvme_remove_attrs(struct nvme_dev *dev)
3197 {
3198         if (dev->attrs_added)
3199                 sysfs_remove_group(&dev->ctrl.device->kobj,
3200                                    &nvme_pci_attr_group);
3201 }
3202
3203 /*
3204  * The driver's remove may be called on a device in a partially initialized
3205  * state. This function must not have any dependencies on the device state in
3206  * order to proceed.
3207  */
3208 static void nvme_remove(struct pci_dev *pdev)
3209 {
3210         struct nvme_dev *dev = pci_get_drvdata(pdev);
3211
3212         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3213         pci_set_drvdata(pdev, NULL);
3214
3215         if (!pci_device_is_present(pdev)) {
3216                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3217                 nvme_dev_disable(dev, true);
3218         }
3219
3220         flush_work(&dev->ctrl.reset_work);
3221         nvme_stop_ctrl(&dev->ctrl);
3222         nvme_remove_namespaces(&dev->ctrl);
3223         nvme_dev_disable(dev, true);
3224         nvme_remove_attrs(dev);
3225         nvme_free_host_mem(dev);
3226         nvme_dev_remove_admin(dev);
3227         nvme_free_queues(dev, 0);
3228         nvme_release_prp_pools(dev);
3229         nvme_dev_unmap(dev);
3230         nvme_uninit_ctrl(&dev->ctrl);
3231 }
3232
3233 #ifdef CONFIG_PM_SLEEP
3234 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3235 {
3236         return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3237 }
3238
3239 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3240 {
3241         return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3242 }
3243
3244 static int nvme_resume(struct device *dev)
3245 {
3246         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3247         struct nvme_ctrl *ctrl = &ndev->ctrl;
3248
3249         if (ndev->last_ps == U32_MAX ||
3250             nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3251                 goto reset;
3252         if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3253                 goto reset;
3254
3255         return 0;
3256 reset:
3257         return nvme_try_sched_reset(ctrl);
3258 }
3259
3260 static int nvme_suspend(struct device *dev)
3261 {
3262         struct pci_dev *pdev = to_pci_dev(dev);
3263         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3264         struct nvme_ctrl *ctrl = &ndev->ctrl;
3265         int ret = -EBUSY;
3266
3267         ndev->last_ps = U32_MAX;
3268
3269         /*
3270          * The platform does not remove power for a kernel managed suspend so
3271          * use host managed nvme power settings for lowest idle power if
3272          * possible. This should have quicker resume latency than a full device
3273          * shutdown.  But if the firmware is involved after the suspend or the
3274          * device does not support any non-default power states, shut down the
3275          * device fully.
3276          *
3277          * If ASPM is not enabled for the device, shut down the device and allow
3278          * the PCI bus layer to put it into D3 in order to take the PCIe link
3279          * down, so as to allow the platform to achieve its minimum low-power
3280          * state (which may not be possible if the link is up).
3281          */
3282         if (pm_suspend_via_firmware() || !ctrl->npss ||
3283             !pcie_aspm_enabled(pdev) ||
3284             (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3285                 return nvme_disable_prepare_reset(ndev, true);
3286
3287         nvme_start_freeze(ctrl);
3288         nvme_wait_freeze(ctrl);
3289         nvme_sync_queues(ctrl);
3290
3291         if (ctrl->state != NVME_CTRL_LIVE)
3292                 goto unfreeze;
3293
3294         /*
3295          * Host memory access may not be successful in a system suspend state,
3296          * but the specification allows the controller to access memory in a
3297          * non-operational power state.
3298          */
3299         if (ndev->hmb) {
3300                 ret = nvme_set_host_mem(ndev, 0);
3301                 if (ret < 0)
3302                         goto unfreeze;
3303         }
3304
3305         ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3306         if (ret < 0)
3307                 goto unfreeze;
3308
3309         /*
3310          * A saved state prevents pci pm from generically controlling the
3311          * device's power. If we're using protocol specific settings, we don't
3312          * want pci interfering.
3313          */
3314         pci_save_state(pdev);
3315
3316         ret = nvme_set_power_state(ctrl, ctrl->npss);
3317         if (ret < 0)
3318                 goto unfreeze;
3319
3320         if (ret) {
3321                 /* discard the saved state */
3322                 pci_load_saved_state(pdev, NULL);
3323
3324                 /*
3325                  * Clearing npss forces a controller reset on resume. The
3326                  * correct value will be rediscovered then.
3327                  */
3328                 ret = nvme_disable_prepare_reset(ndev, true);
3329                 ctrl->npss = 0;
3330         }
3331 unfreeze:
3332         nvme_unfreeze(ctrl);
3333         return ret;
3334 }
3335
3336 static int nvme_simple_suspend(struct device *dev)
3337 {
3338         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3339
3340         return nvme_disable_prepare_reset(ndev, true);
3341 }
3342
3343 static int nvme_simple_resume(struct device *dev)
3344 {
3345         struct pci_dev *pdev = to_pci_dev(dev);
3346         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3347
3348         return nvme_try_sched_reset(&ndev->ctrl);
3349 }
3350
3351 static const struct dev_pm_ops nvme_dev_pm_ops = {
3352         .suspend        = nvme_suspend,
3353         .resume         = nvme_resume,
3354         .freeze         = nvme_simple_suspend,
3355         .thaw           = nvme_simple_resume,
3356         .poweroff       = nvme_simple_suspend,
3357         .restore        = nvme_simple_resume,
3358 };
3359 #endif /* CONFIG_PM_SLEEP */
3360
3361 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3362                                                 pci_channel_state_t state)
3363 {
3364         struct nvme_dev *dev = pci_get_drvdata(pdev);
3365
3366         /*
3367          * A frozen channel requires a reset. When detected, this method will
3368          * shutdown the controller to quiesce. The controller will be restarted
3369          * after the slot reset through driver's slot_reset callback.
3370          */
3371         switch (state) {
3372         case pci_channel_io_normal:
3373                 return PCI_ERS_RESULT_CAN_RECOVER;
3374         case pci_channel_io_frozen:
3375                 dev_warn(dev->ctrl.device,
3376                         "frozen state error detected, reset controller\n");
3377                 nvme_dev_disable(dev, false);
3378                 return PCI_ERS_RESULT_NEED_RESET;
3379         case pci_channel_io_perm_failure:
3380                 dev_warn(dev->ctrl.device,
3381                         "failure state error detected, request disconnect\n");
3382                 return PCI_ERS_RESULT_DISCONNECT;
3383         }
3384         return PCI_ERS_RESULT_NEED_RESET;
3385 }
3386
3387 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3388 {
3389         struct nvme_dev *dev = pci_get_drvdata(pdev);
3390
3391         dev_info(dev->ctrl.device, "restart after slot reset\n");
3392         pci_restore_state(pdev);
3393         nvme_reset_ctrl(&dev->ctrl);
3394         return PCI_ERS_RESULT_RECOVERED;
3395 }
3396
3397 static void nvme_error_resume(struct pci_dev *pdev)
3398 {
3399         struct nvme_dev *dev = pci_get_drvdata(pdev);
3400
3401         flush_work(&dev->ctrl.reset_work);
3402 }
3403
3404 static const struct pci_error_handlers nvme_err_handler = {
3405         .error_detected = nvme_error_detected,
3406         .slot_reset     = nvme_slot_reset,
3407         .resume         = nvme_error_resume,
3408         .reset_prepare  = nvme_reset_prepare,
3409         .reset_done     = nvme_reset_done,
3410 };
3411
3412 static const struct pci_device_id nvme_id_table[] = {
3413         { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3414                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3415                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3416         { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3417                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3418                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3419         { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3420                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3421                                 NVME_QUIRK_DEALLOCATE_ZEROES |
3422                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3423         { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3424                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3425                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3426         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3427                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3428                                 NVME_QUIRK_MEDIUM_PRIO_SQ |
3429                                 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3430                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3431         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3432                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3433         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3434                 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3435                                 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3436                                 NVME_QUIRK_BOGUS_NID, },
3437         { PCI_VDEVICE(REDHAT, 0x0010),  /* Qemu emulated controller */
3438                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3439         { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3440                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3441         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3442                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3443                                 NVME_QUIRK_NO_NS_DESC_LIST, },
3444         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3445                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3446         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3447                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3448         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3449                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3450         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3451                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3452         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3453                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3454                                 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3455                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3456         { PCI_DEVICE(0x1987, 0x5016),   /* Phison E16 */
3457                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3458         { PCI_DEVICE(0x1b4b, 0x1092),   /* Lexar 256 GB SSD */
3459                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3460                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3461         { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3462                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3463         { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3464                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3465                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3466         { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3467                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3468         { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3469                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3470         { PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
3471                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3472         { PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3473                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3474         { PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3475                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3476         { PCI_DEVICE(0x1e4B, 0x1001),   /* MAXIO MAP1001 */
3477                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3478         { PCI_DEVICE(0x1e4B, 0x1002),   /* MAXIO MAP1002 */
3479                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3480         { PCI_DEVICE(0x1e4B, 0x1202),   /* MAXIO MAP1202 */
3481                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3482         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3483                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3484         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3485                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3486         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3487                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3488         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3489                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3490         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3491                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3492         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3493                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3494         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3495                 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3496         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3497         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3498                 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3499                                 NVME_QUIRK_128_BYTES_SQES |
3500                                 NVME_QUIRK_SHARED_TAGS |
3501                                 NVME_QUIRK_SKIP_CID_GEN },
3502         { PCI_DEVICE(0x144d, 0xa808),   /* Samsung X5 */
3503                 .driver_data =  NVME_QUIRK_DELAY_BEFORE_CHK_RDY|
3504                                 NVME_QUIRK_NO_DEEPEST_PS |
3505                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3506         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3507         { 0, }
3508 };
3509 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3510
3511 static struct pci_driver nvme_driver = {
3512         .name           = "nvme",
3513         .id_table       = nvme_id_table,
3514         .probe          = nvme_probe,
3515         .remove         = nvme_remove,
3516         .shutdown       = nvme_shutdown,
3517 #ifdef CONFIG_PM_SLEEP
3518         .driver         = {
3519                 .pm     = &nvme_dev_pm_ops,
3520         },
3521 #endif
3522         .sriov_configure = pci_sriov_configure_simple,
3523         .err_handler    = &nvme_err_handler,
3524 };
3525
3526 static int __init nvme_init(void)
3527 {
3528         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3529         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3530         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3531         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3532
3533         return pci_register_driver(&nvme_driver);
3534 }
3535
3536 static void __exit nvme_exit(void)
3537 {
3538         pci_unregister_driver(&nvme_driver);
3539         flush_workqueue(nvme_wq);
3540 }
3541
3542 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3543 MODULE_LICENSE("GPL");
3544 MODULE_VERSION("1.0");
3545 module_init(nvme_init);
3546 module_exit(nvme_exit);