1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
7 #include <linux/acpi.h>
9 #include <linux/async.h>
10 #include <linux/blkdev.h>
11 #include <linux/blk-mq.h>
12 #include <linux/blk-mq-pci.h>
13 #include <linux/blk-integrity.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
18 #include <linux/kstrtox.h>
19 #include <linux/memremap.h>
21 #include <linux/module.h>
22 #include <linux/mutex.h>
23 #include <linux/once.h>
24 #include <linux/pci.h>
25 #include <linux/suspend.h>
26 #include <linux/t10-pi.h>
27 #include <linux/types.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
29 #include <linux/io-64-nonatomic-hi-lo.h>
30 #include <linux/sed-opal.h>
31 #include <linux/pci-p2pdma.h>
36 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
37 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
39 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
42 * These can be higher, but we need to ensure that any command doesn't
43 * require an sg allocation that needs more than a page of data.
45 #define NVME_MAX_KB_SZ 4096
46 #define NVME_MAX_SEGS 127
48 static int use_threaded_interrupts;
49 module_param(use_threaded_interrupts, int, 0444);
51 static bool use_cmb_sqes = true;
52 module_param(use_cmb_sqes, bool, 0444);
53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
55 static unsigned int max_host_mem_size_mb = 128;
56 module_param(max_host_mem_size_mb, uint, 0444);
57 MODULE_PARM_DESC(max_host_mem_size_mb,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
60 static unsigned int sgl_threshold = SZ_32K;
61 module_param(sgl_threshold, uint, 0644);
62 MODULE_PARM_DESC(sgl_threshold,
63 "Use SGLs when average request segment size is larger or equal to "
64 "this size. Use 0 to disable SGLs.");
66 #define NVME_PCI_MIN_QUEUE_SIZE 2
67 #define NVME_PCI_MAX_QUEUE_SIZE 4095
68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
71 .get = param_get_uint,
74 static unsigned int io_queue_depth = 1024;
75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
78 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
83 ret = kstrtouint(val, 10, &n);
84 if (ret != 0 || n > num_possible_cpus())
86 return param_set_uint(val, kp);
89 static const struct kernel_param_ops io_queue_count_ops = {
90 .set = io_queue_count_set,
91 .get = param_get_uint,
94 static unsigned int write_queues;
95 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
96 MODULE_PARM_DESC(write_queues,
97 "Number of queues to use for writes. If not set, reads and writes "
98 "will share a queue set.");
100 static unsigned int poll_queues;
101 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
102 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
105 module_param(noacpi, bool, 0444);
106 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
111 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
112 static void nvme_delete_io_queues(struct nvme_dev *dev);
115 * Represents an NVM Express device. Each nvme_dev is a PCI function.
118 struct nvme_queue *queues;
119 struct blk_mq_tag_set tagset;
120 struct blk_mq_tag_set admin_tagset;
123 struct dma_pool *prp_page_pool;
124 struct dma_pool *prp_small_pool;
125 unsigned online_queues;
127 unsigned io_queues[HCTX_MAX_TYPES];
128 unsigned int num_vecs;
133 unsigned long bar_mapped_size;
134 struct mutex shutdown_lock;
140 struct nvme_ctrl ctrl;
144 mempool_t *iod_mempool;
146 /* shadow doorbell buffer support: */
148 dma_addr_t dbbuf_dbs_dma_addr;
150 dma_addr_t dbbuf_eis_dma_addr;
152 /* host memory buffer support: */
154 u32 nr_host_mem_descs;
155 dma_addr_t host_mem_descs_dma;
156 struct nvme_host_mem_buf_desc *host_mem_descs;
157 void **host_mem_desc_bufs;
158 unsigned int nr_allocated_queues;
159 unsigned int nr_write_queues;
160 unsigned int nr_poll_queues;
163 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
165 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
166 NVME_PCI_MAX_QUEUE_SIZE);
169 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171 return qid * 2 * stride;
174 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176 return (qid * 2 + 1) * stride;
179 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181 return container_of(ctrl, struct nvme_dev, ctrl);
185 * An NVM Express queue. Each device has at least two (one for admin
186 * commands and one for I/O commands).
189 struct nvme_dev *dev;
192 /* only used for poll queues: */
193 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
194 struct nvme_completion *cqes;
195 dma_addr_t sq_dma_addr;
196 dma_addr_t cq_dma_addr;
207 #define NVMEQ_ENABLED 0
208 #define NVMEQ_SQ_CMB 1
209 #define NVMEQ_DELETE_ERROR 2
210 #define NVMEQ_POLLED 3
215 struct completion delete_done;
219 * The nvme_iod describes the data in an I/O.
221 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
222 * to the actual struct scatterlist.
225 struct nvme_request req;
226 struct nvme_command cmd;
229 s8 nr_allocations; /* PRP list pool allocations. 0 means small
231 unsigned int dma_len; /* length of single DMA segment mapping */
232 dma_addr_t first_dma;
237 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
239 return dev->nr_allocated_queues * 8 * dev->db_stride;
242 static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
244 unsigned int mem_size = nvme_dbbuf_size(dev);
246 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
249 if (dev->dbbuf_dbs) {
251 * Clear the dbbuf memory so the driver doesn't observe stale
252 * values from the previous instantiation.
254 memset(dev->dbbuf_dbs, 0, mem_size);
255 memset(dev->dbbuf_eis, 0, mem_size);
259 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
260 &dev->dbbuf_dbs_dma_addr,
264 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
265 &dev->dbbuf_eis_dma_addr,
268 goto fail_free_dbbuf_dbs;
272 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
273 dev->dbbuf_dbs_dma_addr);
274 dev->dbbuf_dbs = NULL;
276 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
279 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
281 unsigned int mem_size = nvme_dbbuf_size(dev);
283 if (dev->dbbuf_dbs) {
284 dma_free_coherent(dev->dev, mem_size,
285 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
286 dev->dbbuf_dbs = NULL;
288 if (dev->dbbuf_eis) {
289 dma_free_coherent(dev->dev, mem_size,
290 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
291 dev->dbbuf_eis = NULL;
295 static void nvme_dbbuf_init(struct nvme_dev *dev,
296 struct nvme_queue *nvmeq, int qid)
298 if (!dev->dbbuf_dbs || !qid)
301 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
302 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
303 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
304 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
307 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
312 nvmeq->dbbuf_sq_db = NULL;
313 nvmeq->dbbuf_cq_db = NULL;
314 nvmeq->dbbuf_sq_ei = NULL;
315 nvmeq->dbbuf_cq_ei = NULL;
318 static void nvme_dbbuf_set(struct nvme_dev *dev)
320 struct nvme_command c = { };
326 c.dbbuf.opcode = nvme_admin_dbbuf;
327 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
328 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
330 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
331 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
332 /* Free memory and continue on */
333 nvme_dbbuf_dma_free(dev);
335 for (i = 1; i <= dev->online_queues; i++)
336 nvme_dbbuf_free(&dev->queues[i]);
340 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
342 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
345 /* Update dbbuf and return true if an MMIO is required */
346 static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
347 volatile __le32 *dbbuf_ei)
350 u16 old_value, event_idx;
353 * Ensure that the queue is written before updating
354 * the doorbell in memory
358 old_value = le32_to_cpu(*dbbuf_db);
359 *dbbuf_db = cpu_to_le32(value);
362 * Ensure that the doorbell is updated before reading the event
363 * index from memory. The controller needs to provide similar
364 * ordering to ensure the envent index is updated before reading
369 event_idx = le32_to_cpu(*dbbuf_ei);
370 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
378 * Will slightly overestimate the number of pages needed. This is OK
379 * as it only leads to a small amount of wasted memory for the lifetime of
382 static int nvme_pci_npages_prp(void)
384 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
385 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
386 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
390 * Calculates the number of pages needed for the SGL segments. For example a 4k
391 * page can accommodate 256 SGL descriptors.
393 static int nvme_pci_npages_sgl(void)
395 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
399 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
400 unsigned int hctx_idx)
402 struct nvme_dev *dev = to_nvme_dev(data);
403 struct nvme_queue *nvmeq = &dev->queues[0];
405 WARN_ON(hctx_idx != 0);
406 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
408 hctx->driver_data = nvmeq;
412 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
413 unsigned int hctx_idx)
415 struct nvme_dev *dev = to_nvme_dev(data);
416 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
418 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
419 hctx->driver_data = nvmeq;
423 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
424 struct request *req, unsigned int hctx_idx,
425 unsigned int numa_node)
427 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
428 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
430 nvme_req(req)->ctrl = &dev->ctrl;
431 nvme_req(req)->cmd = &iod->cmd;
435 static int queue_irq_offset(struct nvme_dev *dev)
437 /* if we have more than 1 vec, admin queue offsets us by 1 */
438 if (dev->num_vecs > 1)
444 static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
446 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
449 offset = queue_irq_offset(dev);
450 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
451 struct blk_mq_queue_map *map = &set->map[i];
453 map->nr_queues = dev->io_queues[i];
454 if (!map->nr_queues) {
455 BUG_ON(i == HCTX_TYPE_DEFAULT);
460 * The poll queue(s) doesn't have an IRQ (and hence IRQ
461 * affinity), so use the regular blk-mq cpu mapping
463 map->queue_offset = qoff;
464 if (i != HCTX_TYPE_POLL && offset)
465 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
467 blk_mq_map_queues(map);
468 qoff += map->nr_queues;
469 offset += map->nr_queues;
474 * Write sq tail if we are asked to, or if the next command would wrap.
476 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
479 u16 next_tail = nvmeq->sq_tail + 1;
481 if (next_tail == nvmeq->q_depth)
483 if (next_tail != nvmeq->last_sq_tail)
487 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
488 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
489 writel(nvmeq->sq_tail, nvmeq->q_db);
490 nvmeq->last_sq_tail = nvmeq->sq_tail;
493 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
494 struct nvme_command *cmd)
496 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
497 absolute_pointer(cmd), sizeof(*cmd));
498 if (++nvmeq->sq_tail == nvmeq->q_depth)
502 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
504 struct nvme_queue *nvmeq = hctx->driver_data;
506 spin_lock(&nvmeq->sq_lock);
507 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
508 nvme_write_sq_db(nvmeq, true);
509 spin_unlock(&nvmeq->sq_lock);
512 static void **nvme_pci_iod_list(struct request *req)
514 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
515 return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req));
518 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
520 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
521 int nseg = blk_rq_nr_phys_segments(req);
522 unsigned int avg_seg_size;
524 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
526 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
530 if (!sgl_threshold || avg_seg_size < sgl_threshold)
535 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
537 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
538 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
539 dma_addr_t dma_addr = iod->first_dma;
542 for (i = 0; i < iod->nr_allocations; i++) {
543 __le64 *prp_list = nvme_pci_iod_list(req)[i];
544 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
546 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
547 dma_addr = next_dma_addr;
551 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
553 const int last_sg = SGES_PER_PAGE - 1;
554 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
555 dma_addr_t dma_addr = iod->first_dma;
558 for (i = 0; i < iod->nr_allocations; i++) {
559 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
560 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
562 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
563 dma_addr = next_dma_addr;
567 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
569 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
572 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
577 WARN_ON_ONCE(!iod->sgt.nents);
579 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
581 if (iod->nr_allocations == 0)
582 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
584 else if (iod->use_sgl)
585 nvme_free_sgls(dev, req);
587 nvme_free_prps(dev, req);
588 mempool_free(iod->sgt.sgl, dev->iod_mempool);
591 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
594 struct scatterlist *sg;
596 for_each_sg(sgl, sg, nents, i) {
597 dma_addr_t phys = sg_phys(sg);
598 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
599 "dma_address:%pad dma_length:%d\n",
600 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
605 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
606 struct request *req, struct nvme_rw_command *cmnd)
608 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
609 struct dma_pool *pool;
610 int length = blk_rq_payload_bytes(req);
611 struct scatterlist *sg = iod->sgt.sgl;
612 int dma_len = sg_dma_len(sg);
613 u64 dma_addr = sg_dma_address(sg);
614 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
616 void **list = nvme_pci_iod_list(req);
620 length -= (NVME_CTRL_PAGE_SIZE - offset);
626 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
628 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
631 dma_addr = sg_dma_address(sg);
632 dma_len = sg_dma_len(sg);
635 if (length <= NVME_CTRL_PAGE_SIZE) {
636 iod->first_dma = dma_addr;
640 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
641 if (nprps <= (256 / 8)) {
642 pool = dev->prp_small_pool;
643 iod->nr_allocations = 0;
645 pool = dev->prp_page_pool;
646 iod->nr_allocations = 1;
649 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
651 iod->nr_allocations = -1;
652 return BLK_STS_RESOURCE;
655 iod->first_dma = prp_dma;
658 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
659 __le64 *old_prp_list = prp_list;
660 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
663 list[iod->nr_allocations++] = prp_list;
664 prp_list[0] = old_prp_list[i - 1];
665 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
668 prp_list[i++] = cpu_to_le64(dma_addr);
669 dma_len -= NVME_CTRL_PAGE_SIZE;
670 dma_addr += NVME_CTRL_PAGE_SIZE;
671 length -= NVME_CTRL_PAGE_SIZE;
676 if (unlikely(dma_len < 0))
679 dma_addr = sg_dma_address(sg);
680 dma_len = sg_dma_len(sg);
683 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
684 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
687 nvme_free_prps(dev, req);
688 return BLK_STS_RESOURCE;
690 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
691 "Invalid SGL for payload:%d nents:%d\n",
692 blk_rq_payload_bytes(req), iod->sgt.nents);
693 return BLK_STS_IOERR;
696 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
697 struct scatterlist *sg)
699 sge->addr = cpu_to_le64(sg_dma_address(sg));
700 sge->length = cpu_to_le32(sg_dma_len(sg));
701 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
704 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
705 dma_addr_t dma_addr, int entries)
707 sge->addr = cpu_to_le64(dma_addr);
708 if (entries < SGES_PER_PAGE) {
709 sge->length = cpu_to_le32(entries * sizeof(*sge));
710 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
712 sge->length = cpu_to_le32(PAGE_SIZE);
713 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
717 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
718 struct request *req, struct nvme_rw_command *cmd)
720 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
721 struct dma_pool *pool;
722 struct nvme_sgl_desc *sg_list;
723 struct scatterlist *sg = iod->sgt.sgl;
724 unsigned int entries = iod->sgt.nents;
728 /* setting the transfer type as SGL */
729 cmd->flags = NVME_CMD_SGL_METABUF;
732 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
736 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
737 pool = dev->prp_small_pool;
738 iod->nr_allocations = 0;
740 pool = dev->prp_page_pool;
741 iod->nr_allocations = 1;
744 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
746 iod->nr_allocations = -1;
747 return BLK_STS_RESOURCE;
750 nvme_pci_iod_list(req)[0] = sg_list;
751 iod->first_dma = sgl_dma;
753 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
756 if (i == SGES_PER_PAGE) {
757 struct nvme_sgl_desc *old_sg_desc = sg_list;
758 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
760 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
765 nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list;
766 sg_list[i++] = *link;
767 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
770 nvme_pci_sgl_set_data(&sg_list[i++], sg);
772 } while (--entries > 0);
776 nvme_free_sgls(dev, req);
777 return BLK_STS_RESOURCE;
780 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
781 struct request *req, struct nvme_rw_command *cmnd,
784 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
785 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
786 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
788 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
789 if (dma_mapping_error(dev->dev, iod->first_dma))
790 return BLK_STS_RESOURCE;
791 iod->dma_len = bv->bv_len;
793 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
794 if (bv->bv_len > first_prp_len)
795 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
801 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
802 struct request *req, struct nvme_rw_command *cmnd,
805 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
807 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
808 if (dma_mapping_error(dev->dev, iod->first_dma))
809 return BLK_STS_RESOURCE;
810 iod->dma_len = bv->bv_len;
812 cmnd->flags = NVME_CMD_SGL_METABUF;
813 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
814 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
815 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
819 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
820 struct nvme_command *cmnd)
822 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
823 blk_status_t ret = BLK_STS_RESOURCE;
826 if (blk_rq_nr_phys_segments(req) == 1) {
827 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
828 struct bio_vec bv = req_bvec(req);
830 if (!is_pci_p2pdma_page(bv.bv_page)) {
831 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
832 return nvme_setup_prp_simple(dev, req,
835 if (nvmeq->qid && sgl_threshold &&
836 nvme_ctrl_sgl_supported(&dev->ctrl))
837 return nvme_setup_sgl_simple(dev, req,
843 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
845 return BLK_STS_RESOURCE;
846 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
847 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
848 if (!iod->sgt.orig_nents)
851 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
854 if (rc == -EREMOTEIO)
855 ret = BLK_STS_TARGET;
859 iod->use_sgl = nvme_pci_use_sgls(dev, req);
861 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
863 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
864 if (ret != BLK_STS_OK)
869 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
871 mempool_free(iod->sgt.sgl, dev->iod_mempool);
875 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
876 struct nvme_command *cmnd)
878 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
880 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
882 if (dma_mapping_error(dev->dev, iod->meta_dma))
883 return BLK_STS_IOERR;
884 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
888 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
890 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
893 iod->aborted = false;
894 iod->nr_allocations = -1;
897 ret = nvme_setup_cmd(req->q->queuedata, req);
901 if (blk_rq_nr_phys_segments(req)) {
902 ret = nvme_map_data(dev, req, &iod->cmd);
907 if (blk_integrity_rq(req)) {
908 ret = nvme_map_metadata(dev, req, &iod->cmd);
913 nvme_start_request(req);
916 nvme_unmap_data(dev, req);
918 nvme_cleanup_cmd(req);
923 * NOTE: ns is NULL when called on the admin queue.
925 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
926 const struct blk_mq_queue_data *bd)
928 struct nvme_queue *nvmeq = hctx->driver_data;
929 struct nvme_dev *dev = nvmeq->dev;
930 struct request *req = bd->rq;
931 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
935 * We should not need to do this, but we're still using this to
936 * ensure we can drain requests on a dying queue.
938 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
939 return BLK_STS_IOERR;
941 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
942 return nvme_fail_nonready_command(&dev->ctrl, req);
944 ret = nvme_prep_rq(dev, req);
947 spin_lock(&nvmeq->sq_lock);
948 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
949 nvme_write_sq_db(nvmeq, bd->last);
950 spin_unlock(&nvmeq->sq_lock);
954 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
956 spin_lock(&nvmeq->sq_lock);
957 while (!rq_list_empty(*rqlist)) {
958 struct request *req = rq_list_pop(rqlist);
959 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
961 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
963 nvme_write_sq_db(nvmeq, true);
964 spin_unlock(&nvmeq->sq_lock);
967 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
970 * We should not need to do this, but we're still using this to
971 * ensure we can drain requests on a dying queue.
973 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
975 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
978 req->mq_hctx->tags->rqs[req->tag] = req;
979 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
982 static void nvme_queue_rqs(struct request **rqlist)
984 struct request *req, *next, *prev = NULL;
985 struct request *requeue_list = NULL;
987 rq_list_for_each_safe(rqlist, req, next) {
988 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
990 if (!nvme_prep_rq_batch(nvmeq, req)) {
991 /* detach 'req' and add to remainder list */
992 rq_list_move(rqlist, &requeue_list, req, prev);
999 if (!next || req->mq_hctx != next->mq_hctx) {
1000 /* detach rest of list, and submit */
1001 req->rq_next = NULL;
1002 nvme_submit_cmds(nvmeq, rqlist);
1009 *rqlist = requeue_list;
1012 static __always_inline void nvme_pci_unmap_rq(struct request *req)
1014 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1015 struct nvme_dev *dev = nvmeq->dev;
1017 if (blk_integrity_rq(req)) {
1018 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1020 dma_unmap_page(dev->dev, iod->meta_dma,
1021 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
1024 if (blk_rq_nr_phys_segments(req))
1025 nvme_unmap_data(dev, req);
1028 static void nvme_pci_complete_rq(struct request *req)
1030 nvme_pci_unmap_rq(req);
1031 nvme_complete_rq(req);
1034 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1036 nvme_complete_batch(iob, nvme_pci_unmap_rq);
1039 /* We read the CQE phase first to check if the rest of the entry is valid */
1040 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
1042 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1044 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
1047 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
1049 u16 head = nvmeq->cq_head;
1051 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1052 nvmeq->dbbuf_cq_ei))
1053 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1056 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1059 return nvmeq->dev->admin_tagset.tags[0];
1060 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1063 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1064 struct io_comp_batch *iob, u16 idx)
1066 struct nvme_completion *cqe = &nvmeq->cqes[idx];
1067 __u16 command_id = READ_ONCE(cqe->command_id);
1068 struct request *req;
1071 * AEN requests are special as they don't time out and can
1072 * survive any kind of queue freeze and often don't respond to
1073 * aborts. We don't even bother to allocate a struct request
1074 * for them but rather special case them here.
1076 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1077 nvme_complete_async_event(&nvmeq->dev->ctrl,
1078 cqe->status, &cqe->result);
1082 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1083 if (unlikely(!req)) {
1084 dev_warn(nvmeq->dev->ctrl.device,
1085 "invalid id %d completed on queue %d\n",
1086 command_id, le16_to_cpu(cqe->sq_id));
1090 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1091 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1092 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1093 nvme_pci_complete_batch))
1094 nvme_pci_complete_rq(req);
1097 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1099 u32 tmp = nvmeq->cq_head + 1;
1101 if (tmp == nvmeq->q_depth) {
1103 nvmeq->cq_phase ^= 1;
1105 nvmeq->cq_head = tmp;
1109 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1110 struct io_comp_batch *iob)
1114 while (nvme_cqe_pending(nvmeq)) {
1117 * load-load control dependency between phase and the rest of
1118 * the cqe requires a full read memory barrier
1121 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1122 nvme_update_cq_head(nvmeq);
1126 nvme_ring_cq_doorbell(nvmeq);
1130 static irqreturn_t nvme_irq(int irq, void *data)
1132 struct nvme_queue *nvmeq = data;
1133 DEFINE_IO_COMP_BATCH(iob);
1135 if (nvme_poll_cq(nvmeq, &iob)) {
1136 if (!rq_list_empty(iob.req_list))
1137 nvme_pci_complete_batch(&iob);
1143 static irqreturn_t nvme_irq_check(int irq, void *data)
1145 struct nvme_queue *nvmeq = data;
1147 if (nvme_cqe_pending(nvmeq))
1148 return IRQ_WAKE_THREAD;
1153 * Poll for completions for any interrupt driven queue
1154 * Can be called from any context.
1156 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1158 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1160 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1162 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1163 nvme_poll_cq(nvmeq, NULL);
1164 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1167 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1169 struct nvme_queue *nvmeq = hctx->driver_data;
1172 if (!nvme_cqe_pending(nvmeq))
1175 spin_lock(&nvmeq->cq_poll_lock);
1176 found = nvme_poll_cq(nvmeq, iob);
1177 spin_unlock(&nvmeq->cq_poll_lock);
1182 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1184 struct nvme_dev *dev = to_nvme_dev(ctrl);
1185 struct nvme_queue *nvmeq = &dev->queues[0];
1186 struct nvme_command c = { };
1188 c.common.opcode = nvme_admin_async_event;
1189 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1191 spin_lock(&nvmeq->sq_lock);
1192 nvme_sq_copy_cmd(nvmeq, &c);
1193 nvme_write_sq_db(nvmeq, true);
1194 spin_unlock(&nvmeq->sq_lock);
1197 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1199 struct nvme_command c = { };
1201 c.delete_queue.opcode = opcode;
1202 c.delete_queue.qid = cpu_to_le16(id);
1204 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1207 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1208 struct nvme_queue *nvmeq, s16 vector)
1210 struct nvme_command c = { };
1211 int flags = NVME_QUEUE_PHYS_CONTIG;
1213 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1214 flags |= NVME_CQ_IRQ_ENABLED;
1217 * Note: we (ab)use the fact that the prp fields survive if no data
1218 * is attached to the request.
1220 c.create_cq.opcode = nvme_admin_create_cq;
1221 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1222 c.create_cq.cqid = cpu_to_le16(qid);
1223 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1224 c.create_cq.cq_flags = cpu_to_le16(flags);
1225 c.create_cq.irq_vector = cpu_to_le16(vector);
1227 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1230 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1231 struct nvme_queue *nvmeq)
1233 struct nvme_ctrl *ctrl = &dev->ctrl;
1234 struct nvme_command c = { };
1235 int flags = NVME_QUEUE_PHYS_CONTIG;
1238 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1239 * set. Since URGENT priority is zeroes, it makes all queues
1242 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1243 flags |= NVME_SQ_PRIO_MEDIUM;
1246 * Note: we (ab)use the fact that the prp fields survive if no data
1247 * is attached to the request.
1249 c.create_sq.opcode = nvme_admin_create_sq;
1250 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1251 c.create_sq.sqid = cpu_to_le16(qid);
1252 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1253 c.create_sq.sq_flags = cpu_to_le16(flags);
1254 c.create_sq.cqid = cpu_to_le16(qid);
1256 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1259 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1261 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1264 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1266 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1269 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
1271 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1273 dev_warn(nvmeq->dev->ctrl.device,
1274 "Abort status: 0x%x", nvme_req(req)->status);
1275 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1276 blk_mq_free_request(req);
1277 return RQ_END_IO_NONE;
1280 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1282 /* If true, indicates loss of adapter communication, possibly by a
1283 * NVMe Subsystem reset.
1285 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1287 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1288 switch (dev->ctrl.state) {
1289 case NVME_CTRL_RESETTING:
1290 case NVME_CTRL_CONNECTING:
1296 /* We shouldn't reset unless the controller is on fatal error state
1297 * _or_ if we lost the communication with it.
1299 if (!(csts & NVME_CSTS_CFS) && !nssro)
1305 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1307 /* Read a config register to help see what died. */
1311 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1313 if (result == PCIBIOS_SUCCESSFUL)
1314 dev_warn(dev->ctrl.device,
1315 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1318 dev_warn(dev->ctrl.device,
1319 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1325 dev_warn(dev->ctrl.device,
1326 "Does your device have a faulty power saving mode enabled?\n");
1327 dev_warn(dev->ctrl.device,
1328 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
1331 static enum blk_eh_timer_return nvme_timeout(struct request *req)
1333 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1334 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1335 struct nvme_dev *dev = nvmeq->dev;
1336 struct request *abort_req;
1337 struct nvme_command cmd = { };
1338 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1340 /* If PCI error recovery process is happening, we cannot reset or
1341 * the recovery mechanism will surely fail.
1344 if (pci_channel_offline(to_pci_dev(dev->dev)))
1345 return BLK_EH_RESET_TIMER;
1348 * Reset immediately if the controller is failed
1350 if (nvme_should_reset(dev, csts)) {
1351 nvme_warn_reset(dev, csts);
1352 nvme_dev_disable(dev, false);
1353 nvme_reset_ctrl(&dev->ctrl);
1358 * Did we miss an interrupt?
1360 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1361 nvme_poll(req->mq_hctx, NULL);
1363 nvme_poll_irqdisable(nvmeq);
1365 if (blk_mq_request_completed(req)) {
1366 dev_warn(dev->ctrl.device,
1367 "I/O %d QID %d timeout, completion polled\n",
1368 req->tag, nvmeq->qid);
1373 * Shutdown immediately if controller times out while starting. The
1374 * reset work will see the pci device disabled when it gets the forced
1375 * cancellation error. All outstanding requests are completed on
1376 * shutdown, so we return BLK_EH_DONE.
1378 switch (dev->ctrl.state) {
1379 case NVME_CTRL_CONNECTING:
1380 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1382 case NVME_CTRL_DELETING:
1383 dev_warn_ratelimited(dev->ctrl.device,
1384 "I/O %d QID %d timeout, disable controller\n",
1385 req->tag, nvmeq->qid);
1386 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1387 nvme_dev_disable(dev, true);
1389 case NVME_CTRL_RESETTING:
1390 return BLK_EH_RESET_TIMER;
1396 * Shutdown the controller immediately and schedule a reset if the
1397 * command was already aborted once before and still hasn't been
1398 * returned to the driver, or if this is the admin queue.
1400 if (!nvmeq->qid || iod->aborted) {
1401 dev_warn(dev->ctrl.device,
1402 "I/O %d QID %d timeout, reset controller\n",
1403 req->tag, nvmeq->qid);
1404 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1405 nvme_dev_disable(dev, false);
1406 nvme_reset_ctrl(&dev->ctrl);
1411 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1412 atomic_inc(&dev->ctrl.abort_limit);
1413 return BLK_EH_RESET_TIMER;
1415 iod->aborted = true;
1417 cmd.abort.opcode = nvme_admin_abort_cmd;
1418 cmd.abort.cid = nvme_cid(req);
1419 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1421 dev_warn(nvmeq->dev->ctrl.device,
1422 "I/O %d (%s) QID %d timeout, aborting\n",
1424 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1427 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1429 if (IS_ERR(abort_req)) {
1430 atomic_inc(&dev->ctrl.abort_limit);
1431 return BLK_EH_RESET_TIMER;
1433 nvme_init_request(abort_req, &cmd);
1435 abort_req->end_io = abort_endio;
1436 abort_req->end_io_data = NULL;
1437 blk_execute_rq_nowait(abort_req, false);
1440 * The aborted req will be completed on receiving the abort req.
1441 * We enable the timer again. If hit twice, it'll cause a device reset,
1442 * as the device then is in a faulty state.
1444 return BLK_EH_RESET_TIMER;
1447 static void nvme_free_queue(struct nvme_queue *nvmeq)
1449 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1450 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1451 if (!nvmeq->sq_cmds)
1454 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1455 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1456 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1458 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1459 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1463 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1467 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1468 dev->ctrl.queue_count--;
1469 nvme_free_queue(&dev->queues[i]);
1473 static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
1475 struct nvme_queue *nvmeq = &dev->queues[qid];
1477 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1480 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1483 nvmeq->dev->online_queues--;
1484 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1485 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
1486 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1487 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
1490 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1494 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1495 nvme_suspend_queue(dev, i);
1499 * Called only on a device that has been disabled and after all other threads
1500 * that can check this device's completion queues have synced, except
1501 * nvme_poll(). This is the last chance for the driver to see a natural
1502 * completion before nvme_cancel_request() terminates all incomplete requests.
1504 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1508 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1509 spin_lock(&dev->queues[i].cq_poll_lock);
1510 nvme_poll_cq(&dev->queues[i], NULL);
1511 spin_unlock(&dev->queues[i].cq_poll_lock);
1515 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1518 int q_depth = dev->q_depth;
1519 unsigned q_size_aligned = roundup(q_depth * entry_size,
1520 NVME_CTRL_PAGE_SIZE);
1522 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1523 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1525 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1526 q_depth = div_u64(mem_per_q, entry_size);
1529 * Ensure the reduced q_depth is above some threshold where it
1530 * would be better to map queues in system memory with the
1540 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1543 struct pci_dev *pdev = to_pci_dev(dev->dev);
1545 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1546 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1547 if (nvmeq->sq_cmds) {
1548 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1550 if (nvmeq->sq_dma_addr) {
1551 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1555 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1559 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1560 &nvmeq->sq_dma_addr, GFP_KERNEL);
1561 if (!nvmeq->sq_cmds)
1566 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1568 struct nvme_queue *nvmeq = &dev->queues[qid];
1570 if (dev->ctrl.queue_count > qid)
1573 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1574 nvmeq->q_depth = depth;
1575 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1576 &nvmeq->cq_dma_addr, GFP_KERNEL);
1580 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1584 spin_lock_init(&nvmeq->sq_lock);
1585 spin_lock_init(&nvmeq->cq_poll_lock);
1587 nvmeq->cq_phase = 1;
1588 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1590 dev->ctrl.queue_count++;
1595 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1596 nvmeq->cq_dma_addr);
1601 static int queue_request_irq(struct nvme_queue *nvmeq)
1603 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1604 int nr = nvmeq->dev->ctrl.instance;
1606 if (use_threaded_interrupts) {
1607 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1608 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1610 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1611 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1615 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1617 struct nvme_dev *dev = nvmeq->dev;
1620 nvmeq->last_sq_tail = 0;
1622 nvmeq->cq_phase = 1;
1623 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1624 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1625 nvme_dbbuf_init(dev, nvmeq, qid);
1626 dev->online_queues++;
1627 wmb(); /* ensure the first interrupt sees the initialization */
1631 * Try getting shutdown_lock while setting up IO queues.
1633 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1636 * Give up if the lock is being held by nvme_dev_disable.
1638 if (!mutex_trylock(&dev->shutdown_lock))
1642 * Controller is in wrong state, fail early.
1644 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1645 mutex_unlock(&dev->shutdown_lock);
1652 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1654 struct nvme_dev *dev = nvmeq->dev;
1658 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1661 * A queue's vector matches the queue identifier unless the controller
1662 * has only one vector available.
1665 vector = dev->num_vecs == 1 ? 0 : qid;
1667 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1669 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1673 result = adapter_alloc_sq(dev, qid, nvmeq);
1679 nvmeq->cq_vector = vector;
1681 result = nvme_setup_io_queues_trylock(dev);
1684 nvme_init_queue(nvmeq, qid);
1686 result = queue_request_irq(nvmeq);
1691 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1692 mutex_unlock(&dev->shutdown_lock);
1696 dev->online_queues--;
1697 mutex_unlock(&dev->shutdown_lock);
1698 adapter_delete_sq(dev, qid);
1700 adapter_delete_cq(dev, qid);
1704 static const struct blk_mq_ops nvme_mq_admin_ops = {
1705 .queue_rq = nvme_queue_rq,
1706 .complete = nvme_pci_complete_rq,
1707 .init_hctx = nvme_admin_init_hctx,
1708 .init_request = nvme_pci_init_request,
1709 .timeout = nvme_timeout,
1712 static const struct blk_mq_ops nvme_mq_ops = {
1713 .queue_rq = nvme_queue_rq,
1714 .queue_rqs = nvme_queue_rqs,
1715 .complete = nvme_pci_complete_rq,
1716 .commit_rqs = nvme_commit_rqs,
1717 .init_hctx = nvme_init_hctx,
1718 .init_request = nvme_pci_init_request,
1719 .map_queues = nvme_pci_map_queues,
1720 .timeout = nvme_timeout,
1724 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1726 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1728 * If the controller was reset during removal, it's possible
1729 * user requests may be waiting on a stopped queue. Start the
1730 * queue to flush these to completion.
1732 nvme_unquiesce_admin_queue(&dev->ctrl);
1733 nvme_remove_admin_tag_set(&dev->ctrl);
1737 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1739 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1742 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1744 struct pci_dev *pdev = to_pci_dev(dev->dev);
1746 if (size <= dev->bar_mapped_size)
1748 if (size > pci_resource_len(pdev, 0))
1752 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1754 dev->bar_mapped_size = 0;
1757 dev->bar_mapped_size = size;
1758 dev->dbs = dev->bar + NVME_REG_DBS;
1763 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1767 struct nvme_queue *nvmeq;
1769 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1773 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1774 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1776 if (dev->subsystem &&
1777 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1778 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1781 * If the device has been passed off to us in an enabled state, just
1782 * clear the enabled bit. The spec says we should set the 'shutdown
1783 * notification bits', but doing so may cause the device to complete
1784 * commands to the admin queue ... and we don't know what memory that
1785 * might be pointing at!
1787 result = nvme_disable_ctrl(&dev->ctrl, false);
1791 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1795 dev->ctrl.numa_node = dev_to_node(dev->dev);
1797 nvmeq = &dev->queues[0];
1798 aqa = nvmeq->q_depth - 1;
1801 writel(aqa, dev->bar + NVME_REG_AQA);
1802 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1803 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1805 result = nvme_enable_ctrl(&dev->ctrl);
1809 nvmeq->cq_vector = 0;
1810 nvme_init_queue(nvmeq, 0);
1811 result = queue_request_irq(nvmeq);
1813 dev->online_queues--;
1817 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1821 static int nvme_create_io_queues(struct nvme_dev *dev)
1823 unsigned i, max, rw_queues;
1826 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1827 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1833 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1834 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1835 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1836 dev->io_queues[HCTX_TYPE_READ];
1841 for (i = dev->online_queues; i <= max; i++) {
1842 bool polled = i > rw_queues;
1844 ret = nvme_create_queue(&dev->queues[i], i, polled);
1850 * Ignore failing Create SQ/CQ commands, we can continue with less
1851 * than the desired amount of queues, and even a controller without
1852 * I/O queues can still be used to issue admin commands. This might
1853 * be useful to upgrade a buggy firmware for example.
1855 return ret >= 0 ? 0 : ret;
1858 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1860 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1862 return 1ULL << (12 + 4 * szu);
1865 static u32 nvme_cmb_size(struct nvme_dev *dev)
1867 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1870 static void nvme_map_cmb(struct nvme_dev *dev)
1873 resource_size_t bar_size;
1874 struct pci_dev *pdev = to_pci_dev(dev->dev);
1880 if (NVME_CAP_CMBS(dev->ctrl.cap))
1881 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1883 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1886 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1888 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1889 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1890 bar = NVME_CMB_BIR(dev->cmbloc);
1891 bar_size = pci_resource_len(pdev, bar);
1893 if (offset > bar_size)
1897 * Tell the controller about the host side address mapping the CMB,
1898 * and enable CMB decoding for the NVMe 1.4+ scheme:
1900 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1901 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1902 (pci_bus_address(pdev, bar) + offset),
1903 dev->bar + NVME_REG_CMBMSC);
1907 * Controllers may support a CMB size larger than their BAR,
1908 * for example, due to being behind a bridge. Reduce the CMB to
1909 * the reported size of the BAR
1911 if (size > bar_size - offset)
1912 size = bar_size - offset;
1914 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1915 dev_warn(dev->ctrl.device,
1916 "failed to register the CMB\n");
1920 dev->cmb_size = size;
1921 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1923 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1924 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1925 pci_p2pmem_publish(pdev, true);
1928 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1930 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1931 u64 dma_addr = dev->host_mem_descs_dma;
1932 struct nvme_command c = { };
1935 c.features.opcode = nvme_admin_set_features;
1936 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1937 c.features.dword11 = cpu_to_le32(bits);
1938 c.features.dword12 = cpu_to_le32(host_mem_size);
1939 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1940 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1941 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1943 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1945 dev_warn(dev->ctrl.device,
1946 "failed to set host mem (err %d, flags %#x).\n",
1949 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1954 static void nvme_free_host_mem(struct nvme_dev *dev)
1958 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1959 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1960 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1962 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1963 le64_to_cpu(desc->addr),
1964 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1967 kfree(dev->host_mem_desc_bufs);
1968 dev->host_mem_desc_bufs = NULL;
1969 dma_free_coherent(dev->dev,
1970 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1971 dev->host_mem_descs, dev->host_mem_descs_dma);
1972 dev->host_mem_descs = NULL;
1973 dev->nr_host_mem_descs = 0;
1976 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1979 struct nvme_host_mem_buf_desc *descs;
1980 u32 max_entries, len;
1981 dma_addr_t descs_dma;
1986 tmp = (preferred + chunk_size - 1);
1987 do_div(tmp, chunk_size);
1990 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1991 max_entries = dev->ctrl.hmmaxd;
1993 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1994 &descs_dma, GFP_KERNEL);
1998 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2000 goto out_free_descs;
2002 for (size = 0; size < preferred && i < max_entries; size += len) {
2003 dma_addr_t dma_addr;
2005 len = min_t(u64, chunk_size, preferred - size);
2006 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2007 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2011 descs[i].addr = cpu_to_le64(dma_addr);
2012 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
2019 dev->nr_host_mem_descs = i;
2020 dev->host_mem_size = size;
2021 dev->host_mem_descs = descs;
2022 dev->host_mem_descs_dma = descs_dma;
2023 dev->host_mem_desc_bufs = bufs;
2028 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
2030 dma_free_attrs(dev->dev, size, bufs[i],
2031 le64_to_cpu(descs[i].addr),
2032 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2037 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2040 dev->host_mem_descs = NULL;
2044 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2046 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2047 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2050 /* start big and work our way down */
2051 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2052 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2053 if (!min || dev->host_mem_size >= min)
2055 nvme_free_host_mem(dev);
2062 static int nvme_setup_host_mem(struct nvme_dev *dev)
2064 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2065 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2066 u64 min = (u64)dev->ctrl.hmmin * 4096;
2067 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2070 if (!dev->ctrl.hmpre)
2073 preferred = min(preferred, max);
2075 dev_warn(dev->ctrl.device,
2076 "min host memory (%lld MiB) above limit (%d MiB).\n",
2077 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2078 nvme_free_host_mem(dev);
2083 * If we already have a buffer allocated check if we can reuse it.
2085 if (dev->host_mem_descs) {
2086 if (dev->host_mem_size >= min)
2087 enable_bits |= NVME_HOST_MEM_RETURN;
2089 nvme_free_host_mem(dev);
2092 if (!dev->host_mem_descs) {
2093 if (nvme_alloc_host_mem(dev, min, preferred)) {
2094 dev_warn(dev->ctrl.device,
2095 "failed to allocate host memory buffer.\n");
2096 return 0; /* controller must work without HMB */
2099 dev_info(dev->ctrl.device,
2100 "allocated %lld MiB host memory buffer.\n",
2101 dev->host_mem_size >> ilog2(SZ_1M));
2104 ret = nvme_set_host_mem(dev, enable_bits);
2106 nvme_free_host_mem(dev);
2110 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2113 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2115 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2116 ndev->cmbloc, ndev->cmbsz);
2118 static DEVICE_ATTR_RO(cmb);
2120 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2123 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2125 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2127 static DEVICE_ATTR_RO(cmbloc);
2129 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2132 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2134 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2136 static DEVICE_ATTR_RO(cmbsz);
2138 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2141 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2143 return sysfs_emit(buf, "%d\n", ndev->hmb);
2146 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2147 const char *buf, size_t count)
2149 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2153 if (kstrtobool(buf, &new) < 0)
2156 if (new == ndev->hmb)
2160 ret = nvme_setup_host_mem(ndev);
2162 ret = nvme_set_host_mem(ndev, 0);
2164 nvme_free_host_mem(ndev);
2172 static DEVICE_ATTR_RW(hmb);
2174 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2175 struct attribute *a, int n)
2177 struct nvme_ctrl *ctrl =
2178 dev_get_drvdata(container_of(kobj, struct device, kobj));
2179 struct nvme_dev *dev = to_nvme_dev(ctrl);
2181 if (a == &dev_attr_cmb.attr ||
2182 a == &dev_attr_cmbloc.attr ||
2183 a == &dev_attr_cmbsz.attr) {
2187 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2193 static struct attribute *nvme_pci_attrs[] = {
2195 &dev_attr_cmbloc.attr,
2196 &dev_attr_cmbsz.attr,
2201 static const struct attribute_group nvme_pci_dev_attrs_group = {
2202 .attrs = nvme_pci_attrs,
2203 .is_visible = nvme_pci_attrs_are_visible,
2206 static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2207 &nvme_dev_attrs_group,
2208 &nvme_pci_dev_attrs_group,
2213 * nirqs is the number of interrupts available for write and read
2214 * queues. The core already reserved an interrupt for the admin queue.
2216 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2218 struct nvme_dev *dev = affd->priv;
2219 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2222 * If there is no interrupt available for queues, ensure that
2223 * the default queue is set to 1. The affinity set size is
2224 * also set to one, but the irq core ignores it for this case.
2226 * If only one interrupt is available or 'write_queue' == 0, combine
2227 * write and read queues.
2229 * If 'write_queues' > 0, ensure it leaves room for at least one read
2235 } else if (nrirqs == 1 || !nr_write_queues) {
2237 } else if (nr_write_queues >= nrirqs) {
2240 nr_read_queues = nrirqs - nr_write_queues;
2243 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2244 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2245 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2246 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2247 affd->nr_sets = nr_read_queues ? 2 : 1;
2250 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2252 struct pci_dev *pdev = to_pci_dev(dev->dev);
2253 struct irq_affinity affd = {
2255 .calc_sets = nvme_calc_irq_sets,
2258 unsigned int irq_queues, poll_queues;
2261 * Poll queues don't need interrupts, but we need at least one I/O queue
2262 * left over for non-polled I/O.
2264 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2265 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2268 * Initialize for the single interrupt case, will be updated in
2269 * nvme_calc_irq_sets().
2271 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2272 dev->io_queues[HCTX_TYPE_READ] = 0;
2275 * We need interrupts for the admin queue and each non-polled I/O queue,
2276 * but some Apple controllers require all queues to use the first
2280 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2281 irq_queues += (nr_io_queues - poll_queues);
2282 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2283 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2286 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2289 * If tags are shared with admin queue (Apple bug), then
2290 * make sure we only use one IO queue.
2292 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2294 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2297 static int nvme_setup_io_queues(struct nvme_dev *dev)
2299 struct nvme_queue *adminq = &dev->queues[0];
2300 struct pci_dev *pdev = to_pci_dev(dev->dev);
2301 unsigned int nr_io_queues;
2306 * Sample the module parameters once at reset time so that we have
2307 * stable values to work with.
2309 dev->nr_write_queues = write_queues;
2310 dev->nr_poll_queues = poll_queues;
2312 nr_io_queues = dev->nr_allocated_queues - 1;
2313 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2317 if (nr_io_queues == 0)
2321 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2322 * from set to unset. If there is a window to it is truely freed,
2323 * pci_free_irq_vectors() jumping into this window will crash.
2324 * And take lock to avoid racing with pci_free_irq_vectors() in
2325 * nvme_dev_disable() path.
2327 result = nvme_setup_io_queues_trylock(dev);
2330 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2331 pci_free_irq(pdev, 0, adminq);
2333 if (dev->cmb_use_sqes) {
2334 result = nvme_cmb_qdepth(dev, nr_io_queues,
2335 sizeof(struct nvme_command));
2337 dev->q_depth = result;
2339 dev->cmb_use_sqes = false;
2343 size = db_bar_size(dev, nr_io_queues);
2344 result = nvme_remap_bar(dev, size);
2347 if (!--nr_io_queues) {
2352 adminq->q_db = dev->dbs;
2355 /* Deregister the admin queue's interrupt */
2356 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2357 pci_free_irq(pdev, 0, adminq);
2360 * If we enable msix early due to not intx, disable it again before
2361 * setting up the full range we need.
2363 pci_free_irq_vectors(pdev);
2365 result = nvme_setup_irqs(dev, nr_io_queues);
2371 dev->num_vecs = result;
2372 result = max(result - 1, 1);
2373 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2376 * Should investigate if there's a performance win from allocating
2377 * more queues than interrupt vectors; it might allow the submission
2378 * path to scale better, even if the receive path is limited by the
2379 * number of interrupts.
2381 result = queue_request_irq(adminq);
2384 set_bit(NVMEQ_ENABLED, &adminq->flags);
2385 mutex_unlock(&dev->shutdown_lock);
2387 result = nvme_create_io_queues(dev);
2388 if (result || dev->online_queues < 2)
2391 if (dev->online_queues - 1 < dev->max_qid) {
2392 nr_io_queues = dev->online_queues - 1;
2393 nvme_delete_io_queues(dev);
2394 result = nvme_setup_io_queues_trylock(dev);
2397 nvme_suspend_io_queues(dev);
2400 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2401 dev->io_queues[HCTX_TYPE_DEFAULT],
2402 dev->io_queues[HCTX_TYPE_READ],
2403 dev->io_queues[HCTX_TYPE_POLL]);
2406 mutex_unlock(&dev->shutdown_lock);
2410 static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2413 struct nvme_queue *nvmeq = req->end_io_data;
2415 blk_mq_free_request(req);
2416 complete(&nvmeq->delete_done);
2417 return RQ_END_IO_NONE;
2420 static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2423 struct nvme_queue *nvmeq = req->end_io_data;
2426 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2428 return nvme_del_queue_end(req, error);
2431 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2433 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2434 struct request *req;
2435 struct nvme_command cmd = { };
2437 cmd.delete_queue.opcode = opcode;
2438 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2440 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2442 return PTR_ERR(req);
2443 nvme_init_request(req, &cmd);
2445 if (opcode == nvme_admin_delete_cq)
2446 req->end_io = nvme_del_cq_end;
2448 req->end_io = nvme_del_queue_end;
2449 req->end_io_data = nvmeq;
2451 init_completion(&nvmeq->delete_done);
2452 blk_execute_rq_nowait(req, false);
2456 static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
2458 int nr_queues = dev->online_queues - 1, sent = 0;
2459 unsigned long timeout;
2462 timeout = NVME_ADMIN_TIMEOUT;
2463 while (nr_queues > 0) {
2464 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2470 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2472 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2484 static void nvme_delete_io_queues(struct nvme_dev *dev)
2486 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2487 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2490 static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
2492 if (dev->io_queues[HCTX_TYPE_POLL])
2494 if (dev->io_queues[HCTX_TYPE_READ])
2499 static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2501 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2502 /* free previously allocated queues that are no longer usable */
2503 nvme_free_queues(dev, dev->online_queues);
2506 static int nvme_pci_enable(struct nvme_dev *dev)
2508 int result = -ENOMEM;
2509 struct pci_dev *pdev = to_pci_dev(dev->dev);
2510 int dma_address_bits = 64;
2512 if (pci_enable_device_mem(pdev))
2515 pci_set_master(pdev);
2517 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2518 dma_address_bits = 48;
2519 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2522 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2528 * Some devices and/or platforms don't advertise or work with INTx
2529 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2530 * adjust this later.
2532 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2536 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2538 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2540 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2541 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2542 dev->dbs = dev->bar + 4096;
2545 * Some Apple controllers require a non-standard SQE size.
2546 * Interestingly they also seem to ignore the CC:IOSQES register
2547 * so we don't bother updating it here.
2549 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2552 dev->io_sqes = NVME_NVM_IOSQES;
2555 * Temporary fix for the Apple controller found in the MacBook8,1 and
2556 * some MacBook7,1 to avoid controller resets and data loss.
2558 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2560 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2561 "set queue depth=%u to work around controller resets\n",
2563 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2564 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2565 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2567 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2568 "set queue depth=%u\n", dev->q_depth);
2572 * Controllers with the shared tags quirk need the IO queue to be
2573 * big enough so that we get 32 tags for the admin queue
2575 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2576 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2577 dev->q_depth = NVME_AQ_DEPTH + 2;
2578 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2585 pci_enable_pcie_error_reporting(pdev);
2586 pci_save_state(pdev);
2588 return nvme_pci_configure_admin_queue(dev);
2591 pci_disable_device(pdev);
2595 static void nvme_dev_unmap(struct nvme_dev *dev)
2599 pci_release_mem_regions(to_pci_dev(dev->dev));
2602 static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
2604 struct pci_dev *pdev = to_pci_dev(dev->dev);
2607 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2609 if (pdev->error_state != pci_channel_io_normal)
2612 csts = readl(dev->bar + NVME_REG_CSTS);
2613 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
2616 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2618 struct pci_dev *pdev = to_pci_dev(dev->dev);
2621 mutex_lock(&dev->shutdown_lock);
2622 dead = nvme_pci_ctrl_is_dead(dev);
2623 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2624 dev->ctrl.state == NVME_CTRL_RESETTING) {
2625 if (pci_is_enabled(pdev))
2626 nvme_start_freeze(&dev->ctrl);
2628 * Give the controller a chance to complete all entered requests
2629 * if doing a safe shutdown.
2631 if (!dead && shutdown)
2632 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2635 nvme_quiesce_io_queues(&dev->ctrl);
2637 if (!dead && dev->ctrl.queue_count > 0) {
2638 nvme_delete_io_queues(dev);
2639 nvme_disable_ctrl(&dev->ctrl, shutdown);
2640 nvme_poll_irqdisable(&dev->queues[0]);
2642 nvme_suspend_io_queues(dev);
2643 nvme_suspend_queue(dev, 0);
2644 pci_free_irq_vectors(pdev);
2645 if (pci_is_enabled(pdev)) {
2646 pci_disable_pcie_error_reporting(pdev);
2647 pci_disable_device(pdev);
2649 nvme_reap_pending_cqes(dev);
2651 nvme_cancel_tagset(&dev->ctrl);
2652 nvme_cancel_admin_tagset(&dev->ctrl);
2655 * The driver will not be starting up queues again if shutting down so
2656 * must flush all entered requests to their failed completion to avoid
2657 * deadlocking blk-mq hot-cpu notifier.
2660 nvme_unquiesce_io_queues(&dev->ctrl);
2661 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2662 nvme_unquiesce_admin_queue(&dev->ctrl);
2664 mutex_unlock(&dev->shutdown_lock);
2667 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2669 if (!nvme_wait_reset(&dev->ctrl))
2671 nvme_dev_disable(dev, shutdown);
2675 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2677 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2678 NVME_CTRL_PAGE_SIZE,
2679 NVME_CTRL_PAGE_SIZE, 0);
2680 if (!dev->prp_page_pool)
2683 /* Optimisation for I/Os between 4k and 128k */
2684 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2686 if (!dev->prp_small_pool) {
2687 dma_pool_destroy(dev->prp_page_pool);
2693 static void nvme_release_prp_pools(struct nvme_dev *dev)
2695 dma_pool_destroy(dev->prp_page_pool);
2696 dma_pool_destroy(dev->prp_small_pool);
2699 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2701 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
2702 size_t alloc_size = sizeof(__le64 *) * npages +
2703 sizeof(struct scatterlist) * NVME_MAX_SEGS;
2705 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2706 dev->iod_mempool = mempool_create_node(1,
2707 mempool_kmalloc, mempool_kfree,
2708 (void *)alloc_size, GFP_KERNEL,
2709 dev_to_node(dev->dev));
2710 if (!dev->iod_mempool)
2715 static void nvme_free_tagset(struct nvme_dev *dev)
2717 if (dev->tagset.tags)
2718 nvme_remove_io_tag_set(&dev->ctrl);
2719 dev->ctrl.tagset = NULL;
2722 /* pairs with nvme_pci_alloc_dev */
2723 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2725 struct nvme_dev *dev = to_nvme_dev(ctrl);
2727 nvme_free_tagset(dev);
2728 put_device(dev->dev);
2733 static void nvme_reset_work(struct work_struct *work)
2735 struct nvme_dev *dev =
2736 container_of(work, struct nvme_dev, ctrl.reset_work);
2737 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2740 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2741 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2747 * If we're called to reset a live controller first shut it down before
2750 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2751 nvme_dev_disable(dev, false);
2752 nvme_sync_queues(&dev->ctrl);
2754 mutex_lock(&dev->shutdown_lock);
2755 result = nvme_pci_enable(dev);
2758 nvme_unquiesce_admin_queue(&dev->ctrl);
2759 mutex_unlock(&dev->shutdown_lock);
2762 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2763 * initializing procedure here.
2765 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2766 dev_warn(dev->ctrl.device,
2767 "failed to mark controller CONNECTING\n");
2772 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
2776 nvme_dbbuf_dma_alloc(dev);
2778 result = nvme_setup_host_mem(dev);
2782 result = nvme_setup_io_queues(dev);
2787 * Freeze and update the number of I/O queues as thos might have
2788 * changed. If there are no I/O queues left after this reset, keep the
2789 * controller around but remove all namespaces.
2791 if (dev->online_queues > 1) {
2792 nvme_unquiesce_io_queues(&dev->ctrl);
2793 nvme_wait_freeze(&dev->ctrl);
2794 nvme_pci_update_nr_queues(dev);
2795 nvme_dbbuf_set(dev);
2796 nvme_unfreeze(&dev->ctrl);
2798 dev_warn(dev->ctrl.device, "IO queues lost\n");
2799 nvme_mark_namespaces_dead(&dev->ctrl);
2800 nvme_unquiesce_io_queues(&dev->ctrl);
2801 nvme_remove_namespaces(&dev->ctrl);
2802 nvme_free_tagset(dev);
2806 * If only admin queue live, keep it to do further investigation or
2809 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2810 dev_warn(dev->ctrl.device,
2811 "failed to mark controller live state\n");
2816 nvme_start_ctrl(&dev->ctrl);
2820 mutex_unlock(&dev->shutdown_lock);
2823 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2824 * may be holding this pci_dev's device lock.
2826 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2828 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2829 nvme_dev_disable(dev, true);
2830 nvme_mark_namespaces_dead(&dev->ctrl);
2831 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2834 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2836 *val = readl(to_nvme_dev(ctrl)->bar + off);
2840 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2842 writel(val, to_nvme_dev(ctrl)->bar + off);
2846 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2848 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2852 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2854 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2856 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2859 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2861 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2862 struct nvme_subsystem *subsys = ctrl->subsys;
2864 dev_err(ctrl->device,
2865 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2866 pdev->vendor, pdev->device,
2867 nvme_strlen(subsys->model, sizeof(subsys->model)),
2868 subsys->model, nvme_strlen(subsys->firmware_rev,
2869 sizeof(subsys->firmware_rev)),
2870 subsys->firmware_rev);
2873 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2875 struct nvme_dev *dev = to_nvme_dev(ctrl);
2877 return dma_pci_p2pdma_supported(dev->dev);
2880 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2882 .module = THIS_MODULE,
2883 .flags = NVME_F_METADATA_SUPPORTED,
2884 .dev_attr_groups = nvme_pci_dev_attr_groups,
2885 .reg_read32 = nvme_pci_reg_read32,
2886 .reg_write32 = nvme_pci_reg_write32,
2887 .reg_read64 = nvme_pci_reg_read64,
2888 .free_ctrl = nvme_pci_free_ctrl,
2889 .submit_async_event = nvme_pci_submit_async_event,
2890 .get_address = nvme_pci_get_address,
2891 .print_device_info = nvme_pci_print_device_info,
2892 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
2895 static int nvme_dev_map(struct nvme_dev *dev)
2897 struct pci_dev *pdev = to_pci_dev(dev->dev);
2899 if (pci_request_mem_regions(pdev, "nvme"))
2902 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2907 pci_release_mem_regions(pdev);
2911 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2913 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2915 * Several Samsung devices seem to drop off the PCIe bus
2916 * randomly when APST is on and uses the deepest sleep state.
2917 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2918 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2919 * 950 PRO 256GB", but it seems to be restricted to two Dell
2922 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2923 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2924 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2925 return NVME_QUIRK_NO_DEEPEST_PS;
2926 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2928 * Samsung SSD 960 EVO drops off the PCIe bus after system
2929 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2930 * within few minutes after bootup on a Coffee Lake board -
2933 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2934 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2935 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2936 return NVME_QUIRK_NO_APST;
2937 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2938 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2939 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2941 * Forcing to use host managed nvme power settings for
2942 * lowest idle power with quick resume latency on
2943 * Samsung and Toshiba SSDs based on suspend behavior
2944 * on Coffee Lake board for LENOVO C640
2946 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2947 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2948 return NVME_QUIRK_SIMPLE_SUSPEND;
2954 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2955 const struct pci_device_id *id)
2957 unsigned long quirks = id->driver_data;
2958 int node = dev_to_node(&pdev->dev);
2959 struct nvme_dev *dev;
2962 if (node == NUMA_NO_NODE)
2963 set_dev_node(&pdev->dev, first_memory_node);
2965 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2968 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2969 mutex_init(&dev->shutdown_lock);
2971 dev->nr_write_queues = write_queues;
2972 dev->nr_poll_queues = poll_queues;
2973 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2974 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2975 sizeof(struct nvme_queue), GFP_KERNEL, node);
2979 dev->dev = get_device(&pdev->dev);
2981 quirks |= check_vendor_combination_bug(pdev);
2982 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
2984 * Some systems use a bios work around to ask for D3 on
2985 * platforms that support kernel managed suspend.
2987 dev_info(&pdev->dev,
2988 "platform quirk: setting simple suspend\n");
2989 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2991 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2994 goto out_put_device;
2996 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
2997 dma_set_max_seg_size(&pdev->dev, 0xffffffff);
3000 * Limit the max command size to prevent iod->sg allocations going
3001 * over a single page.
3003 dev->ctrl.max_hw_sectors = min_t(u32,
3004 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9);
3005 dev->ctrl.max_segments = NVME_MAX_SEGS;
3008 * There is no support for SGLs for metadata (yet), so we are limited to
3009 * a single integrity segment for the separate metadata pointer.
3011 dev->ctrl.max_integrity_segments = 1;
3015 put_device(dev->dev);
3019 return ERR_PTR(ret);
3022 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3024 struct nvme_dev *dev;
3025 int result = -ENOMEM;
3027 dev = nvme_pci_alloc_dev(pdev, id);
3031 result = nvme_dev_map(dev);
3033 goto out_uninit_ctrl;
3035 result = nvme_setup_prp_pools(dev);
3039 result = nvme_pci_alloc_iod_mempool(dev);
3041 goto out_release_prp_pools;
3043 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3045 result = nvme_pci_enable(dev);
3047 goto out_release_iod_mempool;
3049 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3050 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
3055 * Mark the controller as connecting before sending admin commands to
3056 * allow the timeout handler to do the right thing.
3058 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3059 dev_warn(dev->ctrl.device,
3060 "failed to mark controller CONNECTING\n");
3065 result = nvme_init_ctrl_finish(&dev->ctrl, false);
3069 nvme_dbbuf_dma_alloc(dev);
3071 result = nvme_setup_host_mem(dev);
3075 result = nvme_setup_io_queues(dev);
3079 if (dev->online_queues > 1) {
3080 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3081 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
3082 nvme_dbbuf_set(dev);
3085 if (!dev->ctrl.tagset)
3086 dev_warn(dev->ctrl.device, "IO queues not created\n");
3088 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3089 dev_warn(dev->ctrl.device,
3090 "failed to mark controller live state\n");
3095 pci_set_drvdata(pdev, dev);
3097 nvme_start_ctrl(&dev->ctrl);
3098 nvme_put_ctrl(&dev->ctrl);
3102 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3103 nvme_dev_disable(dev, true);
3104 nvme_free_host_mem(dev);
3105 nvme_dev_remove_admin(dev);
3106 nvme_dbbuf_dma_free(dev);
3107 nvme_free_queues(dev, 0);
3108 out_release_iod_mempool:
3109 mempool_destroy(dev->iod_mempool);
3110 out_release_prp_pools:
3111 nvme_release_prp_pools(dev);
3113 nvme_dev_unmap(dev);
3115 nvme_uninit_ctrl(&dev->ctrl);
3119 static void nvme_reset_prepare(struct pci_dev *pdev)
3121 struct nvme_dev *dev = pci_get_drvdata(pdev);
3124 * We don't need to check the return value from waiting for the reset
3125 * state as pci_dev device lock is held, making it impossible to race
3128 nvme_disable_prepare_reset(dev, false);
3129 nvme_sync_queues(&dev->ctrl);
3132 static void nvme_reset_done(struct pci_dev *pdev)
3134 struct nvme_dev *dev = pci_get_drvdata(pdev);
3136 if (!nvme_try_sched_reset(&dev->ctrl))
3137 flush_work(&dev->ctrl.reset_work);
3140 static void nvme_shutdown(struct pci_dev *pdev)
3142 struct nvme_dev *dev = pci_get_drvdata(pdev);
3144 nvme_disable_prepare_reset(dev, true);
3148 * The driver's remove may be called on a device in a partially initialized
3149 * state. This function must not have any dependencies on the device state in
3152 static void nvme_remove(struct pci_dev *pdev)
3154 struct nvme_dev *dev = pci_get_drvdata(pdev);
3156 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3157 pci_set_drvdata(pdev, NULL);
3159 if (!pci_device_is_present(pdev)) {
3160 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3161 nvme_dev_disable(dev, true);
3164 flush_work(&dev->ctrl.reset_work);
3165 nvme_stop_ctrl(&dev->ctrl);
3166 nvme_remove_namespaces(&dev->ctrl);
3167 nvme_dev_disable(dev, true);
3168 nvme_free_host_mem(dev);
3169 nvme_dev_remove_admin(dev);
3170 nvme_dbbuf_dma_free(dev);
3171 nvme_free_queues(dev, 0);
3172 mempool_destroy(dev->iod_mempool);
3173 nvme_release_prp_pools(dev);
3174 nvme_dev_unmap(dev);
3175 nvme_uninit_ctrl(&dev->ctrl);
3178 #ifdef CONFIG_PM_SLEEP
3179 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3181 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3184 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3186 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3189 static int nvme_resume(struct device *dev)
3191 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3192 struct nvme_ctrl *ctrl = &ndev->ctrl;
3194 if (ndev->last_ps == U32_MAX ||
3195 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3197 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3202 return nvme_try_sched_reset(ctrl);
3205 static int nvme_suspend(struct device *dev)
3207 struct pci_dev *pdev = to_pci_dev(dev);
3208 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3209 struct nvme_ctrl *ctrl = &ndev->ctrl;
3212 ndev->last_ps = U32_MAX;
3215 * The platform does not remove power for a kernel managed suspend so
3216 * use host managed nvme power settings for lowest idle power if
3217 * possible. This should have quicker resume latency than a full device
3218 * shutdown. But if the firmware is involved after the suspend or the
3219 * device does not support any non-default power states, shut down the
3222 * If ASPM is not enabled for the device, shut down the device and allow
3223 * the PCI bus layer to put it into D3 in order to take the PCIe link
3224 * down, so as to allow the platform to achieve its minimum low-power
3225 * state (which may not be possible if the link is up).
3227 if (pm_suspend_via_firmware() || !ctrl->npss ||
3228 !pcie_aspm_enabled(pdev) ||
3229 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3230 return nvme_disable_prepare_reset(ndev, true);
3232 nvme_start_freeze(ctrl);
3233 nvme_wait_freeze(ctrl);
3234 nvme_sync_queues(ctrl);
3236 if (ctrl->state != NVME_CTRL_LIVE)
3240 * Host memory access may not be successful in a system suspend state,
3241 * but the specification allows the controller to access memory in a
3242 * non-operational power state.
3245 ret = nvme_set_host_mem(ndev, 0);
3250 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3255 * A saved state prevents pci pm from generically controlling the
3256 * device's power. If we're using protocol specific settings, we don't
3257 * want pci interfering.
3259 pci_save_state(pdev);
3261 ret = nvme_set_power_state(ctrl, ctrl->npss);
3266 /* discard the saved state */
3267 pci_load_saved_state(pdev, NULL);
3270 * Clearing npss forces a controller reset on resume. The
3271 * correct value will be rediscovered then.
3273 ret = nvme_disable_prepare_reset(ndev, true);
3277 nvme_unfreeze(ctrl);
3281 static int nvme_simple_suspend(struct device *dev)
3283 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3285 return nvme_disable_prepare_reset(ndev, true);
3288 static int nvme_simple_resume(struct device *dev)
3290 struct pci_dev *pdev = to_pci_dev(dev);
3291 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3293 return nvme_try_sched_reset(&ndev->ctrl);
3296 static const struct dev_pm_ops nvme_dev_pm_ops = {
3297 .suspend = nvme_suspend,
3298 .resume = nvme_resume,
3299 .freeze = nvme_simple_suspend,
3300 .thaw = nvme_simple_resume,
3301 .poweroff = nvme_simple_suspend,
3302 .restore = nvme_simple_resume,
3304 #endif /* CONFIG_PM_SLEEP */
3306 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3307 pci_channel_state_t state)
3309 struct nvme_dev *dev = pci_get_drvdata(pdev);
3312 * A frozen channel requires a reset. When detected, this method will
3313 * shutdown the controller to quiesce. The controller will be restarted
3314 * after the slot reset through driver's slot_reset callback.
3317 case pci_channel_io_normal:
3318 return PCI_ERS_RESULT_CAN_RECOVER;
3319 case pci_channel_io_frozen:
3320 dev_warn(dev->ctrl.device,
3321 "frozen state error detected, reset controller\n");
3322 nvme_dev_disable(dev, false);
3323 return PCI_ERS_RESULT_NEED_RESET;
3324 case pci_channel_io_perm_failure:
3325 dev_warn(dev->ctrl.device,
3326 "failure state error detected, request disconnect\n");
3327 return PCI_ERS_RESULT_DISCONNECT;
3329 return PCI_ERS_RESULT_NEED_RESET;
3332 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3334 struct nvme_dev *dev = pci_get_drvdata(pdev);
3336 dev_info(dev->ctrl.device, "restart after slot reset\n");
3337 pci_restore_state(pdev);
3338 nvme_reset_ctrl(&dev->ctrl);
3339 return PCI_ERS_RESULT_RECOVERED;
3342 static void nvme_error_resume(struct pci_dev *pdev)
3344 struct nvme_dev *dev = pci_get_drvdata(pdev);
3346 flush_work(&dev->ctrl.reset_work);
3349 static const struct pci_error_handlers nvme_err_handler = {
3350 .error_detected = nvme_error_detected,
3351 .slot_reset = nvme_slot_reset,
3352 .resume = nvme_error_resume,
3353 .reset_prepare = nvme_reset_prepare,
3354 .reset_done = nvme_reset_done,
3357 static const struct pci_device_id nvme_id_table[] = {
3358 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3359 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3360 NVME_QUIRK_DEALLOCATE_ZEROES, },
3361 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
3362 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3363 NVME_QUIRK_DEALLOCATE_ZEROES, },
3364 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
3365 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3366 NVME_QUIRK_DEALLOCATE_ZEROES |
3367 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3368 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
3369 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3370 NVME_QUIRK_DEALLOCATE_ZEROES, },
3371 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3372 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3373 NVME_QUIRK_MEDIUM_PRIO_SQ |
3374 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3375 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3376 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3377 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3378 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3379 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3380 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3381 NVME_QUIRK_BOGUS_NID, },
3382 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3383 .driver_data = NVME_QUIRK_BOGUS_NID, },
3384 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3385 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3386 NVME_QUIRK_BOGUS_NID, },
3387 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3388 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3389 NVME_QUIRK_NO_NS_DESC_LIST, },
3390 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3391 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3392 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3393 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3394 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3395 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3396 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3397 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3398 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3399 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3400 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3401 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3402 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3403 .driver_data = NVME_QUIRK_BOGUS_NID, },
3404 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3405 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3406 NVME_QUIRK_BOGUS_NID, },
3407 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3408 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3409 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3410 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3411 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3412 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3413 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3414 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3415 .driver_data = NVME_QUIRK_BOGUS_NID, },
3416 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3417 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3418 NVME_QUIRK_BOGUS_NID, },
3419 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3420 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3421 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3422 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3423 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3424 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3425 .driver_data = NVME_QUIRK_BOGUS_NID, },
3426 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3427 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3428 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3429 .driver_data = NVME_QUIRK_BOGUS_NID, },
3430 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3431 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3432 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3433 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3434 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3435 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3436 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3437 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3438 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3439 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3440 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3441 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3442 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3443 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3444 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3445 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3446 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3447 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3448 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3449 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3450 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3451 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3452 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3453 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3454 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3455 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3456 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
3457 .driver_data = NVME_QUIRK_BOGUS_NID, },
3458 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3459 .driver_data = NVME_QUIRK_BOGUS_NID, },
3460 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3461 .driver_data = NVME_QUIRK_BOGUS_NID, },
3462 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3463 .driver_data = NVME_QUIRK_BOGUS_NID, },
3464 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3465 .driver_data = NVME_QUIRK_BOGUS_NID, },
3466 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3467 .driver_data = NVME_QUIRK_BOGUS_NID, },
3468 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3469 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3470 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3471 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3472 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3473 .driver_data = NVME_QUIRK_BOGUS_NID, },
3474 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3475 .driver_data = NVME_QUIRK_BOGUS_NID, },
3476 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3477 .driver_data = NVME_QUIRK_BOGUS_NID, },
3478 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3479 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3480 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3481 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3482 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3483 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3484 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3485 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3486 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3487 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3488 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3489 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3490 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3491 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3492 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3493 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3494 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3495 NVME_QUIRK_128_BYTES_SQES |
3496 NVME_QUIRK_SHARED_TAGS |
3497 NVME_QUIRK_SKIP_CID_GEN },
3498 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3501 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3503 static struct pci_driver nvme_driver = {
3505 .id_table = nvme_id_table,
3506 .probe = nvme_probe,
3507 .remove = nvme_remove,
3508 .shutdown = nvme_shutdown,
3510 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3511 #ifdef CONFIG_PM_SLEEP
3512 .pm = &nvme_dev_pm_ops,
3515 .sriov_configure = pci_sriov_configure_simple,
3516 .err_handler = &nvme_err_handler,
3519 static int __init nvme_init(void)
3521 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3522 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3523 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3524 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3525 BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) >
3528 return pci_register_driver(&nvme_driver);
3531 static void __exit nvme_exit(void)
3533 pci_unregister_driver(&nvme_driver);
3534 flush_workqueue(nvme_wq);
3537 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3538 MODULE_LICENSE("GPL");
3539 MODULE_VERSION("1.0");
3540 module_init(nvme_init);
3541 module_exit(nvme_exit);