1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/once.h>
20 #include <linux/pci.h>
21 #include <linux/t10-pi.h>
22 #include <linux/types.h>
23 #include <linux/io-64-nonatomic-lo-hi.h>
24 #include <linux/sed-opal.h>
25 #include <linux/pci-p2pdma.h>
30 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
31 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
33 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
36 * These can be higher, but we need to ensure that any command doesn't
37 * require an sg allocation that needs more than a page of data.
39 #define NVME_MAX_KB_SZ 4096
40 #define NVME_MAX_SEGS 127
42 static int use_threaded_interrupts;
43 module_param(use_threaded_interrupts, int, 0);
45 static bool use_cmb_sqes = true;
46 module_param(use_cmb_sqes, bool, 0444);
47 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49 static unsigned int max_host_mem_size_mb = 128;
50 module_param(max_host_mem_size_mb, uint, 0444);
51 MODULE_PARM_DESC(max_host_mem_size_mb,
52 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
54 static unsigned int sgl_threshold = SZ_32K;
55 module_param(sgl_threshold, uint, 0644);
56 MODULE_PARM_DESC(sgl_threshold,
57 "Use SGLs when average request segment size is larger or equal to "
58 "this size. Use 0 to disable SGLs.");
60 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
61 static const struct kernel_param_ops io_queue_depth_ops = {
62 .set = io_queue_depth_set,
66 static int io_queue_depth = 1024;
67 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
68 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70 static int queue_count_set(const char *val, const struct kernel_param *kp);
71 static const struct kernel_param_ops queue_count_ops = {
72 .set = queue_count_set,
76 static int write_queues;
77 module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
78 MODULE_PARM_DESC(write_queues,
79 "Number of queues to use for writes. If not set, reads and writes "
80 "will share a queue set.");
82 static int poll_queues = 0;
83 module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
84 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
89 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
90 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
93 * Represents an NVM Express device. Each nvme_dev is a PCI function.
96 struct nvme_queue *queues;
97 struct blk_mq_tag_set tagset;
98 struct blk_mq_tag_set admin_tagset;
101 struct dma_pool *prp_page_pool;
102 struct dma_pool *prp_small_pool;
103 unsigned online_queues;
105 unsigned io_queues[HCTX_MAX_TYPES];
106 unsigned int num_vecs;
110 unsigned long bar_mapped_size;
111 struct work_struct remove_work;
112 struct mutex shutdown_lock;
118 struct nvme_ctrl ctrl;
120 mempool_t *iod_mempool;
122 /* shadow doorbell buffer support: */
124 dma_addr_t dbbuf_dbs_dma_addr;
126 dma_addr_t dbbuf_eis_dma_addr;
128 /* host memory buffer support: */
130 u32 nr_host_mem_descs;
131 dma_addr_t host_mem_descs_dma;
132 struct nvme_host_mem_buf_desc *host_mem_descs;
133 void **host_mem_desc_bufs;
136 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
140 ret = kstrtoint(val, 10, &n);
141 if (ret != 0 || n < 2)
144 return param_set_int(val, kp);
147 static int queue_count_set(const char *val, const struct kernel_param *kp)
151 ret = kstrtoint(val, 10, &n);
154 if (n > num_possible_cpus())
155 n = num_possible_cpus();
157 return param_set_int(val, kp);
160 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
162 return qid * 2 * stride;
165 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
167 return (qid * 2 + 1) * stride;
170 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
172 return container_of(ctrl, struct nvme_dev, ctrl);
176 * An NVM Express queue. Each device has at least two (one for admin
177 * commands and one for I/O commands).
180 struct nvme_dev *dev;
182 struct nvme_command *sq_cmds;
183 /* only used for poll queues: */
184 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
185 volatile struct nvme_completion *cqes;
186 struct blk_mq_tags **tags;
187 dma_addr_t sq_dma_addr;
188 dma_addr_t cq_dma_addr;
199 #define NVMEQ_ENABLED 0
200 #define NVMEQ_SQ_CMB 1
201 #define NVMEQ_DELETE_ERROR 2
202 #define NVMEQ_POLLED 3
207 struct completion delete_done;
211 * The nvme_iod describes the data in an I/O.
213 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
214 * to the actual struct scatterlist.
217 struct nvme_request req;
218 struct nvme_queue *nvmeq;
221 int npages; /* In the PRP list. 0 means small pool in use */
222 int nents; /* Used in scatterlist */
223 dma_addr_t first_dma;
224 unsigned int dma_len; /* length of single DMA segment mapping */
226 struct scatterlist *sg;
230 * Check we didin't inadvertently grow the command struct
232 static inline void _nvme_check_size(void)
234 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
235 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
236 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
237 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
238 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
239 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
240 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
241 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
242 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
243 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
244 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
245 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
246 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
249 static unsigned int max_io_queues(void)
251 return num_possible_cpus() + write_queues + poll_queues;
254 static unsigned int max_queue_count(void)
256 /* IO queues + admin queue */
257 return 1 + max_io_queues();
260 static inline unsigned int nvme_dbbuf_size(u32 stride)
262 return (max_queue_count() * 8 * stride);
265 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
267 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
272 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
273 &dev->dbbuf_dbs_dma_addr,
277 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
278 &dev->dbbuf_eis_dma_addr,
280 if (!dev->dbbuf_eis) {
281 dma_free_coherent(dev->dev, mem_size,
282 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
283 dev->dbbuf_dbs = NULL;
290 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
292 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
294 if (dev->dbbuf_dbs) {
295 dma_free_coherent(dev->dev, mem_size,
296 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
297 dev->dbbuf_dbs = NULL;
299 if (dev->dbbuf_eis) {
300 dma_free_coherent(dev->dev, mem_size,
301 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
302 dev->dbbuf_eis = NULL;
306 static void nvme_dbbuf_init(struct nvme_dev *dev,
307 struct nvme_queue *nvmeq, int qid)
309 if (!dev->dbbuf_dbs || !qid)
312 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
313 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
314 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
315 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
318 static void nvme_dbbuf_set(struct nvme_dev *dev)
320 struct nvme_command c;
325 memset(&c, 0, sizeof(c));
326 c.dbbuf.opcode = nvme_admin_dbbuf;
327 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
328 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
330 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
331 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
332 /* Free memory and continue on */
333 nvme_dbbuf_dma_free(dev);
337 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
339 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
342 /* Update dbbuf and return true if an MMIO is required */
343 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
344 volatile u32 *dbbuf_ei)
350 * Ensure that the queue is written before updating
351 * the doorbell in memory
355 old_value = *dbbuf_db;
359 * Ensure that the doorbell is updated before reading the event
360 * index from memory. The controller needs to provide similar
361 * ordering to ensure the envent index is updated before reading
366 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
374 * Will slightly overestimate the number of pages needed. This is OK
375 * as it only leads to a small amount of wasted memory for the lifetime of
378 static int nvme_npages(unsigned size, struct nvme_dev *dev)
380 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
381 dev->ctrl.page_size);
382 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
386 * Calculates the number of pages needed for the SGL segments. For example a 4k
387 * page can accommodate 256 SGL descriptors.
389 static int nvme_pci_npages_sgl(unsigned int num_seg)
391 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
394 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
395 unsigned int size, unsigned int nseg, bool use_sgl)
400 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
402 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
404 return alloc_size + sizeof(struct scatterlist) * nseg;
407 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
408 unsigned int hctx_idx)
410 struct nvme_dev *dev = data;
411 struct nvme_queue *nvmeq = &dev->queues[0];
413 WARN_ON(hctx_idx != 0);
414 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
415 WARN_ON(nvmeq->tags);
417 hctx->driver_data = nvmeq;
418 nvmeq->tags = &dev->admin_tagset.tags[0];
422 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
424 struct nvme_queue *nvmeq = hctx->driver_data;
429 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
430 unsigned int hctx_idx)
432 struct nvme_dev *dev = data;
433 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
436 nvmeq->tags = &dev->tagset.tags[hctx_idx];
438 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
439 hctx->driver_data = nvmeq;
443 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
444 unsigned int hctx_idx, unsigned int numa_node)
446 struct nvme_dev *dev = set->driver_data;
447 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
448 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
449 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
454 nvme_req(req)->ctrl = &dev->ctrl;
458 static int queue_irq_offset(struct nvme_dev *dev)
460 /* if we have more than 1 vec, admin queue offsets us by 1 */
461 if (dev->num_vecs > 1)
467 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
469 struct nvme_dev *dev = set->driver_data;
472 offset = queue_irq_offset(dev);
473 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
474 struct blk_mq_queue_map *map = &set->map[i];
476 map->nr_queues = dev->io_queues[i];
477 if (!map->nr_queues) {
478 BUG_ON(i == HCTX_TYPE_DEFAULT);
483 * The poll queue(s) doesn't have an IRQ (and hence IRQ
484 * affinity), so use the regular blk-mq cpu mapping
486 map->queue_offset = qoff;
487 if (i != HCTX_TYPE_POLL)
488 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
490 blk_mq_map_queues(map);
491 qoff += map->nr_queues;
492 offset += map->nr_queues;
499 * Write sq tail if we are asked to, or if the next command would wrap.
501 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
504 u16 next_tail = nvmeq->sq_tail + 1;
506 if (next_tail == nvmeq->q_depth)
508 if (next_tail != nvmeq->last_sq_tail)
512 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
513 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
514 writel(nvmeq->sq_tail, nvmeq->q_db);
515 nvmeq->last_sq_tail = nvmeq->sq_tail;
519 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
520 * @nvmeq: The queue to use
521 * @cmd: The command to send
522 * @write_sq: whether to write to the SQ doorbell
524 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
527 spin_lock(&nvmeq->sq_lock);
528 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
529 if (++nvmeq->sq_tail == nvmeq->q_depth)
531 nvme_write_sq_db(nvmeq, write_sq);
532 spin_unlock(&nvmeq->sq_lock);
535 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
537 struct nvme_queue *nvmeq = hctx->driver_data;
539 spin_lock(&nvmeq->sq_lock);
540 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
541 nvme_write_sq_db(nvmeq, true);
542 spin_unlock(&nvmeq->sq_lock);
545 static void **nvme_pci_iod_list(struct request *req)
547 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
548 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
551 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
553 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
554 int nseg = blk_rq_nr_phys_segments(req);
555 unsigned int avg_seg_size;
560 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
562 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
564 if (!iod->nvmeq->qid)
566 if (!sgl_threshold || avg_seg_size < sgl_threshold)
571 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
573 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
574 enum dma_data_direction dma_dir = rq_data_dir(req) ?
575 DMA_TO_DEVICE : DMA_FROM_DEVICE;
576 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
577 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
581 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, dma_dir);
585 WARN_ON_ONCE(!iod->nents);
587 /* P2PDMA requests do not need to be unmapped */
588 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
589 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
592 if (iod->npages == 0)
593 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
596 for (i = 0; i < iod->npages; i++) {
597 void *addr = nvme_pci_iod_list(req)[i];
600 struct nvme_sgl_desc *sg_list = addr;
603 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
605 __le64 *prp_list = addr;
607 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
610 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
611 dma_addr = next_dma_addr;
614 mempool_free(iod->sg, dev->iod_mempool);
617 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
620 struct scatterlist *sg;
622 for_each_sg(sgl, sg, nents, i) {
623 dma_addr_t phys = sg_phys(sg);
624 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
625 "dma_address:%pad dma_length:%d\n",
626 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
631 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
632 struct request *req, struct nvme_rw_command *cmnd)
634 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
635 struct dma_pool *pool;
636 int length = blk_rq_payload_bytes(req);
637 struct scatterlist *sg = iod->sg;
638 int dma_len = sg_dma_len(sg);
639 u64 dma_addr = sg_dma_address(sg);
640 u32 page_size = dev->ctrl.page_size;
641 int offset = dma_addr & (page_size - 1);
643 void **list = nvme_pci_iod_list(req);
647 length -= (page_size - offset);
653 dma_len -= (page_size - offset);
655 dma_addr += (page_size - offset);
658 dma_addr = sg_dma_address(sg);
659 dma_len = sg_dma_len(sg);
662 if (length <= page_size) {
663 iod->first_dma = dma_addr;
667 nprps = DIV_ROUND_UP(length, page_size);
668 if (nprps <= (256 / 8)) {
669 pool = dev->prp_small_pool;
672 pool = dev->prp_page_pool;
676 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
678 iod->first_dma = dma_addr;
680 return BLK_STS_RESOURCE;
683 iod->first_dma = prp_dma;
686 if (i == page_size >> 3) {
687 __le64 *old_prp_list = prp_list;
688 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
690 return BLK_STS_RESOURCE;
691 list[iod->npages++] = prp_list;
692 prp_list[0] = old_prp_list[i - 1];
693 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
696 prp_list[i++] = cpu_to_le64(dma_addr);
697 dma_len -= page_size;
698 dma_addr += page_size;
704 if (unlikely(dma_len < 0))
707 dma_addr = sg_dma_address(sg);
708 dma_len = sg_dma_len(sg);
712 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
713 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
718 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
719 "Invalid SGL for payload:%d nents:%d\n",
720 blk_rq_payload_bytes(req), iod->nents);
721 return BLK_STS_IOERR;
724 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
725 struct scatterlist *sg)
727 sge->addr = cpu_to_le64(sg_dma_address(sg));
728 sge->length = cpu_to_le32(sg_dma_len(sg));
729 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
732 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
733 dma_addr_t dma_addr, int entries)
735 sge->addr = cpu_to_le64(dma_addr);
736 if (entries < SGES_PER_PAGE) {
737 sge->length = cpu_to_le32(entries * sizeof(*sge));
738 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
740 sge->length = cpu_to_le32(PAGE_SIZE);
741 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
745 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
746 struct request *req, struct nvme_rw_command *cmd, int entries)
748 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
749 struct dma_pool *pool;
750 struct nvme_sgl_desc *sg_list;
751 struct scatterlist *sg = iod->sg;
755 /* setting the transfer type as SGL */
756 cmd->flags = NVME_CMD_SGL_METABUF;
759 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
763 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
764 pool = dev->prp_small_pool;
767 pool = dev->prp_page_pool;
771 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
774 return BLK_STS_RESOURCE;
777 nvme_pci_iod_list(req)[0] = sg_list;
778 iod->first_dma = sgl_dma;
780 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
783 if (i == SGES_PER_PAGE) {
784 struct nvme_sgl_desc *old_sg_desc = sg_list;
785 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
787 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
789 return BLK_STS_RESOURCE;
792 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
793 sg_list[i++] = *link;
794 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
797 nvme_pci_sgl_set_data(&sg_list[i++], sg);
799 } while (--entries > 0);
804 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
805 struct request *req, struct nvme_rw_command *cmnd,
808 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
809 unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset;
811 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
812 if (dma_mapping_error(dev->dev, iod->first_dma))
813 return BLK_STS_RESOURCE;
814 iod->dma_len = bv->bv_len;
816 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
817 if (bv->bv_len > first_prp_len)
818 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
822 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
823 struct request *req, struct nvme_rw_command *cmnd,
826 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
828 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
829 if (dma_mapping_error(dev->dev, iod->first_dma))
830 return BLK_STS_RESOURCE;
831 iod->dma_len = bv->bv_len;
833 cmnd->flags = NVME_CMD_SGL_METABUF;
834 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
835 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
836 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
840 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
841 struct nvme_command *cmnd)
843 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
844 blk_status_t ret = BLK_STS_RESOURCE;
847 if (blk_rq_nr_phys_segments(req) == 1) {
848 struct bio_vec bv = req_bvec(req);
850 if (!is_pci_p2pdma_page(bv.bv_page)) {
851 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
852 return nvme_setup_prp_simple(dev, req,
855 if (iod->nvmeq->qid &&
856 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
857 return nvme_setup_sgl_simple(dev, req,
863 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
865 return BLK_STS_RESOURCE;
866 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
867 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
871 if (is_pci_p2pdma_page(sg_page(iod->sg)))
872 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
875 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
876 rq_dma_dir(req), DMA_ATTR_NO_WARN);
880 iod->use_sgl = nvme_pci_use_sgls(dev, req);
882 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
884 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
886 if (ret != BLK_STS_OK)
887 nvme_unmap_data(dev, req);
891 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
892 struct nvme_command *cmnd)
894 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
896 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
898 if (dma_mapping_error(dev->dev, iod->meta_dma))
899 return BLK_STS_IOERR;
900 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
905 * NOTE: ns is NULL when called on the admin queue.
907 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
908 const struct blk_mq_queue_data *bd)
910 struct nvme_ns *ns = hctx->queue->queuedata;
911 struct nvme_queue *nvmeq = hctx->driver_data;
912 struct nvme_dev *dev = nvmeq->dev;
913 struct request *req = bd->rq;
914 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
915 struct nvme_command cmnd;
923 * We should not need to do this, but we're still using this to
924 * ensure we can drain requests on a dying queue.
926 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
927 return BLK_STS_IOERR;
929 ret = nvme_setup_cmd(ns, req, &cmnd);
933 if (blk_rq_nr_phys_segments(req)) {
934 ret = nvme_map_data(dev, req, &cmnd);
939 if (blk_integrity_rq(req)) {
940 ret = nvme_map_metadata(dev, req, &cmnd);
945 blk_mq_start_request(req);
946 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
949 nvme_unmap_data(dev, req);
951 nvme_cleanup_cmd(req);
955 static void nvme_pci_complete_rq(struct request *req)
957 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
958 struct nvme_dev *dev = iod->nvmeq->dev;
960 nvme_cleanup_cmd(req);
961 if (blk_integrity_rq(req))
962 dma_unmap_page(dev->dev, iod->meta_dma,
963 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
964 if (blk_rq_nr_phys_segments(req))
965 nvme_unmap_data(dev, req);
966 nvme_complete_rq(req);
969 /* We read the CQE phase first to check if the rest of the entry is valid */
970 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
972 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
976 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
978 u16 head = nvmeq->cq_head;
980 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
982 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
985 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
987 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
990 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
991 dev_warn(nvmeq->dev->ctrl.device,
992 "invalid id %d completed on queue %d\n",
993 cqe->command_id, le16_to_cpu(cqe->sq_id));
998 * AEN requests are special as they don't time out and can
999 * survive any kind of queue freeze and often don't respond to
1000 * aborts. We don't even bother to allocate a struct request
1001 * for them but rather special case them here.
1003 if (unlikely(nvmeq->qid == 0 &&
1004 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
1005 nvme_complete_async_event(&nvmeq->dev->ctrl,
1006 cqe->status, &cqe->result);
1010 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
1011 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1012 nvme_end_request(req, cqe->status, cqe->result);
1015 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
1017 while (start != end) {
1018 nvme_handle_cqe(nvmeq, start);
1019 if (++start == nvmeq->q_depth)
1024 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1026 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
1028 nvmeq->cq_phase = !nvmeq->cq_phase;
1034 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1035 u16 *end, unsigned int tag)
1039 *start = nvmeq->cq_head;
1040 while (nvme_cqe_pending(nvmeq)) {
1041 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1043 nvme_update_cq_head(nvmeq);
1045 *end = nvmeq->cq_head;
1048 nvme_ring_cq_doorbell(nvmeq);
1052 static irqreturn_t nvme_irq(int irq, void *data)
1054 struct nvme_queue *nvmeq = data;
1055 irqreturn_t ret = IRQ_NONE;
1059 * The rmb/wmb pair ensures we see all updates from a previous run of
1060 * the irq handler, even if that was on another CPU.
1063 if (nvmeq->cq_head != nvmeq->last_cq_head)
1065 nvme_process_cq(nvmeq, &start, &end, -1);
1066 nvmeq->last_cq_head = nvmeq->cq_head;
1070 nvme_complete_cqes(nvmeq, start, end);
1077 static irqreturn_t nvme_irq_check(int irq, void *data)
1079 struct nvme_queue *nvmeq = data;
1080 if (nvme_cqe_pending(nvmeq))
1081 return IRQ_WAKE_THREAD;
1086 * Poll for completions any queue, including those not dedicated to polling.
1087 * Can be called from any context.
1089 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
1091 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1096 * For a poll queue we need to protect against the polling thread
1097 * using the CQ lock. For normal interrupt driven threads we have
1098 * to disable the interrupt to avoid racing with it.
1100 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) {
1101 spin_lock(&nvmeq->cq_poll_lock);
1102 found = nvme_process_cq(nvmeq, &start, &end, tag);
1103 spin_unlock(&nvmeq->cq_poll_lock);
1105 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1106 found = nvme_process_cq(nvmeq, &start, &end, tag);
1107 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1110 nvme_complete_cqes(nvmeq, start, end);
1114 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1116 struct nvme_queue *nvmeq = hctx->driver_data;
1120 if (!nvme_cqe_pending(nvmeq))
1123 spin_lock(&nvmeq->cq_poll_lock);
1124 found = nvme_process_cq(nvmeq, &start, &end, -1);
1125 spin_unlock(&nvmeq->cq_poll_lock);
1127 nvme_complete_cqes(nvmeq, start, end);
1131 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1133 struct nvme_dev *dev = to_nvme_dev(ctrl);
1134 struct nvme_queue *nvmeq = &dev->queues[0];
1135 struct nvme_command c;
1137 memset(&c, 0, sizeof(c));
1138 c.common.opcode = nvme_admin_async_event;
1139 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1140 nvme_submit_cmd(nvmeq, &c, true);
1143 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1145 struct nvme_command c;
1147 memset(&c, 0, sizeof(c));
1148 c.delete_queue.opcode = opcode;
1149 c.delete_queue.qid = cpu_to_le16(id);
1151 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1154 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1155 struct nvme_queue *nvmeq, s16 vector)
1157 struct nvme_command c;
1158 int flags = NVME_QUEUE_PHYS_CONTIG;
1160 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1161 flags |= NVME_CQ_IRQ_ENABLED;
1164 * Note: we (ab)use the fact that the prp fields survive if no data
1165 * is attached to the request.
1167 memset(&c, 0, sizeof(c));
1168 c.create_cq.opcode = nvme_admin_create_cq;
1169 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1170 c.create_cq.cqid = cpu_to_le16(qid);
1171 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1172 c.create_cq.cq_flags = cpu_to_le16(flags);
1173 c.create_cq.irq_vector = cpu_to_le16(vector);
1175 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1178 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1179 struct nvme_queue *nvmeq)
1181 struct nvme_ctrl *ctrl = &dev->ctrl;
1182 struct nvme_command c;
1183 int flags = NVME_QUEUE_PHYS_CONTIG;
1186 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1187 * set. Since URGENT priority is zeroes, it makes all queues
1190 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1191 flags |= NVME_SQ_PRIO_MEDIUM;
1194 * Note: we (ab)use the fact that the prp fields survive if no data
1195 * is attached to the request.
1197 memset(&c, 0, sizeof(c));
1198 c.create_sq.opcode = nvme_admin_create_sq;
1199 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1200 c.create_sq.sqid = cpu_to_le16(qid);
1201 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1202 c.create_sq.sq_flags = cpu_to_le16(flags);
1203 c.create_sq.cqid = cpu_to_le16(qid);
1205 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1208 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1210 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1213 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1215 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1218 static void abort_endio(struct request *req, blk_status_t error)
1220 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1221 struct nvme_queue *nvmeq = iod->nvmeq;
1223 dev_warn(nvmeq->dev->ctrl.device,
1224 "Abort status: 0x%x", nvme_req(req)->status);
1225 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1226 blk_mq_free_request(req);
1229 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1232 /* If true, indicates loss of adapter communication, possibly by a
1233 * NVMe Subsystem reset.
1235 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1237 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1238 switch (dev->ctrl.state) {
1239 case NVME_CTRL_RESETTING:
1240 case NVME_CTRL_CONNECTING:
1246 /* We shouldn't reset unless the controller is on fatal error state
1247 * _or_ if we lost the communication with it.
1249 if (!(csts & NVME_CSTS_CFS) && !nssro)
1255 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1257 /* Read a config register to help see what died. */
1261 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1263 if (result == PCIBIOS_SUCCESSFUL)
1264 dev_warn(dev->ctrl.device,
1265 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1268 dev_warn(dev->ctrl.device,
1269 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1273 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1275 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1276 struct nvme_queue *nvmeq = iod->nvmeq;
1277 struct nvme_dev *dev = nvmeq->dev;
1278 struct request *abort_req;
1279 struct nvme_command cmd;
1280 bool shutdown = false;
1281 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1283 /* If PCI error recovery process is happening, we cannot reset or
1284 * the recovery mechanism will surely fail.
1287 if (pci_channel_offline(to_pci_dev(dev->dev)))
1288 return BLK_EH_RESET_TIMER;
1291 * Reset immediately if the controller is failed
1293 if (nvme_should_reset(dev, csts)) {
1294 nvme_warn_reset(dev, csts);
1295 nvme_dev_disable(dev, false);
1296 nvme_reset_ctrl(&dev->ctrl);
1301 * Did we miss an interrupt?
1303 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
1304 dev_warn(dev->ctrl.device,
1305 "I/O %d QID %d timeout, completion polled\n",
1306 req->tag, nvmeq->qid);
1311 * Shutdown immediately if controller times out while starting. The
1312 * reset work will see the pci device disabled when it gets the forced
1313 * cancellation error. All outstanding requests are completed on
1314 * shutdown, so we return BLK_EH_DONE.
1316 switch (dev->ctrl.state) {
1317 case NVME_CTRL_DELETING:
1319 case NVME_CTRL_CONNECTING:
1320 case NVME_CTRL_RESETTING:
1321 dev_warn_ratelimited(dev->ctrl.device,
1322 "I/O %d QID %d timeout, disable controller\n",
1323 req->tag, nvmeq->qid);
1324 nvme_dev_disable(dev, shutdown);
1325 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1332 * Shutdown the controller immediately and schedule a reset if the
1333 * command was already aborted once before and still hasn't been
1334 * returned to the driver, or if this is the admin queue.
1336 if (!nvmeq->qid || iod->aborted) {
1337 dev_warn(dev->ctrl.device,
1338 "I/O %d QID %d timeout, reset controller\n",
1339 req->tag, nvmeq->qid);
1340 nvme_dev_disable(dev, false);
1341 nvme_reset_ctrl(&dev->ctrl);
1343 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1347 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1348 atomic_inc(&dev->ctrl.abort_limit);
1349 return BLK_EH_RESET_TIMER;
1353 memset(&cmd, 0, sizeof(cmd));
1354 cmd.abort.opcode = nvme_admin_abort_cmd;
1355 cmd.abort.cid = req->tag;
1356 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1358 dev_warn(nvmeq->dev->ctrl.device,
1359 "I/O %d QID %d timeout, aborting\n",
1360 req->tag, nvmeq->qid);
1362 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1363 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1364 if (IS_ERR(abort_req)) {
1365 atomic_inc(&dev->ctrl.abort_limit);
1366 return BLK_EH_RESET_TIMER;
1369 abort_req->timeout = ADMIN_TIMEOUT;
1370 abort_req->end_io_data = NULL;
1371 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1374 * The aborted req will be completed on receiving the abort req.
1375 * We enable the timer again. If hit twice, it'll cause a device reset,
1376 * as the device then is in a faulty state.
1378 return BLK_EH_RESET_TIMER;
1381 static void nvme_free_queue(struct nvme_queue *nvmeq)
1383 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth),
1384 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1385 if (!nvmeq->sq_cmds)
1388 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1389 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1390 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1392 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth),
1393 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1397 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1401 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1402 dev->ctrl.queue_count--;
1403 nvme_free_queue(&dev->queues[i]);
1408 * nvme_suspend_queue - put queue into suspended state
1409 * @nvmeq: queue to suspend
1411 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1413 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1416 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1419 nvmeq->dev->online_queues--;
1420 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1421 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1422 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1423 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1427 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1431 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1432 nvme_suspend_queue(&dev->queues[i]);
1435 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1437 struct nvme_queue *nvmeq = &dev->queues[0];
1440 nvme_shutdown_ctrl(&dev->ctrl);
1442 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1444 nvme_poll_irqdisable(nvmeq, -1);
1447 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1450 int q_depth = dev->q_depth;
1451 unsigned q_size_aligned = roundup(q_depth * entry_size,
1452 dev->ctrl.page_size);
1454 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1455 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1456 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1457 q_depth = div_u64(mem_per_q, entry_size);
1460 * Ensure the reduced q_depth is above some threshold where it
1461 * would be better to map queues in system memory with the
1471 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1474 struct pci_dev *pdev = to_pci_dev(dev->dev);
1476 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1477 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1478 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1480 if (nvmeq->sq_dma_addr) {
1481 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1486 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1487 &nvmeq->sq_dma_addr, GFP_KERNEL);
1488 if (!nvmeq->sq_cmds)
1493 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1495 struct nvme_queue *nvmeq = &dev->queues[qid];
1497 if (dev->ctrl.queue_count > qid)
1500 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
1501 &nvmeq->cq_dma_addr, GFP_KERNEL);
1505 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1509 spin_lock_init(&nvmeq->sq_lock);
1510 spin_lock_init(&nvmeq->cq_poll_lock);
1512 nvmeq->cq_phase = 1;
1513 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1514 nvmeq->q_depth = depth;
1516 dev->ctrl.queue_count++;
1521 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1522 nvmeq->cq_dma_addr);
1527 static int queue_request_irq(struct nvme_queue *nvmeq)
1529 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1530 int nr = nvmeq->dev->ctrl.instance;
1532 if (use_threaded_interrupts) {
1533 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1534 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1536 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1537 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1541 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1543 struct nvme_dev *dev = nvmeq->dev;
1546 nvmeq->last_sq_tail = 0;
1548 nvmeq->cq_phase = 1;
1549 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1550 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1551 nvme_dbbuf_init(dev, nvmeq, qid);
1552 dev->online_queues++;
1553 wmb(); /* ensure the first interrupt sees the initialization */
1556 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1558 struct nvme_dev *dev = nvmeq->dev;
1562 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1565 * A queue's vector matches the queue identifier unless the controller
1566 * has only one vector available.
1569 vector = dev->num_vecs == 1 ? 0 : qid;
1571 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1573 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1577 result = adapter_alloc_sq(dev, qid, nvmeq);
1583 nvmeq->cq_vector = vector;
1584 nvme_init_queue(nvmeq, qid);
1587 nvmeq->cq_vector = vector;
1588 result = queue_request_irq(nvmeq);
1593 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1597 dev->online_queues--;
1598 adapter_delete_sq(dev, qid);
1600 adapter_delete_cq(dev, qid);
1604 static const struct blk_mq_ops nvme_mq_admin_ops = {
1605 .queue_rq = nvme_queue_rq,
1606 .complete = nvme_pci_complete_rq,
1607 .init_hctx = nvme_admin_init_hctx,
1608 .exit_hctx = nvme_admin_exit_hctx,
1609 .init_request = nvme_init_request,
1610 .timeout = nvme_timeout,
1613 static const struct blk_mq_ops nvme_mq_ops = {
1614 .queue_rq = nvme_queue_rq,
1615 .complete = nvme_pci_complete_rq,
1616 .commit_rqs = nvme_commit_rqs,
1617 .init_hctx = nvme_init_hctx,
1618 .init_request = nvme_init_request,
1619 .map_queues = nvme_pci_map_queues,
1620 .timeout = nvme_timeout,
1624 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1626 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1628 * If the controller was reset during removal, it's possible
1629 * user requests may be waiting on a stopped queue. Start the
1630 * queue to flush these to completion.
1632 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1633 blk_cleanup_queue(dev->ctrl.admin_q);
1634 blk_mq_free_tag_set(&dev->admin_tagset);
1638 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1640 if (!dev->ctrl.admin_q) {
1641 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1642 dev->admin_tagset.nr_hw_queues = 1;
1644 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1645 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1646 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1647 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1648 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1649 dev->admin_tagset.driver_data = dev;
1651 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1653 dev->ctrl.admin_tagset = &dev->admin_tagset;
1655 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1656 if (IS_ERR(dev->ctrl.admin_q)) {
1657 blk_mq_free_tag_set(&dev->admin_tagset);
1660 if (!blk_get_queue(dev->ctrl.admin_q)) {
1661 nvme_dev_remove_admin(dev);
1662 dev->ctrl.admin_q = NULL;
1666 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1671 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1673 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1676 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1678 struct pci_dev *pdev = to_pci_dev(dev->dev);
1680 if (size <= dev->bar_mapped_size)
1682 if (size > pci_resource_len(pdev, 0))
1686 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1688 dev->bar_mapped_size = 0;
1691 dev->bar_mapped_size = size;
1692 dev->dbs = dev->bar + NVME_REG_DBS;
1697 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1701 struct nvme_queue *nvmeq;
1703 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1707 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1708 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1710 if (dev->subsystem &&
1711 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1712 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1714 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1718 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1722 nvmeq = &dev->queues[0];
1723 aqa = nvmeq->q_depth - 1;
1726 writel(aqa, dev->bar + NVME_REG_AQA);
1727 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1728 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1730 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1734 nvmeq->cq_vector = 0;
1735 nvme_init_queue(nvmeq, 0);
1736 result = queue_request_irq(nvmeq);
1738 dev->online_queues--;
1742 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1746 static int nvme_create_io_queues(struct nvme_dev *dev)
1748 unsigned i, max, rw_queues;
1751 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1752 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1758 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1759 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1760 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1761 dev->io_queues[HCTX_TYPE_READ];
1766 for (i = dev->online_queues; i <= max; i++) {
1767 bool polled = i > rw_queues;
1769 ret = nvme_create_queue(&dev->queues[i], i, polled);
1775 * Ignore failing Create SQ/CQ commands, we can continue with less
1776 * than the desired amount of queues, and even a controller without
1777 * I/O queues can still be used to issue admin commands. This might
1778 * be useful to upgrade a buggy firmware for example.
1780 return ret >= 0 ? 0 : ret;
1783 static ssize_t nvme_cmb_show(struct device *dev,
1784 struct device_attribute *attr,
1787 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1789 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1790 ndev->cmbloc, ndev->cmbsz);
1792 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1794 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1796 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1798 return 1ULL << (12 + 4 * szu);
1801 static u32 nvme_cmb_size(struct nvme_dev *dev)
1803 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1806 static void nvme_map_cmb(struct nvme_dev *dev)
1809 resource_size_t bar_size;
1810 struct pci_dev *pdev = to_pci_dev(dev->dev);
1816 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1819 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1821 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1822 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1823 bar = NVME_CMB_BIR(dev->cmbloc);
1824 bar_size = pci_resource_len(pdev, bar);
1826 if (offset > bar_size)
1830 * Controllers may support a CMB size larger than their BAR,
1831 * for example, due to being behind a bridge. Reduce the CMB to
1832 * the reported size of the BAR
1834 if (size > bar_size - offset)
1835 size = bar_size - offset;
1837 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1838 dev_warn(dev->ctrl.device,
1839 "failed to register the CMB\n");
1843 dev->cmb_size = size;
1844 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1846 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1847 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1848 pci_p2pmem_publish(pdev, true);
1850 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1851 &dev_attr_cmb.attr, NULL))
1852 dev_warn(dev->ctrl.device,
1853 "failed to add sysfs attribute for CMB\n");
1856 static inline void nvme_release_cmb(struct nvme_dev *dev)
1858 if (dev->cmb_size) {
1859 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1860 &dev_attr_cmb.attr, NULL);
1865 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1867 u64 dma_addr = dev->host_mem_descs_dma;
1868 struct nvme_command c;
1871 memset(&c, 0, sizeof(c));
1872 c.features.opcode = nvme_admin_set_features;
1873 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1874 c.features.dword11 = cpu_to_le32(bits);
1875 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1876 ilog2(dev->ctrl.page_size));
1877 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1878 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1879 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1881 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1883 dev_warn(dev->ctrl.device,
1884 "failed to set host mem (err %d, flags %#x).\n",
1890 static void nvme_free_host_mem(struct nvme_dev *dev)
1894 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1895 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1896 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1898 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1899 le64_to_cpu(desc->addr),
1900 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1903 kfree(dev->host_mem_desc_bufs);
1904 dev->host_mem_desc_bufs = NULL;
1905 dma_free_coherent(dev->dev,
1906 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1907 dev->host_mem_descs, dev->host_mem_descs_dma);
1908 dev->host_mem_descs = NULL;
1909 dev->nr_host_mem_descs = 0;
1912 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1915 struct nvme_host_mem_buf_desc *descs;
1916 u32 max_entries, len;
1917 dma_addr_t descs_dma;
1922 tmp = (preferred + chunk_size - 1);
1923 do_div(tmp, chunk_size);
1926 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1927 max_entries = dev->ctrl.hmmaxd;
1929 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1930 &descs_dma, GFP_KERNEL);
1934 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1936 goto out_free_descs;
1938 for (size = 0; size < preferred && i < max_entries; size += len) {
1939 dma_addr_t dma_addr;
1941 len = min_t(u64, chunk_size, preferred - size);
1942 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1943 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1947 descs[i].addr = cpu_to_le64(dma_addr);
1948 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1955 dev->nr_host_mem_descs = i;
1956 dev->host_mem_size = size;
1957 dev->host_mem_descs = descs;
1958 dev->host_mem_descs_dma = descs_dma;
1959 dev->host_mem_desc_bufs = bufs;
1964 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1966 dma_free_attrs(dev->dev, size, bufs[i],
1967 le64_to_cpu(descs[i].addr),
1968 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1973 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1976 dev->host_mem_descs = NULL;
1980 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1984 /* start big and work our way down */
1985 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1986 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1988 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1989 if (!min || dev->host_mem_size >= min)
1991 nvme_free_host_mem(dev);
1998 static int nvme_setup_host_mem(struct nvme_dev *dev)
2000 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2001 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2002 u64 min = (u64)dev->ctrl.hmmin * 4096;
2003 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2006 preferred = min(preferred, max);
2008 dev_warn(dev->ctrl.device,
2009 "min host memory (%lld MiB) above limit (%d MiB).\n",
2010 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2011 nvme_free_host_mem(dev);
2016 * If we already have a buffer allocated check if we can reuse it.
2018 if (dev->host_mem_descs) {
2019 if (dev->host_mem_size >= min)
2020 enable_bits |= NVME_HOST_MEM_RETURN;
2022 nvme_free_host_mem(dev);
2025 if (!dev->host_mem_descs) {
2026 if (nvme_alloc_host_mem(dev, min, preferred)) {
2027 dev_warn(dev->ctrl.device,
2028 "failed to allocate host memory buffer.\n");
2029 return 0; /* controller must work without HMB */
2032 dev_info(dev->ctrl.device,
2033 "allocated %lld MiB host memory buffer.\n",
2034 dev->host_mem_size >> ilog2(SZ_1M));
2037 ret = nvme_set_host_mem(dev, enable_bits);
2039 nvme_free_host_mem(dev);
2044 * nirqs is the number of interrupts available for write and read
2045 * queues. The core already reserved an interrupt for the admin queue.
2047 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2049 struct nvme_dev *dev = affd->priv;
2050 unsigned int nr_read_queues;
2053 * If there is no interupt available for queues, ensure that
2054 * the default queue is set to 1. The affinity set size is
2055 * also set to one, but the irq core ignores it for this case.
2057 * If only one interrupt is available or 'write_queue' == 0, combine
2058 * write and read queues.
2060 * If 'write_queues' > 0, ensure it leaves room for at least one read
2066 } else if (nrirqs == 1 || !write_queues) {
2068 } else if (write_queues >= nrirqs) {
2071 nr_read_queues = nrirqs - write_queues;
2074 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2075 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2076 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2077 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2078 affd->nr_sets = nr_read_queues ? 2 : 1;
2081 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2083 struct pci_dev *pdev = to_pci_dev(dev->dev);
2084 struct irq_affinity affd = {
2086 .calc_sets = nvme_calc_irq_sets,
2089 unsigned int irq_queues, this_p_queues;
2092 * Poll queues don't need interrupts, but we need at least one IO
2093 * queue left over for non-polled IO.
2095 this_p_queues = poll_queues;
2096 if (this_p_queues >= nr_io_queues) {
2097 this_p_queues = nr_io_queues - 1;
2100 irq_queues = nr_io_queues - this_p_queues + 1;
2102 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2104 /* Initialize for the single interrupt case */
2105 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2106 dev->io_queues[HCTX_TYPE_READ] = 0;
2108 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2109 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2112 static void nvme_disable_io_queues(struct nvme_dev *dev)
2114 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2115 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2118 static int nvme_setup_io_queues(struct nvme_dev *dev)
2120 struct nvme_queue *adminq = &dev->queues[0];
2121 struct pci_dev *pdev = to_pci_dev(dev->dev);
2122 int result, nr_io_queues;
2125 nr_io_queues = max_io_queues();
2126 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2130 if (nr_io_queues == 0)
2133 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2135 if (dev->cmb_use_sqes) {
2136 result = nvme_cmb_qdepth(dev, nr_io_queues,
2137 sizeof(struct nvme_command));
2139 dev->q_depth = result;
2141 dev->cmb_use_sqes = false;
2145 size = db_bar_size(dev, nr_io_queues);
2146 result = nvme_remap_bar(dev, size);
2149 if (!--nr_io_queues)
2152 adminq->q_db = dev->dbs;
2155 /* Deregister the admin queue's interrupt */
2156 pci_free_irq(pdev, 0, adminq);
2159 * If we enable msix early due to not intx, disable it again before
2160 * setting up the full range we need.
2162 pci_free_irq_vectors(pdev);
2164 result = nvme_setup_irqs(dev, nr_io_queues);
2168 dev->num_vecs = result;
2169 result = max(result - 1, 1);
2170 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2173 * Should investigate if there's a performance win from allocating
2174 * more queues than interrupt vectors; it might allow the submission
2175 * path to scale better, even if the receive path is limited by the
2176 * number of interrupts.
2178 result = queue_request_irq(adminq);
2181 set_bit(NVMEQ_ENABLED, &adminq->flags);
2183 result = nvme_create_io_queues(dev);
2184 if (result || dev->online_queues < 2)
2187 if (dev->online_queues - 1 < dev->max_qid) {
2188 nr_io_queues = dev->online_queues - 1;
2189 nvme_disable_io_queues(dev);
2190 nvme_suspend_io_queues(dev);
2193 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2194 dev->io_queues[HCTX_TYPE_DEFAULT],
2195 dev->io_queues[HCTX_TYPE_READ],
2196 dev->io_queues[HCTX_TYPE_POLL]);
2200 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2202 struct nvme_queue *nvmeq = req->end_io_data;
2204 blk_mq_free_request(req);
2205 complete(&nvmeq->delete_done);
2208 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2210 struct nvme_queue *nvmeq = req->end_io_data;
2213 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2215 nvme_del_queue_end(req, error);
2218 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2220 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2221 struct request *req;
2222 struct nvme_command cmd;
2224 memset(&cmd, 0, sizeof(cmd));
2225 cmd.delete_queue.opcode = opcode;
2226 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2228 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2230 return PTR_ERR(req);
2232 req->timeout = ADMIN_TIMEOUT;
2233 req->end_io_data = nvmeq;
2235 init_completion(&nvmeq->delete_done);
2236 blk_execute_rq_nowait(q, NULL, req, false,
2237 opcode == nvme_admin_delete_cq ?
2238 nvme_del_cq_end : nvme_del_queue_end);
2242 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2244 int nr_queues = dev->online_queues - 1, sent = 0;
2245 unsigned long timeout;
2248 timeout = ADMIN_TIMEOUT;
2249 while (nr_queues > 0) {
2250 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2256 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2258 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2263 /* handle any remaining CQEs */
2264 if (opcode == nvme_admin_delete_cq &&
2265 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2266 nvme_poll_irqdisable(nvmeq, -1);
2276 * return error value only when tagset allocation failed
2278 static int nvme_dev_add(struct nvme_dev *dev)
2282 if (!dev->ctrl.tagset) {
2283 dev->tagset.ops = &nvme_mq_ops;
2284 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2285 dev->tagset.nr_maps = 2; /* default + read */
2286 if (dev->io_queues[HCTX_TYPE_POLL])
2287 dev->tagset.nr_maps++;
2288 dev->tagset.timeout = NVME_IO_TIMEOUT;
2289 dev->tagset.numa_node = dev_to_node(dev->dev);
2290 dev->tagset.queue_depth =
2291 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2292 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2293 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2294 dev->tagset.driver_data = dev;
2296 ret = blk_mq_alloc_tag_set(&dev->tagset);
2298 dev_warn(dev->ctrl.device,
2299 "IO queues tagset allocation failed %d\n", ret);
2302 dev->ctrl.tagset = &dev->tagset;
2304 nvme_dbbuf_set(dev);
2306 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2308 /* Free previously allocated queues that are no longer usable */
2309 nvme_free_queues(dev, dev->online_queues);
2315 static int nvme_pci_enable(struct nvme_dev *dev)
2317 int result = -ENOMEM;
2318 struct pci_dev *pdev = to_pci_dev(dev->dev);
2320 if (pci_enable_device_mem(pdev))
2323 pci_set_master(pdev);
2325 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2326 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2329 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2335 * Some devices and/or platforms don't advertise or work with INTx
2336 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2337 * adjust this later.
2339 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2343 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2345 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2347 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2348 dev->dbs = dev->bar + 4096;
2351 * Temporary fix for the Apple controller found in the MacBook8,1 and
2352 * some MacBook7,1 to avoid controller resets and data loss.
2354 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2356 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2357 "set queue depth=%u to work around controller resets\n",
2359 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2360 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2361 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2363 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2364 "set queue depth=%u\n", dev->q_depth);
2369 pci_enable_pcie_error_reporting(pdev);
2370 pci_save_state(pdev);
2374 pci_disable_device(pdev);
2378 static void nvme_dev_unmap(struct nvme_dev *dev)
2382 pci_release_mem_regions(to_pci_dev(dev->dev));
2385 static void nvme_pci_disable(struct nvme_dev *dev)
2387 struct pci_dev *pdev = to_pci_dev(dev->dev);
2389 pci_free_irq_vectors(pdev);
2391 if (pci_is_enabled(pdev)) {
2392 pci_disable_pcie_error_reporting(pdev);
2393 pci_disable_device(pdev);
2397 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2400 struct pci_dev *pdev = to_pci_dev(dev->dev);
2402 mutex_lock(&dev->shutdown_lock);
2403 if (pci_is_enabled(pdev)) {
2404 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2406 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2407 dev->ctrl.state == NVME_CTRL_RESETTING)
2408 nvme_start_freeze(&dev->ctrl);
2409 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2410 pdev->error_state != pci_channel_io_normal);
2414 * Give the controller a chance to complete all entered requests if
2415 * doing a safe shutdown.
2419 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2422 nvme_stop_queues(&dev->ctrl);
2424 if (!dead && dev->ctrl.queue_count > 0) {
2425 nvme_disable_io_queues(dev);
2426 nvme_disable_admin_queue(dev, shutdown);
2428 nvme_suspend_io_queues(dev);
2429 nvme_suspend_queue(&dev->queues[0]);
2430 nvme_pci_disable(dev);
2432 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2433 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2436 * The driver will not be starting up queues again if shutting down so
2437 * must flush all entered requests to their failed completion to avoid
2438 * deadlocking blk-mq hot-cpu notifier.
2441 nvme_start_queues(&dev->ctrl);
2442 mutex_unlock(&dev->shutdown_lock);
2445 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2447 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2448 PAGE_SIZE, PAGE_SIZE, 0);
2449 if (!dev->prp_page_pool)
2452 /* Optimisation for I/Os between 4k and 128k */
2453 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2455 if (!dev->prp_small_pool) {
2456 dma_pool_destroy(dev->prp_page_pool);
2462 static void nvme_release_prp_pools(struct nvme_dev *dev)
2464 dma_pool_destroy(dev->prp_page_pool);
2465 dma_pool_destroy(dev->prp_small_pool);
2468 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2470 struct nvme_dev *dev = to_nvme_dev(ctrl);
2472 nvme_dbbuf_dma_free(dev);
2473 put_device(dev->dev);
2474 if (dev->tagset.tags)
2475 blk_mq_free_tag_set(&dev->tagset);
2476 if (dev->ctrl.admin_q)
2477 blk_put_queue(dev->ctrl.admin_q);
2479 free_opal_dev(dev->ctrl.opal_dev);
2480 mempool_destroy(dev->iod_mempool);
2484 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2486 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2488 nvme_get_ctrl(&dev->ctrl);
2489 nvme_dev_disable(dev, false);
2490 nvme_kill_queues(&dev->ctrl);
2491 if (!queue_work(nvme_wq, &dev->remove_work))
2492 nvme_put_ctrl(&dev->ctrl);
2495 static void nvme_reset_work(struct work_struct *work)
2497 struct nvme_dev *dev =
2498 container_of(work, struct nvme_dev, ctrl.reset_work);
2499 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2500 int result = -ENODEV;
2501 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2503 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2507 * If we're called to reset a live controller first shut it down before
2510 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2511 nvme_dev_disable(dev, false);
2513 mutex_lock(&dev->shutdown_lock);
2514 result = nvme_pci_enable(dev);
2518 result = nvme_pci_configure_admin_queue(dev);
2522 result = nvme_alloc_admin_tags(dev);
2527 * Limit the max command size to prevent iod->sg allocations going
2528 * over a single page.
2530 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2531 dev->ctrl.max_segments = NVME_MAX_SEGS;
2532 mutex_unlock(&dev->shutdown_lock);
2535 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2536 * initializing procedure here.
2538 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2539 dev_warn(dev->ctrl.device,
2540 "failed to mark controller CONNECTING\n");
2544 result = nvme_init_identify(&dev->ctrl);
2548 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2549 if (!dev->ctrl.opal_dev)
2550 dev->ctrl.opal_dev =
2551 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2552 else if (was_suspend)
2553 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2555 free_opal_dev(dev->ctrl.opal_dev);
2556 dev->ctrl.opal_dev = NULL;
2559 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2560 result = nvme_dbbuf_dma_alloc(dev);
2563 "unable to allocate dma for dbbuf\n");
2566 if (dev->ctrl.hmpre) {
2567 result = nvme_setup_host_mem(dev);
2572 result = nvme_setup_io_queues(dev);
2577 * Keep the controller around but remove all namespaces if we don't have
2578 * any working I/O queue.
2580 if (dev->online_queues < 2) {
2581 dev_warn(dev->ctrl.device, "IO queues not created\n");
2582 nvme_kill_queues(&dev->ctrl);
2583 nvme_remove_namespaces(&dev->ctrl);
2584 new_state = NVME_CTRL_ADMIN_ONLY;
2586 nvme_start_queues(&dev->ctrl);
2587 nvme_wait_freeze(&dev->ctrl);
2588 /* hit this only when allocate tagset fails */
2589 if (nvme_dev_add(dev))
2590 new_state = NVME_CTRL_ADMIN_ONLY;
2591 nvme_unfreeze(&dev->ctrl);
2595 * If only admin queue live, keep it to do further investigation or
2598 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2599 dev_warn(dev->ctrl.device,
2600 "failed to mark controller state %d\n", new_state);
2604 nvme_start_ctrl(&dev->ctrl);
2608 mutex_unlock(&dev->shutdown_lock);
2610 nvme_remove_dead_ctrl(dev, result);
2613 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2615 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2616 struct pci_dev *pdev = to_pci_dev(dev->dev);
2618 if (pci_get_drvdata(pdev))
2619 device_release_driver(&pdev->dev);
2620 nvme_put_ctrl(&dev->ctrl);
2623 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2625 *val = readl(to_nvme_dev(ctrl)->bar + off);
2629 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2631 writel(val, to_nvme_dev(ctrl)->bar + off);
2635 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2637 *val = readq(to_nvme_dev(ctrl)->bar + off);
2641 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2643 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2645 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2648 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2650 .module = THIS_MODULE,
2651 .flags = NVME_F_METADATA_SUPPORTED |
2653 .reg_read32 = nvme_pci_reg_read32,
2654 .reg_write32 = nvme_pci_reg_write32,
2655 .reg_read64 = nvme_pci_reg_read64,
2656 .free_ctrl = nvme_pci_free_ctrl,
2657 .submit_async_event = nvme_pci_submit_async_event,
2658 .get_address = nvme_pci_get_address,
2661 static int nvme_dev_map(struct nvme_dev *dev)
2663 struct pci_dev *pdev = to_pci_dev(dev->dev);
2665 if (pci_request_mem_regions(pdev, "nvme"))
2668 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2673 pci_release_mem_regions(pdev);
2677 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2679 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2681 * Several Samsung devices seem to drop off the PCIe bus
2682 * randomly when APST is on and uses the deepest sleep state.
2683 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2684 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2685 * 950 PRO 256GB", but it seems to be restricted to two Dell
2688 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2689 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2690 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2691 return NVME_QUIRK_NO_DEEPEST_PS;
2692 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2694 * Samsung SSD 960 EVO drops off the PCIe bus after system
2695 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2696 * within few minutes after bootup on a Coffee Lake board -
2699 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2700 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2701 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2702 return NVME_QUIRK_NO_APST;
2708 static void nvme_async_probe(void *data, async_cookie_t cookie)
2710 struct nvme_dev *dev = data;
2712 nvme_reset_ctrl_sync(&dev->ctrl);
2713 flush_work(&dev->ctrl.scan_work);
2714 nvme_put_ctrl(&dev->ctrl);
2717 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2719 int node, result = -ENOMEM;
2720 struct nvme_dev *dev;
2721 unsigned long quirks = id->driver_data;
2724 node = dev_to_node(&pdev->dev);
2725 if (node == NUMA_NO_NODE)
2726 set_dev_node(&pdev->dev, first_memory_node);
2728 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2732 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2737 dev->dev = get_device(&pdev->dev);
2738 pci_set_drvdata(pdev, dev);
2740 result = nvme_dev_map(dev);
2744 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2745 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2746 mutex_init(&dev->shutdown_lock);
2748 result = nvme_setup_prp_pools(dev);
2752 quirks |= check_vendor_combination_bug(pdev);
2755 * Double check that our mempool alloc size will cover the biggest
2756 * command we support.
2758 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2759 NVME_MAX_SEGS, true);
2760 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2762 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2764 (void *) alloc_size,
2766 if (!dev->iod_mempool) {
2771 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2774 goto release_mempool;
2776 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2778 nvme_get_ctrl(&dev->ctrl);
2779 async_schedule(nvme_async_probe, dev);
2784 mempool_destroy(dev->iod_mempool);
2786 nvme_release_prp_pools(dev);
2788 nvme_dev_unmap(dev);
2790 put_device(dev->dev);
2797 static void nvme_reset_prepare(struct pci_dev *pdev)
2799 struct nvme_dev *dev = pci_get_drvdata(pdev);
2800 nvme_dev_disable(dev, false);
2803 static void nvme_reset_done(struct pci_dev *pdev)
2805 struct nvme_dev *dev = pci_get_drvdata(pdev);
2806 nvme_reset_ctrl_sync(&dev->ctrl);
2809 static void nvme_shutdown(struct pci_dev *pdev)
2811 struct nvme_dev *dev = pci_get_drvdata(pdev);
2812 nvme_dev_disable(dev, true);
2816 * The driver's remove may be called on a device in a partially initialized
2817 * state. This function must not have any dependencies on the device state in
2820 static void nvme_remove(struct pci_dev *pdev)
2822 struct nvme_dev *dev = pci_get_drvdata(pdev);
2824 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2825 pci_set_drvdata(pdev, NULL);
2827 if (!pci_device_is_present(pdev)) {
2828 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2829 nvme_dev_disable(dev, true);
2830 nvme_dev_remove_admin(dev);
2833 flush_work(&dev->ctrl.reset_work);
2834 nvme_stop_ctrl(&dev->ctrl);
2835 nvme_remove_namespaces(&dev->ctrl);
2836 nvme_dev_disable(dev, true);
2837 nvme_release_cmb(dev);
2838 nvme_free_host_mem(dev);
2839 nvme_dev_remove_admin(dev);
2840 nvme_free_queues(dev, 0);
2841 nvme_uninit_ctrl(&dev->ctrl);
2842 nvme_release_prp_pools(dev);
2843 nvme_dev_unmap(dev);
2844 nvme_put_ctrl(&dev->ctrl);
2847 #ifdef CONFIG_PM_SLEEP
2848 static int nvme_suspend(struct device *dev)
2850 struct pci_dev *pdev = to_pci_dev(dev);
2851 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2853 nvme_dev_disable(ndev, true);
2857 static int nvme_resume(struct device *dev)
2859 struct pci_dev *pdev = to_pci_dev(dev);
2860 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2862 nvme_reset_ctrl(&ndev->ctrl);
2867 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2869 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2870 pci_channel_state_t state)
2872 struct nvme_dev *dev = pci_get_drvdata(pdev);
2875 * A frozen channel requires a reset. When detected, this method will
2876 * shutdown the controller to quiesce. The controller will be restarted
2877 * after the slot reset through driver's slot_reset callback.
2880 case pci_channel_io_normal:
2881 return PCI_ERS_RESULT_CAN_RECOVER;
2882 case pci_channel_io_frozen:
2883 dev_warn(dev->ctrl.device,
2884 "frozen state error detected, reset controller\n");
2885 nvme_dev_disable(dev, false);
2886 return PCI_ERS_RESULT_NEED_RESET;
2887 case pci_channel_io_perm_failure:
2888 dev_warn(dev->ctrl.device,
2889 "failure state error detected, request disconnect\n");
2890 return PCI_ERS_RESULT_DISCONNECT;
2892 return PCI_ERS_RESULT_NEED_RESET;
2895 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2897 struct nvme_dev *dev = pci_get_drvdata(pdev);
2899 dev_info(dev->ctrl.device, "restart after slot reset\n");
2900 pci_restore_state(pdev);
2901 nvme_reset_ctrl(&dev->ctrl);
2902 return PCI_ERS_RESULT_RECOVERED;
2905 static void nvme_error_resume(struct pci_dev *pdev)
2907 struct nvme_dev *dev = pci_get_drvdata(pdev);
2909 flush_work(&dev->ctrl.reset_work);
2912 static const struct pci_error_handlers nvme_err_handler = {
2913 .error_detected = nvme_error_detected,
2914 .slot_reset = nvme_slot_reset,
2915 .resume = nvme_error_resume,
2916 .reset_prepare = nvme_reset_prepare,
2917 .reset_done = nvme_reset_done,
2920 static const struct pci_device_id nvme_id_table[] = {
2921 { PCI_VDEVICE(INTEL, 0x0953),
2922 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2923 NVME_QUIRK_DEALLOCATE_ZEROES, },
2924 { PCI_VDEVICE(INTEL, 0x0a53),
2925 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2926 NVME_QUIRK_DEALLOCATE_ZEROES, },
2927 { PCI_VDEVICE(INTEL, 0x0a54),
2928 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2929 NVME_QUIRK_DEALLOCATE_ZEROES, },
2930 { PCI_VDEVICE(INTEL, 0x0a55),
2931 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2932 NVME_QUIRK_DEALLOCATE_ZEROES, },
2933 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2934 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2935 NVME_QUIRK_MEDIUM_PRIO_SQ },
2936 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
2937 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2938 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2939 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
2940 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
2941 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2942 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2943 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2944 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2945 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2946 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2947 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2948 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2949 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2950 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2951 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2952 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2953 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2954 .driver_data = NVME_QUIRK_LIGHTNVM, },
2955 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2956 .driver_data = NVME_QUIRK_LIGHTNVM, },
2957 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2958 .driver_data = NVME_QUIRK_LIGHTNVM, },
2959 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2960 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2961 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2964 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2966 static struct pci_driver nvme_driver = {
2968 .id_table = nvme_id_table,
2969 .probe = nvme_probe,
2970 .remove = nvme_remove,
2971 .shutdown = nvme_shutdown,
2973 .pm = &nvme_dev_pm_ops,
2975 .sriov_configure = pci_sriov_configure_simple,
2976 .err_handler = &nvme_err_handler,
2979 static int __init nvme_init(void)
2981 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
2982 return pci_register_driver(&nvme_driver);
2985 static void __exit nvme_exit(void)
2987 pci_unregister_driver(&nvme_driver);
2988 flush_workqueue(nvme_wq);
2992 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2993 MODULE_LICENSE("GPL");
2994 MODULE_VERSION("1.0");
2995 module_init(nvme_init);
2996 module_exit(nvme_exit);