drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/aer.h>
   9 #include <linux/async.h>
  10 #include <linux/blkdev.h>
  11 #include <linux/blk-mq.h>
  12 #include <linux/blk-mq-pci.h>
  13 #include <linux/dmi.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/once.h>
  21 #include <linux/pci.h>
  22 #include <linux/suspend.h>
  23 #include <linux/t10-pi.h>
  24 #include <linux/types.h>
  25 #include <linux/io-64-nonatomic-lo-hi.h>
  26 #include <linux/io-64-nonatomic-hi-lo.h>
  27 #include <linux/sed-opal.h>
  28 #include <linux/pci-p2pdma.h>
  29
  30 #include "trace.h"
  31 #include "nvme.h"
  32
  33 #define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  34 #define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  35
  36 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  37
  38 /*
  39  * These can be higher, but we need to ensure that any command doesn't
  40  * require an sg allocation that needs more than a page of data.
  41  */
  42 #define NVME_MAX_KB_SZ  4096
  43 #define NVME_MAX_SEGS   127
  44
  45 static int use_threaded_interrupts;
  46 module_param(use_threaded_interrupts, int, 0);
  47
  48 static bool use_cmb_sqes = true;
  49 module_param(use_cmb_sqes, bool, 0444);
  50 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  51
  52 static unsigned int max_host_mem_size_mb = 128;
  53 module_param(max_host_mem_size_mb, uint, 0444);
  54 MODULE_PARM_DESC(max_host_mem_size_mb,
  55         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  56
  57 static unsigned int sgl_threshold = SZ_32K;
  58 module_param(sgl_threshold, uint, 0644);
  59 MODULE_PARM_DESC(sgl_threshold,
  60                 "Use SGLs when average request segment size is larger or equal to "
  61                 "this size. Use 0 to disable SGLs.");
  62
  63 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  64 static const struct kernel_param_ops io_queue_depth_ops = {
  65         .set = io_queue_depth_set,
  66         .get = param_get_uint,
  67 };
  68
  69 static unsigned int io_queue_depth = 1024;
  70 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  71 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
  72
  73 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  74 {
  75         unsigned int n;
  76         int ret;
  77
  78         ret = kstrtouint(val, 10, &n);
  79         if (ret != 0 || n > num_possible_cpus())
  80                 return -EINVAL;
  81         return param_set_uint(val, kp);
  82 }
  83
  84 static const struct kernel_param_ops io_queue_count_ops = {
  85         .set = io_queue_count_set,
  86         .get = param_get_uint,
  87 };
  88
  89 static unsigned int write_queues;
  90 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  91 MODULE_PARM_DESC(write_queues,
  92         "Number of queues to use for writes. If not set, reads and writes "
  93         "will share a queue set.");
  94
  95 static unsigned int poll_queues;
  96 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
  97 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
  98
  99 static bool noacpi;
 100 module_param(noacpi, bool, 0444);
 101 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 102
 103 struct nvme_dev;
 104 struct nvme_queue;
 105
 106 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 107 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
 108
 109 /*
 110  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 111  */
 112 struct nvme_dev {
 113         struct nvme_queue *queues;
 114         struct blk_mq_tag_set tagset;
 115         struct blk_mq_tag_set admin_tagset;
 116         u32 __iomem *dbs;
 117         struct device *dev;
 118         struct dma_pool *prp_page_pool;
 119         struct dma_pool *prp_small_pool;
 120         unsigned online_queues;
 121         unsigned max_qid;
 122         unsigned io_queues[HCTX_MAX_TYPES];
 123         unsigned int num_vecs;
 124         u32 q_depth;
 125         int io_sqes;
 126         u32 db_stride;
 127         void __iomem *bar;
 128         unsigned long bar_mapped_size;
 129         struct work_struct remove_work;
 130         struct mutex shutdown_lock;
 131         bool subsystem;
 132         u64 cmb_size;
 133         bool cmb_use_sqes;
 134         u32 cmbsz;
 135         u32 cmbloc;
 136         struct nvme_ctrl ctrl;
 137         u32 last_ps;
 138
 139         mempool_t *iod_mempool;
 140
 141         /* shadow doorbell buffer support: */
 142         u32 *dbbuf_dbs;
 143         dma_addr_t dbbuf_dbs_dma_addr;
 144         u32 *dbbuf_eis;
 145         dma_addr_t dbbuf_eis_dma_addr;
 146
 147         /* host memory buffer support: */
 148         u64 host_mem_size;
 149         u32 nr_host_mem_descs;
 150         dma_addr_t host_mem_descs_dma;
 151         struct nvme_host_mem_buf_desc *host_mem_descs;
 152         void **host_mem_desc_bufs;
 153         unsigned int nr_allocated_queues;
 154         unsigned int nr_write_queues;
 155         unsigned int nr_poll_queues;
 156 };
 157
 158 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 159 {
 160         int ret;
 161         u32 n;
 162
 163         ret = kstrtou32(val, 10, &n);
 164         if (ret != 0 || n < 2)
 165                 return -EINVAL;
 166
 167         return param_set_uint(val, kp);
 168 }
 169
 170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 171 {
 172         return qid * 2 * stride;
 173 }
 174
 175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 176 {
 177         return (qid * 2 + 1) * stride;
 178 }
 179
 180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 181 {
 182         return container_of(ctrl, struct nvme_dev, ctrl);
 183 }
 184
 185 /*
 186  * An NVM Express queue.  Each device has at least two (one for admin
 187  * commands and one for I/O commands).
 188  */
 189 struct nvme_queue {
 190         struct nvme_dev *dev;
 191         spinlock_t sq_lock;
 192         void *sq_cmds;
 193          /* only used for poll queues: */
 194         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 195         struct nvme_completion *cqes;
 196         dma_addr_t sq_dma_addr;
 197         dma_addr_t cq_dma_addr;
 198         u32 __iomem *q_db;
 199         u32 q_depth;
 200         u16 cq_vector;
 201         u16 sq_tail;
 202         u16 last_sq_tail;
 203         u16 cq_head;
 204         u16 qid;
 205         u8 cq_phase;
 206         u8 sqes;
 207         unsigned long flags;
 208 #define NVMEQ_ENABLED           0
 209 #define NVMEQ_SQ_CMB            1
 210 #define NVMEQ_DELETE_ERROR      2
 211 #define NVMEQ_POLLED            3
 212         u32 *dbbuf_sq_db;
 213         u32 *dbbuf_cq_db;
 214         u32 *dbbuf_sq_ei;
 215         u32 *dbbuf_cq_ei;
 216         struct completion delete_done;
 217 };
 218
 219 /*
 220  * The nvme_iod describes the data in an I/O.
 221  *
 222  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 223  * to the actual struct scatterlist.
 224  */
 225 struct nvme_iod {
 226         struct nvme_request req;
 227         struct nvme_queue *nvmeq;
 228         bool use_sgl;
 229         int aborted;
 230         int npages;             /* In the PRP list. 0 means small pool in use */
 231         int nents;              /* Used in scatterlist */
 232         dma_addr_t first_dma;
 233         unsigned int dma_len;   /* length of single DMA segment mapping */
 234         dma_addr_t meta_dma;
 235         struct scatterlist *sg;
 236 };
 237
 238 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 239 {
 240         return dev->nr_allocated_queues * 8 * dev->db_stride;
 241 }
 242
 243 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 244 {
 245         unsigned int mem_size = nvme_dbbuf_size(dev);
 246
 247         if (dev->dbbuf_dbs)
 248                 return 0;
 249
 250         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 251                                             &dev->dbbuf_dbs_dma_addr,
 252                                             GFP_KERNEL);
 253         if (!dev->dbbuf_dbs)
 254                 return -ENOMEM;
 255         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 256                                             &dev->dbbuf_eis_dma_addr,
 257                                             GFP_KERNEL);
 258         if (!dev->dbbuf_eis) {
 259                 dma_free_coherent(dev->dev, mem_size,
 260                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 261                 dev->dbbuf_dbs = NULL;
 262                 return -ENOMEM;
 263         }
 264
 265         return 0;
 266 }
 267
 268 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 269 {
 270         unsigned int mem_size = nvme_dbbuf_size(dev);
 271
 272         if (dev->dbbuf_dbs) {
 273                 dma_free_coherent(dev->dev, mem_size,
 274                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 275                 dev->dbbuf_dbs = NULL;
 276         }
 277         if (dev->dbbuf_eis) {
 278                 dma_free_coherent(dev->dev, mem_size,
 279                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 280                 dev->dbbuf_eis = NULL;
 281         }
 282 }
 283
 284 static void nvme_dbbuf_init(struct nvme_dev *dev,
 285                             struct nvme_queue *nvmeq, int qid)
 286 {
 287         if (!dev->dbbuf_dbs || !qid)
 288                 return;
 289
 290         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 291         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 292         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 293         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 294 }
 295
 296 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 297 {
 298         if (!nvmeq->qid)
 299                 return;
 300
 301         nvmeq->dbbuf_sq_db = NULL;
 302         nvmeq->dbbuf_cq_db = NULL;
 303         nvmeq->dbbuf_sq_ei = NULL;
 304         nvmeq->dbbuf_cq_ei = NULL;
 305 }
 306
 307 static void nvme_dbbuf_set(struct nvme_dev *dev)
 308 {
 309         struct nvme_command c;
 310         unsigned int i;
 311
 312         if (!dev->dbbuf_dbs)
 313                 return;
 314
 315         memset(&c, 0, sizeof(c));
 316         c.dbbuf.opcode = nvme_admin_dbbuf;
 317         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 318         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 319
 320         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 321                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 322                 /* Free memory and continue on */
 323                 nvme_dbbuf_dma_free(dev);
 324
 325                 for (i = 1; i <= dev->online_queues; i++)
 326                         nvme_dbbuf_free(&dev->queues[i]);
 327         }
 328 }
 329
 330 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 331 {
 332         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 333 }
 334
 335 /* Update dbbuf and return true if an MMIO is required */
 336 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 337                                               volatile u32 *dbbuf_ei)
 338 {
 339         if (dbbuf_db) {
 340                 u16 old_value;
 341
 342                 /*
 343                  * Ensure that the queue is written before updating
 344                  * the doorbell in memory
 345                  */
 346                 wmb();
 347
 348                 old_value = *dbbuf_db;
 349                 *dbbuf_db = value;
 350
 351                 /*
 352                  * Ensure that the doorbell is updated before reading the event
 353                  * index from memory.  The controller needs to provide similar
 354                  * ordering to ensure the envent index is updated before reading
 355                  * the doorbell.
 356                  */
 357                 mb();
 358
 359                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 360                         return false;
 361         }
 362
 363         return true;
 364 }
 365
 366 /*
 367  * Will slightly overestimate the number of pages needed.  This is OK
 368  * as it only leads to a small amount of wasted memory for the lifetime of
 369  * the I/O.
 370  */
 371 static int nvme_pci_npages_prp(void)
 372 {
 373         unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
 374                                       NVME_CTRL_PAGE_SIZE);
 375         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 376 }
 377
 378 /*
 379  * Calculates the number of pages needed for the SGL segments. For example a 4k
 380  * page can accommodate 256 SGL descriptors.
 381  */
 382 static int nvme_pci_npages_sgl(void)
 383 {
 384         return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
 385                         PAGE_SIZE);
 386 }
 387
 388 static size_t nvme_pci_iod_alloc_size(void)
 389 {
 390         size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
 391
 392         return sizeof(__le64 *) * npages +
 393                 sizeof(struct scatterlist) * NVME_MAX_SEGS;
 394 }
 395
 396 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 397                                 unsigned int hctx_idx)
 398 {
 399         struct nvme_dev *dev = data;
 400         struct nvme_queue *nvmeq = &dev->queues[0];
 401
 402         WARN_ON(hctx_idx != 0);
 403         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 404
 405         hctx->driver_data = nvmeq;
 406         return 0;
 407 }
 408
 409 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 410                           unsigned int hctx_idx)
 411 {
 412         struct nvme_dev *dev = data;
 413         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 414
 415         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 416         hctx->driver_data = nvmeq;
 417         return 0;
 418 }
 419
 420 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 421                 unsigned int hctx_idx, unsigned int numa_node)
 422 {
 423         struct nvme_dev *dev = set->driver_data;
 424         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 425         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 426         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 427
 428         BUG_ON(!nvmeq);
 429         iod->nvmeq = nvmeq;
 430
 431         nvme_req(req)->ctrl = &dev->ctrl;
 432         return 0;
 433 }
 434
 435 static int queue_irq_offset(struct nvme_dev *dev)
 436 {
 437         /* if we have more than 1 vec, admin queue offsets us by 1 */
 438         if (dev->num_vecs > 1)
 439                 return 1;
 440
 441         return 0;
 442 }
 443
 444 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 445 {
 446         struct nvme_dev *dev = set->driver_data;
 447         int i, qoff, offset;
 448
 449         offset = queue_irq_offset(dev);
 450         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 451                 struct blk_mq_queue_map *map = &set->map[i];
 452
 453                 map->nr_queues = dev->io_queues[i];
 454                 if (!map->nr_queues) {
 455                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 456                         continue;
 457                 }
 458
 459                 /*
 460                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 461                  * affinity), so use the regular blk-mq cpu mapping
 462                  */
 463                 map->queue_offset = qoff;
 464                 if (i != HCTX_TYPE_POLL && offset)
 465                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 466                 else
 467                         blk_mq_map_queues(map);
 468                 qoff += map->nr_queues;
 469                 offset += map->nr_queues;
 470         }
 471
 472         return 0;
 473 }
 474
 475 /*
 476  * Write sq tail if we are asked to, or if the next command would wrap.
 477  */
 478 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 479 {
 480         if (!write_sq) {
 481                 u16 next_tail = nvmeq->sq_tail + 1;
 482
 483                 if (next_tail == nvmeq->q_depth)
 484                         next_tail = 0;
 485                 if (next_tail != nvmeq->last_sq_tail)
 486                         return;
 487         }
 488
 489         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 490                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 491                 writel(nvmeq->sq_tail, nvmeq->q_db);
 492         nvmeq->last_sq_tail = nvmeq->sq_tail;
 493 }
 494
 495 /**
 496  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 497  * @nvmeq: The queue to use
 498  * @cmd: The command to send
 499  * @write_sq: whether to write to the SQ doorbell
 500  */
 501 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
 502                             bool write_sq)
 503 {
 504         spin_lock(&nvmeq->sq_lock);
 505         memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 506                cmd, sizeof(*cmd));
 507         if (++nvmeq->sq_tail == nvmeq->q_depth)
 508                 nvmeq->sq_tail = 0;
 509         nvme_write_sq_db(nvmeq, write_sq);
 510         spin_unlock(&nvmeq->sq_lock);
 511 }
 512
 513 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 514 {
 515         struct nvme_queue *nvmeq = hctx->driver_data;
 516
 517         spin_lock(&nvmeq->sq_lock);
 518         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 519                 nvme_write_sq_db(nvmeq, true);
 520         spin_unlock(&nvmeq->sq_lock);
 521 }
 522
 523 static void **nvme_pci_iod_list(struct request *req)
 524 {
 525         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 526         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 527 }
 528
 529 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 530 {
 531         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 532         int nseg = blk_rq_nr_phys_segments(req);
 533         unsigned int avg_seg_size;
 534
 535         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 536
 537         if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
 538                 return false;
 539         if (!iod->nvmeq->qid)
 540                 return false;
 541         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 542                 return false;
 543         return true;
 544 }
 545
 546 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 547 {
 548         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 549         const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 550         dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
 551         int i;
 552
 553         if (iod->dma_len) {
 554                 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
 555                                rq_dma_dir(req));
 556                 return;
 557         }
 558
 559         WARN_ON_ONCE(!iod->nents);
 560
 561         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 562                 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
 563                                     rq_dma_dir(req));
 564         else
 565                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
 566
 567
 568         if (iod->npages == 0)
 569                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 570                         dma_addr);
 571
 572         for (i = 0; i < iod->npages; i++) {
 573                 void *addr = nvme_pci_iod_list(req)[i];
 574
 575                 if (iod->use_sgl) {
 576                         struct nvme_sgl_desc *sg_list = addr;
 577
 578                         next_dma_addr =
 579                             le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
 580                 } else {
 581                         __le64 *prp_list = addr;
 582
 583                         next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 584                 }
 585
 586                 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
 587                 dma_addr = next_dma_addr;
 588         }
 589
 590         mempool_free(iod->sg, dev->iod_mempool);
 591 }
 592
 593 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 594 {
 595         int i;
 596         struct scatterlist *sg;
 597
 598         for_each_sg(sgl, sg, nents, i) {
 599                 dma_addr_t phys = sg_phys(sg);
 600                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 601                         "dma_address:%pad dma_length:%d\n",
 602                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 603                         sg_dma_len(sg));
 604         }
 605 }
 606
 607 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 608                 struct request *req, struct nvme_rw_command *cmnd)
 609 {
 610         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 611         struct dma_pool *pool;
 612         int length = blk_rq_payload_bytes(req);
 613         struct scatterlist *sg = iod->sg;
 614         int dma_len = sg_dma_len(sg);
 615         u64 dma_addr = sg_dma_address(sg);
 616         int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 617         __le64 *prp_list;
 618         void **list = nvme_pci_iod_list(req);
 619         dma_addr_t prp_dma;
 620         int nprps, i;
 621
 622         length -= (NVME_CTRL_PAGE_SIZE - offset);
 623         if (length <= 0) {
 624                 iod->first_dma = 0;
 625                 goto done;
 626         }
 627
 628         dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 629         if (dma_len) {
 630                 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 631         } else {
 632                 sg = sg_next(sg);
 633                 dma_addr = sg_dma_address(sg);
 634                 dma_len = sg_dma_len(sg);
 635         }
 636
 637         if (length <= NVME_CTRL_PAGE_SIZE) {
 638                 iod->first_dma = dma_addr;
 639                 goto done;
 640         }
 641
 642         nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 643         if (nprps <= (256 / 8)) {
 644                 pool = dev->prp_small_pool;
 645                 iod->npages = 0;
 646         } else {
 647                 pool = dev->prp_page_pool;
 648                 iod->npages = 1;
 649         }
 650
 651         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 652         if (!prp_list) {
 653                 iod->first_dma = dma_addr;
 654                 iod->npages = -1;
 655                 return BLK_STS_RESOURCE;
 656         }
 657         list[0] = prp_list;
 658         iod->first_dma = prp_dma;
 659         i = 0;
 660         for (;;) {
 661                 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 662                         __le64 *old_prp_list = prp_list;
 663                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 664                         if (!prp_list)
 665                                 return BLK_STS_RESOURCE;
 666                         list[iod->npages++] = prp_list;
 667                         prp_list[0] = old_prp_list[i - 1];
 668                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 669                         i = 1;
 670                 }
 671                 prp_list[i++] = cpu_to_le64(dma_addr);
 672                 dma_len -= NVME_CTRL_PAGE_SIZE;
 673                 dma_addr += NVME_CTRL_PAGE_SIZE;
 674                 length -= NVME_CTRL_PAGE_SIZE;
 675                 if (length <= 0)
 676                         break;
 677                 if (dma_len > 0)
 678                         continue;
 679                 if (unlikely(dma_len < 0))
 680                         goto bad_sgl;
 681                 sg = sg_next(sg);
 682                 dma_addr = sg_dma_address(sg);
 683                 dma_len = sg_dma_len(sg);
 684         }
 685
 686 done:
 687         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 688         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 689
 690         return BLK_STS_OK;
 691
 692  bad_sgl:
 693         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 694                         "Invalid SGL for payload:%d nents:%d\n",
 695                         blk_rq_payload_bytes(req), iod->nents);
 696         return BLK_STS_IOERR;
 697 }
 698
 699 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 700                 struct scatterlist *sg)
 701 {
 702         sge->addr = cpu_to_le64(sg_dma_address(sg));
 703         sge->length = cpu_to_le32(sg_dma_len(sg));
 704         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 705 }
 706
 707 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 708                 dma_addr_t dma_addr, int entries)
 709 {
 710         sge->addr = cpu_to_le64(dma_addr);
 711         if (entries < SGES_PER_PAGE) {
 712                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 713                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 714         } else {
 715                 sge->length = cpu_to_le32(PAGE_SIZE);
 716                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 717         }
 718 }
 719
 720 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 721                 struct request *req, struct nvme_rw_command *cmd, int entries)
 722 {
 723         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 724         struct dma_pool *pool;
 725         struct nvme_sgl_desc *sg_list;
 726         struct scatterlist *sg = iod->sg;
 727         dma_addr_t sgl_dma;
 728         int i = 0;
 729
 730         /* setting the transfer type as SGL */
 731         cmd->flags = NVME_CMD_SGL_METABUF;
 732
 733         if (entries == 1) {
 734                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 735                 return BLK_STS_OK;
 736         }
 737
 738         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 739                 pool = dev->prp_small_pool;
 740                 iod->npages = 0;
 741         } else {
 742                 pool = dev->prp_page_pool;
 743                 iod->npages = 1;
 744         }
 745
 746         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 747         if (!sg_list) {
 748                 iod->npages = -1;
 749                 return BLK_STS_RESOURCE;
 750         }
 751
 752         nvme_pci_iod_list(req)[0] = sg_list;
 753         iod->first_dma = sgl_dma;
 754
 755         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 756
 757         do {
 758                 if (i == SGES_PER_PAGE) {
 759                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 760                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 761
 762                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 763                         if (!sg_list)
 764                                 return BLK_STS_RESOURCE;
 765
 766                         i = 0;
 767                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 768                         sg_list[i++] = *link;
 769                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 770                 }
 771
 772                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 773                 sg = sg_next(sg);
 774         } while (--entries > 0);
 775
 776         return BLK_STS_OK;
 777 }
 778
 779 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 780                 struct request *req, struct nvme_rw_command *cmnd,
 781                 struct bio_vec *bv)
 782 {
 783         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 784         unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 785         unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 786
 787         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 788         if (dma_mapping_error(dev->dev, iod->first_dma))
 789                 return BLK_STS_RESOURCE;
 790         iod->dma_len = bv->bv_len;
 791
 792         cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 793         if (bv->bv_len > first_prp_len)
 794                 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 795         return BLK_STS_OK;
 796 }
 797
 798 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 799                 struct request *req, struct nvme_rw_command *cmnd,
 800                 struct bio_vec *bv)
 801 {
 802         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 803
 804         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 805         if (dma_mapping_error(dev->dev, iod->first_dma))
 806                 return BLK_STS_RESOURCE;
 807         iod->dma_len = bv->bv_len;
 808
 809         cmnd->flags = NVME_CMD_SGL_METABUF;
 810         cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 811         cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 812         cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 813         return BLK_STS_OK;
 814 }
 815
 816 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 817                 struct nvme_command *cmnd)
 818 {
 819         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 820         blk_status_t ret = BLK_STS_RESOURCE;
 821         int nr_mapped;
 822
 823         if (blk_rq_nr_phys_segments(req) == 1) {
 824                 struct bio_vec bv = req_bvec(req);
 825
 826                 if (!is_pci_p2pdma_page(bv.bv_page)) {
 827                         if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 828                                 return nvme_setup_prp_simple(dev, req,
 829                                                              &cmnd->rw, &bv);
 830
 831                         if (iod->nvmeq->qid &&
 832                             dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
 833                                 return nvme_setup_sgl_simple(dev, req,
 834                                                              &cmnd->rw, &bv);
 835                 }
 836         }
 837
 838         iod->dma_len = 0;
 839         iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 840         if (!iod->sg)
 841                 return BLK_STS_RESOURCE;
 842         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 843         iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
 844         if (!iod->nents)
 845                 goto out;
 846
 847         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 848                 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
 849                                 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
 850         else
 851                 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
 852                                              rq_dma_dir(req), DMA_ATTR_NO_WARN);
 853         if (!nr_mapped)
 854                 goto out;
 855
 856         iod->use_sgl = nvme_pci_use_sgls(dev, req);
 857         if (iod->use_sgl)
 858                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
 859         else
 860                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 861 out:
 862         if (ret != BLK_STS_OK)
 863                 nvme_unmap_data(dev, req);
 864         return ret;
 865 }
 866
 867 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 868                 struct nvme_command *cmnd)
 869 {
 870         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 871
 872         iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 873                         rq_dma_dir(req), 0);
 874         if (dma_mapping_error(dev->dev, iod->meta_dma))
 875                 return BLK_STS_IOERR;
 876         cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 877         return BLK_STS_OK;
 878 }
 879
 880 /*
 881  * NOTE: ns is NULL when called on the admin queue.
 882  */
 883 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 884                          const struct blk_mq_queue_data *bd)
 885 {
 886         struct nvme_ns *ns = hctx->queue->queuedata;
 887         struct nvme_queue *nvmeq = hctx->driver_data;
 888         struct nvme_dev *dev = nvmeq->dev;
 889         struct request *req = bd->rq;
 890         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 891         struct nvme_command cmnd;
 892         blk_status_t ret;
 893
 894         iod->aborted = 0;
 895         iod->npages = -1;
 896         iod->nents = 0;
 897
 898         /*
 899          * We should not need to do this, but we're still using this to
 900          * ensure we can drain requests on a dying queue.
 901          */
 902         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 903                 return BLK_STS_IOERR;
 904
 905         ret = nvme_setup_cmd(ns, req, &cmnd);
 906         if (ret)
 907                 return ret;
 908
 909         if (blk_rq_nr_phys_segments(req)) {
 910                 ret = nvme_map_data(dev, req, &cmnd);
 911                 if (ret)
 912                         goto out_free_cmd;
 913         }
 914
 915         if (blk_integrity_rq(req)) {
 916                 ret = nvme_map_metadata(dev, req, &cmnd);
 917                 if (ret)
 918                         goto out_unmap_data;
 919         }
 920
 921         blk_mq_start_request(req);
 922         nvme_submit_cmd(nvmeq, &cmnd, bd->last);
 923         return BLK_STS_OK;
 924 out_unmap_data:
 925         nvme_unmap_data(dev, req);
 926 out_free_cmd:
 927         nvme_cleanup_cmd(req);
 928         return ret;
 929 }
 930
 931 static void nvme_pci_complete_rq(struct request *req)
 932 {
 933         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 934         struct nvme_dev *dev = iod->nvmeq->dev;
 935
 936         if (blk_integrity_rq(req))
 937                 dma_unmap_page(dev->dev, iod->meta_dma,
 938                                rq_integrity_vec(req)->bv_len, rq_data_dir(req));
 939         if (blk_rq_nr_phys_segments(req))
 940                 nvme_unmap_data(dev, req);
 941         nvme_complete_rq(req);
 942 }
 943
 944 /* We read the CQE phase first to check if the rest of the entry is valid */
 945 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
 946 {
 947         struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
 948
 949         return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
 950 }
 951
 952 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 953 {
 954         u16 head = nvmeq->cq_head;
 955
 956         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 957                                               nvmeq->dbbuf_cq_ei))
 958                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 959 }
 960
 961 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
 962 {
 963         if (!nvmeq->qid)
 964                 return nvmeq->dev->admin_tagset.tags[0];
 965         return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
 966 }
 967
 968 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
 969 {
 970         struct nvme_completion *cqe = &nvmeq->cqes[idx];
 971         __u16 command_id = READ_ONCE(cqe->command_id);
 972         struct request *req;
 973
 974         /*
 975          * AEN requests are special as they don't time out and can
 976          * survive any kind of queue freeze and often don't respond to
 977          * aborts.  We don't even bother to allocate a struct request
 978          * for them but rather special case them here.
 979          */
 980         if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
 981                 nvme_complete_async_event(&nvmeq->dev->ctrl,
 982                                 cqe->status, &cqe->result);
 983                 return;
 984         }
 985
 986         req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id);
 987         if (unlikely(!req)) {
 988                 dev_warn(nvmeq->dev->ctrl.device,
 989                         "invalid id %d completed on queue %d\n",
 990                         command_id, le16_to_cpu(cqe->sq_id));
 991                 return;
 992         }
 993
 994         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
 995         if (!nvme_try_complete_req(req, cqe->status, cqe->result))
 996                 nvme_pci_complete_rq(req);
 997 }
 998
 999 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1000 {
1001         u16 tmp = nvmeq->cq_head + 1;
1002
1003         if (tmp == nvmeq->q_depth) {
1004                 nvmeq->cq_head = 0;
1005                 nvmeq->cq_phase ^= 1;
1006         } else {
1007                 nvmeq->cq_head = tmp;
1008         }
1009 }
1010
1011 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
1012 {
1013         int found = 0;
1014
1015         while (nvme_cqe_pending(nvmeq)) {
1016                 found++;
1017                 /*
1018                  * load-load control dependency between phase and the rest of
1019                  * the cqe requires a full read memory barrier
1020                  */
1021                 dma_rmb();
1022                 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1023                 nvme_update_cq_head(nvmeq);
1024         }
1025
1026         if (found)
1027                 nvme_ring_cq_doorbell(nvmeq);
1028         return found;
1029 }
1030
1031 static irqreturn_t nvme_irq(int irq, void *data)
1032 {
1033         struct nvme_queue *nvmeq = data;
1034         irqreturn_t ret = IRQ_NONE;
1035
1036         /*
1037          * The rmb/wmb pair ensures we see all updates from a previous run of
1038          * the irq handler, even if that was on another CPU.
1039          */
1040         rmb();
1041         if (nvme_process_cq(nvmeq))
1042                 ret = IRQ_HANDLED;
1043         wmb();
1044
1045         return ret;
1046 }
1047
1048 static irqreturn_t nvme_irq_check(int irq, void *data)
1049 {
1050         struct nvme_queue *nvmeq = data;
1051
1052         if (nvme_cqe_pending(nvmeq))
1053                 return IRQ_WAKE_THREAD;
1054         return IRQ_NONE;
1055 }
1056
1057 /*
1058  * Poll for completions for any interrupt driven queue
1059  * Can be called from any context.
1060  */
1061 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1062 {
1063         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1064
1065         WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1066
1067         disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1068         nvme_process_cq(nvmeq);
1069         enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1070 }
1071
1072 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1073 {
1074         struct nvme_queue *nvmeq = hctx->driver_data;
1075         bool found;
1076
1077         if (!nvme_cqe_pending(nvmeq))
1078                 return 0;
1079
1080         spin_lock(&nvmeq->cq_poll_lock);
1081         found = nvme_process_cq(nvmeq);
1082         spin_unlock(&nvmeq->cq_poll_lock);
1083
1084         return found;
1085 }
1086
1087 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1088 {
1089         struct nvme_dev *dev = to_nvme_dev(ctrl);
1090         struct nvme_queue *nvmeq = &dev->queues[0];
1091         struct nvme_command c;
1092
1093         memset(&c, 0, sizeof(c));
1094         c.common.opcode = nvme_admin_async_event;
1095         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1096         nvme_submit_cmd(nvmeq, &c, true);
1097 }
1098
1099 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1100 {
1101         struct nvme_command c;
1102
1103         memset(&c, 0, sizeof(c));
1104         c.delete_queue.opcode = opcode;
1105         c.delete_queue.qid = cpu_to_le16(id);
1106
1107         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1108 }
1109
1110 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1111                 struct nvme_queue *nvmeq, s16 vector)
1112 {
1113         struct nvme_command c;
1114         int flags = NVME_QUEUE_PHYS_CONTIG;
1115
1116         if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1117                 flags |= NVME_CQ_IRQ_ENABLED;
1118
1119         /*
1120          * Note: we (ab)use the fact that the prp fields survive if no data
1121          * is attached to the request.
1122          */
1123         memset(&c, 0, sizeof(c));
1124         c.create_cq.opcode = nvme_admin_create_cq;
1125         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1126         c.create_cq.cqid = cpu_to_le16(qid);
1127         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1128         c.create_cq.cq_flags = cpu_to_le16(flags);
1129         c.create_cq.irq_vector = cpu_to_le16(vector);
1130
1131         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1132 }
1133
1134 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1135                                                 struct nvme_queue *nvmeq)
1136 {
1137         struct nvme_ctrl *ctrl = &dev->ctrl;
1138         struct nvme_command c;
1139         int flags = NVME_QUEUE_PHYS_CONTIG;
1140
1141         /*
1142          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1143          * set. Since URGENT priority is zeroes, it makes all queues
1144          * URGENT.
1145          */
1146         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1147                 flags |= NVME_SQ_PRIO_MEDIUM;
1148
1149         /*
1150          * Note: we (ab)use the fact that the prp fields survive if no data
1151          * is attached to the request.
1152          */
1153         memset(&c, 0, sizeof(c));
1154         c.create_sq.opcode = nvme_admin_create_sq;
1155         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1156         c.create_sq.sqid = cpu_to_le16(qid);
1157         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1158         c.create_sq.sq_flags = cpu_to_le16(flags);
1159         c.create_sq.cqid = cpu_to_le16(qid);
1160
1161         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1162 }
1163
1164 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1165 {
1166         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1167 }
1168
1169 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1170 {
1171         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1172 }
1173
1174 static void abort_endio(struct request *req, blk_status_t error)
1175 {
1176         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1177         struct nvme_queue *nvmeq = iod->nvmeq;
1178
1179         dev_warn(nvmeq->dev->ctrl.device,
1180                  "Abort status: 0x%x", nvme_req(req)->status);
1181         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1182         blk_mq_free_request(req);
1183 }
1184
1185 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1186 {
1187         /* If true, indicates loss of adapter communication, possibly by a
1188          * NVMe Subsystem reset.
1189          */
1190         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1191
1192         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1193         switch (dev->ctrl.state) {
1194         case NVME_CTRL_RESETTING:
1195         case NVME_CTRL_CONNECTING:
1196                 return false;
1197         default:
1198                 break;
1199         }
1200
1201         /* We shouldn't reset unless the controller is on fatal error state
1202          * _or_ if we lost the communication with it.
1203          */
1204         if (!(csts & NVME_CSTS_CFS) && !nssro)
1205                 return false;
1206
1207         return true;
1208 }
1209
1210 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1211 {
1212         /* Read a config register to help see what died. */
1213         u16 pci_status;
1214         int result;
1215
1216         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1217                                       &pci_status);
1218         if (result == PCIBIOS_SUCCESSFUL)
1219                 dev_warn(dev->ctrl.device,
1220                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1221                          csts, pci_status);
1222         else
1223                 dev_warn(dev->ctrl.device,
1224                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1225                          csts, result);
1226 }
1227
1228 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1229 {
1230         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1231         struct nvme_queue *nvmeq = iod->nvmeq;
1232         struct nvme_dev *dev = nvmeq->dev;
1233         struct request *abort_req;
1234         struct nvme_command cmd;
1235         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1236
1237         /* If PCI error recovery process is happening, we cannot reset or
1238          * the recovery mechanism will surely fail.
1239          */
1240         mb();
1241         if (pci_channel_offline(to_pci_dev(dev->dev)))
1242                 return BLK_EH_RESET_TIMER;
1243
1244         /*
1245          * Reset immediately if the controller is failed
1246          */
1247         if (nvme_should_reset(dev, csts)) {
1248                 nvme_warn_reset(dev, csts);
1249                 nvme_dev_disable(dev, false);
1250                 nvme_reset_ctrl(&dev->ctrl);
1251                 return BLK_EH_DONE;
1252         }
1253
1254         /*
1255          * Did we miss an interrupt?
1256          */
1257         if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1258                 nvme_poll(req->mq_hctx);
1259         else
1260                 nvme_poll_irqdisable(nvmeq);
1261
1262         if (blk_mq_request_completed(req)) {
1263                 dev_warn(dev->ctrl.device,
1264                          "I/O %d QID %d timeout, completion polled\n",
1265                          req->tag, nvmeq->qid);
1266                 return BLK_EH_DONE;
1267         }
1268
1269         /*
1270          * Shutdown immediately if controller times out while starting. The
1271          * reset work will see the pci device disabled when it gets the forced
1272          * cancellation error. All outstanding requests are completed on
1273          * shutdown, so we return BLK_EH_DONE.
1274          */
1275         switch (dev->ctrl.state) {
1276         case NVME_CTRL_CONNECTING:
1277                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1278                 fallthrough;
1279         case NVME_CTRL_DELETING:
1280                 dev_warn_ratelimited(dev->ctrl.device,
1281                          "I/O %d QID %d timeout, disable controller\n",
1282                          req->tag, nvmeq->qid);
1283                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1284                 nvme_dev_disable(dev, true);
1285                 return BLK_EH_DONE;
1286         case NVME_CTRL_RESETTING:
1287                 return BLK_EH_RESET_TIMER;
1288         default:
1289                 break;
1290         }
1291
1292         /*
1293          * Shutdown the controller immediately and schedule a reset if the
1294          * command was already aborted once before and still hasn't been
1295          * returned to the driver, or if this is the admin queue.
1296          */
1297         if (!nvmeq->qid || iod->aborted) {
1298                 dev_warn(dev->ctrl.device,
1299                          "I/O %d QID %d timeout, reset controller\n",
1300                          req->tag, nvmeq->qid);
1301                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1302                 nvme_dev_disable(dev, false);
1303                 nvme_reset_ctrl(&dev->ctrl);
1304
1305                 return BLK_EH_DONE;
1306         }
1307
1308         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1309                 atomic_inc(&dev->ctrl.abort_limit);
1310                 return BLK_EH_RESET_TIMER;
1311         }
1312         iod->aborted = 1;
1313
1314         memset(&cmd, 0, sizeof(cmd));
1315         cmd.abort.opcode = nvme_admin_abort_cmd;
1316         cmd.abort.cid = req->tag;
1317         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1318
1319         dev_warn(nvmeq->dev->ctrl.device,
1320                 "I/O %d QID %d timeout, aborting\n",
1321                  req->tag, nvmeq->qid);
1322
1323         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1324                         BLK_MQ_REQ_NOWAIT);
1325         if (IS_ERR(abort_req)) {
1326                 atomic_inc(&dev->ctrl.abort_limit);
1327                 return BLK_EH_RESET_TIMER;
1328         }
1329
1330         abort_req->end_io_data = NULL;
1331         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1332
1333         /*
1334          * The aborted req will be completed on receiving the abort req.
1335          * We enable the timer again. If hit twice, it'll cause a device reset,
1336          * as the device then is in a faulty state.
1337          */
1338         return BLK_EH_RESET_TIMER;
1339 }
1340
1341 static void nvme_free_queue(struct nvme_queue *nvmeq)
1342 {
1343         dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1344                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1345         if (!nvmeq->sq_cmds)
1346                 return;
1347
1348         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1349                 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1350                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1351         } else {
1352                 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1353                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1354         }
1355 }
1356
1357 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1358 {
1359         int i;
1360
1361         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1362                 dev->ctrl.queue_count--;
1363                 nvme_free_queue(&dev->queues[i]);
1364         }
1365 }
1366
1367 /**
1368  * nvme_suspend_queue - put queue into suspended state
1369  * @nvmeq: queue to suspend
1370  */
1371 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1372 {
1373         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1374                 return 1;
1375
1376         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1377         mb();
1378
1379         nvmeq->dev->online_queues--;
1380         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1381                 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1382         if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1383                 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1384         return 0;
1385 }
1386
1387 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1388 {
1389         int i;
1390
1391         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1392                 nvme_suspend_queue(&dev->queues[i]);
1393 }
1394
1395 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1396 {
1397         struct nvme_queue *nvmeq = &dev->queues[0];
1398
1399         if (shutdown)
1400                 nvme_shutdown_ctrl(&dev->ctrl);
1401         else
1402                 nvme_disable_ctrl(&dev->ctrl);
1403
1404         nvme_poll_irqdisable(nvmeq);
1405 }
1406
1407 /*
1408  * Called only on a device that has been disabled and after all other threads
1409  * that can check this device's completion queues have synced, except
1410  * nvme_poll(). This is the last chance for the driver to see a natural
1411  * completion before nvme_cancel_request() terminates all incomplete requests.
1412  */
1413 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1414 {
1415         int i;
1416
1417         for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1418                 spin_lock(&dev->queues[i].cq_poll_lock);
1419                 nvme_process_cq(&dev->queues[i]);
1420                 spin_unlock(&dev->queues[i].cq_poll_lock);
1421         }
1422 }
1423
1424 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1425                                 int entry_size)
1426 {
1427         int q_depth = dev->q_depth;
1428         unsigned q_size_aligned = roundup(q_depth * entry_size,
1429                                           NVME_CTRL_PAGE_SIZE);
1430
1431         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1432                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1433
1434                 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1435                 q_depth = div_u64(mem_per_q, entry_size);
1436
1437                 /*
1438                  * Ensure the reduced q_depth is above some threshold where it
1439                  * would be better to map queues in system memory with the
1440                  * original depth
1441                  */
1442                 if (q_depth < 64)
1443                         return -ENOMEM;
1444         }
1445
1446         return q_depth;
1447 }
1448
1449 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1450                                 int qid)
1451 {
1452         struct pci_dev *pdev = to_pci_dev(dev->dev);
1453
1454         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1455                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1456                 if (nvmeq->sq_cmds) {
1457                         nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1458                                                         nvmeq->sq_cmds);
1459                         if (nvmeq->sq_dma_addr) {
1460                                 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1461                                 return 0;
1462                         }
1463
1464                         pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1465                 }
1466         }
1467
1468         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1469                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1470         if (!nvmeq->sq_cmds)
1471                 return -ENOMEM;
1472         return 0;
1473 }
1474
1475 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1476 {
1477         struct nvme_queue *nvmeq = &dev->queues[qid];
1478
1479         if (dev->ctrl.queue_count > qid)
1480                 return 0;
1481
1482         nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1483         nvmeq->q_depth = depth;
1484         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1485                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1486         if (!nvmeq->cqes)
1487                 goto free_nvmeq;
1488
1489         if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1490                 goto free_cqdma;
1491
1492         nvmeq->dev = dev;
1493         spin_lock_init(&nvmeq->sq_lock);
1494         spin_lock_init(&nvmeq->cq_poll_lock);
1495         nvmeq->cq_head = 0;
1496         nvmeq->cq_phase = 1;
1497         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1498         nvmeq->qid = qid;
1499         dev->ctrl.queue_count++;
1500
1501         return 0;
1502
1503  free_cqdma:
1504         dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1505                           nvmeq->cq_dma_addr);
1506  free_nvmeq:
1507         return -ENOMEM;
1508 }
1509
1510 static int queue_request_irq(struct nvme_queue *nvmeq)
1511 {
1512         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1513         int nr = nvmeq->dev->ctrl.instance;
1514
1515         if (use_threaded_interrupts) {
1516                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1517                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1518         } else {
1519                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1520                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1521         }
1522 }
1523
1524 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1525 {
1526         struct nvme_dev *dev = nvmeq->dev;
1527
1528         nvmeq->sq_tail = 0;
1529         nvmeq->last_sq_tail = 0;
1530         nvmeq->cq_head = 0;
1531         nvmeq->cq_phase = 1;
1532         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1533         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1534         nvme_dbbuf_init(dev, nvmeq, qid);
1535         dev->online_queues++;
1536         wmb(); /* ensure the first interrupt sees the initialization */
1537 }
1538
1539 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1540 {
1541         struct nvme_dev *dev = nvmeq->dev;
1542         int result;
1543         u16 vector = 0;
1544
1545         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1546
1547         /*
1548          * A queue's vector matches the queue identifier unless the controller
1549          * has only one vector available.
1550          */
1551         if (!polled)
1552                 vector = dev->num_vecs == 1 ? 0 : qid;
1553         else
1554                 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1555
1556         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1557         if (result)
1558                 return result;
1559
1560         result = adapter_alloc_sq(dev, qid, nvmeq);
1561         if (result < 0)
1562                 return result;
1563         if (result)
1564                 goto release_cq;
1565
1566         nvmeq->cq_vector = vector;
1567         nvme_init_queue(nvmeq, qid);
1568
1569         if (!polled) {
1570                 result = queue_request_irq(nvmeq);
1571                 if (result < 0)
1572                         goto release_sq;
1573         }
1574
1575         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1576         return result;
1577
1578 release_sq:
1579         dev->online_queues--;
1580         adapter_delete_sq(dev, qid);
1581 release_cq:
1582         adapter_delete_cq(dev, qid);
1583         return result;
1584 }
1585
1586 static const struct blk_mq_ops nvme_mq_admin_ops = {
1587         .queue_rq       = nvme_queue_rq,
1588         .complete       = nvme_pci_complete_rq,
1589         .init_hctx      = nvme_admin_init_hctx,
1590         .init_request   = nvme_init_request,
1591         .timeout        = nvme_timeout,
1592 };
1593
1594 static const struct blk_mq_ops nvme_mq_ops = {
1595         .queue_rq       = nvme_queue_rq,
1596         .complete       = nvme_pci_complete_rq,
1597         .commit_rqs     = nvme_commit_rqs,
1598         .init_hctx      = nvme_init_hctx,
1599         .init_request   = nvme_init_request,
1600         .map_queues     = nvme_pci_map_queues,
1601         .timeout        = nvme_timeout,
1602         .poll           = nvme_poll,
1603 };
1604
1605 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1606 {
1607         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1608                 /*
1609                  * If the controller was reset during removal, it's possible
1610                  * user requests may be waiting on a stopped queue. Start the
1611                  * queue to flush these to completion.
1612                  */
1613                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1614                 blk_cleanup_queue(dev->ctrl.admin_q);
1615                 blk_mq_free_tag_set(&dev->admin_tagset);
1616         }
1617 }
1618
1619 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1620 {
1621         if (!dev->ctrl.admin_q) {
1622                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1623                 dev->admin_tagset.nr_hw_queues = 1;
1624
1625                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1626                 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1627                 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1628                 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1629                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1630                 dev->admin_tagset.driver_data = dev;
1631
1632                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1633                         return -ENOMEM;
1634                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1635
1636                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1637                 if (IS_ERR(dev->ctrl.admin_q)) {
1638                         blk_mq_free_tag_set(&dev->admin_tagset);
1639                         return -ENOMEM;
1640                 }
1641                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1642                         nvme_dev_remove_admin(dev);
1643                         dev->ctrl.admin_q = NULL;
1644                         return -ENODEV;
1645                 }
1646         } else
1647                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1648
1649         return 0;
1650 }
1651
1652 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1653 {
1654         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1655 }
1656
1657 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1658 {
1659         struct pci_dev *pdev = to_pci_dev(dev->dev);
1660
1661         if (size <= dev->bar_mapped_size)
1662                 return 0;
1663         if (size > pci_resource_len(pdev, 0))
1664                 return -ENOMEM;
1665         if (dev->bar)
1666                 iounmap(dev->bar);
1667         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1668         if (!dev->bar) {
1669                 dev->bar_mapped_size = 0;
1670                 return -ENOMEM;
1671         }
1672         dev->bar_mapped_size = size;
1673         dev->dbs = dev->bar + NVME_REG_DBS;
1674
1675         return 0;
1676 }
1677
1678 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1679 {
1680         int result;
1681         u32 aqa;
1682         struct nvme_queue *nvmeq;
1683
1684         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1685         if (result < 0)
1686                 return result;
1687
1688         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1689                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1690
1691         if (dev->subsystem &&
1692             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1693                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1694
1695         result = nvme_disable_ctrl(&dev->ctrl);
1696         if (result < 0)
1697                 return result;
1698
1699         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1700         if (result)
1701                 return result;
1702
1703         dev->ctrl.numa_node = dev_to_node(dev->dev);
1704
1705         nvmeq = &dev->queues[0];
1706         aqa = nvmeq->q_depth - 1;
1707         aqa |= aqa << 16;
1708
1709         writel(aqa, dev->bar + NVME_REG_AQA);
1710         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1711         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1712
1713         result = nvme_enable_ctrl(&dev->ctrl);
1714         if (result)
1715                 return result;
1716
1717         nvmeq->cq_vector = 0;
1718         nvme_init_queue(nvmeq, 0);
1719         result = queue_request_irq(nvmeq);
1720         if (result) {
1721                 dev->online_queues--;
1722                 return result;
1723         }
1724
1725         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1726         return result;
1727 }
1728
1729 static int nvme_create_io_queues(struct nvme_dev *dev)
1730 {
1731         unsigned i, max, rw_queues;
1732         int ret = 0;
1733
1734         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1735                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1736                         ret = -ENOMEM;
1737                         break;
1738                 }
1739         }
1740
1741         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1742         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1743                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1744                                 dev->io_queues[HCTX_TYPE_READ];
1745         } else {
1746                 rw_queues = max;
1747         }
1748
1749         for (i = dev->online_queues; i <= max; i++) {
1750                 bool polled = i > rw_queues;
1751
1752                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1753                 if (ret)
1754                         break;
1755         }
1756
1757         /*
1758          * Ignore failing Create SQ/CQ commands, we can continue with less
1759          * than the desired amount of queues, and even a controller without
1760          * I/O queues can still be used to issue admin commands.  This might
1761          * be useful to upgrade a buggy firmware for example.
1762          */
1763         return ret >= 0 ? 0 : ret;
1764 }
1765
1766 static ssize_t nvme_cmb_show(struct device *dev,
1767                              struct device_attribute *attr,
1768                              char *buf)
1769 {
1770         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1771
1772         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1773                        ndev->cmbloc, ndev->cmbsz);
1774 }
1775 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1776
1777 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1778 {
1779         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1780
1781         return 1ULL << (12 + 4 * szu);
1782 }
1783
1784 static u32 nvme_cmb_size(struct nvme_dev *dev)
1785 {
1786         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1787 }
1788
1789 static void nvme_map_cmb(struct nvme_dev *dev)
1790 {
1791         u64 size, offset;
1792         resource_size_t bar_size;
1793         struct pci_dev *pdev = to_pci_dev(dev->dev);
1794         int bar;
1795
1796         if (dev->cmb_size)
1797                 return;
1798
1799         if (NVME_CAP_CMBS(dev->ctrl.cap))
1800                 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1801
1802         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1803         if (!dev->cmbsz)
1804                 return;
1805         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1806
1807         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1808         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1809         bar = NVME_CMB_BIR(dev->cmbloc);
1810         bar_size = pci_resource_len(pdev, bar);
1811
1812         if (offset > bar_size)
1813                 return;
1814
1815         /*
1816          * Tell the controller about the host side address mapping the CMB,
1817          * and enable CMB decoding for the NVMe 1.4+ scheme:
1818          */
1819         if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1820                 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1821                              (pci_bus_address(pdev, bar) + offset),
1822                              dev->bar + NVME_REG_CMBMSC);
1823         }
1824
1825         /*
1826          * Controllers may support a CMB size larger than their BAR,
1827          * for example, due to being behind a bridge. Reduce the CMB to
1828          * the reported size of the BAR
1829          */
1830         if (size > bar_size - offset)
1831                 size = bar_size - offset;
1832
1833         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1834                 dev_warn(dev->ctrl.device,
1835                          "failed to register the CMB\n");
1836                 return;
1837         }
1838
1839         dev->cmb_size = size;
1840         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1841
1842         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1843                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1844                 pci_p2pmem_publish(pdev, true);
1845
1846         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1847                                     &dev_attr_cmb.attr, NULL))
1848                 dev_warn(dev->ctrl.device,
1849                          "failed to add sysfs attribute for CMB\n");
1850 }
1851
1852 static inline void nvme_release_cmb(struct nvme_dev *dev)
1853 {
1854         if (dev->cmb_size) {
1855                 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1856                                              &dev_attr_cmb.attr, NULL);
1857                 dev->cmb_size = 0;
1858         }
1859 }
1860
1861 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1862 {
1863         u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1864         u64 dma_addr = dev->host_mem_descs_dma;
1865         struct nvme_command c;
1866         int ret;
1867
1868         memset(&c, 0, sizeof(c));
1869         c.features.opcode       = nvme_admin_set_features;
1870         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1871         c.features.dword11      = cpu_to_le32(bits);
1872         c.features.dword12      = cpu_to_le32(host_mem_size);
1873         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1874         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1875         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1876
1877         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1878         if (ret) {
1879                 dev_warn(dev->ctrl.device,
1880                          "failed to set host mem (err %d, flags %#x).\n",
1881                          ret, bits);
1882         }
1883         return ret;
1884 }
1885
1886 static void nvme_free_host_mem(struct nvme_dev *dev)
1887 {
1888         int i;
1889
1890         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1891                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1892                 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1893
1894                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1895                                le64_to_cpu(desc->addr),
1896                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1897         }
1898
1899         kfree(dev->host_mem_desc_bufs);
1900         dev->host_mem_desc_bufs = NULL;
1901         dma_free_coherent(dev->dev,
1902                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1903                         dev->host_mem_descs, dev->host_mem_descs_dma);
1904         dev->host_mem_descs = NULL;
1905         dev->nr_host_mem_descs = 0;
1906 }
1907
1908 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1909                 u32 chunk_size)
1910 {
1911         struct nvme_host_mem_buf_desc *descs;
1912         u32 max_entries, len;
1913         dma_addr_t descs_dma;
1914         int i = 0;
1915         void **bufs;
1916         u64 size, tmp;
1917
1918         tmp = (preferred + chunk_size - 1);
1919         do_div(tmp, chunk_size);
1920         max_entries = tmp;
1921
1922         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1923                 max_entries = dev->ctrl.hmmaxd;
1924
1925         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1926                                    &descs_dma, GFP_KERNEL);
1927         if (!descs)
1928                 goto out;
1929
1930         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1931         if (!bufs)
1932                 goto out_free_descs;
1933
1934         for (size = 0; size < preferred && i < max_entries; size += len) {
1935                 dma_addr_t dma_addr;
1936
1937                 len = min_t(u64, chunk_size, preferred - size);
1938                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1939                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1940                 if (!bufs[i])
1941                         break;
1942
1943                 descs[i].addr = cpu_to_le64(dma_addr);
1944                 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1945                 i++;
1946         }
1947
1948         if (!size)
1949                 goto out_free_bufs;
1950
1951         dev->nr_host_mem_descs = i;
1952         dev->host_mem_size = size;
1953         dev->host_mem_descs = descs;
1954         dev->host_mem_descs_dma = descs_dma;
1955         dev->host_mem_desc_bufs = bufs;
1956         return 0;
1957
1958 out_free_bufs:
1959         while (--i >= 0) {
1960                 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1961
1962                 dma_free_attrs(dev->dev, size, bufs[i],
1963                                le64_to_cpu(descs[i].addr),
1964                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1965         }
1966
1967         kfree(bufs);
1968 out_free_descs:
1969         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1970                         descs_dma);
1971 out:
1972         dev->host_mem_descs = NULL;
1973         return -ENOMEM;
1974 }
1975
1976 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1977 {
1978         u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1979         u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1980         u64 chunk_size;
1981
1982         /* start big and work our way down */
1983         for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
1984                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1985                         if (!min || dev->host_mem_size >= min)
1986                                 return 0;
1987                         nvme_free_host_mem(dev);
1988                 }
1989         }
1990
1991         return -ENOMEM;
1992 }
1993
1994 static int nvme_setup_host_mem(struct nvme_dev *dev)
1995 {
1996         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1997         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1998         u64 min = (u64)dev->ctrl.hmmin * 4096;
1999         u32 enable_bits = NVME_HOST_MEM_ENABLE;
2000         int ret;
2001
2002         preferred = min(preferred, max);
2003         if (min > max) {
2004                 dev_warn(dev->ctrl.device,
2005                         "min host memory (%lld MiB) above limit (%d MiB).\n",
2006                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
2007                 nvme_free_host_mem(dev);
2008                 return 0;
2009         }
2010
2011         /*
2012          * If we already have a buffer allocated check if we can reuse it.
2013          */
2014         if (dev->host_mem_descs) {
2015                 if (dev->host_mem_size >= min)
2016                         enable_bits |= NVME_HOST_MEM_RETURN;
2017                 else
2018                         nvme_free_host_mem(dev);
2019         }
2020
2021         if (!dev->host_mem_descs) {
2022                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2023                         dev_warn(dev->ctrl.device,
2024                                 "failed to allocate host memory buffer.\n");
2025                         return 0; /* controller must work without HMB */
2026                 }
2027
2028                 dev_info(dev->ctrl.device,
2029                         "allocated %lld MiB host memory buffer.\n",
2030                         dev->host_mem_size >> ilog2(SZ_1M));
2031         }
2032
2033         ret = nvme_set_host_mem(dev, enable_bits);
2034         if (ret)
2035                 nvme_free_host_mem(dev);
2036         return ret;
2037 }
2038
2039 /*
2040  * nirqs is the number of interrupts available for write and read
2041  * queues. The core already reserved an interrupt for the admin queue.
2042  */
2043 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2044 {
2045         struct nvme_dev *dev = affd->priv;
2046         unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2047
2048         /*
2049          * If there is no interrupt available for queues, ensure that
2050          * the default queue is set to 1. The affinity set size is
2051          * also set to one, but the irq core ignores it for this case.
2052          *
2053          * If only one interrupt is available or 'write_queue' == 0, combine
2054          * write and read queues.
2055          *
2056          * If 'write_queues' > 0, ensure it leaves room for at least one read
2057          * queue.
2058          */
2059         if (!nrirqs) {
2060                 nrirqs = 1;
2061                 nr_read_queues = 0;
2062         } else if (nrirqs == 1 || !nr_write_queues) {
2063                 nr_read_queues = 0;
2064         } else if (nr_write_queues >= nrirqs) {
2065                 nr_read_queues = 1;
2066         } else {
2067                 nr_read_queues = nrirqs - nr_write_queues;
2068         }
2069
2070         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2071         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2072         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2073         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2074         affd->nr_sets = nr_read_queues ? 2 : 1;
2075 }
2076
2077 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2078 {
2079         struct pci_dev *pdev = to_pci_dev(dev->dev);
2080         struct irq_affinity affd = {
2081                 .pre_vectors    = 1,
2082                 .calc_sets      = nvme_calc_irq_sets,
2083                 .priv           = dev,
2084         };
2085         unsigned int irq_queues, poll_queues;
2086
2087         /*
2088          * Poll queues don't need interrupts, but we need at least one I/O queue
2089          * left over for non-polled I/O.
2090          */
2091         poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2092         dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2093
2094         /*
2095          * Initialize for the single interrupt case, will be updated in
2096          * nvme_calc_irq_sets().
2097          */
2098         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2099         dev->io_queues[HCTX_TYPE_READ] = 0;
2100
2101         /*
2102          * We need interrupts for the admin queue and each non-polled I/O queue,
2103          * but some Apple controllers require all queues to use the first
2104          * vector.
2105          */
2106         irq_queues = 1;
2107         if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2108                 irq_queues += (nr_io_queues - poll_queues);
2109         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2110                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2111 }
2112
2113 static void nvme_disable_io_queues(struct nvme_dev *dev)
2114 {
2115         if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2116                 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2117 }
2118
2119 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2120 {
2121         /*
2122          * If tags are shared with admin queue (Apple bug), then
2123          * make sure we only use one IO queue.
2124          */
2125         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2126                 return 1;
2127         return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2128 }
2129
2130 static int nvme_setup_io_queues(struct nvme_dev *dev)
2131 {
2132         struct nvme_queue *adminq = &dev->queues[0];
2133         struct pci_dev *pdev = to_pci_dev(dev->dev);
2134         unsigned int nr_io_queues;
2135         unsigned long size;
2136         int result;
2137
2138         /*
2139          * Sample the module parameters once at reset time so that we have
2140          * stable values to work with.
2141          */
2142         dev->nr_write_queues = write_queues;
2143         dev->nr_poll_queues = poll_queues;
2144
2145         nr_io_queues = dev->nr_allocated_queues - 1;
2146         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2147         if (result < 0)
2148                 return result;
2149
2150         if (nr_io_queues == 0)
2151                 return 0;
2152
2153         clear_bit(NVMEQ_ENABLED, &adminq->flags);
2154
2155         if (dev->cmb_use_sqes) {
2156                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2157                                 sizeof(struct nvme_command));
2158                 if (result > 0)
2159                         dev->q_depth = result;
2160                 else
2161                         dev->cmb_use_sqes = false;
2162         }
2163
2164         do {
2165                 size = db_bar_size(dev, nr_io_queues);
2166                 result = nvme_remap_bar(dev, size);
2167                 if (!result)
2168                         break;
2169                 if (!--nr_io_queues)
2170                         return -ENOMEM;
2171         } while (1);
2172         adminq->q_db = dev->dbs;
2173
2174  retry:
2175         /* Deregister the admin queue's interrupt */
2176         pci_free_irq(pdev, 0, adminq);
2177
2178         /*
2179          * If we enable msix early due to not intx, disable it again before
2180          * setting up the full range we need.
2181          */
2182         pci_free_irq_vectors(pdev);
2183
2184         result = nvme_setup_irqs(dev, nr_io_queues);
2185         if (result <= 0)
2186                 return -EIO;
2187
2188         dev->num_vecs = result;
2189         result = max(result - 1, 1);
2190         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2191
2192         /*
2193          * Should investigate if there's a performance win from allocating
2194          * more queues than interrupt vectors; it might allow the submission
2195          * path to scale better, even if the receive path is limited by the
2196          * number of interrupts.
2197          */
2198         result = queue_request_irq(adminq);
2199         if (result)
2200                 return result;
2201         set_bit(NVMEQ_ENABLED, &adminq->flags);
2202
2203         result = nvme_create_io_queues(dev);
2204         if (result || dev->online_queues < 2)
2205                 return result;
2206
2207         if (dev->online_queues - 1 < dev->max_qid) {
2208                 nr_io_queues = dev->online_queues - 1;
2209                 nvme_disable_io_queues(dev);
2210                 nvme_suspend_io_queues(dev);
2211                 goto retry;
2212         }
2213         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2214                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2215                                         dev->io_queues[HCTX_TYPE_READ],
2216                                         dev->io_queues[HCTX_TYPE_POLL]);
2217         return 0;
2218 }
2219
2220 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2221 {
2222         struct nvme_queue *nvmeq = req->end_io_data;
2223
2224         blk_mq_free_request(req);
2225         complete(&nvmeq->delete_done);
2226 }
2227
2228 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2229 {
2230         struct nvme_queue *nvmeq = req->end_io_data;
2231
2232         if (error)
2233                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2234
2235         nvme_del_queue_end(req, error);
2236 }
2237
2238 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2239 {
2240         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2241         struct request *req;
2242         struct nvme_command cmd;
2243
2244         memset(&cmd, 0, sizeof(cmd));
2245         cmd.delete_queue.opcode = opcode;
2246         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2247
2248         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
2249         if (IS_ERR(req))
2250                 return PTR_ERR(req);
2251
2252         req->end_io_data = nvmeq;
2253
2254         init_completion(&nvmeq->delete_done);
2255         blk_execute_rq_nowait(q, NULL, req, false,
2256                         opcode == nvme_admin_delete_cq ?
2257                                 nvme_del_cq_end : nvme_del_queue_end);
2258         return 0;
2259 }
2260
2261 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2262 {
2263         int nr_queues = dev->online_queues - 1, sent = 0;
2264         unsigned long timeout;
2265
2266  retry:
2267         timeout = NVME_ADMIN_TIMEOUT;
2268         while (nr_queues > 0) {
2269                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2270                         break;
2271                 nr_queues--;
2272                 sent++;
2273         }
2274         while (sent) {
2275                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2276
2277                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2278                                 timeout);
2279                 if (timeout == 0)
2280                         return false;
2281
2282                 sent--;
2283                 if (nr_queues)
2284                         goto retry;
2285         }
2286         return true;
2287 }
2288
2289 static void nvme_dev_add(struct nvme_dev *dev)
2290 {
2291         int ret;
2292
2293         if (!dev->ctrl.tagset) {
2294                 dev->tagset.ops = &nvme_mq_ops;
2295                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2296                 dev->tagset.nr_maps = 2; /* default + read */
2297                 if (dev->io_queues[HCTX_TYPE_POLL])
2298                         dev->tagset.nr_maps++;
2299                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2300                 dev->tagset.numa_node = dev->ctrl.numa_node;
2301                 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2302                                                 BLK_MQ_MAX_DEPTH) - 1;
2303                 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2304                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2305                 dev->tagset.driver_data = dev;
2306
2307                 /*
2308                  * Some Apple controllers requires tags to be unique
2309                  * across admin and IO queue, so reserve the first 32
2310                  * tags of the IO queue.
2311                  */
2312                 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2313                         dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2314
2315                 ret = blk_mq_alloc_tag_set(&dev->tagset);
2316                 if (ret) {
2317                         dev_warn(dev->ctrl.device,
2318                                 "IO queues tagset allocation failed %d\n", ret);
2319                         return;
2320                 }
2321                 dev->ctrl.tagset = &dev->tagset;
2322         } else {
2323                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2324
2325                 /* Free previously allocated queues that are no longer usable */
2326                 nvme_free_queues(dev, dev->online_queues);
2327         }
2328
2329         nvme_dbbuf_set(dev);
2330 }
2331
2332 static int nvme_pci_enable(struct nvme_dev *dev)
2333 {
2334         int result = -ENOMEM;
2335         struct pci_dev *pdev = to_pci_dev(dev->dev);
2336
2337         if (pci_enable_device_mem(pdev))
2338                 return result;
2339
2340         pci_set_master(pdev);
2341
2342         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
2343                 goto disable;
2344
2345         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2346                 result = -ENODEV;
2347                 goto disable;
2348         }
2349
2350         /*
2351          * Some devices and/or platforms don't advertise or work with INTx
2352          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2353          * adjust this later.
2354          */
2355         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2356         if (result < 0)
2357                 return result;
2358
2359         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2360
2361         dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2362                                 io_queue_depth);
2363         dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2364         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2365         dev->dbs = dev->bar + 4096;
2366
2367         /*
2368          * Some Apple controllers require a non-standard SQE size.
2369          * Interestingly they also seem to ignore the CC:IOSQES register
2370          * so we don't bother updating it here.
2371          */
2372         if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2373                 dev->io_sqes = 7;
2374         else
2375                 dev->io_sqes = NVME_NVM_IOSQES;
2376
2377         /*
2378          * Temporary fix for the Apple controller found in the MacBook8,1 and
2379          * some MacBook7,1 to avoid controller resets and data loss.
2380          */
2381         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2382                 dev->q_depth = 2;
2383                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2384                         "set queue depth=%u to work around controller resets\n",
2385                         dev->q_depth);
2386         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2387                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2388                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2389                 dev->q_depth = 64;
2390                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2391                         "set queue depth=%u\n", dev->q_depth);
2392         }
2393
2394         /*
2395          * Controllers with the shared tags quirk need the IO queue to be
2396          * big enough so that we get 32 tags for the admin queue
2397          */
2398         if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2399             (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2400                 dev->q_depth = NVME_AQ_DEPTH + 2;
2401                 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2402                          dev->q_depth);
2403         }
2404
2405
2406         nvme_map_cmb(dev);
2407
2408         pci_enable_pcie_error_reporting(pdev);
2409         pci_save_state(pdev);
2410         return 0;
2411
2412  disable:
2413         pci_disable_device(pdev);
2414         return result;
2415 }
2416
2417 static void nvme_dev_unmap(struct nvme_dev *dev)
2418 {
2419         if (dev->bar)
2420                 iounmap(dev->bar);
2421         pci_release_mem_regions(to_pci_dev(dev->dev));
2422 }
2423
2424 static void nvme_pci_disable(struct nvme_dev *dev)
2425 {
2426         struct pci_dev *pdev = to_pci_dev(dev->dev);
2427
2428         pci_free_irq_vectors(pdev);
2429
2430         if (pci_is_enabled(pdev)) {
2431                 pci_disable_pcie_error_reporting(pdev);
2432                 pci_disable_device(pdev);
2433         }
2434 }
2435
2436 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2437 {
2438         bool dead = true, freeze = false;
2439         struct pci_dev *pdev = to_pci_dev(dev->dev);
2440
2441         mutex_lock(&dev->shutdown_lock);
2442         if (pci_is_enabled(pdev)) {
2443                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2444
2445                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2446                     dev->ctrl.state == NVME_CTRL_RESETTING) {
2447                         freeze = true;
2448                         nvme_start_freeze(&dev->ctrl);
2449                 }
2450                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2451                         pdev->error_state  != pci_channel_io_normal);
2452         }
2453
2454         /*
2455          * Give the controller a chance to complete all entered requests if
2456          * doing a safe shutdown.
2457          */
2458         if (!dead && shutdown && freeze)
2459                 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2460
2461         nvme_stop_queues(&dev->ctrl);
2462
2463         if (!dead && dev->ctrl.queue_count > 0) {
2464                 nvme_disable_io_queues(dev);
2465                 nvme_disable_admin_queue(dev, shutdown);
2466         }
2467         nvme_suspend_io_queues(dev);
2468         nvme_suspend_queue(&dev->queues[0]);
2469         nvme_pci_disable(dev);
2470         nvme_reap_pending_cqes(dev);
2471
2472         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2473         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2474         blk_mq_tagset_wait_completed_request(&dev->tagset);
2475         blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2476
2477         /*
2478          * The driver will not be starting up queues again if shutting down so
2479          * must flush all entered requests to their failed completion to avoid
2480          * deadlocking blk-mq hot-cpu notifier.
2481          */
2482         if (shutdown) {
2483                 nvme_start_queues(&dev->ctrl);
2484                 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2485                         blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2486         }
2487         mutex_unlock(&dev->shutdown_lock);
2488 }
2489
2490 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2491 {
2492         if (!nvme_wait_reset(&dev->ctrl))
2493                 return -EBUSY;
2494         nvme_dev_disable(dev, shutdown);
2495         return 0;
2496 }
2497
2498 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2499 {
2500         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2501                                                 NVME_CTRL_PAGE_SIZE,
2502                                                 NVME_CTRL_PAGE_SIZE, 0);
2503         if (!dev->prp_page_pool)
2504                 return -ENOMEM;
2505
2506         /* Optimisation for I/Os between 4k and 128k */
2507         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2508                                                 256, 256, 0);
2509         if (!dev->prp_small_pool) {
2510                 dma_pool_destroy(dev->prp_page_pool);
2511                 return -ENOMEM;
2512         }
2513         return 0;
2514 }
2515
2516 static void nvme_release_prp_pools(struct nvme_dev *dev)
2517 {
2518         dma_pool_destroy(dev->prp_page_pool);
2519         dma_pool_destroy(dev->prp_small_pool);
2520 }
2521
2522 static void nvme_free_tagset(struct nvme_dev *dev)
2523 {
2524         if (dev->tagset.tags)
2525                 blk_mq_free_tag_set(&dev->tagset);
2526         dev->ctrl.tagset = NULL;
2527 }
2528
2529 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2530 {
2531         struct nvme_dev *dev = to_nvme_dev(ctrl);
2532
2533         nvme_dbbuf_dma_free(dev);
2534         nvme_free_tagset(dev);
2535         if (dev->ctrl.admin_q)
2536                 blk_put_queue(dev->ctrl.admin_q);
2537         free_opal_dev(dev->ctrl.opal_dev);
2538         mempool_destroy(dev->iod_mempool);
2539         put_device(dev->dev);
2540         kfree(dev->queues);
2541         kfree(dev);
2542 }
2543
2544 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2545 {
2546         /*
2547          * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2548          * may be holding this pci_dev's device lock.
2549          */
2550         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2551         nvme_get_ctrl(&dev->ctrl);
2552         nvme_dev_disable(dev, false);
2553         nvme_kill_queues(&dev->ctrl);
2554         if (!queue_work(nvme_wq, &dev->remove_work))
2555                 nvme_put_ctrl(&dev->ctrl);
2556 }
2557
2558 static void nvme_reset_work(struct work_struct *work)
2559 {
2560         struct nvme_dev *dev =
2561                 container_of(work, struct nvme_dev, ctrl.reset_work);
2562         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2563         int result;
2564
2565         if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2566                 result = -ENODEV;
2567                 goto out;
2568         }
2569
2570         /*
2571          * If we're called to reset a live controller first shut it down before
2572          * moving on.
2573          */
2574         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2575                 nvme_dev_disable(dev, false);
2576         nvme_sync_queues(&dev->ctrl);
2577
2578         mutex_lock(&dev->shutdown_lock);
2579         result = nvme_pci_enable(dev);
2580         if (result)
2581                 goto out_unlock;
2582
2583         result = nvme_pci_configure_admin_queue(dev);
2584         if (result)
2585                 goto out_unlock;
2586
2587         result = nvme_alloc_admin_tags(dev);
2588         if (result)
2589                 goto out_unlock;
2590
2591         /*
2592          * Limit the max command size to prevent iod->sg allocations going
2593          * over a single page.
2594          */
2595         dev->ctrl.max_hw_sectors = min_t(u32,
2596                 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2597         dev->ctrl.max_segments = NVME_MAX_SEGS;
2598
2599         /*
2600          * Don't limit the IOMMU merged segment size.
2601          */
2602         dma_set_max_seg_size(dev->dev, 0xffffffff);
2603
2604         mutex_unlock(&dev->shutdown_lock);
2605
2606         /*
2607          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2608          * initializing procedure here.
2609          */
2610         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2611                 dev_warn(dev->ctrl.device,
2612                         "failed to mark controller CONNECTING\n");
2613                 result = -EBUSY;
2614                 goto out;
2615         }
2616
2617         /*
2618          * We do not support an SGL for metadata (yet), so we are limited to a
2619          * single integrity segment for the separate metadata pointer.
2620          */
2621         dev->ctrl.max_integrity_segments = 1;
2622
2623         result = nvme_init_identify(&dev->ctrl);
2624         if (result)
2625                 goto out;
2626
2627         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2628                 if (!dev->ctrl.opal_dev)
2629                         dev->ctrl.opal_dev =
2630                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2631                 else if (was_suspend)
2632                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2633         } else {
2634                 free_opal_dev(dev->ctrl.opal_dev);
2635                 dev->ctrl.opal_dev = NULL;
2636         }
2637
2638         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2639                 result = nvme_dbbuf_dma_alloc(dev);
2640                 if (result)
2641                         dev_warn(dev->dev,
2642                                  "unable to allocate dma for dbbuf\n");
2643         }
2644
2645         if (dev->ctrl.hmpre) {
2646                 result = nvme_setup_host_mem(dev);
2647                 if (result < 0)
2648                         goto out;
2649         }
2650
2651         result = nvme_setup_io_queues(dev);
2652         if (result)
2653                 goto out;
2654
2655         /*
2656          * Keep the controller around but remove all namespaces if we don't have
2657          * any working I/O queue.
2658          */
2659         if (dev->online_queues < 2) {
2660                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2661                 nvme_kill_queues(&dev->ctrl);
2662                 nvme_remove_namespaces(&dev->ctrl);
2663                 nvme_free_tagset(dev);
2664         } else {
2665                 nvme_start_queues(&dev->ctrl);
2666                 nvme_wait_freeze(&dev->ctrl);
2667                 nvme_dev_add(dev);
2668                 nvme_unfreeze(&dev->ctrl);
2669         }
2670
2671         /*
2672          * If only admin queue live, keep it to do further investigation or
2673          * recovery.
2674          */
2675         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2676                 dev_warn(dev->ctrl.device,
2677                         "failed to mark controller live state\n");
2678                 result = -ENODEV;
2679                 goto out;
2680         }
2681
2682         nvme_start_ctrl(&dev->ctrl);
2683         return;
2684
2685  out_unlock:
2686         mutex_unlock(&dev->shutdown_lock);
2687  out:
2688         if (result)
2689                 dev_warn(dev->ctrl.device,
2690                          "Removing after probe failure status: %d\n", result);
2691         nvme_remove_dead_ctrl(dev);
2692 }
2693
2694 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2695 {
2696         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2697         struct pci_dev *pdev = to_pci_dev(dev->dev);
2698
2699         if (pci_get_drvdata(pdev))
2700                 device_release_driver(&pdev->dev);
2701         nvme_put_ctrl(&dev->ctrl);
2702 }
2703
2704 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2705 {
2706         *val = readl(to_nvme_dev(ctrl)->bar + off);
2707         return 0;
2708 }
2709
2710 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2711 {
2712         writel(val, to_nvme_dev(ctrl)->bar + off);
2713         return 0;
2714 }
2715
2716 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2717 {
2718         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2719         return 0;
2720 }
2721
2722 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2723 {
2724         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2725
2726         return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2727 }
2728
2729 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2730         .name                   = "pcie",
2731         .module                 = THIS_MODULE,
2732         .flags                  = NVME_F_METADATA_SUPPORTED |
2733                                   NVME_F_PCI_P2PDMA,
2734         .reg_read32             = nvme_pci_reg_read32,
2735         .reg_write32            = nvme_pci_reg_write32,
2736         .reg_read64             = nvme_pci_reg_read64,
2737         .free_ctrl              = nvme_pci_free_ctrl,
2738         .submit_async_event     = nvme_pci_submit_async_event,
2739         .get_address            = nvme_pci_get_address,
2740 };
2741
2742 static int nvme_dev_map(struct nvme_dev *dev)
2743 {
2744         struct pci_dev *pdev = to_pci_dev(dev->dev);
2745
2746         if (pci_request_mem_regions(pdev, "nvme"))
2747                 return -ENODEV;
2748
2749         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2750                 goto release;
2751
2752         return 0;
2753   release:
2754         pci_release_mem_regions(pdev);
2755         return -ENODEV;
2756 }
2757
2758 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2759 {
2760         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2761                 /*
2762                  * Several Samsung devices seem to drop off the PCIe bus
2763                  * randomly when APST is on and uses the deepest sleep state.
2764                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2765                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2766                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2767                  * laptops.
2768                  */
2769                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2770                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2771                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2772                         return NVME_QUIRK_NO_DEEPEST_PS;
2773         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2774                 /*
2775                  * Samsung SSD 960 EVO drops off the PCIe bus after system
2776                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2777                  * within few minutes after bootup on a Coffee Lake board -
2778                  * ASUS PRIME Z370-A
2779                  */
2780                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2781                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2782                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2783                         return NVME_QUIRK_NO_APST;
2784         } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2785                     pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2786                    (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2787                 /*
2788                  * Forcing to use host managed nvme power settings for
2789                  * lowest idle power with quick resume latency on
2790                  * Samsung and Toshiba SSDs based on suspend behavior
2791                  * on Coffee Lake board for LENOVO C640
2792                  */
2793                 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2794                      dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2795                         return NVME_QUIRK_SIMPLE_SUSPEND;
2796         }
2797
2798         return 0;
2799 }
2800
2801 #ifdef CONFIG_ACPI
2802 static bool nvme_acpi_storage_d3(struct pci_dev *dev)
2803 {
2804         struct acpi_device *adev;
2805         struct pci_dev *root;
2806         acpi_handle handle;
2807         acpi_status status;
2808         u8 val;
2809
2810         /*
2811          * Look for _DSD property specifying that the storage device on the port
2812          * must use D3 to support deep platform power savings during
2813          * suspend-to-idle.
2814          */
2815         root = pcie_find_root_port(dev);
2816         if (!root)
2817                 return false;
2818
2819         adev = ACPI_COMPANION(&root->dev);
2820         if (!adev)
2821                 return false;
2822
2823         /*
2824          * The property is defined in the PXSX device for South complex ports
2825          * and in the PEGP device for North complex ports.
2826          */
2827         status = acpi_get_handle(adev->handle, "PXSX", &handle);
2828         if (ACPI_FAILURE(status)) {
2829                 status = acpi_get_handle(adev->handle, "PEGP", &handle);
2830                 if (ACPI_FAILURE(status))
2831                         return false;
2832         }
2833
2834         if (acpi_bus_get_device(handle, &adev))
2835                 return false;
2836
2837         if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
2838                         &val))
2839                 return false;
2840         return val == 1;
2841 }
2842 #else
2843 static inline bool nvme_acpi_storage_d3(struct pci_dev *dev)
2844 {
2845         return false;
2846 }
2847 #endif /* CONFIG_ACPI */
2848
2849 static void nvme_async_probe(void *data, async_cookie_t cookie)
2850 {
2851         struct nvme_dev *dev = data;
2852
2853         flush_work(&dev->ctrl.reset_work);
2854         flush_work(&dev->ctrl.scan_work);
2855         nvme_put_ctrl(&dev->ctrl);
2856 }
2857
2858 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2859 {
2860         int node, result = -ENOMEM;
2861         struct nvme_dev *dev;
2862         unsigned long quirks = id->driver_data;
2863         size_t alloc_size;
2864
2865         node = dev_to_node(&pdev->dev);
2866         if (node == NUMA_NO_NODE)
2867                 set_dev_node(&pdev->dev, first_memory_node);
2868
2869         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2870         if (!dev)
2871                 return -ENOMEM;
2872
2873         dev->nr_write_queues = write_queues;
2874         dev->nr_poll_queues = poll_queues;
2875         dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2876         dev->queues = kcalloc_node(dev->nr_allocated_queues,
2877                         sizeof(struct nvme_queue), GFP_KERNEL, node);
2878         if (!dev->queues)
2879                 goto free;
2880
2881         dev->dev = get_device(&pdev->dev);
2882         pci_set_drvdata(pdev, dev);
2883
2884         result = nvme_dev_map(dev);
2885         if (result)
2886                 goto put_pci;
2887
2888         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2889         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2890         mutex_init(&dev->shutdown_lock);
2891
2892         result = nvme_setup_prp_pools(dev);
2893         if (result)
2894                 goto unmap;
2895
2896         quirks |= check_vendor_combination_bug(pdev);
2897
2898         if (!noacpi && nvme_acpi_storage_d3(pdev)) {
2899                 /*
2900                  * Some systems use a bios work around to ask for D3 on
2901                  * platforms that support kernel managed suspend.
2902                  */
2903                 dev_info(&pdev->dev,
2904                          "platform quirk: setting simple suspend\n");
2905                 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2906         }
2907
2908         /*
2909          * Double check that our mempool alloc size will cover the biggest
2910          * command we support.
2911          */
2912         alloc_size = nvme_pci_iod_alloc_size();
2913         WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2914
2915         dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2916                                                 mempool_kfree,
2917                                                 (void *) alloc_size,
2918                                                 GFP_KERNEL, node);
2919         if (!dev->iod_mempool) {
2920                 result = -ENOMEM;
2921                 goto release_pools;
2922         }
2923
2924         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2925                         quirks);
2926         if (result)
2927                 goto release_mempool;
2928
2929         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2930
2931         nvme_reset_ctrl(&dev->ctrl);
2932         async_schedule(nvme_async_probe, dev);
2933
2934         return 0;
2935
2936  release_mempool:
2937         mempool_destroy(dev->iod_mempool);
2938  release_pools:
2939         nvme_release_prp_pools(dev);
2940  unmap:
2941         nvme_dev_unmap(dev);
2942  put_pci:
2943         put_device(dev->dev);
2944  free:
2945         kfree(dev->queues);
2946         kfree(dev);
2947         return result;
2948 }
2949
2950 static void nvme_reset_prepare(struct pci_dev *pdev)
2951 {
2952         struct nvme_dev *dev = pci_get_drvdata(pdev);
2953
2954         /*
2955          * We don't need to check the return value from waiting for the reset
2956          * state as pci_dev device lock is held, making it impossible to race
2957          * with ->remove().
2958          */
2959         nvme_disable_prepare_reset(dev, false);
2960         nvme_sync_queues(&dev->ctrl);
2961 }
2962
2963 static void nvme_reset_done(struct pci_dev *pdev)
2964 {
2965         struct nvme_dev *dev = pci_get_drvdata(pdev);
2966
2967         if (!nvme_try_sched_reset(&dev->ctrl))
2968                 flush_work(&dev->ctrl.reset_work);
2969 }
2970
2971 static void nvme_shutdown(struct pci_dev *pdev)
2972 {
2973         struct nvme_dev *dev = pci_get_drvdata(pdev);
2974
2975         nvme_disable_prepare_reset(dev, true);
2976 }
2977
2978 /*
2979  * The driver's remove may be called on a device in a partially initialized
2980  * state. This function must not have any dependencies on the device state in
2981  * order to proceed.
2982  */
2983 static void nvme_remove(struct pci_dev *pdev)
2984 {
2985         struct nvme_dev *dev = pci_get_drvdata(pdev);
2986
2987         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2988         pci_set_drvdata(pdev, NULL);
2989
2990         if (!pci_device_is_present(pdev)) {
2991                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2992                 nvme_dev_disable(dev, true);
2993                 nvme_dev_remove_admin(dev);
2994         }
2995
2996         flush_work(&dev->ctrl.reset_work);
2997         nvme_stop_ctrl(&dev->ctrl);
2998         nvme_remove_namespaces(&dev->ctrl);
2999         nvme_dev_disable(dev, true);
3000         nvme_release_cmb(dev);
3001         nvme_free_host_mem(dev);
3002         nvme_dev_remove_admin(dev);
3003         nvme_free_queues(dev, 0);
3004         nvme_release_prp_pools(dev);
3005         nvme_dev_unmap(dev);
3006         nvme_uninit_ctrl(&dev->ctrl);
3007 }
3008
3009 #ifdef CONFIG_PM_SLEEP
3010 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3011 {
3012         return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3013 }
3014
3015 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3016 {
3017         return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3018 }
3019
3020 static int nvme_resume(struct device *dev)
3021 {
3022         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3023         struct nvme_ctrl *ctrl = &ndev->ctrl;
3024
3025         if (ndev->last_ps == U32_MAX ||
3026             nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3027                 return nvme_try_sched_reset(&ndev->ctrl);
3028         return 0;
3029 }
3030
3031 static int nvme_suspend(struct device *dev)
3032 {
3033         struct pci_dev *pdev = to_pci_dev(dev);
3034         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3035         struct nvme_ctrl *ctrl = &ndev->ctrl;
3036         int ret = -EBUSY;
3037
3038         ndev->last_ps = U32_MAX;
3039
3040         /*
3041          * The platform does not remove power for a kernel managed suspend so
3042          * use host managed nvme power settings for lowest idle power if
3043          * possible. This should have quicker resume latency than a full device
3044          * shutdown.  But if the firmware is involved after the suspend or the
3045          * device does not support any non-default power states, shut down the
3046          * device fully.
3047          *
3048          * If ASPM is not enabled for the device, shut down the device and allow
3049          * the PCI bus layer to put it into D3 in order to take the PCIe link
3050          * down, so as to allow the platform to achieve its minimum low-power
3051          * state (which may not be possible if the link is up).
3052          *
3053          * If a host memory buffer is enabled, shut down the device as the NVMe
3054          * specification allows the device to access the host memory buffer in
3055          * host DRAM from all power states, but hosts will fail access to DRAM
3056          * during S3.
3057          */
3058         if (pm_suspend_via_firmware() || !ctrl->npss ||
3059             !pcie_aspm_enabled(pdev) ||
3060             ndev->nr_host_mem_descs ||
3061             (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3062                 return nvme_disable_prepare_reset(ndev, true);
3063
3064         nvme_start_freeze(ctrl);
3065         nvme_wait_freeze(ctrl);
3066         nvme_sync_queues(ctrl);
3067
3068         if (ctrl->state != NVME_CTRL_LIVE)
3069                 goto unfreeze;
3070
3071         ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3072         if (ret < 0)
3073                 goto unfreeze;
3074
3075         /*
3076          * A saved state prevents pci pm from generically controlling the
3077          * device's power. If we're using protocol specific settings, we don't
3078          * want pci interfering.
3079          */
3080         pci_save_state(pdev);
3081
3082         ret = nvme_set_power_state(ctrl, ctrl->npss);
3083         if (ret < 0)
3084                 goto unfreeze;
3085
3086         if (ret) {
3087                 /* discard the saved state */
3088                 pci_load_saved_state(pdev, NULL);
3089
3090                 /*
3091                  * Clearing npss forces a controller reset on resume. The
3092                  * correct value will be rediscovered then.
3093                  */
3094                 ret = nvme_disable_prepare_reset(ndev, true);
3095                 ctrl->npss = 0;
3096         }
3097 unfreeze:
3098         nvme_unfreeze(ctrl);
3099         return ret;
3100 }
3101
3102 static int nvme_simple_suspend(struct device *dev)
3103 {
3104         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3105
3106         return nvme_disable_prepare_reset(ndev, true);
3107 }
3108
3109 static int nvme_simple_resume(struct device *dev)
3110 {
3111         struct pci_dev *pdev = to_pci_dev(dev);
3112         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3113
3114         return nvme_try_sched_reset(&ndev->ctrl);
3115 }
3116
3117 static const struct dev_pm_ops nvme_dev_pm_ops = {
3118         .suspend        = nvme_suspend,
3119         .resume         = nvme_resume,
3120         .freeze         = nvme_simple_suspend,
3121         .thaw           = nvme_simple_resume,
3122         .poweroff       = nvme_simple_suspend,
3123         .restore        = nvme_simple_resume,
3124 };
3125 #endif /* CONFIG_PM_SLEEP */
3126
3127 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3128                                                 pci_channel_state_t state)
3129 {
3130         struct nvme_dev *dev = pci_get_drvdata(pdev);
3131
3132         /*
3133          * A frozen channel requires a reset. When detected, this method will
3134          * shutdown the controller to quiesce. The controller will be restarted
3135          * after the slot reset through driver's slot_reset callback.
3136          */
3137         switch (state) {
3138         case pci_channel_io_normal:
3139                 return PCI_ERS_RESULT_CAN_RECOVER;
3140         case pci_channel_io_frozen:
3141                 dev_warn(dev->ctrl.device,
3142                         "frozen state error detected, reset controller\n");
3143                 nvme_dev_disable(dev, false);
3144                 return PCI_ERS_RESULT_NEED_RESET;
3145         case pci_channel_io_perm_failure:
3146                 dev_warn(dev->ctrl.device,
3147                         "failure state error detected, request disconnect\n");
3148                 return PCI_ERS_RESULT_DISCONNECT;
3149         }
3150         return PCI_ERS_RESULT_NEED_RESET;
3151 }
3152
3153 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3154 {
3155         struct nvme_dev *dev = pci_get_drvdata(pdev);
3156
3157         dev_info(dev->ctrl.device, "restart after slot reset\n");
3158         pci_restore_state(pdev);
3159         nvme_reset_ctrl(&dev->ctrl);
3160         return PCI_ERS_RESULT_RECOVERED;
3161 }
3162
3163 static void nvme_error_resume(struct pci_dev *pdev)
3164 {
3165         struct nvme_dev *dev = pci_get_drvdata(pdev);
3166
3167         flush_work(&dev->ctrl.reset_work);
3168 }
3169
3170 static const struct pci_error_handlers nvme_err_handler = {
3171         .error_detected = nvme_error_detected,
3172         .slot_reset     = nvme_slot_reset,
3173         .resume         = nvme_error_resume,
3174         .reset_prepare  = nvme_reset_prepare,
3175         .reset_done     = nvme_reset_done,
3176 };
3177
3178 static const struct pci_device_id nvme_id_table[] = {
3179         { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3180                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3181                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3182         { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3183                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3184                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3185         { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3186                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3187                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3188         { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3189                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3190                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3191         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3192                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3193                                 NVME_QUIRK_MEDIUM_PRIO_SQ |
3194                                 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3195                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3196         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3197                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3198         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3199                 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3200                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3201         { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3202                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3203         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3204                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3205         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3206                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3207         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3208                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3209         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3210                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3211         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3212                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3213         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3214                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3215                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3216         { PCI_DEVICE(0x1d1d, 0x1f1f),   /* LighNVM qemu device */
3217                 .driver_data = NVME_QUIRK_LIGHTNVM, },
3218         { PCI_DEVICE(0x1d1d, 0x2807),   /* CNEX WL */
3219                 .driver_data = NVME_QUIRK_LIGHTNVM, },
3220         { PCI_DEVICE(0x1d1d, 0x2601),   /* CNEX Granby */
3221                 .driver_data = NVME_QUIRK_LIGHTNVM, },
3222         { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3223                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3224         { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3225                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3226                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3227         { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3228                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3229         { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3230                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3231         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3232                 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3233         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3234         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3235                 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3236                                 NVME_QUIRK_128_BYTES_SQES |
3237                                 NVME_QUIRK_SHARED_TAGS },
3238
3239         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3240         { 0, }
3241 };
3242 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3243
3244 static struct pci_driver nvme_driver = {
3245         .name           = "nvme",
3246         .id_table       = nvme_id_table,
3247         .probe          = nvme_probe,
3248         .remove         = nvme_remove,
3249         .shutdown       = nvme_shutdown,
3250 #ifdef CONFIG_PM_SLEEP
3251         .driver         = {
3252                 .pm     = &nvme_dev_pm_ops,
3253         },
3254 #endif
3255         .sriov_configure = pci_sriov_configure_simple,
3256         .err_handler    = &nvme_err_handler,
3257 };
3258
3259 static int __init nvme_init(void)
3260 {
3261         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3262         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3263         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3264         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3265
3266         return pci_register_driver(&nvme_driver);
3267 }
3268
3269 static void __exit nvme_exit(void)
3270 {
3271         pci_unregister_driver(&nvme_driver);
3272         flush_workqueue(nvme_wq);
3273 }
3274
3275 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3276 MODULE_LICENSE("GPL");
3277 MODULE_VERSION("1.0");
3278 module_init(nvme_init);
3279 module_exit(nvme_exit);