2 * This file is part of wl18xx
4 * Copyright (C) 2011 Texas Instruments. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 #ifndef __WL18XX_ACX_H__
23 #define __WL18XX_ACX_H__
25 #include "../wlcore/wlcore.h"
26 #include "../wlcore/acx.h"
29 ACX_NS_IPV6_FILTER = 0x0050,
30 ACX_PEER_HT_OPERATION_MODE_CFG = 0x0051,
31 ACX_CSUM_CONFIG = 0x0052,
32 ACX_SIM_CONFIG = 0x0053,
33 ACX_CLEAR_STATISTICS = 0x0054,
34 ACX_AUTO_RX_STREAMING = 0x0055,
35 ACX_PEER_CAP = 0x0056,
36 ACX_INTERRUPT_NOTIFY = 0x0057,
37 ACX_RX_BA_FILTER = 0x0058,
38 ACX_AP_SLEEP_CFG = 0x0059
41 /* numbers of bits the length field takes (add 1 for the actual number) */
42 #define WL18XX_HOST_IF_LEN_SIZE_FIELD 15
44 #define WL18XX_ACX_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \
45 WL1271_ACX_INTR_INIT_COMPLETE | \
46 WL1271_ACX_INTR_EVENT_A | \
47 WL1271_ACX_INTR_EVENT_B | \
48 WL1271_ACX_INTR_CMD_COMPLETE | \
49 WL1271_ACX_INTR_HW_AVAILABLE | \
50 WL1271_ACX_INTR_DATA | \
51 WL1271_ACX_SW_INTR_WATCHDOG)
53 #define WL18XX_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \
54 WL1271_ACX_INTR_EVENT_A | \
55 WL1271_ACX_INTR_EVENT_B | \
56 WL1271_ACX_INTR_HW_AVAILABLE | \
57 WL1271_ACX_INTR_DATA | \
58 WL1271_ACX_SW_INTR_WATCHDOG)
60 struct wl18xx_acx_host_config_bitmap {
61 struct acx_header header;
63 __le32 host_cfg_bitmap;
65 __le32 host_sdio_block_size;
67 /* extra mem blocks per frame in TX. */
68 __le32 extra_mem_blocks;
71 * number of bits of the length field in the first TX word
72 * (up to 15 - for using the entire 16 bits).
74 __le32 length_field_size;
79 CHECKSUM_OFFLOAD_DISABLED = 0,
80 CHECKSUM_OFFLOAD_ENABLED = 1,
81 CHECKSUM_OFFLOAD_FAKE_RX = 2,
82 CHECKSUM_OFFLOAD_INVALID = 0xFF
85 struct wl18xx_acx_checksum_state {
86 struct acx_header header;
88 /* enum acx_checksum_state */
94 struct wl18xx_acx_error_stats {
96 u32 error_null_Frame_tx_start;
97 u32 error_numll_frame_cts_start;
99 u32 error_frame_cts_nul_flid;
102 struct wl18xx_acx_debug_stats {
111 struct wl18xx_acx_ring_stats {
116 struct wl18xx_acx_tx_stats {
117 u32 tx_prepared_descs;
119 u32 tx_template_prepared;
120 u32 tx_data_prepared;
121 u32 tx_template_programmed;
122 u32 tx_data_programmed;
123 u32 tx_burst_programmed;
126 u32 tx_start_templates;
127 u32 tx_start_int_templates;
130 u32 tx_start_null_frame;
132 u32 tx_retry_template;
136 u32 tx_done_template;
138 u32 tx_done_int_template;
139 u32 tx_frame_checksum;
140 u32 tx_checksum_result;
142 u32 frag_mpdu_alloc_failed;
143 u32 frag_init_called;
144 u32 frag_in_process_called;
145 u32 frag_tkip_called;
146 u32 frag_key_not_found;
147 u32 frag_need_fragmentation;
148 u32 frag_bad_mblk_num;
154 struct wl18xx_acx_rx_stats {
155 u32 rx_beacon_early_term;
156 u32 rx_out_of_mpdu_nodes;
158 u32 rx_dropped_frame;
169 u32 rx_wa_density_dropped_frame;
170 u32 rx_wa_ba_not_expected;
171 u32 rx_frame_checksum;
172 u32 rx_checksum_result;
174 u32 defrag_init_called;
175 u32 defrag_in_process_called;
176 u32 defrag_tkip_called;
177 u32 defrag_need_defrag;
178 u32 defrag_decrypt_failed;
179 u32 decrypt_key_not_found;
180 u32 defrag_need_decrypt;
184 struct wl18xx_acx_isr_stats {
188 #define PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD 10
190 struct wl18xx_acx_pwr_stats {
191 u32 missing_bcns_cnt;
193 u32 connection_out_of_sync;
194 u32 cont_miss_bcns_spread[PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD];
195 u32 rcvd_awake_bcns_cnt;
198 struct wl18xx_acx_event_stats {
204 struct wl18xx_acx_ps_poll_stats {
205 u32 ps_poll_timeouts;
207 u32 upsd_max_ap_turn;
208 u32 ps_poll_max_ap_turn;
209 u32 ps_poll_utilization;
210 u32 upsd_utilization;
213 struct wl18xx_acx_rx_filter_stats {
220 u32 protection_filter;
221 u32 accum_arp_pend_requests;
222 u32 max_arp_queue_dep;
225 struct wl18xx_acx_rx_rate_stats {
226 u32 rx_frames_per_rates[50];
229 #define AGGR_STATS_TX_AGG 16
230 #define AGGR_STATS_TX_RATE 16
231 #define AGGR_STATS_RX_SIZE_LEN 16
233 struct wl18xx_acx_aggr_stats {
234 u32 tx_agg_vs_rate[AGGR_STATS_TX_AGG * AGGR_STATS_TX_RATE];
235 u32 rx_size[AGGR_STATS_RX_SIZE_LEN];
238 #define PIPE_STATS_HW_FIFO 11
240 struct wl18xx_acx_pipeline_stats {
241 u32 hs_tx_stat_fifo_int;
242 u32 hs_rx_stat_fifo_int;
243 u32 tcp_tx_stat_fifo_int;
244 u32 tcp_rx_stat_fifo_int;
245 u32 enc_tx_stat_fifo_int;
246 u32 enc_rx_stat_fifo_int;
247 u32 rx_complete_stat_fifo_int;
251 u32 pre_to_defrag_swi;
252 u32 defrag_to_csum_swi;
253 u32 csum_to_rx_xfer_swi;
255 u32 dec_packet_in_fifo_full;
258 u32 cs_rx_packet_out;
259 u16 pipeline_fifo_full[PIPE_STATS_HW_FIFO];
262 struct wl18xx_acx_mem_stats {
263 u32 rx_free_mem_blks;
264 u32 tx_free_mem_blks;
265 u32 fwlog_free_mem_blks;
266 u32 fw_gen_free_mem_blks;
269 struct wl18xx_acx_statistics {
270 struct acx_header header;
272 struct wl18xx_acx_error_stats error;
273 struct wl18xx_acx_debug_stats debug;
274 struct wl18xx_acx_tx_stats tx;
275 struct wl18xx_acx_rx_stats rx;
276 struct wl18xx_acx_isr_stats isr;
277 struct wl18xx_acx_pwr_stats pwr;
278 struct wl18xx_acx_ps_poll_stats ps_poll;
279 struct wl18xx_acx_rx_filter_stats rx_filter;
280 struct wl18xx_acx_rx_rate_stats rx_rate;
281 struct wl18xx_acx_aggr_stats aggr_size;
282 struct wl18xx_acx_pipeline_stats pipeline;
283 struct wl18xx_acx_mem_stats mem;
286 struct wl18xx_acx_clear_statistics {
287 struct acx_header header;
290 enum wlcore_bandwidth {
291 WLCORE_BANDWIDTH_20MHZ,
292 WLCORE_BANDWIDTH_40MHZ,
295 struct wlcore_peer_ht_operation_mode {
296 struct acx_header header;
299 u8 bandwidth; /* enum wlcore_bandwidth */
305 * this struct is very similar to wl1271_acx_ht_capabilities, with the
306 * addition of supported rates
308 struct wlcore_acx_peer_cap {
309 struct acx_header header;
311 /* bitmask of capability bits supported by the peer */
312 __le32 ht_capabilites;
314 /* rates supported by the remote peer */
315 __le32 supported_rates;
317 /* Indicates to which link these capabilities apply. */
321 * This the maximum A-MPDU length supported by the AP. The FW may not
322 * exceed this length when sending A-MPDUs
326 /* This is the minimal spacing required when sending A-MPDUs to the AP*/
327 u8 ampdu_min_spacing;
333 * ACX_INTERRUPT_NOTIFY
334 * enable/disable fast-link/PSM notification from FW
336 struct wl18xx_acx_interrupt_notify {
337 struct acx_header header;
343 * enable/disable RX BA filtering in FW
345 struct wl18xx_acx_rx_ba_filter {
346 struct acx_header header;
350 struct acx_ap_sleep_cfg {
351 struct acx_header header;
352 /* Duty Cycle (20-80% of staying Awake) for IDLE AP
356 /* Duty Cycle (20-80% of staying Awake) for Connected AP
359 u8 connected_duty_cycle;
360 /* Maximum stations that are allowed to be connected to AP
363 u8 max_stations_thresh;
364 /* Timeout till enabling the Sleep Mechanism after data stops
370 int wl18xx_acx_host_if_cfg_bitmap(struct wl1271 *wl, u32 host_cfg_bitmap,
371 u32 sdio_blk_size, u32 extra_mem_blks,
373 int wl18xx_acx_set_checksum_state(struct wl1271 *wl);
374 int wl18xx_acx_clear_statistics(struct wl1271 *wl);
375 int wl18xx_acx_peer_ht_operation_mode(struct wl1271 *wl, u8 hlid, bool wide);
376 int wl18xx_acx_set_peer_cap(struct wl1271 *wl,
377 struct ieee80211_sta_ht_cap *ht_cap,
378 bool allow_ht_operation,
379 u32 rate_set, u8 hlid);
380 int wl18xx_acx_interrupt_notify_config(struct wl1271 *wl, bool action);
381 int wl18xx_acx_rx_ba_filter(struct wl1271 *wl, bool action);
382 int wl18xx_acx_ap_sleep(struct wl1271 *wl);
384 #endif /* __WL18XX_ACX_H__ */