drivers/net/wireless/ti/wl12xx/main.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24
  25 #include <linux/err.h>
  26
  27 #include <linux/wl12xx.h>
  28
  29 #include "../wlcore/wlcore.h"
  30 #include "../wlcore/debug.h"
  31 #include "../wlcore/io.h"
  32 #include "../wlcore/acx.h"
  33 #include "../wlcore/tx.h"
  34 #include "../wlcore/rx.h"
  35 #include "../wlcore/io.h"
  36 #include "../wlcore/boot.h"
  37
  38 #include "wl12xx.h"
  39 #include "reg.h"
  40 #include "cmd.h"
  41 #include "acx.h"
  42 #include "debugfs.h"
  43
  44 static char *fref_param;
  45 static char *tcxo_param;
  46
  47 static struct wlcore_conf wl12xx_conf = {
  48         .sg = {
  49                 .params = {
  50                         [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
  51                         [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
  52                         [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
  53                         [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
  54                         [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
  55                         [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
  56                         [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
  57                         [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
  58                         [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
  59                         [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
  60                         [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
  61                         [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
  62                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
  63                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
  64                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
  65                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
  66                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
  67                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
  68                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
  69                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
  70                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
  71                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
  72                         [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
  73                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
  74                         [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
  75                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
  76                         /* active scan params */
  77                         [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
  78                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
  79                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
  80                         /* passive scan params */
  81                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
  82                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
  83                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
  84                         /* passive scan in dual antenna params */
  85                         [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
  86                         [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
  87                         [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
  88                         /* general params */
  89                         [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
  90                         [CONF_SG_ANTENNA_CONFIGURATION] = 0,
  91                         [CONF_SG_BEACON_MISS_PERCENT] = 60,
  92                         [CONF_SG_DHCP_TIME] = 5000,
  93                         [CONF_SG_RXT] = 1200,
  94                         [CONF_SG_TXT] = 1000,
  95                         [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
  96                         [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
  97                         [CONF_SG_HV3_MAX_SERVED] = 6,
  98                         [CONF_SG_PS_POLL_TIMEOUT] = 10,
  99                         [CONF_SG_UPSD_TIMEOUT] = 10,
 100                         [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
 101                         [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
 102                         [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
 103                         /* AP params */
 104                         [CONF_AP_BEACON_MISS_TX] = 3,
 105                         [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
 106                         [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
 107                         [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
 108                         [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
 109                         [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
 110                         /* CTS Diluting params */
 111                         [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
 112                         [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
 113                 },
 114                 .state = CONF_SG_PROTECTIVE,
 115         },
 116         .rx = {
 117                 .rx_msdu_life_time           = 512000,
 118                 .packet_detection_threshold  = 0,
 119                 .ps_poll_timeout             = 15,
 120                 .upsd_timeout                = 15,
 121                 .rts_threshold               = IEEE80211_MAX_RTS_THRESHOLD,
 122                 .rx_cca_threshold            = 0,
 123                 .irq_blk_threshold           = 0xFFFF,
 124                 .irq_pkt_threshold           = 0,
 125                 .irq_timeout                 = 600,
 126                 .queue_type                  = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
 127         },
 128         .tx = {
 129                 .tx_energy_detection         = 0,
 130                 .sta_rc_conf                 = {
 131                         .enabled_rates       = 0,
 132                         .short_retry_limit   = 10,
 133                         .long_retry_limit    = 10,
 134                         .aflags              = 0,
 135                 },
 136                 .ac_conf_count               = 4,
 137                 .ac_conf                     = {
 138                         [CONF_TX_AC_BE] = {
 139                                 .ac          = CONF_TX_AC_BE,
 140                                 .cw_min      = 15,
 141                                 .cw_max      = 63,
 142                                 .aifsn       = 3,
 143                                 .tx_op_limit = 0,
 144                         },
 145                         [CONF_TX_AC_BK] = {
 146                                 .ac          = CONF_TX_AC_BK,
 147                                 .cw_min      = 15,
 148                                 .cw_max      = 63,
 149                                 .aifsn       = 7,
 150                                 .tx_op_limit = 0,
 151                         },
 152                         [CONF_TX_AC_VI] = {
 153                                 .ac          = CONF_TX_AC_VI,
 154                                 .cw_min      = 15,
 155                                 .cw_max      = 63,
 156                                 .aifsn       = CONF_TX_AIFS_PIFS,
 157                                 .tx_op_limit = 3008,
 158                         },
 159                         [CONF_TX_AC_VO] = {
 160                                 .ac          = CONF_TX_AC_VO,
 161                                 .cw_min      = 15,
 162                                 .cw_max      = 63,
 163                                 .aifsn       = CONF_TX_AIFS_PIFS,
 164                                 .tx_op_limit = 1504,
 165                         },
 166                 },
 167                 .max_tx_retries = 100,
 168                 .ap_aging_period = 300,
 169                 .tid_conf_count = 4,
 170                 .tid_conf = {
 171                         [CONF_TX_AC_BE] = {
 172                                 .queue_id    = CONF_TX_AC_BE,
 173                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 174                                 .tsid        = CONF_TX_AC_BE,
 175                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 176                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 177                                 .apsd_conf   = {0, 0},
 178                         },
 179                         [CONF_TX_AC_BK] = {
 180                                 .queue_id    = CONF_TX_AC_BK,
 181                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 182                                 .tsid        = CONF_TX_AC_BK,
 183                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 184                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 185                                 .apsd_conf   = {0, 0},
 186                         },
 187                         [CONF_TX_AC_VI] = {
 188                                 .queue_id    = CONF_TX_AC_VI,
 189                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 190                                 .tsid        = CONF_TX_AC_VI,
 191                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 192                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 193                                 .apsd_conf   = {0, 0},
 194                         },
 195                         [CONF_TX_AC_VO] = {
 196                                 .queue_id    = CONF_TX_AC_VO,
 197                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 198                                 .tsid        = CONF_TX_AC_VO,
 199                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 200                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 201                                 .apsd_conf   = {0, 0},
 202                         },
 203                 },
 204                 .frag_threshold              = IEEE80211_MAX_FRAG_THRESHOLD,
 205                 .tx_compl_timeout            = 700,
 206                 .tx_compl_threshold          = 4,
 207                 .basic_rate                  = CONF_HW_BIT_RATE_1MBPS,
 208                 .basic_rate_5                = CONF_HW_BIT_RATE_6MBPS,
 209                 .tmpl_short_retry_limit      = 10,
 210                 .tmpl_long_retry_limit       = 10,
 211                 .tx_watchdog_timeout         = 5000,
 212         },
 213         .conn = {
 214                 .wake_up_event               = CONF_WAKE_UP_EVENT_DTIM,
 215                 .listen_interval             = 1,
 216                 .suspend_wake_up_event       = CONF_WAKE_UP_EVENT_N_DTIM,
 217                 .suspend_listen_interval     = 3,
 218                 .bcn_filt_mode               = CONF_BCN_FILT_MODE_ENABLED,
 219                 .bcn_filt_ie_count           = 2,
 220                 .bcn_filt_ie = {
 221                         [0] = {
 222                                 .ie          = WLAN_EID_CHANNEL_SWITCH,
 223                                 .rule        = CONF_BCN_RULE_PASS_ON_APPEARANCE,
 224                         },
 225                         [1] = {
 226                                 .ie          = WLAN_EID_HT_OPERATION,
 227                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 228                         },
 229                 },
 230                 .synch_fail_thold            = 10,
 231                 .bss_lose_timeout            = 100,
 232                 .beacon_rx_timeout           = 10000,
 233                 .broadcast_timeout           = 20000,
 234                 .rx_broadcast_in_ps          = 1,
 235                 .ps_poll_threshold           = 10,
 236                 .bet_enable                  = CONF_BET_MODE_ENABLE,
 237                 .bet_max_consecutive         = 50,
 238                 .psm_entry_retries           = 8,
 239                 .psm_exit_retries            = 16,
 240                 .psm_entry_nullfunc_retries  = 3,
 241                 .dynamic_ps_timeout          = 40,
 242                 .forced_ps                   = false,
 243                 .keep_alive_interval         = 55000,
 244                 .max_listen_interval         = 20,
 245         },
 246         .itrim = {
 247                 .enable = false,
 248                 .timeout = 50000,
 249         },
 250         .pm_config = {
 251                 .host_clk_settling_time = 5000,
 252                 .host_fast_wakeup_support = false
 253         },
 254         .roam_trigger = {
 255                 .trigger_pacing               = 1,
 256                 .avg_weight_rssi_beacon       = 20,
 257                 .avg_weight_rssi_data         = 10,
 258                 .avg_weight_snr_beacon        = 20,
 259                 .avg_weight_snr_data          = 10,
 260         },
 261         .scan = {
 262                 .min_dwell_time_active        = 7500,
 263                 .max_dwell_time_active        = 30000,
 264                 .min_dwell_time_passive       = 100000,
 265                 .max_dwell_time_passive       = 100000,
 266                 .num_probe_reqs               = 2,
 267                 .split_scan_timeout           = 50000,
 268         },
 269         .sched_scan = {
 270                 /*
 271                  * Values are in TU/1000 but since sched scan FW command
 272                  * params are in TUs rounding up may occur.
 273                  */
 274                 .base_dwell_time                = 7500,
 275                 .max_dwell_time_delta           = 22500,
 276                 /* based on 250bits per probe @1Mbps */
 277                 .dwell_time_delta_per_probe     = 2000,
 278                 /* based on 250bits per probe @6Mbps (plus a bit more) */
 279                 .dwell_time_delta_per_probe_5   = 350,
 280                 .dwell_time_passive             = 100000,
 281                 .dwell_time_dfs                 = 150000,
 282                 .num_probe_reqs                 = 2,
 283                 .rssi_threshold                 = -90,
 284                 .snr_threshold                  = 0,
 285         },
 286         .ht = {
 287                 .rx_ba_win_size = 8,
 288                 .tx_ba_win_size = 64,
 289                 .inactivity_timeout = 10000,
 290                 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
 291         },
 292         /*
 293          * Memory config for wl127x chips is given in the
 294          * wl12xx_default_priv_conf struct. The below configuration is
 295          * for wl128x chips.
 296          */
 297         .mem = {
 298                 .num_stations                 = 1,
 299                 .ssid_profiles                = 1,
 300                 .rx_block_num                 = 40,
 301                 .tx_min_block_num             = 40,
 302                 .dynamic_memory               = 1,
 303                 .min_req_tx_blocks            = 45,
 304                 .min_req_rx_blocks            = 22,
 305                 .tx_min                       = 27,
 306         },
 307         .fm_coex = {
 308                 .enable                       = true,
 309                 .swallow_period               = 5,
 310                 .n_divider_fref_set_1         = 0xff,       /* default */
 311                 .n_divider_fref_set_2         = 12,
 312                 .m_divider_fref_set_1         = 148,
 313                 .m_divider_fref_set_2         = 0xffff,     /* default */
 314                 .coex_pll_stabilization_time  = 0xffffffff, /* default */
 315                 .ldo_stabilization_time       = 0xffff,     /* default */
 316                 .fm_disturbed_band_margin     = 0xff,       /* default */
 317                 .swallow_clk_diff             = 0xff,       /* default */
 318         },
 319         .rx_streaming = {
 320                 .duration                      = 150,
 321                 .queues                        = 0x1,
 322                 .interval                      = 20,
 323                 .always                        = 0,
 324         },
 325         .fwlog = {
 326                 .mode                         = WL12XX_FWLOG_ON_DEMAND,
 327                 .mem_blocks                   = 2,
 328                 .severity                     = 0,
 329                 .timestamp                    = WL12XX_FWLOG_TIMESTAMP_DISABLED,
 330                 .output                       = WL12XX_FWLOG_OUTPUT_HOST,
 331                 .threshold                    = 0,
 332         },
 333         .rate = {
 334                 .rate_retry_score = 32000,
 335                 .per_add = 8192,
 336                 .per_th1 = 2048,
 337                 .per_th2 = 4096,
 338                 .max_per = 8100,
 339                 .inverse_curiosity_factor = 5,
 340                 .tx_fail_low_th = 4,
 341                 .tx_fail_high_th = 10,
 342                 .per_alpha_shift = 4,
 343                 .per_add_shift = 13,
 344                 .per_beta1_shift = 10,
 345                 .per_beta2_shift = 8,
 346                 .rate_check_up = 2,
 347                 .rate_check_down = 12,
 348                 .rate_retry_policy = {
 349                         0x00, 0x00, 0x00, 0x00, 0x00,
 350                         0x00, 0x00, 0x00, 0x00, 0x00,
 351                         0x00, 0x00, 0x00,
 352                 },
 353         },
 354         .hangover = {
 355                 .recover_time               = 0,
 356                 .hangover_period            = 20,
 357                 .dynamic_mode               = 1,
 358                 .early_termination_mode     = 1,
 359                 .max_period                 = 20,
 360                 .min_period                 = 1,
 361                 .increase_delta             = 1,
 362                 .decrease_delta             = 2,
 363                 .quiet_time                 = 4,
 364                 .increase_time              = 1,
 365                 .window_size                = 16,
 366         },
 367 };
 368
 369 static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
 370         .rf = {
 371                 .tx_per_channel_power_compensation_2 = {
 372                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 373                 },
 374                 .tx_per_channel_power_compensation_5 = {
 375                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 376                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 377                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 378                 },
 379         },
 380         .mem_wl127x = {
 381                 .num_stations                 = 1,
 382                 .ssid_profiles                = 1,
 383                 .rx_block_num                 = 70,
 384                 .tx_min_block_num             = 40,
 385                 .dynamic_memory               = 1,
 386                 .min_req_tx_blocks            = 100,
 387                 .min_req_rx_blocks            = 22,
 388                 .tx_min                       = 27,
 389         },
 390
 391 };
 392
 393 #define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT        1
 394 #define WL12XX_TX_HW_BLOCK_GEM_SPARE            2
 395 #define WL12XX_TX_HW_BLOCK_SIZE                 252
 396
 397 static const u8 wl12xx_rate_to_idx_2ghz[] = {
 398         /* MCS rates are used only with 11n */
 399         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
 400         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
 401         6,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
 402         5,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
 403         4,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
 404         3,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
 405         2,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
 406         1,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
 407         0,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
 408
 409         11,                            /* WL12XX_CONF_HW_RXTX_RATE_54   */
 410         10,                            /* WL12XX_CONF_HW_RXTX_RATE_48   */
 411         9,                             /* WL12XX_CONF_HW_RXTX_RATE_36   */
 412         8,                             /* WL12XX_CONF_HW_RXTX_RATE_24   */
 413
 414         /* TI-specific rate */
 415         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22   */
 416
 417         7,                             /* WL12XX_CONF_HW_RXTX_RATE_18   */
 418         6,                             /* WL12XX_CONF_HW_RXTX_RATE_12   */
 419         3,                             /* WL12XX_CONF_HW_RXTX_RATE_11   */
 420         5,                             /* WL12XX_CONF_HW_RXTX_RATE_9    */
 421         4,                             /* WL12XX_CONF_HW_RXTX_RATE_6    */
 422         2,                             /* WL12XX_CONF_HW_RXTX_RATE_5_5  */
 423         1,                             /* WL12XX_CONF_HW_RXTX_RATE_2    */
 424         0                              /* WL12XX_CONF_HW_RXTX_RATE_1    */
 425 };
 426
 427 static const u8 wl12xx_rate_to_idx_5ghz[] = {
 428         /* MCS rates are used only with 11n */
 429         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
 430         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
 431         6,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
 432         5,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
 433         4,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
 434         3,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
 435         2,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
 436         1,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
 437         0,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
 438
 439         7,                             /* WL12XX_CONF_HW_RXTX_RATE_54   */
 440         6,                             /* WL12XX_CONF_HW_RXTX_RATE_48   */
 441         5,                             /* WL12XX_CONF_HW_RXTX_RATE_36   */
 442         4,                             /* WL12XX_CONF_HW_RXTX_RATE_24   */
 443
 444         /* TI-specific rate */
 445         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22   */
 446
 447         3,                             /* WL12XX_CONF_HW_RXTX_RATE_18   */
 448         2,                             /* WL12XX_CONF_HW_RXTX_RATE_12   */
 449         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11   */
 450         1,                             /* WL12XX_CONF_HW_RXTX_RATE_9    */
 451         0,                             /* WL12XX_CONF_HW_RXTX_RATE_6    */
 452         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5  */
 453         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2    */
 454         CONF_HW_RXTX_RATE_UNSUPPORTED  /* WL12XX_CONF_HW_RXTX_RATE_1    */
 455 };
 456
 457 static const u8 *wl12xx_band_rate_to_idx[] = {
 458         [IEEE80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
 459         [IEEE80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
 460 };
 461
 462 enum wl12xx_hw_rates {
 463         WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
 464         WL12XX_CONF_HW_RXTX_RATE_MCS7,
 465         WL12XX_CONF_HW_RXTX_RATE_MCS6,
 466         WL12XX_CONF_HW_RXTX_RATE_MCS5,
 467         WL12XX_CONF_HW_RXTX_RATE_MCS4,
 468         WL12XX_CONF_HW_RXTX_RATE_MCS3,
 469         WL12XX_CONF_HW_RXTX_RATE_MCS2,
 470         WL12XX_CONF_HW_RXTX_RATE_MCS1,
 471         WL12XX_CONF_HW_RXTX_RATE_MCS0,
 472         WL12XX_CONF_HW_RXTX_RATE_54,
 473         WL12XX_CONF_HW_RXTX_RATE_48,
 474         WL12XX_CONF_HW_RXTX_RATE_36,
 475         WL12XX_CONF_HW_RXTX_RATE_24,
 476         WL12XX_CONF_HW_RXTX_RATE_22,
 477         WL12XX_CONF_HW_RXTX_RATE_18,
 478         WL12XX_CONF_HW_RXTX_RATE_12,
 479         WL12XX_CONF_HW_RXTX_RATE_11,
 480         WL12XX_CONF_HW_RXTX_RATE_9,
 481         WL12XX_CONF_HW_RXTX_RATE_6,
 482         WL12XX_CONF_HW_RXTX_RATE_5_5,
 483         WL12XX_CONF_HW_RXTX_RATE_2,
 484         WL12XX_CONF_HW_RXTX_RATE_1,
 485         WL12XX_CONF_HW_RXTX_RATE_MAX,
 486 };
 487
 488 static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
 489         [PART_DOWN] = {
 490                 .mem = {
 491                         .start = 0x00000000,
 492                         .size  = 0x000177c0
 493                 },
 494                 .reg = {
 495                         .start = REGISTERS_BASE,
 496                         .size  = 0x00008800
 497                 },
 498                 .mem2 = {
 499                         .start = 0x00000000,
 500                         .size  = 0x00000000
 501                 },
 502                 .mem3 = {
 503                         .start = 0x00000000,
 504                         .size  = 0x00000000
 505                 },
 506         },
 507
 508         [PART_BOOT] = { /* in wl12xx we can use a mix of work and down
 509                          * partition here */
 510                 .mem = {
 511                         .start = 0x00040000,
 512                         .size  = 0x00014fc0
 513                 },
 514                 .reg = {
 515                         .start = REGISTERS_BASE,
 516                         .size  = 0x00008800
 517                 },
 518                 .mem2 = {
 519                         .start = 0x00000000,
 520                         .size  = 0x00000000
 521                 },
 522                 .mem3 = {
 523                         .start = 0x00000000,
 524                         .size  = 0x00000000
 525                 },
 526         },
 527
 528         [PART_WORK] = {
 529                 .mem = {
 530                         .start = 0x00040000,
 531                         .size  = 0x00014fc0
 532                 },
 533                 .reg = {
 534                         .start = REGISTERS_BASE,
 535                         .size  = 0x0000a000
 536                 },
 537                 .mem2 = {
 538                         .start = 0x003004f8,
 539                         .size  = 0x00000004
 540                 },
 541                 .mem3 = {
 542                         .start = 0x00040404,
 543                         .size  = 0x00000000
 544                 },
 545         },
 546
 547         [PART_DRPW] = {
 548                 .mem = {
 549                         .start = 0x00040000,
 550                         .size  = 0x00014fc0
 551                 },
 552                 .reg = {
 553                         .start = DRPW_BASE,
 554                         .size  = 0x00006000
 555                 },
 556                 .mem2 = {
 557                         .start = 0x00000000,
 558                         .size  = 0x00000000
 559                 },
 560                 .mem3 = {
 561                         .start = 0x00000000,
 562                         .size  = 0x00000000
 563                 }
 564         }
 565 };
 566
 567 static const int wl12xx_rtable[REG_TABLE_LEN] = {
 568         [REG_ECPU_CONTROL]              = WL12XX_REG_ECPU_CONTROL,
 569         [REG_INTERRUPT_NO_CLEAR]        = WL12XX_REG_INTERRUPT_NO_CLEAR,
 570         [REG_INTERRUPT_ACK]             = WL12XX_REG_INTERRUPT_ACK,
 571         [REG_COMMAND_MAILBOX_PTR]       = WL12XX_REG_COMMAND_MAILBOX_PTR,
 572         [REG_EVENT_MAILBOX_PTR]         = WL12XX_REG_EVENT_MAILBOX_PTR,
 573         [REG_INTERRUPT_TRIG]            = WL12XX_REG_INTERRUPT_TRIG,
 574         [REG_INTERRUPT_MASK]            = WL12XX_REG_INTERRUPT_MASK,
 575         [REG_PC_ON_RECOVERY]            = WL12XX_SCR_PAD4,
 576         [REG_CHIP_ID_B]                 = WL12XX_CHIP_ID_B,
 577         [REG_CMD_MBOX_ADDRESS]          = WL12XX_CMD_MBOX_ADDRESS,
 578
 579         /* data access memory addresses, used with partition translation */
 580         [REG_SLV_MEM_DATA]              = WL1271_SLV_MEM_DATA,
 581         [REG_SLV_REG_DATA]              = WL1271_SLV_REG_DATA,
 582
 583         /* raw data access memory addresses */
 584         [REG_RAW_FW_STATUS_ADDR]        = FW_STATUS_ADDR,
 585 };
 586
 587 /* TODO: maybe move to a new header file? */
 588 #define WL127X_FW_NAME_MULTI    "ti-connectivity/wl127x-fw-4-mr.bin"
 589 #define WL127X_FW_NAME_SINGLE   "ti-connectivity/wl127x-fw-4-sr.bin"
 590 #define WL127X_PLT_FW_NAME      "ti-connectivity/wl127x-fw-4-plt.bin"
 591
 592 #define WL128X_FW_NAME_MULTI    "ti-connectivity/wl128x-fw-4-mr.bin"
 593 #define WL128X_FW_NAME_SINGLE   "ti-connectivity/wl128x-fw-4-sr.bin"
 594 #define WL128X_PLT_FW_NAME      "ti-connectivity/wl128x-fw-4-plt.bin"
 595
 596 static void wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
 597 {
 598         if (wl->chip.id != CHIP_ID_1283_PG20) {
 599                 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
 600                 struct wl127x_rx_mem_pool_addr rx_mem_addr;
 601
 602                 /*
 603                  * Choose the block we want to read
 604                  * For aggregated packets, only the first memory block
 605                  * should be retrieved. The FW takes care of the rest.
 606                  */
 607                 u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
 608
 609                 rx_mem_addr.addr = (mem_block << 8) +
 610                         le32_to_cpu(wl_mem_map->packet_memory_pool_start);
 611
 612                 rx_mem_addr.addr_extra = rx_mem_addr.addr + 4;
 613
 614                 wl1271_write(wl, WL1271_SLV_REG_DATA,
 615                              &rx_mem_addr, sizeof(rx_mem_addr), false);
 616         }
 617 }
 618
 619 static int wl12xx_identify_chip(struct wl1271 *wl)
 620 {
 621         int ret = 0;
 622
 623         switch (wl->chip.id) {
 624         case CHIP_ID_1271_PG10:
 625                 wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
 626                                wl->chip.id);
 627
 628                 /* clear the alignment quirk, since we don't support it */
 629                 wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
 630
 631                 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS;
 632                 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
 633                 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
 634                 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
 635                        sizeof(wl->conf.mem));
 636
 637                 /* read data preparation is only needed by wl127x */
 638                 wl->ops->prepare_read = wl127x_prepare_read;
 639
 640                 break;
 641
 642         case CHIP_ID_1271_PG20:
 643                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
 644                              wl->chip.id);
 645
 646                 /* clear the alignment quirk, since we don't support it */
 647                 wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
 648
 649                 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS;
 650                 wl->plt_fw_name = WL127X_PLT_FW_NAME;
 651                 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
 652                 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
 653                 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
 654                        sizeof(wl->conf.mem));
 655
 656                 /* read data preparation is only needed by wl127x */
 657                 wl->ops->prepare_read = wl127x_prepare_read;
 658
 659                 break;
 660
 661         case CHIP_ID_1283_PG20:
 662                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
 663                              wl->chip.id);
 664                 wl->plt_fw_name = WL128X_PLT_FW_NAME;
 665                 wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
 666                 wl->mr_fw_name = WL128X_FW_NAME_MULTI;
 667                 break;
 668         case CHIP_ID_1283_PG10:
 669         default:
 670                 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
 671                 ret = -ENODEV;
 672                 goto out;
 673         }
 674
 675 out:
 676         return ret;
 677 }
 678
 679 static void wl12xx_top_reg_write(struct wl1271 *wl, int addr, u16 val)
 680 {
 681         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 682         addr = (addr >> 1) + 0x30000;
 683         wl1271_write32(wl, WL12XX_OCP_POR_CTR, addr);
 684
 685         /* write value to OCP_POR_WDATA */
 686         wl1271_write32(wl, WL12XX_OCP_DATA_WRITE, val);
 687
 688         /* write 1 to OCP_CMD */
 689         wl1271_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
 690 }
 691
 692 static u16 wl12xx_top_reg_read(struct wl1271 *wl, int addr)
 693 {
 694         u32 val;
 695         int timeout = OCP_CMD_LOOP;
 696
 697         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 698         addr = (addr >> 1) + 0x30000;
 699         wl1271_write32(wl, WL12XX_OCP_POR_CTR, addr);
 700
 701         /* write 2 to OCP_CMD */
 702         wl1271_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
 703
 704         /* poll for data ready */
 705         do {
 706                 val = wl1271_read32(wl, WL12XX_OCP_DATA_READ);
 707         } while (!(val & OCP_READY_MASK) && --timeout);
 708
 709         if (!timeout) {
 710                 wl1271_warning("Top register access timed out.");
 711                 return 0xffff;
 712         }
 713
 714         /* check data status and return if OK */
 715         if ((val & OCP_STATUS_MASK) == OCP_STATUS_OK)
 716                 return val & 0xffff;
 717         else {
 718                 wl1271_warning("Top register access returned error.");
 719                 return 0xffff;
 720         }
 721 }
 722
 723 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
 724 {
 725         u16 spare_reg;
 726
 727         /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
 728         spare_reg = wl12xx_top_reg_read(wl, WL_SPARE_REG);
 729         if (spare_reg == 0xFFFF)
 730                 return -EFAULT;
 731         spare_reg |= (BIT(3) | BIT(5) | BIT(6));
 732         wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 733
 734         /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
 735         wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
 736                              WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
 737
 738         /* Delay execution for 15msec, to let the HW settle */
 739         mdelay(15);
 740
 741         return 0;
 742 }
 743
 744 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
 745 {
 746         u16 tcxo_detection;
 747
 748         tcxo_detection = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG);
 749         if (tcxo_detection & TCXO_DET_FAILED)
 750                 return false;
 751
 752         return true;
 753 }
 754
 755 static bool wl128x_is_fref_valid(struct wl1271 *wl)
 756 {
 757         u16 fref_detection;
 758
 759         fref_detection = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG);
 760         if (fref_detection & FREF_CLK_DETECT_FAIL)
 761                 return false;
 762
 763         return true;
 764 }
 765
 766 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
 767 {
 768         wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
 769         wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
 770         wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, MCS_PLL_CONFIG_REG_VAL);
 771
 772         return 0;
 773 }
 774
 775 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
 776 {
 777         u16 spare_reg;
 778         u16 pll_config;
 779         u8 input_freq;
 780         struct wl12xx_priv *priv = wl->priv;
 781
 782         /* Mask bits [3:1] in the sys_clk_cfg register */
 783         spare_reg = wl12xx_top_reg_read(wl, WL_SPARE_REG);
 784         if (spare_reg == 0xFFFF)
 785                 return -EFAULT;
 786         spare_reg |= BIT(2);
 787         wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 788
 789         /* Handle special cases of the TCXO clock */
 790         if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
 791             priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
 792                 return wl128x_manually_configure_mcs_pll(wl);
 793
 794         /* Set the input frequency according to the selected clock source */
 795         input_freq = (clk & 1) + 1;
 796
 797         pll_config = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG);
 798         if (pll_config == 0xFFFF)
 799                 return -EFAULT;
 800         pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
 801         pll_config |= MCS_PLL_ENABLE_HP;
 802         wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
 803
 804         return 0;
 805 }
 806
 807 /*
 808  * WL128x has two clocks input - TCXO and FREF.
 809  * TCXO is the main clock of the device, while FREF is used to sync
 810  * between the GPS and the cellular modem.
 811  * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
 812  * as the WLAN/BT main clock.
 813  */
 814 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
 815 {
 816         struct wl12xx_priv *priv = wl->priv;
 817         u16 sys_clk_cfg;
 818
 819         /* For XTAL-only modes, FREF will be used after switching from TCXO */
 820         if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
 821             priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
 822                 if (!wl128x_switch_tcxo_to_fref(wl))
 823                         return -EINVAL;
 824                 goto fref_clk;
 825         }
 826
 827         /* Query the HW, to determine which clock source we should use */
 828         sys_clk_cfg = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG);
 829         if (sys_clk_cfg == 0xFFFF)
 830                 return -EINVAL;
 831         if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
 832                 goto fref_clk;
 833
 834         /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
 835         if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
 836             priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
 837                 if (!wl128x_switch_tcxo_to_fref(wl))
 838                         return -EINVAL;
 839                 goto fref_clk;
 840         }
 841
 842         /* TCXO clock is selected */
 843         if (!wl128x_is_tcxo_valid(wl))
 844                 return -EINVAL;
 845         *selected_clock = priv->tcxo_clock;
 846         goto config_mcs_pll;
 847
 848 fref_clk:
 849         /* FREF clock is selected */
 850         if (!wl128x_is_fref_valid(wl))
 851                 return -EINVAL;
 852         *selected_clock = priv->ref_clock;
 853
 854 config_mcs_pll:
 855         return wl128x_configure_mcs_pll(wl, *selected_clock);
 856 }
 857
 858 static int wl127x_boot_clk(struct wl1271 *wl)
 859 {
 860         struct wl12xx_priv *priv = wl->priv;
 861         u32 pause;
 862         u32 clk;
 863
 864         if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
 865                 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
 866
 867         if (priv->ref_clock == CONF_REF_CLK_19_2_E ||
 868             priv->ref_clock == CONF_REF_CLK_38_4_E ||
 869             priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
 870                 /* ref clk: 19.2/38.4/38.4-XTAL */
 871                 clk = 0x3;
 872         else if (priv->ref_clock == CONF_REF_CLK_26_E ||
 873                  priv->ref_clock == CONF_REF_CLK_52_E)
 874                 /* ref clk: 26/52 */
 875                 clk = 0x5;
 876         else
 877                 return -EINVAL;
 878
 879         if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
 880                 u16 val;
 881                 /* Set clock type (open drain) */
 882                 val = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE);
 883                 val &= FREF_CLK_TYPE_BITS;
 884                 wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
 885
 886                 /* Set clock pull mode (no pull) */
 887                 val = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL);
 888                 val |= NO_PULL;
 889                 wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
 890         } else {
 891                 u16 val;
 892                 /* Set clock polarity */
 893                 val = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY);
 894                 val &= FREF_CLK_POLARITY_BITS;
 895                 val |= CLK_REQ_OUTN_SEL;
 896                 wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
 897         }
 898
 899         wl1271_write32(wl, WL12XX_PLL_PARAMETERS, clk);
 900
 901         pause = wl1271_read32(wl, WL12XX_PLL_PARAMETERS);
 902
 903         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
 904
 905         pause &= ~(WU_COUNTER_PAUSE_VAL);
 906         pause |= WU_COUNTER_PAUSE_VAL;
 907         wl1271_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
 908
 909         return 0;
 910 }
 911
 912 static int wl1271_boot_soft_reset(struct wl1271 *wl)
 913 {
 914         unsigned long timeout;
 915         u32 boot_data;
 916
 917         /* perform soft reset */
 918         wl1271_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
 919
 920         /* SOFT_RESET is self clearing */
 921         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
 922         while (1) {
 923                 boot_data = wl1271_read32(wl, WL12XX_SLV_SOFT_RESET);
 924                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
 925                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
 926                         break;
 927
 928                 if (time_after(jiffies, timeout)) {
 929                         /* 1.2 check pWhalBus->uSelfClearTime if the
 930                          * timeout was reached */
 931                         wl1271_error("soft reset timeout");
 932                         return -1;
 933                 }
 934
 935                 udelay(SOFT_RESET_STALL_TIME);
 936         }
 937
 938         /* disable Rx/Tx */
 939         wl1271_write32(wl, WL12XX_ENABLE, 0x0);
 940
 941         /* disable auto calibration on start*/
 942         wl1271_write32(wl, WL12XX_SPARE_A2, 0xffff);
 943
 944         return 0;
 945 }
 946
 947 static int wl12xx_pre_boot(struct wl1271 *wl)
 948 {
 949         struct wl12xx_priv *priv = wl->priv;
 950         int ret = 0;
 951         u32 clk;
 952         int selected_clock = -1;
 953
 954         if (wl->chip.id == CHIP_ID_1283_PG20) {
 955                 ret = wl128x_boot_clk(wl, &selected_clock);
 956                 if (ret < 0)
 957                         goto out;
 958         } else {
 959                 ret = wl127x_boot_clk(wl);
 960                 if (ret < 0)
 961                         goto out;
 962         }
 963
 964         /* Continue the ELP wake up sequence */
 965         wl1271_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 966         udelay(500);
 967
 968         wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
 969
 970         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
 971            to be used by DRPw FW. The RTRIM value will be added by the FW
 972            before taking DRPw out of reset */
 973
 974         clk = wl1271_read32(wl, WL12XX_DRPW_SCRATCH_START);
 975
 976         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
 977
 978         if (wl->chip.id == CHIP_ID_1283_PG20)
 979                 clk |= ((selected_clock & 0x3) << 1) << 4;
 980         else
 981                 clk |= (priv->ref_clock << 1) << 4;
 982
 983         wl1271_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
 984
 985         wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
 986
 987         /* Disable interrupts */
 988         wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 989
 990         ret = wl1271_boot_soft_reset(wl);
 991         if (ret < 0)
 992                 goto out;
 993
 994 out:
 995         return ret;
 996 }
 997
 998 static void wl12xx_pre_upload(struct wl1271 *wl)
 999 {
1000         u32 tmp;
1001
1002         /* write firmware's last address (ie. it's length) to
1003          * ACX_EEPROMLESS_IND_REG */
1004         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
1005
1006         wl1271_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1007
1008         tmp = wlcore_read_reg(wl, REG_CHIP_ID_B);
1009
1010         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
1011
1012         /* 6. read the EEPROM parameters */
1013         tmp = wl1271_read32(wl, WL12XX_SCR_PAD2);
1014
1015         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
1016          * to upload_fw) */
1017
1018         if (wl->chip.id == CHIP_ID_1283_PG20)
1019                 wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1020 }
1021
1022 static void wl12xx_enable_interrupts(struct wl1271 *wl)
1023 {
1024         u32 polarity;
1025
1026         polarity = wl12xx_top_reg_read(wl, OCP_REG_POLARITY);
1027
1028         /* We use HIGH polarity, so unset the LOW bit */
1029         polarity &= ~POLARITY_LOW;
1030         wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1031
1032         wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR);
1033
1034         wlcore_enable_interrupts(wl);
1035         wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1036                          WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
1037
1038         wl1271_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1039 }
1040
1041 static int wl12xx_boot(struct wl1271 *wl)
1042 {
1043         int ret;
1044
1045         ret = wl12xx_pre_boot(wl);
1046         if (ret < 0)
1047                 goto out;
1048
1049         ret = wlcore_boot_upload_nvs(wl);
1050         if (ret < 0)
1051                 goto out;
1052
1053         wl12xx_pre_upload(wl);
1054
1055         ret = wlcore_boot_upload_firmware(wl);
1056         if (ret < 0)
1057                 goto out;
1058
1059         ret = wlcore_boot_run_firmware(wl);
1060         if (ret < 0)
1061                 goto out;
1062
1063         wl12xx_enable_interrupts(wl);
1064
1065 out:
1066         return ret;
1067 }
1068
1069 static void wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1070                                void *buf, size_t len)
1071 {
1072         wl1271_write(wl, cmd_box_addr, buf, len, false);
1073         wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1074 }
1075
1076 static void wl12xx_ack_event(struct wl1271 *wl)
1077 {
1078         wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_EVENT_ACK);
1079 }
1080
1081 static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1082 {
1083         u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
1084         u32 align_len = wlcore_calc_packet_alignment(wl, len);
1085
1086         return (align_len + blk_size - 1) / blk_size + spare_blks;
1087 }
1088
1089 static void
1090 wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1091                           u32 blks, u32 spare_blks)
1092 {
1093         if (wl->chip.id == CHIP_ID_1283_PG20) {
1094                 desc->wl128x_mem.total_mem_blocks = blks;
1095         } else {
1096                 desc->wl127x_mem.extra_blocks = spare_blks;
1097                 desc->wl127x_mem.total_mem_blocks = blks;
1098         }
1099 }
1100
1101 static void
1102 wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1103                             struct sk_buff *skb)
1104 {
1105         u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
1106
1107         if (wl->chip.id == CHIP_ID_1283_PG20) {
1108                 desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
1109                 desc->length = cpu_to_le16(aligned_len >> 2);
1110
1111                 wl1271_debug(DEBUG_TX,
1112                              "tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
1113                              desc->hlid,
1114                              le16_to_cpu(desc->length),
1115                              le16_to_cpu(desc->life_time),
1116                              desc->wl128x_mem.total_mem_blocks,
1117                              desc->wl128x_mem.extra_bytes);
1118         } else {
1119                 /* calculate number of padding bytes */
1120                 int pad = aligned_len - skb->len;
1121                 desc->tx_attr |=
1122                         cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
1123
1124                 /* Store the aligned length in terms of words */
1125                 desc->length = cpu_to_le16(aligned_len >> 2);
1126
1127                 wl1271_debug(DEBUG_TX,
1128                              "tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
1129                              pad, desc->hlid,
1130                              le16_to_cpu(desc->length),
1131                              le16_to_cpu(desc->life_time),
1132                              desc->wl127x_mem.total_mem_blocks);
1133         }
1134 }
1135
1136 static enum wl_rx_buf_align
1137 wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1138 {
1139         if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
1140                 return WLCORE_RX_BUF_UNALIGNED;
1141
1142         return WLCORE_RX_BUF_ALIGNED;
1143 }
1144
1145 static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1146                                     u32 data_len)
1147 {
1148         struct wl1271_rx_descriptor *desc = rx_data;
1149
1150         /* invalid packet */
1151         if (data_len < sizeof(*desc) ||
1152             data_len < sizeof(*desc) + desc->pad_len)
1153                 return 0;
1154
1155         return data_len - sizeof(*desc) - desc->pad_len;
1156 }
1157
1158 static void wl12xx_tx_delayed_compl(struct wl1271 *wl)
1159 {
1160         if (wl->fw_status_1->tx_results_counter ==
1161             (wl->tx_results_count & 0xff))
1162                 return;
1163
1164         wl1271_tx_complete(wl);
1165 }
1166
1167 static int wl12xx_hw_init(struct wl1271 *wl)
1168 {
1169         int ret;
1170
1171         if (wl->chip.id == CHIP_ID_1283_PG20) {
1172                 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
1173
1174                 ret = wl128x_cmd_general_parms(wl);
1175                 if (ret < 0)
1176                         goto out;
1177                 ret = wl128x_cmd_radio_parms(wl);
1178                 if (ret < 0)
1179                         goto out;
1180
1181                 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
1182                         /* Enable SDIO padding */
1183                         host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1184
1185                 /* Must be before wl1271_acx_init_mem_config() */
1186                 ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
1187                 if (ret < 0)
1188                         goto out;
1189         } else {
1190                 ret = wl1271_cmd_general_parms(wl);
1191                 if (ret < 0)
1192                         goto out;
1193                 ret = wl1271_cmd_radio_parms(wl);
1194                 if (ret < 0)
1195                         goto out;
1196                 ret = wl1271_cmd_ext_radio_parms(wl);
1197                 if (ret < 0)
1198                         goto out;
1199         }
1200 out:
1201         return ret;
1202 }
1203
1204 static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1205                                        struct wl12xx_vif *wlvif)
1206 {
1207         return wlvif->rate_set;
1208 }
1209
1210 static int wl12xx_identify_fw(struct wl1271 *wl)
1211 {
1212         unsigned int *fw_ver = wl->chip.fw_ver;
1213
1214         /* Only new station firmwares support routing fw logs to the host */
1215         if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
1216             (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN))
1217                 wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
1218
1219         /* This feature is not yet supported for AP mode */
1220         if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP)
1221                 wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
1222
1223         return 0;
1224 }
1225
1226 static void wl12xx_conf_init(struct wl1271 *wl)
1227 {
1228         struct wl12xx_priv *priv = wl->priv;
1229
1230         /* apply driver default configuration */
1231         memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
1232
1233         /* apply default private configuration */
1234         memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
1235 }
1236
1237 static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1238 {
1239         bool supported = false;
1240         u8 major, minor;
1241
1242         if (wl->chip.id == CHIP_ID_1283_PG20) {
1243                 major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
1244                 minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
1245
1246                 /* in wl128x we have the MAC address if the PG is >= (2, 1) */
1247                 if (major > 2 || (major == 2 && minor >= 1))
1248                         supported = true;
1249         } else {
1250                 major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
1251                 minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
1252
1253                 /* in wl127x we have the MAC address if the PG is >= (3, 1) */
1254                 if (major == 3 && minor >= 1)
1255                         supported = true;
1256         }
1257
1258         wl1271_debug(DEBUG_PROBE,
1259                      "PG Ver major = %d minor = %d, MAC %s present",
1260                      major, minor, supported ? "is" : "is not");
1261
1262         return supported;
1263 }
1264
1265 static void wl12xx_get_fuse_mac(struct wl1271 *wl)
1266 {
1267         u32 mac1, mac2;
1268
1269         wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1270
1271         mac1 = wl1271_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1);
1272         mac2 = wl1271_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2);
1273
1274         /* these are the two parts of the BD_ADDR */
1275         wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1276                 ((mac1 & 0xff000000) >> 24);
1277         wl->fuse_nic_addr = mac1 & 0xffffff;
1278
1279         wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1280 }
1281
1282 static s8 wl12xx_get_pg_ver(struct wl1271 *wl)
1283 {
1284         u32 die_info;
1285
1286         if (wl->chip.id == CHIP_ID_1283_PG20)
1287                 die_info = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1);
1288         else
1289                 die_info = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1);
1290
1291         return (s8) (die_info & PG_VER_MASK) >> PG_VER_OFFSET;
1292 }
1293
1294 static void wl12xx_get_mac(struct wl1271 *wl)
1295 {
1296         if (wl12xx_mac_in_fuse(wl))
1297                 wl12xx_get_fuse_mac(wl);
1298 }
1299
1300 static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
1301                                     struct wl1271_tx_hw_descr *desc,
1302                                     struct sk_buff *skb)
1303 {
1304         desc->wl12xx_reserved = 0;
1305 }
1306
1307 static int wl12xx_plt_init(struct wl1271 *wl)
1308 {
1309         int ret;
1310
1311         ret = wl->ops->boot(wl);
1312         if (ret < 0)
1313                 goto out;
1314
1315         ret = wl->ops->hw_init(wl);
1316         if (ret < 0)
1317                 goto out_irq_disable;
1318
1319         ret = wl1271_acx_init_mem_config(wl);
1320         if (ret < 0)
1321                 goto out_irq_disable;
1322
1323         ret = wl12xx_acx_mem_cfg(wl);
1324         if (ret < 0)
1325                 goto out_free_memmap;
1326
1327         /* Enable data path */
1328         ret = wl1271_cmd_data_path(wl, 1);
1329         if (ret < 0)
1330                 goto out_free_memmap;
1331
1332         /* Configure for CAM power saving (ie. always active) */
1333         ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
1334         if (ret < 0)
1335                 goto out_free_memmap;
1336
1337         /* configure PM */
1338         ret = wl1271_acx_pm_config(wl);
1339         if (ret < 0)
1340                 goto out_free_memmap;
1341
1342         goto out;
1343
1344 out_free_memmap:
1345         kfree(wl->target_mem_map);
1346         wl->target_mem_map = NULL;
1347
1348 out_irq_disable:
1349         mutex_unlock(&wl->mutex);
1350         /* Unlocking the mutex in the middle of handling is
1351            inherently unsafe. In this case we deem it safe to do,
1352            because we need to let any possibly pending IRQ out of
1353            the system (and while we are WL1271_STATE_OFF the IRQ
1354            work function will not do anything.) Also, any other
1355            possible concurrent operations will fail due to the
1356            current state, hence the wl1271 struct should be safe. */
1357         wlcore_disable_interrupts(wl);
1358         mutex_lock(&wl->mutex);
1359 out:
1360         return ret;
1361 }
1362
1363 static struct wlcore_ops wl12xx_ops = {
1364         .identify_chip          = wl12xx_identify_chip,
1365         .identify_fw            = wl12xx_identify_fw,
1366         .boot                   = wl12xx_boot,
1367         .plt_init               = wl12xx_plt_init,
1368         .trigger_cmd            = wl12xx_trigger_cmd,
1369         .ack_event              = wl12xx_ack_event,
1370         .calc_tx_blocks         = wl12xx_calc_tx_blocks,
1371         .set_tx_desc_blocks     = wl12xx_set_tx_desc_blocks,
1372         .set_tx_desc_data_len   = wl12xx_set_tx_desc_data_len,
1373         .get_rx_buf_align       = wl12xx_get_rx_buf_align,
1374         .get_rx_packet_len      = wl12xx_get_rx_packet_len,
1375         .tx_immediate_compl     = NULL,
1376         .tx_delayed_compl       = wl12xx_tx_delayed_compl,
1377         .hw_init                = wl12xx_hw_init,
1378         .init_vif               = NULL,
1379         .sta_get_ap_rate_mask   = wl12xx_sta_get_ap_rate_mask,
1380         .get_pg_ver             = wl12xx_get_pg_ver,
1381         .get_mac                = wl12xx_get_mac,
1382         .set_tx_desc_csum       = wl12xx_set_tx_desc_csum,
1383         .set_rx_csum            = NULL,
1384         .ap_get_mimo_wide_rate_mask = NULL,
1385         .debugfs_init           = wl12xx_debugfs_add_files,
1386 };
1387
1388 static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
1389         .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
1390                (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
1391         .ht_supported = true,
1392         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
1393         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
1394         .mcs = {
1395                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1396                 .rx_highest = cpu_to_le16(72),
1397                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1398                 },
1399 };
1400
1401 static int __devinit wl12xx_probe(struct platform_device *pdev)
1402 {
1403         struct wl12xx_platform_data *pdata = pdev->dev.platform_data;
1404         struct wl1271 *wl;
1405         struct ieee80211_hw *hw;
1406         struct wl12xx_priv *priv;
1407
1408         hw = wlcore_alloc_hw(sizeof(*priv));
1409         if (IS_ERR(hw)) {
1410                 wl1271_error("can't allocate hw");
1411                 return PTR_ERR(hw);
1412         }
1413
1414         wl = hw->priv;
1415         priv = wl->priv;
1416         wl->ops = &wl12xx_ops;
1417         wl->ptable = wl12xx_ptable;
1418         wl->rtable = wl12xx_rtable;
1419         wl->num_tx_desc = 16;
1420         wl->num_rx_desc = 8;
1421         wl->normal_tx_spare = WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
1422         wl->gem_tx_spare = WL12XX_TX_HW_BLOCK_GEM_SPARE;
1423         wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
1424         wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
1425         wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1426         wl->fw_status_priv_len = 0;
1427         wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1428         memcpy(&wl->ht_cap, &wl12xx_ht_cap, sizeof(wl12xx_ht_cap));
1429         wl12xx_conf_init(wl);
1430
1431         if (!fref_param) {
1432                 priv->ref_clock = pdata->board_ref_clock;
1433         } else {
1434                 if (!strcmp(fref_param, "19.2"))
1435                         priv->ref_clock = WL12XX_REFCLOCK_19;
1436                 else if (!strcmp(fref_param, "26"))
1437                         priv->ref_clock = WL12XX_REFCLOCK_26;
1438                 else if (!strcmp(fref_param, "26x"))
1439                         priv->ref_clock = WL12XX_REFCLOCK_26_XTAL;
1440                 else if (!strcmp(fref_param, "38.4"))
1441                         priv->ref_clock = WL12XX_REFCLOCK_38;
1442                 else if (!strcmp(fref_param, "38.4x"))
1443                         priv->ref_clock = WL12XX_REFCLOCK_38_XTAL;
1444                 else if (!strcmp(fref_param, "52"))
1445                         priv->ref_clock = WL12XX_REFCLOCK_52;
1446                 else
1447                         wl1271_error("Invalid fref parameter %s", fref_param);
1448         }
1449
1450         if (!tcxo_param) {
1451                 priv->tcxo_clock = pdata->board_tcxo_clock;
1452         } else {
1453                 if (!strcmp(tcxo_param, "19.2"))
1454                         priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
1455                 else if (!strcmp(tcxo_param, "26"))
1456                         priv->tcxo_clock = WL12XX_TCXOCLOCK_26;
1457                 else if (!strcmp(tcxo_param, "38.4"))
1458                         priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4;
1459                 else if (!strcmp(tcxo_param, "52"))
1460                         priv->tcxo_clock = WL12XX_TCXOCLOCK_52;
1461                 else if (!strcmp(tcxo_param, "16.368"))
1462                         priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368;
1463                 else if (!strcmp(tcxo_param, "32.736"))
1464                         priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736;
1465                 else if (!strcmp(tcxo_param, "16.8"))
1466                         priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8;
1467                 else if (!strcmp(tcxo_param, "33.6"))
1468                         priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6;
1469                 else
1470                         wl1271_error("Invalid tcxo parameter %s", tcxo_param);
1471         }
1472
1473         return wlcore_probe(wl, pdev);
1474 }
1475
1476 static const struct platform_device_id wl12xx_id_table[] __devinitconst = {
1477         { "wl12xx", 0 },
1478         {  } /* Terminating Entry */
1479 };
1480 MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
1481
1482 static struct platform_driver wl12xx_driver = {
1483         .probe          = wl12xx_probe,
1484         .remove         = __devexit_p(wlcore_remove),
1485         .id_table       = wl12xx_id_table,
1486         .driver = {
1487                 .name   = "wl12xx_driver",
1488                 .owner  = THIS_MODULE,
1489         }
1490 };
1491
1492 static int __init wl12xx_init(void)
1493 {
1494         return platform_driver_register(&wl12xx_driver);
1495 }
1496 module_init(wl12xx_init);
1497
1498 static void __exit wl12xx_exit(void)
1499 {
1500         platform_driver_unregister(&wl12xx_driver);
1501 }
1502 module_exit(wl12xx_exit);
1503
1504 module_param_named(fref, fref_param, charp, 0);
1505 MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
1506
1507 module_param_named(tcxo, tcxo_param, charp, 0);
1508 MODULE_PARM_DESC(tcxo,
1509                  "TCXO clock: 19.2, 26, 38.4, 52, 16.368, 32.736, 16.8, 33.6");
1510
1511 MODULE_LICENSE("GPL v2");
1512 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1513 MODULE_FIRMWARE(WL127X_FW_NAME_SINGLE);
1514 MODULE_FIRMWARE(WL127X_FW_NAME_MULTI);
1515 MODULE_FIRMWARE(WL127X_PLT_FW_NAME);
1516 MODULE_FIRMWARE(WL128X_FW_NAME_SINGLE);
1517 MODULE_FIRMWARE(WL128X_FW_NAME_MULTI);
1518 MODULE_FIRMWARE(WL128X_PLT_FW_NAME);