drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 /*
  20         Module: rt2500pci
  21         Abstract: rt2500pci device specific routines.
  22         Supported chipsets: RT2560.
  23  */
  24
  25 #include <linux/delay.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/init.h>
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/eeprom_93cx6.h>
  32 #include <linux/slab.h>
  33
  34 #include "rt2x00.h"
  35 #include "rt2x00mmio.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2500pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00mmio_register_read and rt2x00mmio_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 #define WAIT_FOR_BBP(__dev, __reg) \
  53         rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  54 #define WAIT_FOR_RF(__dev, __reg) \
  55         rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  56
  57 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  58                                 const unsigned int word, const u8 value)
  59 {
  60         u32 reg;
  61
  62         mutex_lock(&rt2x00dev->csr_mutex);
  63
  64         /*
  65          * Wait until the BBP becomes available, afterwards we
  66          * can safely write the new data into the register.
  67          */
  68         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  69                 reg = 0;
  70                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  71                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  72                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  73                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  74
  75                 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
  76         }
  77
  78         mutex_unlock(&rt2x00dev->csr_mutex);
  79 }
  80
  81 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  82                                const unsigned int word, u8 *value)
  83 {
  84         u32 reg;
  85
  86         mutex_lock(&rt2x00dev->csr_mutex);
  87
  88         /*
  89          * Wait until the BBP becomes available, afterwards we
  90          * can safely write the read request into the register.
  91          * After the data has been written, we wait until hardware
  92          * returns the correct value, if at any time the register
  93          * doesn't become available in time, reg will be 0xffffffff
  94          * which means we return 0xff to the caller.
  95          */
  96         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  97                 reg = 0;
  98                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  99                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 100                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 101
 102                 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
 103
 104                 WAIT_FOR_BBP(rt2x00dev, &reg);
 105         }
 106
 107         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 113                                const unsigned int word, const u32 value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the RF becomes available, afterwards we
 121          * can safely write the new data into the register.
 122          */
 123         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 124                 reg = 0;
 125                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 126                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 127                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 128                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 129
 130                 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
 131                 rt2x00_rf_write(rt2x00dev, word, value);
 132         }
 133
 134         mutex_unlock(&rt2x00dev->csr_mutex);
 135 }
 136
 137 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 138 {
 139         struct rt2x00_dev *rt2x00dev = eeprom->data;
 140         u32 reg;
 141
 142         rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
 143
 144         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 145         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 146         eeprom->reg_data_clock =
 147             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 148         eeprom->reg_chip_select =
 149             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 150 }
 151
 152 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 153 {
 154         struct rt2x00_dev *rt2x00dev = eeprom->data;
 155         u32 reg = 0;
 156
 157         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 160                            !!eeprom->reg_data_clock);
 161         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 162                            !!eeprom->reg_chip_select);
 163
 164         rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
 165 }
 166
 167 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 168 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 169         .owner  = THIS_MODULE,
 170         .csr    = {
 171                 .read           = rt2x00mmio_register_read,
 172                 .write          = rt2x00mmio_register_write,
 173                 .flags          = RT2X00DEBUGFS_OFFSET,
 174                 .word_base      = CSR_REG_BASE,
 175                 .word_size      = sizeof(u32),
 176                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 177         },
 178         .eeprom = {
 179                 .read           = rt2x00_eeprom_read,
 180                 .write          = rt2x00_eeprom_write,
 181                 .word_base      = EEPROM_BASE,
 182                 .word_size      = sizeof(u16),
 183                 .word_count     = EEPROM_SIZE / sizeof(u16),
 184         },
 185         .bbp    = {
 186                 .read           = rt2500pci_bbp_read,
 187                 .write          = rt2500pci_bbp_write,
 188                 .word_base      = BBP_BASE,
 189                 .word_size      = sizeof(u8),
 190                 .word_count     = BBP_SIZE / sizeof(u8),
 191         },
 192         .rf     = {
 193                 .read           = rt2x00_rf_read,
 194                 .write          = rt2500pci_rf_write,
 195                 .word_base      = RF_BASE,
 196                 .word_size      = sizeof(u32),
 197                 .word_count     = RF_SIZE / sizeof(u32),
 198         },
 199 };
 200 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 201
 202 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 203 {
 204         u32 reg;
 205
 206         rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
 207         return rt2x00_get_field32(reg, GPIOCSR_VAL0);
 208 }
 209
 210 #ifdef CONFIG_RT2X00_LIB_LEDS
 211 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
 212                                      enum led_brightness brightness)
 213 {
 214         struct rt2x00_led *led =
 215             container_of(led_cdev, struct rt2x00_led, led_dev);
 216         unsigned int enabled = brightness != LED_OFF;
 217         u32 reg;
 218
 219         rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
 220
 221         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 222                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 223         else if (led->type == LED_TYPE_ACTIVITY)
 224                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 225
 226         rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
 227 }
 228
 229 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
 230                                unsigned long *delay_on,
 231                                unsigned long *delay_off)
 232 {
 233         struct rt2x00_led *led =
 234             container_of(led_cdev, struct rt2x00_led, led_dev);
 235         u32 reg;
 236
 237         rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
 238         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 239         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 240         rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
 241
 242         return 0;
 243 }
 244
 245 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
 246                                struct rt2x00_led *led,
 247                                enum led_type type)
 248 {
 249         led->rt2x00dev = rt2x00dev;
 250         led->type = type;
 251         led->led_dev.brightness_set = rt2500pci_brightness_set;
 252         led->led_dev.blink_set = rt2500pci_blink_set;
 253         led->flags = LED_INITIALIZED;
 254 }
 255 #endif /* CONFIG_RT2X00_LIB_LEDS */
 256
 257 /*
 258  * Configuration handlers.
 259  */
 260 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 261                                     const unsigned int filter_flags)
 262 {
 263         u32 reg;
 264
 265         /*
 266          * Start configuration steps.
 267          * Note that the version error will always be dropped
 268          * and broadcast frames will always be accepted since
 269          * there is no filter for it at this time.
 270          */
 271         rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
 272         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 273                            !(filter_flags & FIF_FCSFAIL));
 274         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 275                            !(filter_flags & FIF_PLCPFAIL));
 276         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 277                            !(filter_flags & FIF_CONTROL));
 278         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 279                            !(filter_flags & FIF_PROMISC_IN_BSS));
 280         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 281                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 282                            !rt2x00dev->intf_ap_count);
 283         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 284         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 285                            !(filter_flags & FIF_ALLMULTI));
 286         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 287         rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 288 }
 289
 290 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 291                                   struct rt2x00_intf *intf,
 292                                   struct rt2x00intf_conf *conf,
 293                                   const unsigned int flags)
 294 {
 295         struct data_queue *queue = rt2x00dev->bcn;
 296         unsigned int bcn_preload;
 297         u32 reg;
 298
 299         if (flags & CONFIG_UPDATE_TYPE) {
 300                 /*
 301                  * Enable beacon config
 302                  */
 303                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
 304                 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, &reg);
 305                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 306                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 307                 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
 308
 309                 /*
 310                  * Enable synchronisation.
 311                  */
 312                 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 313                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 314                 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 315         }
 316
 317         if (flags & CONFIG_UPDATE_MAC)
 318                 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
 319                                               conf->mac, sizeof(conf->mac));
 320
 321         if (flags & CONFIG_UPDATE_BSSID)
 322                 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
 323                                               conf->bssid, sizeof(conf->bssid));
 324 }
 325
 326 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 327                                  struct rt2x00lib_erp *erp,
 328                                  u32 changed)
 329 {
 330         int preamble_mask;
 331         u32 reg;
 332
 333         /*
 334          * When short preamble is enabled, we should set bit 0x08
 335          */
 336         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 337                 preamble_mask = erp->short_preamble << 3;
 338
 339                 rt2x00mmio_register_read(rt2x00dev, TXCSR1, &reg);
 340                 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
 341                 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
 342                 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 343                 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 344                 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
 345
 346                 rt2x00mmio_register_read(rt2x00dev, ARCSR2, &reg);
 347                 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 348                 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 349                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 350                                    GET_DURATION(ACK_SIZE, 10));
 351                 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
 352
 353                 rt2x00mmio_register_read(rt2x00dev, ARCSR3, &reg);
 354                 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 355                 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 356                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 357                                    GET_DURATION(ACK_SIZE, 20));
 358                 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
 359
 360                 rt2x00mmio_register_read(rt2x00dev, ARCSR4, &reg);
 361                 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 362                 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 363                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 364                                    GET_DURATION(ACK_SIZE, 55));
 365                 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
 366
 367                 rt2x00mmio_register_read(rt2x00dev, ARCSR5, &reg);
 368                 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 369                 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 370                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 371                                    GET_DURATION(ACK_SIZE, 110));
 372                 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
 373         }
 374
 375         if (changed & BSS_CHANGED_BASIC_RATES)
 376                 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 377
 378         if (changed & BSS_CHANGED_ERP_SLOT) {
 379                 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
 380                 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 381                 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 382
 383                 rt2x00mmio_register_read(rt2x00dev, CSR18, &reg);
 384                 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 385                 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 386                 rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
 387
 388                 rt2x00mmio_register_read(rt2x00dev, CSR19, &reg);
 389                 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 390                 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 391                 rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
 392         }
 393
 394         if (changed & BSS_CHANGED_BEACON_INT) {
 395                 rt2x00mmio_register_read(rt2x00dev, CSR12, &reg);
 396                 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 397                                    erp->beacon_int * 16);
 398                 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 399                                    erp->beacon_int * 16);
 400                 rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
 401         }
 402
 403 }
 404
 405 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
 406                                  struct antenna_setup *ant)
 407 {
 408         u32 reg;
 409         u8 r14;
 410         u8 r2;
 411
 412         /*
 413          * We should never come here because rt2x00lib is supposed
 414          * to catch this and send us the correct antenna explicitely.
 415          */
 416         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 417                ant->tx == ANTENNA_SW_DIVERSITY);
 418
 419         rt2x00mmio_register_read(rt2x00dev, BBPCSR1, &reg);
 420         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 421         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 422
 423         /*
 424          * Configure the TX antenna.
 425          */
 426         switch (ant->tx) {
 427         case ANTENNA_A:
 428                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 429                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 430                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 431                 break;
 432         case ANTENNA_B:
 433         default:
 434                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 435                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 436                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 437                 break;
 438         }
 439
 440         /*
 441          * Configure the RX antenna.
 442          */
 443         switch (ant->rx) {
 444         case ANTENNA_A:
 445                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 446                 break;
 447         case ANTENNA_B:
 448         default:
 449                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 450                 break;
 451         }
 452
 453         /*
 454          * RT2525E and RT5222 need to flip TX I/Q
 455          */
 456         if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
 457                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 458                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 459                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 460
 461                 /*
 462                  * RT2525E does not need RX I/Q Flip.
 463                  */
 464                 if (rt2x00_rf(rt2x00dev, RF2525E))
 465                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 466         } else {
 467                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 468                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 469         }
 470
 471         rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg);
 472         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 473         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 474 }
 475
 476 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 477                                      struct rf_channel *rf, const int txpower)
 478 {
 479         u8 r70;
 480
 481         /*
 482          * Set TXpower.
 483          */
 484         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 485
 486         /*
 487          * Switch on tuning bits.
 488          * For RT2523 devices we do not need to update the R1 register.
 489          */
 490         if (!rt2x00_rf(rt2x00dev, RF2523))
 491                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 492         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 493
 494         /*
 495          * For RT2525 we should first set the channel to half band higher.
 496          */
 497         if (rt2x00_rf(rt2x00dev, RF2525)) {
 498                 static const u32 vals[] = {
 499                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 500                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 501                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 502                         0x00080d2e, 0x00080d3a
 503                 };
 504
 505                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 506                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 507                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 508                 if (rf->rf4)
 509                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 510         }
 511
 512         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 513         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 514         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 515         if (rf->rf4)
 516                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 517
 518         /*
 519          * Channel 14 requires the Japan filter bit to be set.
 520          */
 521         r70 = 0x46;
 522         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 523         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 524
 525         msleep(1);
 526
 527         /*
 528          * Switch off tuning bits.
 529          * For RT2523 devices we do not need to update the R1 register.
 530          */
 531         if (!rt2x00_rf(rt2x00dev, RF2523)) {
 532                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 533                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 534         }
 535
 536         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 537         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 538
 539         /*
 540          * Clear false CRC during channel switch.
 541          */
 542         rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1);
 543 }
 544
 545 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 546                                      const int txpower)
 547 {
 548         u32 rf3;
 549
 550         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 551         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 552         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 553 }
 554
 555 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 556                                          struct rt2x00lib_conf *libconf)
 557 {
 558         u32 reg;
 559
 560         rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
 561         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 562                            libconf->conf->long_frame_max_tx_count);
 563         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 564                            libconf->conf->short_frame_max_tx_count);
 565         rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 566 }
 567
 568 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
 569                                 struct rt2x00lib_conf *libconf)
 570 {
 571         enum dev_state state =
 572             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 573                 STATE_SLEEP : STATE_AWAKE;
 574         u32 reg;
 575
 576         if (state == STATE_SLEEP) {
 577                 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
 578                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
 579                                    (rt2x00dev->beacon_int - 20) * 16);
 580                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
 581                                    libconf->conf->listen_interval - 1);
 582
 583                 /* We must first disable autowake before it can be enabled */
 584                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 585                 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 586
 587                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
 588                 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 589         } else {
 590                 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
 591                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 592                 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 593         }
 594
 595         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 596 }
 597
 598 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 599                              struct rt2x00lib_conf *libconf,
 600                              const unsigned int flags)
 601 {
 602         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 603                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 604                                          libconf->conf->power_level);
 605         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 606             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 607                 rt2500pci_config_txpower(rt2x00dev,
 608                                          libconf->conf->power_level);
 609         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 610                 rt2500pci_config_retry_limit(rt2x00dev, libconf);
 611         if (flags & IEEE80211_CONF_CHANGE_PS)
 612                 rt2500pci_config_ps(rt2x00dev, libconf);
 613 }
 614
 615 /*
 616  * Link tuning
 617  */
 618 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 619                                  struct link_qual *qual)
 620 {
 621         u32 reg;
 622
 623         /*
 624          * Update FCS error count from register.
 625          */
 626         rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
 627         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 628
 629         /*
 630          * Update False CCA count from register.
 631          */
 632         rt2x00mmio_register_read(rt2x00dev, CNT3, &reg);
 633         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 634 }
 635
 636 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
 637                                      struct link_qual *qual, u8 vgc_level)
 638 {
 639         if (qual->vgc_level_reg != vgc_level) {
 640                 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
 641                 qual->vgc_level = vgc_level;
 642                 qual->vgc_level_reg = vgc_level;
 643         }
 644 }
 645
 646 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
 647                                   struct link_qual *qual)
 648 {
 649         rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
 650 }
 651
 652 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 653                                  struct link_qual *qual, const u32 count)
 654 {
 655         /*
 656          * To prevent collisions with MAC ASIC on chipsets
 657          * up to version C the link tuning should halt after 20
 658          * seconds while being associated.
 659          */
 660         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
 661             rt2x00dev->intf_associated && count > 20)
 662                 return;
 663
 664         /*
 665          * Chipset versions C and lower should directly continue
 666          * to the dynamic CCA tuning. Chipset version D and higher
 667          * should go straight to dynamic CCA tuning when they
 668          * are not associated.
 669          */
 670         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
 671             !rt2x00dev->intf_associated)
 672                 goto dynamic_cca_tune;
 673
 674         /*
 675          * A too low RSSI will cause too much false CCA which will
 676          * then corrupt the R17 tuning. To remidy this the tuning should
 677          * be stopped (While making sure the R17 value will not exceed limits)
 678          */
 679         if (qual->rssi < -80 && count > 20) {
 680                 if (qual->vgc_level_reg >= 0x41)
 681                         rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 682                 return;
 683         }
 684
 685         /*
 686          * Special big-R17 for short distance
 687          */
 688         if (qual->rssi >= -58) {
 689                 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
 690                 return;
 691         }
 692
 693         /*
 694          * Special mid-R17 for middle distance
 695          */
 696         if (qual->rssi >= -74) {
 697                 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
 698                 return;
 699         }
 700
 701         /*
 702          * Leave short or middle distance condition, restore r17
 703          * to the dynamic tuning range.
 704          */
 705         if (qual->vgc_level_reg >= 0x41) {
 706                 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 707                 return;
 708         }
 709
 710 dynamic_cca_tune:
 711
 712         /*
 713          * R17 is inside the dynamic tuning range,
 714          * start tuning the link based on the false cca counter.
 715          */
 716         if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40)
 717                 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
 718         else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32)
 719                 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
 720 }
 721
 722 /*
 723  * Queue handlers.
 724  */
 725 static void rt2500pci_start_queue(struct data_queue *queue)
 726 {
 727         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 728         u32 reg;
 729
 730         switch (queue->qid) {
 731         case QID_RX:
 732                 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
 733                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
 734                 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 735                 break;
 736         case QID_BEACON:
 737                 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 738                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 739                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 740                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
 741                 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 742                 break;
 743         default:
 744                 break;
 745         }
 746 }
 747
 748 static void rt2500pci_kick_queue(struct data_queue *queue)
 749 {
 750         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 751         u32 reg;
 752
 753         switch (queue->qid) {
 754         case QID_AC_VO:
 755                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 756                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
 757                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 758                 break;
 759         case QID_AC_VI:
 760                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 761                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
 762                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 763                 break;
 764         case QID_ATIM:
 765                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 766                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
 767                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 768                 break;
 769         default:
 770                 break;
 771         }
 772 }
 773
 774 static void rt2500pci_stop_queue(struct data_queue *queue)
 775 {
 776         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 777         u32 reg;
 778
 779         switch (queue->qid) {
 780         case QID_AC_VO:
 781         case QID_AC_VI:
 782         case QID_ATIM:
 783                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 784                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 785                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 786                 break;
 787         case QID_RX:
 788                 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
 789                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
 790                 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 791                 break;
 792         case QID_BEACON:
 793                 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 794                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 795                 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 796                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 797                 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 798
 799                 /*
 800                  * Wait for possibly running tbtt tasklets.
 801                  */
 802                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
 803                 break;
 804         default:
 805                 break;
 806         }
 807 }
 808
 809 /*
 810  * Initialization functions.
 811  */
 812 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
 813 {
 814         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
 815         u32 word;
 816
 817         if (entry->queue->qid == QID_RX) {
 818                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 819
 820                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
 821         } else {
 822                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 823
 824                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
 825                         rt2x00_get_field32(word, TXD_W0_VALID));
 826         }
 827 }
 828
 829 static void rt2500pci_clear_entry(struct queue_entry *entry)
 830 {
 831         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
 832         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 833         u32 word;
 834
 835         if (entry->queue->qid == QID_RX) {
 836                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 837                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 838                 rt2x00_desc_write(entry_priv->desc, 1, word);
 839
 840                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 841                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 842                 rt2x00_desc_write(entry_priv->desc, 0, word);
 843         } else {
 844                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 845                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 846                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 847                 rt2x00_desc_write(entry_priv->desc, 0, word);
 848         }
 849 }
 850
 851 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 852 {
 853         struct queue_entry_priv_mmio *entry_priv;
 854         u32 reg;
 855
 856         /*
 857          * Initialize registers.
 858          */
 859         rt2x00mmio_register_read(rt2x00dev, TXCSR2, &reg);
 860         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 861         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 862         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
 863         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 864         rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
 865
 866         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 867         rt2x00mmio_register_read(rt2x00dev, TXCSR3, &reg);
 868         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 869                            entry_priv->desc_dma);
 870         rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
 871
 872         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 873         rt2x00mmio_register_read(rt2x00dev, TXCSR5, &reg);
 874         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 875                            entry_priv->desc_dma);
 876         rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
 877
 878         entry_priv = rt2x00dev->atim->entries[0].priv_data;
 879         rt2x00mmio_register_read(rt2x00dev, TXCSR4, &reg);
 880         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 881                            entry_priv->desc_dma);
 882         rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
 883
 884         entry_priv = rt2x00dev->bcn->entries[0].priv_data;
 885         rt2x00mmio_register_read(rt2x00dev, TXCSR6, &reg);
 886         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 887                            entry_priv->desc_dma);
 888         rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
 889
 890         rt2x00mmio_register_read(rt2x00dev, RXCSR1, &reg);
 891         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 892         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 893         rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
 894
 895         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 896         rt2x00mmio_register_read(rt2x00dev, RXCSR2, &reg);
 897         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 898                            entry_priv->desc_dma);
 899         rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
 900
 901         return 0;
 902 }
 903
 904 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 905 {
 906         u32 reg;
 907
 908         rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
 909         rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
 910         rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00020002);
 911         rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
 912
 913         rt2x00mmio_register_read(rt2x00dev, TIMECSR, &reg);
 914         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 915         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 916         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 917         rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
 918
 919         rt2x00mmio_register_read(rt2x00dev, CSR9, &reg);
 920         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 921                            rt2x00dev->rx->data_size / 128);
 922         rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
 923
 924         /*
 925          * Always use CWmin and CWmax set in descriptor.
 926          */
 927         rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
 928         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 929         rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 930
 931         rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 932         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 933         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 934         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 935         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 936         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 937         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 938         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 939         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 940         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 941
 942         rt2x00mmio_register_write(rt2x00dev, CNT3, 0);
 943
 944         rt2x00mmio_register_read(rt2x00dev, TXCSR8, &reg);
 945         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 946         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 947         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 948         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 949         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 950         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 951         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 952         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 953         rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg);
 954
 955         rt2x00mmio_register_read(rt2x00dev, ARTCSR0, &reg);
 956         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 957         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 958         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 959         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 960         rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg);
 961
 962         rt2x00mmio_register_read(rt2x00dev, ARTCSR1, &reg);
 963         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 964         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 965         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 966         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 967         rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg);
 968
 969         rt2x00mmio_register_read(rt2x00dev, ARTCSR2, &reg);
 970         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 971         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 972         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 973         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 974         rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg);
 975
 976         rt2x00mmio_register_read(rt2x00dev, RXCSR3, &reg);
 977         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 978         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 979         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 980         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 981         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 982         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 983         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 984         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 985         rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
 986
 987         rt2x00mmio_register_read(rt2x00dev, PCICSR, &reg);
 988         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 989         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 990         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 991         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 992         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 993         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 994         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 995         rt2x00mmio_register_write(rt2x00dev, PCICSR, reg);
 996
 997         rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 998
 999         rt2x00mmio_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
1000         rt2x00mmio_register_write(rt2x00dev, TESTCSR, 0x000000f0);
1001
1002         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1003                 return -EBUSY;
1004
1005         rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00213223);
1006         rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
1007
1008         rt2x00mmio_register_read(rt2x00dev, MACCSR2, &reg);
1009         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
1010         rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
1011
1012         rt2x00mmio_register_read(rt2x00dev, RALINKCSR, &reg);
1013         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
1014         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
1015         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
1016         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
1017         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
1018         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
1019         rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
1020
1021         rt2x00mmio_register_write(rt2x00dev, BBPCSR1, 0x82188200);
1022
1023         rt2x00mmio_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
1024
1025         rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
1026         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
1027         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
1028         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
1029         rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
1030
1031         rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
1032         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
1033         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
1034         rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
1035
1036         /*
1037          * We must clear the FCS and FIFO error count.
1038          * These registers are cleared on read,
1039          * so we may pass a useless variable to store the value.
1040          */
1041         rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
1042         rt2x00mmio_register_read(rt2x00dev, CNT4, &reg);
1043
1044         return 0;
1045 }
1046
1047 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1048 {
1049         unsigned int i;
1050         u8 value;
1051
1052         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1053                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
1054                 if ((value != 0xff) && (value != 0x00))
1055                         return 0;
1056                 udelay(REGISTER_BUSY_DELAY);
1057         }
1058
1059         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
1060         return -EACCES;
1061 }
1062
1063 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1064 {
1065         unsigned int i;
1066         u16 eeprom;
1067         u8 reg_id;
1068         u8 value;
1069
1070         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
1071                 return -EACCES;
1072
1073         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1074         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1075         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1076         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1077         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1078         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1079         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1080         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1081         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1082         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1083         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1084         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1085         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1086         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1087         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1088         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1089         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1090         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1091         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1092         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1093         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1094         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1095         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1096         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1097         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1098         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1099         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1100         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1101         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1102         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1103
1104         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1105                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1106
1107                 if (eeprom != 0xffff && eeprom != 0x0000) {
1108                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1109                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1110                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1111                 }
1112         }
1113
1114         return 0;
1115 }
1116
1117 /*
1118  * Device state switch handlers.
1119  */
1120 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1121                                  enum dev_state state)
1122 {
1123         int mask = (state == STATE_RADIO_IRQ_OFF);
1124         u32 reg;
1125         unsigned long flags;
1126
1127         /*
1128          * When interrupts are being enabled, the interrupt registers
1129          * should clear the register to assure a clean state.
1130          */
1131         if (state == STATE_RADIO_IRQ_ON) {
1132                 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
1133                 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1134         }
1135
1136         /*
1137          * Only toggle the interrupts bits we are going to use.
1138          * Non-checked interrupt bits are disabled by default.
1139          */
1140         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1141
1142         rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1143         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1144         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1145         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1146         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1147         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1148         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1149
1150         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1151
1152         if (state == STATE_RADIO_IRQ_OFF) {
1153                 /*
1154                  * Ensure that all tasklets are finished.
1155                  */
1156                 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1157                 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1158                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1159         }
1160 }
1161
1162 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1163 {
1164         /*
1165          * Initialize all registers.
1166          */
1167         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1168                      rt2500pci_init_registers(rt2x00dev) ||
1169                      rt2500pci_init_bbp(rt2x00dev)))
1170                 return -EIO;
1171
1172         return 0;
1173 }
1174
1175 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1176 {
1177         /*
1178          * Disable power
1179          */
1180         rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
1181 }
1182
1183 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1184                                enum dev_state state)
1185 {
1186         u32 reg, reg2;
1187         unsigned int i;
1188         char put_to_sleep;
1189         char bbp_state;
1190         char rf_state;
1191
1192         put_to_sleep = (state != STATE_AWAKE);
1193
1194         rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg);
1195         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1196         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1197         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1198         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1199         rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1200
1201         /*
1202          * Device is not guaranteed to be in the requested state yet.
1203          * We must wait until the register indicates that the
1204          * device has entered the correct state.
1205          */
1206         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1207                 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg2);
1208                 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1209                 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1210                 if (bbp_state == state && rf_state == state)
1211                         return 0;
1212                 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1213                 msleep(10);
1214         }
1215
1216         return -EBUSY;
1217 }
1218
1219 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1220                                       enum dev_state state)
1221 {
1222         int retval = 0;
1223
1224         switch (state) {
1225         case STATE_RADIO_ON:
1226                 retval = rt2500pci_enable_radio(rt2x00dev);
1227                 break;
1228         case STATE_RADIO_OFF:
1229                 rt2500pci_disable_radio(rt2x00dev);
1230                 break;
1231         case STATE_RADIO_IRQ_ON:
1232         case STATE_RADIO_IRQ_OFF:
1233                 rt2500pci_toggle_irq(rt2x00dev, state);
1234                 break;
1235         case STATE_DEEP_SLEEP:
1236         case STATE_SLEEP:
1237         case STATE_STANDBY:
1238         case STATE_AWAKE:
1239                 retval = rt2500pci_set_state(rt2x00dev, state);
1240                 break;
1241         default:
1242                 retval = -ENOTSUPP;
1243                 break;
1244         }
1245
1246         if (unlikely(retval))
1247                 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1248                            state, retval);
1249
1250         return retval;
1251 }
1252
1253 /*
1254  * TX descriptor initialization
1255  */
1256 static void rt2500pci_write_tx_desc(struct queue_entry *entry,
1257                                     struct txentry_desc *txdesc)
1258 {
1259         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1260         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1261         __le32 *txd = entry_priv->desc;
1262         u32 word;
1263
1264         /*
1265          * Start writing the descriptor words.
1266          */
1267         rt2x00_desc_read(txd, 1, &word);
1268         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1269         rt2x00_desc_write(txd, 1, word);
1270
1271         rt2x00_desc_read(txd, 2, &word);
1272         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1273         rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);
1274         rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);
1275         rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);
1276         rt2x00_desc_write(txd, 2, word);
1277
1278         rt2x00_desc_read(txd, 3, &word);
1279         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1280         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1281         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW,
1282                            txdesc->u.plcp.length_low);
1283         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH,
1284                            txdesc->u.plcp.length_high);
1285         rt2x00_desc_write(txd, 3, word);
1286
1287         rt2x00_desc_read(txd, 10, &word);
1288         rt2x00_set_field32(&word, TXD_W10_RTS,
1289                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1290         rt2x00_desc_write(txd, 10, word);
1291
1292         /*
1293          * Writing TXD word 0 must the last to prevent a race condition with
1294          * the device, whereby the device may take hold of the TXD before we
1295          * finished updating it.
1296          */
1297         rt2x00_desc_read(txd, 0, &word);
1298         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1299         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1300         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1301                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1302         rt2x00_set_field32(&word, TXD_W0_ACK,
1303                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1304         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1305                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1306         rt2x00_set_field32(&word, TXD_W0_OFDM,
1307                            (txdesc->rate_mode == RATE_MODE_OFDM));
1308         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1309         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1310         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1311                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1312         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1313         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1314         rt2x00_desc_write(txd, 0, word);
1315
1316         /*
1317          * Register descriptor details in skb frame descriptor.
1318          */
1319         skbdesc->desc = txd;
1320         skbdesc->desc_len = TXD_DESC_SIZE;
1321 }
1322
1323 /*
1324  * TX data initialization
1325  */
1326 static void rt2500pci_write_beacon(struct queue_entry *entry,
1327                                    struct txentry_desc *txdesc)
1328 {
1329         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1330         u32 reg;
1331
1332         /*
1333          * Disable beaconing while we are reloading the beacon data,
1334          * otherwise we might be sending out invalid data.
1335          */
1336         rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
1337         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1338         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1339
1340         if (rt2x00queue_map_txskb(entry)) {
1341                 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
1342                 goto out;
1343         }
1344
1345         /*
1346          * Write the TX descriptor for the beacon.
1347          */
1348         rt2500pci_write_tx_desc(entry, txdesc);
1349
1350         /*
1351          * Dump beacon to userspace through debugfs.
1352          */
1353         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1354 out:
1355         /*
1356          * Enable beaconing again.
1357          */
1358         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1359         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1360 }
1361
1362 /*
1363  * RX control handlers
1364  */
1365 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1366                                   struct rxdone_entry_desc *rxdesc)
1367 {
1368         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1369         u32 word0;
1370         u32 word2;
1371
1372         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1373         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1374
1375         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1376                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1377         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1378                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1379
1380         /*
1381          * Obtain the status about this packet.
1382          * When frame was received with an OFDM bitrate,
1383          * the signal is the PLCP value. If it was received with
1384          * a CCK bitrate the signal is the rate in 100kbit/s.
1385          */
1386         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1387         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1388             entry->queue->rt2x00dev->rssi_offset;
1389         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1390
1391         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1392                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1393         else
1394                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1395         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1396                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1397 }
1398
1399 /*
1400  * Interrupt functions.
1401  */
1402 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1403                              const enum data_queue_qid queue_idx)
1404 {
1405         struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1406         struct queue_entry_priv_mmio *entry_priv;
1407         struct queue_entry *entry;
1408         struct txdone_entry_desc txdesc;
1409         u32 word;
1410
1411         while (!rt2x00queue_empty(queue)) {
1412                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1413                 entry_priv = entry->priv_data;
1414                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1415
1416                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1417                     !rt2x00_get_field32(word, TXD_W0_VALID))
1418                         break;
1419
1420                 /*
1421                  * Obtain the status about this packet.
1422                  */
1423                 txdesc.flags = 0;
1424                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1425                 case 0: /* Success */
1426                 case 1: /* Success with retry */
1427                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1428                         break;
1429                 case 2: /* Failure, excessive retries */
1430                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1431                         /* Don't break, this is a failed frame! */
1432                 default: /* Failure */
1433                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1434                 }
1435                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1436
1437                 rt2x00lib_txdone(entry, &txdesc);
1438         }
1439 }
1440
1441 static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1442                                               struct rt2x00_field32 irq_field)
1443 {
1444         u32 reg;
1445
1446         /*
1447          * Enable a single interrupt. The interrupt mask register
1448          * access needs locking.
1449          */
1450         spin_lock_irq(&rt2x00dev->irqmask_lock);
1451
1452         rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1453         rt2x00_set_field32(&reg, irq_field, 0);
1454         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1455
1456         spin_unlock_irq(&rt2x00dev->irqmask_lock);
1457 }
1458
1459 static void rt2500pci_txstatus_tasklet(unsigned long data)
1460 {
1461         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1462         u32 reg;
1463
1464         /*
1465          * Handle all tx queues.
1466          */
1467         rt2500pci_txdone(rt2x00dev, QID_ATIM);
1468         rt2500pci_txdone(rt2x00dev, QID_AC_VO);
1469         rt2500pci_txdone(rt2x00dev, QID_AC_VI);
1470
1471         /*
1472          * Enable all TXDONE interrupts again.
1473          */
1474         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1475                 spin_lock_irq(&rt2x00dev->irqmask_lock);
1476
1477                 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1478                 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1479                 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1480                 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1481                 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1482
1483                 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1484         }
1485 }
1486
1487 static void rt2500pci_tbtt_tasklet(unsigned long data)
1488 {
1489         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1490         rt2x00lib_beacondone(rt2x00dev);
1491         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1492                 rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1493 }
1494
1495 static void rt2500pci_rxdone_tasklet(unsigned long data)
1496 {
1497         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1498         if (rt2x00mmio_rxdone(rt2x00dev))
1499                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1500         else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1501                 rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1502 }
1503
1504 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1505 {
1506         struct rt2x00_dev *rt2x00dev = dev_instance;
1507         u32 reg, mask;
1508
1509         /*
1510          * Get the interrupt sources & saved to local variable.
1511          * Write register value back to clear pending interrupts.
1512          */
1513         rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
1514         rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1515
1516         if (!reg)
1517                 return IRQ_NONE;
1518
1519         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1520                 return IRQ_HANDLED;
1521
1522         mask = reg;
1523
1524         /*
1525          * Schedule tasklets for interrupt handling.
1526          */
1527         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1528                 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1529
1530         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1531                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1532
1533         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1534             rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1535             rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1536                 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1537                 /*
1538                  * Mask out all txdone interrupts.
1539                  */
1540                 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1541                 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1542                 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1543         }
1544
1545         /*
1546          * Disable all interrupts for which a tasklet was scheduled right now,
1547          * the tasklet will reenable the appropriate interrupts.
1548          */
1549         spin_lock(&rt2x00dev->irqmask_lock);
1550
1551         rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1552         reg |= mask;
1553         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1554
1555         spin_unlock(&rt2x00dev->irqmask_lock);
1556
1557         return IRQ_HANDLED;
1558 }
1559
1560 /*
1561  * Device probe functions.
1562  */
1563 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1564 {
1565         struct eeprom_93cx6 eeprom;
1566         u32 reg;
1567         u16 word;
1568         u8 *mac;
1569
1570         rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
1571
1572         eeprom.data = rt2x00dev;
1573         eeprom.register_read = rt2500pci_eepromregister_read;
1574         eeprom.register_write = rt2500pci_eepromregister_write;
1575         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1576             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1577         eeprom.reg_data_in = 0;
1578         eeprom.reg_data_out = 0;
1579         eeprom.reg_data_clock = 0;
1580         eeprom.reg_chip_select = 0;
1581
1582         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1583                                EEPROM_SIZE / sizeof(u16));
1584
1585         /*
1586          * Start validation of the data that has been read.
1587          */
1588         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1589         if (!is_valid_ether_addr(mac)) {
1590                 eth_random_addr(mac);
1591                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
1592         }
1593
1594         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1595         if (word == 0xffff) {
1596                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1597                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1598                                    ANTENNA_SW_DIVERSITY);
1599                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1600                                    ANTENNA_SW_DIVERSITY);
1601                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1602                                    LED_MODE_DEFAULT);
1603                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1604                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1605                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1606                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1607                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
1608         }
1609
1610         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1611         if (word == 0xffff) {
1612                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1613                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1614                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1615                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1616                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
1617         }
1618
1619         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1620         if (word == 0xffff) {
1621                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1622                                    DEFAULT_RSSI_OFFSET);
1623                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1624                 rt2x00_eeprom_dbg(rt2x00dev, "Calibrate offset: 0x%04x\n",
1625                                   word);
1626         }
1627
1628         return 0;
1629 }
1630
1631 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1632 {
1633         u32 reg;
1634         u16 value;
1635         u16 eeprom;
1636
1637         /*
1638          * Read EEPROM word for configuration.
1639          */
1640         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1641
1642         /*
1643          * Identify RF chipset.
1644          */
1645         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1646         rt2x00mmio_register_read(rt2x00dev, CSR0, &reg);
1647         rt2x00_set_chip(rt2x00dev, RT2560, value,
1648                         rt2x00_get_field32(reg, CSR0_REVISION));
1649
1650         if (!rt2x00_rf(rt2x00dev, RF2522) &&
1651             !rt2x00_rf(rt2x00dev, RF2523) &&
1652             !rt2x00_rf(rt2x00dev, RF2524) &&
1653             !rt2x00_rf(rt2x00dev, RF2525) &&
1654             !rt2x00_rf(rt2x00dev, RF2525E) &&
1655             !rt2x00_rf(rt2x00dev, RF5222)) {
1656                 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1657                 return -ENODEV;
1658         }
1659
1660         /*
1661          * Identify default antenna configuration.
1662          */
1663         rt2x00dev->default_ant.tx =
1664             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1665         rt2x00dev->default_ant.rx =
1666             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1667
1668         /*
1669          * Store led mode, for correct led behaviour.
1670          */
1671 #ifdef CONFIG_RT2X00_LIB_LEDS
1672         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1673
1674         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1675         if (value == LED_MODE_TXRX_ACTIVITY ||
1676             value == LED_MODE_DEFAULT ||
1677             value == LED_MODE_ASUS)
1678                 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1679                                    LED_TYPE_ACTIVITY);
1680 #endif /* CONFIG_RT2X00_LIB_LEDS */
1681
1682         /*
1683          * Detect if this device has an hardware controlled radio.
1684          */
1685         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1686                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1687
1688         /*
1689          * Check if the BBP tuning should be enabled.
1690          */
1691         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1692         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1693                 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1694
1695         /*
1696          * Read the RSSI <-> dBm offset information.
1697          */
1698         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1699         rt2x00dev->rssi_offset =
1700             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1701
1702         return 0;
1703 }
1704
1705 /*
1706  * RF value list for RF2522
1707  * Supports: 2.4 GHz
1708  */
1709 static const struct rf_channel rf_vals_bg_2522[] = {
1710         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1711         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1712         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1713         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1714         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1715         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1716         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1717         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1718         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1719         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1720         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1721         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1722         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1723         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1724 };
1725
1726 /*
1727  * RF value list for RF2523
1728  * Supports: 2.4 GHz
1729  */
1730 static const struct rf_channel rf_vals_bg_2523[] = {
1731         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1732         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1733         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1734         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1735         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1736         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1737         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1738         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1739         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1740         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1741         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1742         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1743         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1744         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1745 };
1746
1747 /*
1748  * RF value list for RF2524
1749  * Supports: 2.4 GHz
1750  */
1751 static const struct rf_channel rf_vals_bg_2524[] = {
1752         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1753         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1754         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1755         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1756         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1757         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1758         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1759         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1760         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1761         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1762         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1763         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1764         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1765         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1766 };
1767
1768 /*
1769  * RF value list for RF2525
1770  * Supports: 2.4 GHz
1771  */
1772 static const struct rf_channel rf_vals_bg_2525[] = {
1773         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1774         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1775         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1776         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1777         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1778         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1779         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1780         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1781         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1782         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1783         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1784         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1785         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1786         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1787 };
1788
1789 /*
1790  * RF value list for RF2525e
1791  * Supports: 2.4 GHz
1792  */
1793 static const struct rf_channel rf_vals_bg_2525e[] = {
1794         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1795         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1796         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1797         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1798         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1799         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1800         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1801         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1802         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1803         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1804         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1805         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1806         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1807         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1808 };
1809
1810 /*
1811  * RF value list for RF5222
1812  * Supports: 2.4 GHz & 5.2 GHz
1813  */
1814 static const struct rf_channel rf_vals_5222[] = {
1815         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1816         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1817         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1818         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1819         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1820         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1821         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1822         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1823         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1824         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1825         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1826         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1827         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1828         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1829
1830         /* 802.11 UNI / HyperLan 2 */
1831         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1832         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1833         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1834         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1835         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1836         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1837         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1838         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1839
1840         /* 802.11 HyperLan 2 */
1841         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1842         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1843         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1844         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1845         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1846         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1847         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1848         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1849         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1850         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1851
1852         /* 802.11 UNII */
1853         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1854         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1855         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1856         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1857         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1858 };
1859
1860 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1861 {
1862         struct hw_mode_spec *spec = &rt2x00dev->spec;
1863         struct channel_info *info;
1864         char *tx_power;
1865         unsigned int i;
1866
1867         /*
1868          * Initialize all hw fields.
1869          */
1870         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1871                                IEEE80211_HW_SIGNAL_DBM |
1872                                IEEE80211_HW_SUPPORTS_PS |
1873                                IEEE80211_HW_PS_NULLFUNC_STACK;
1874
1875         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1876         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1877                                 rt2x00_eeprom_addr(rt2x00dev,
1878                                                    EEPROM_MAC_ADDR_0));
1879
1880         /*
1881          * Initialize hw_mode information.
1882          */
1883         spec->supported_bands = SUPPORT_BAND_2GHZ;
1884         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1885
1886         if (rt2x00_rf(rt2x00dev, RF2522)) {
1887                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1888                 spec->channels = rf_vals_bg_2522;
1889         } else if (rt2x00_rf(rt2x00dev, RF2523)) {
1890                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1891                 spec->channels = rf_vals_bg_2523;
1892         } else if (rt2x00_rf(rt2x00dev, RF2524)) {
1893                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1894                 spec->channels = rf_vals_bg_2524;
1895         } else if (rt2x00_rf(rt2x00dev, RF2525)) {
1896                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1897                 spec->channels = rf_vals_bg_2525;
1898         } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
1899                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1900                 spec->channels = rf_vals_bg_2525e;
1901         } else if (rt2x00_rf(rt2x00dev, RF5222)) {
1902                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1903                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1904                 spec->channels = rf_vals_5222;
1905         }
1906
1907         /*
1908          * Create channel information array
1909          */
1910         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1911         if (!info)
1912                 return -ENOMEM;
1913
1914         spec->channels_info = info;
1915
1916         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1917         for (i = 0; i < 14; i++) {
1918                 info[i].max_power = MAX_TXPOWER;
1919                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1920         }
1921
1922         if (spec->num_channels > 14) {
1923                 for (i = 14; i < spec->num_channels; i++) {
1924                         info[i].max_power = MAX_TXPOWER;
1925                         info[i].default_power1 = DEFAULT_TXPOWER;
1926                 }
1927         }
1928
1929         return 0;
1930 }
1931
1932 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1933 {
1934         int retval;
1935         u32 reg;
1936
1937         /*
1938          * Allocate eeprom data.
1939          */
1940         retval = rt2500pci_validate_eeprom(rt2x00dev);
1941         if (retval)
1942                 return retval;
1943
1944         retval = rt2500pci_init_eeprom(rt2x00dev);
1945         if (retval)
1946                 return retval;
1947
1948         /*
1949          * Enable rfkill polling by setting GPIO direction of the
1950          * rfkill switch GPIO pin correctly.
1951          */
1952         rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
1953         rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
1954         rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1955
1956         /*
1957          * Initialize hw specifications.
1958          */
1959         retval = rt2500pci_probe_hw_mode(rt2x00dev);
1960         if (retval)
1961                 return retval;
1962
1963         /*
1964          * This device requires the atim queue and DMA-mapped skbs.
1965          */
1966         __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1967         __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1968         __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1969
1970         /*
1971          * Set the rssi offset.
1972          */
1973         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1974
1975         return 0;
1976 }
1977
1978 /*
1979  * IEEE80211 stack callback functions.
1980  */
1981 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw,
1982                              struct ieee80211_vif *vif)
1983 {
1984         struct rt2x00_dev *rt2x00dev = hw->priv;
1985         u64 tsf;
1986         u32 reg;
1987
1988         rt2x00mmio_register_read(rt2x00dev, CSR17, &reg);
1989         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1990         rt2x00mmio_register_read(rt2x00dev, CSR16, &reg);
1991         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1992
1993         return tsf;
1994 }
1995
1996 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1997 {
1998         struct rt2x00_dev *rt2x00dev = hw->priv;
1999         u32 reg;
2000
2001         rt2x00mmio_register_read(rt2x00dev, CSR15, &reg);
2002         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
2003 }
2004
2005 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
2006         .tx                     = rt2x00mac_tx,
2007         .start                  = rt2x00mac_start,
2008         .stop                   = rt2x00mac_stop,
2009         .add_interface          = rt2x00mac_add_interface,
2010         .remove_interface       = rt2x00mac_remove_interface,
2011         .config                 = rt2x00mac_config,
2012         .configure_filter       = rt2x00mac_configure_filter,
2013         .sw_scan_start          = rt2x00mac_sw_scan_start,
2014         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
2015         .get_stats              = rt2x00mac_get_stats,
2016         .bss_info_changed       = rt2x00mac_bss_info_changed,
2017         .conf_tx                = rt2x00mac_conf_tx,
2018         .get_tsf                = rt2500pci_get_tsf,
2019         .tx_last_beacon         = rt2500pci_tx_last_beacon,
2020         .rfkill_poll            = rt2x00mac_rfkill_poll,
2021         .flush                  = rt2x00mac_flush,
2022         .set_antenna            = rt2x00mac_set_antenna,
2023         .get_antenna            = rt2x00mac_get_antenna,
2024         .get_ringparam          = rt2x00mac_get_ringparam,
2025         .tx_frames_pending      = rt2x00mac_tx_frames_pending,
2026 };
2027
2028 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
2029         .irq_handler            = rt2500pci_interrupt,
2030         .txstatus_tasklet       = rt2500pci_txstatus_tasklet,
2031         .tbtt_tasklet           = rt2500pci_tbtt_tasklet,
2032         .rxdone_tasklet         = rt2500pci_rxdone_tasklet,
2033         .probe_hw               = rt2500pci_probe_hw,
2034         .initialize             = rt2x00mmio_initialize,
2035         .uninitialize           = rt2x00mmio_uninitialize,
2036         .get_entry_state        = rt2500pci_get_entry_state,
2037         .clear_entry            = rt2500pci_clear_entry,
2038         .set_device_state       = rt2500pci_set_device_state,
2039         .rfkill_poll            = rt2500pci_rfkill_poll,
2040         .link_stats             = rt2500pci_link_stats,
2041         .reset_tuner            = rt2500pci_reset_tuner,
2042         .link_tuner             = rt2500pci_link_tuner,
2043         .start_queue            = rt2500pci_start_queue,
2044         .kick_queue             = rt2500pci_kick_queue,
2045         .stop_queue             = rt2500pci_stop_queue,
2046         .flush_queue            = rt2x00mmio_flush_queue,
2047         .write_tx_desc          = rt2500pci_write_tx_desc,
2048         .write_beacon           = rt2500pci_write_beacon,
2049         .fill_rxdone            = rt2500pci_fill_rxdone,
2050         .config_filter          = rt2500pci_config_filter,
2051         .config_intf            = rt2500pci_config_intf,
2052         .config_erp             = rt2500pci_config_erp,
2053         .config_ant             = rt2500pci_config_ant,
2054         .config                 = rt2500pci_config,
2055 };
2056
2057 static void rt2500pci_queue_init(struct data_queue *queue)
2058 {
2059         switch (queue->qid) {
2060         case QID_RX:
2061                 queue->limit = 32;
2062                 queue->data_size = DATA_FRAME_SIZE;
2063                 queue->desc_size = RXD_DESC_SIZE;
2064                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2065                 break;
2066
2067         case QID_AC_VO:
2068         case QID_AC_VI:
2069         case QID_AC_BE:
2070         case QID_AC_BK:
2071                 queue->limit = 32;
2072                 queue->data_size = DATA_FRAME_SIZE;
2073                 queue->desc_size = TXD_DESC_SIZE;
2074                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2075                 break;
2076
2077         case QID_BEACON:
2078                 queue->limit = 1;
2079                 queue->data_size = MGMT_FRAME_SIZE;
2080                 queue->desc_size = TXD_DESC_SIZE;
2081                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2082                 break;
2083
2084         case QID_ATIM:
2085                 queue->limit = 8;
2086                 queue->data_size = DATA_FRAME_SIZE;
2087                 queue->desc_size = TXD_DESC_SIZE;
2088                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2089                 break;
2090
2091         default:
2092                 BUG();
2093                 break;
2094         }
2095 }
2096
2097 static const struct rt2x00_ops rt2500pci_ops = {
2098         .name                   = KBUILD_MODNAME,
2099         .max_ap_intf            = 1,
2100         .eeprom_size            = EEPROM_SIZE,
2101         .rf_size                = RF_SIZE,
2102         .tx_queues              = NUM_TX_QUEUES,
2103         .queue_init             = rt2500pci_queue_init,
2104         .lib                    = &rt2500pci_rt2x00_ops,
2105         .hw                     = &rt2500pci_mac80211_ops,
2106 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2107         .debugfs                = &rt2500pci_rt2x00debug,
2108 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2109 };
2110
2111 /*
2112  * RT2500pci module information.
2113  */
2114 static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
2115         { PCI_DEVICE(0x1814, 0x0201) },
2116         { 0, }
2117 };
2118
2119 MODULE_AUTHOR(DRV_PROJECT);
2120 MODULE_VERSION(DRV_VERSION);
2121 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
2122 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
2123 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
2124 MODULE_LICENSE("GPL");
2125
2126 static int rt2500pci_probe(struct pci_dev *pci_dev,
2127                            const struct pci_device_id *id)
2128 {
2129         return rt2x00pci_probe(pci_dev, &rt2500pci_ops);
2130 }
2131
2132 static struct pci_driver rt2500pci_driver = {
2133         .name           = KBUILD_MODNAME,
2134         .id_table       = rt2500pci_device_table,
2135         .probe          = rt2500pci_probe,
2136         .remove         = rt2x00pci_remove,
2137         .suspend        = rt2x00pci_suspend,
2138         .resume         = rt2x00pci_resume,
2139 };
2140
2141 module_pci_driver(rt2500pci_driver);