drivers/net/wireless/realtek/rtw89/phy.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /* Copyright(c) 2019-2020  Realtek Corporation
   3  */
   4
   5 #include "debug.h"
   6 #include "fw.h"
   7 #include "phy.h"
   8 #include "ps.h"
   9 #include "reg.h"
  10 #include "sar.h"
  11 #include "coex.h"
  12
  13 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
  14                              const struct rtw89_ra_report *report)
  15 {
  16         const struct rate_info *txrate = &report->txrate;
  17         u32 bit_rate = report->bit_rate;
  18         u8 mcs;
  19
  20         /* lower than ofdm, do not aggregate */
  21         if (bit_rate < 550)
  22                 return 1;
  23
  24         /* prevent hardware rate fallback to G mode rate */
  25         if (txrate->flags & RATE_INFO_FLAGS_MCS)
  26                 mcs = txrate->mcs & 0x07;
  27         else if (txrate->flags & (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_HE_MCS))
  28                 mcs = txrate->mcs;
  29         else
  30                 mcs = 0;
  31
  32         if (mcs <= 2)
  33                 return 1;
  34
  35         /* lower than 20M vht 2ss mcs8, make it small */
  36         if (bit_rate < 1800)
  37                 return 1200;
  38
  39         /* lower than 40M vht 2ss mcs9, make it medium */
  40         if (bit_rate < 4000)
  41                 return 2600;
  42
  43         /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */
  44         if (bit_rate < 7000)
  45                 return 3500;
  46
  47         return rtwdev->chip->max_amsdu_limit;
  48 }
  49
  50 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap)
  51 {
  52         u64 ra_mask = 0;
  53         u8 mcs_cap;
  54         int i, nss;
  55
  56         for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) {
  57                 mcs_cap = mcs_map & 0x3;
  58                 switch (mcs_cap) {
  59                 case 2:
  60                         ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss;
  61                         break;
  62                 case 1:
  63                         ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss;
  64                         break;
  65                 case 0:
  66                         ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss;
  67                         break;
  68                 default:
  69                         break;
  70                 }
  71         }
  72
  73         return ra_mask;
  74 }
  75
  76 static u64 get_he_ra_mask(struct ieee80211_sta *sta)
  77 {
  78         struct ieee80211_sta_he_cap cap = sta->he_cap;
  79         u16 mcs_map;
  80
  81         switch (sta->bandwidth) {
  82         case IEEE80211_STA_RX_BW_160:
  83                 if (cap.he_cap_elem.phy_cap_info[0] &
  84                     IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G)
  85                         mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80);
  86                 else
  87                         mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160);
  88                 break;
  89         default:
  90                 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80);
  91         }
  92
  93         /* MCS11, MCS9, MCS7 */
  94         return get_mcs_ra_mask(mcs_map, 11, 2);
  95 }
  96
  97 #define RA_FLOOR_TABLE_SIZE     7
  98 #define RA_FLOOR_UP_GAP         3
  99 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi,
 100                                   u8 ratr_state)
 101 {
 102         u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100};
 103         u8 rssi_lv = 0;
 104         u8 i;
 105
 106         rssi >>= 1;
 107         for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
 108                 if (i >= ratr_state)
 109                         rssi_lv_t[i] += RA_FLOOR_UP_GAP;
 110                 if (rssi < rssi_lv_t[i]) {
 111                         rssi_lv = i;
 112                         break;
 113                 }
 114         }
 115         if (rssi_lv == 0)
 116                 return 0xffffffffffffffffULL;
 117         else if (rssi_lv == 1)
 118                 return 0xfffffffffffffff0ULL;
 119         else if (rssi_lv == 2)
 120                 return 0xffffffffffffefe0ULL;
 121         else if (rssi_lv == 3)
 122                 return 0xffffffffffffcfc0ULL;
 123         else if (rssi_lv == 4)
 124                 return 0xffffffffffff8f80ULL;
 125         else if (rssi_lv >= 5)
 126                 return 0xffffffffffff0f00ULL;
 127
 128         return 0xffffffffffffffffULL;
 129 }
 130
 131 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak)
 132 {
 133         if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
 134                 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
 135
 136         if (ra_mask == 0)
 137                 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
 138
 139         return ra_mask;
 140 }
 141
 142 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)
 143 {
 144         struct rtw89_hal *hal = &rtwdev->hal;
 145         struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
 146         struct cfg80211_bitrate_mask *mask = &rtwsta->mask;
 147         enum nl80211_band band;
 148         u64 cfg_mask;
 149
 150         if (!rtwsta->use_cfg_mask)
 151                 return -1;
 152
 153         switch (hal->current_band_type) {
 154         case RTW89_BAND_2G:
 155                 band = NL80211_BAND_2GHZ;
 156                 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy,
 157                                            RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES);
 158                 break;
 159         case RTW89_BAND_5G:
 160                 band = NL80211_BAND_5GHZ;
 161                 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy,
 162                                            RA_MASK_OFDM_RATES);
 163                 break;
 164         default:
 165                 rtw89_warn(rtwdev, "unhandled band type %d\n", hal->current_band_type);
 166                 return -1;
 167         }
 168
 169         if (sta->he_cap.has_he) {
 170                 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0],
 171                                             RA_MASK_HE_1SS_RATES);
 172                 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1],
 173                                             RA_MASK_HE_2SS_RATES);
 174         } else if (sta->vht_cap.vht_supported) {
 175                 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
 176                                             RA_MASK_VHT_1SS_RATES);
 177                 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
 178                                             RA_MASK_VHT_2SS_RATES);
 179         } else if (sta->ht_cap.ht_supported) {
 180                 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
 181                                             RA_MASK_HT_1SS_RATES);
 182                 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
 183                                             RA_MASK_HT_2SS_RATES);
 184         }
 185
 186         return cfg_mask;
 187 }
 188
 189 static const u64
 190 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES,
 191                              RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES};
 192 static const u64
 193 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES,
 194                               RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES};
 195 static const u64
 196 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES,
 197                              RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES};
 198
 199 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev,
 200                                     struct ieee80211_sta *sta, bool csi)
 201 {
 202         struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
 203         struct rtw89_vif *rtwvif = rtwsta->rtwvif;
 204         struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern;
 205         struct rtw89_ra_info *ra = &rtwsta->ra;
 206         const u64 *high_rate_masks = rtw89_ra_mask_ht_rates;
 207         u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi);
 208         u64 ra_mask = 0;
 209         u64 ra_mask_bak;
 210         u8 mode = 0;
 211         u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY;
 212         u8 bw_mode = 0;
 213         u8 stbc_en = 0;
 214         u8 ldpc_en = 0;
 215         u8 i;
 216         bool sgi = false;
 217
 218         memset(ra, 0, sizeof(*ra));
 219         /* Set the ra mask from sta's capability */
 220         if (sta->he_cap.has_he) {
 221                 mode |= RTW89_RA_MODE_HE;
 222                 csi_mode = RTW89_RA_RPT_MODE_HE;
 223                 ra_mask |= get_he_ra_mask(sta);
 224                 high_rate_masks = rtw89_ra_mask_he_rates;
 225                 if (sta->he_cap.he_cap_elem.phy_cap_info[2] &
 226                     IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ)
 227                         stbc_en = 1;
 228                 if (sta->he_cap.he_cap_elem.phy_cap_info[1] &
 229                     IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD)
 230                         ldpc_en = 1;
 231         } else if (sta->vht_cap.vht_supported) {
 232                 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map);
 233
 234                 mode |= RTW89_RA_MODE_VHT;
 235                 csi_mode = RTW89_RA_RPT_MODE_VHT;
 236                 /* MCS9, MCS8, MCS7 */
 237                 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1);
 238                 high_rate_masks = rtw89_ra_mask_vht_rates;
 239                 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
 240                         stbc_en = 1;
 241                 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
 242                         ldpc_en = 1;
 243         } else if (sta->ht_cap.ht_supported) {
 244                 mode |= RTW89_RA_MODE_HT;
 245                 csi_mode = RTW89_RA_RPT_MODE_HT;
 246                 ra_mask |= ((u64)sta->ht_cap.mcs.rx_mask[3] << 48) |
 247                            ((u64)sta->ht_cap.mcs.rx_mask[2] << 36) |
 248                            (sta->ht_cap.mcs.rx_mask[1] << 24) |
 249                            (sta->ht_cap.mcs.rx_mask[0] << 12);
 250                 high_rate_masks = rtw89_ra_mask_ht_rates;
 251                 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
 252                         stbc_en = 1;
 253                 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
 254                         ldpc_en = 1;
 255         }
 256
 257         if (rtwdev->hal.current_band_type == RTW89_BAND_2G) {
 258                 ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ];
 259                 if (sta->supp_rates[NL80211_BAND_2GHZ] <= 0xf)
 260                         mode |= RTW89_RA_MODE_CCK;
 261                 else
 262                         mode |= RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM;
 263         } else {
 264                 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4;
 265                 mode |= RTW89_RA_MODE_OFDM;
 266         }
 267
 268         ra_mask_bak = ra_mask;
 269
 270         if (mode >= RTW89_RA_MODE_HT) {
 271                 u64 mask = 0;
 272                 for (i = 0; i < rtwdev->hal.tx_nss; i++)
 273                         mask |= high_rate_masks[i];
 274                 if (mode & RTW89_RA_MODE_OFDM)
 275                         mask |= RA_MASK_SUBOFDM_RATES;
 276                 if (mode & RTW89_RA_MODE_CCK)
 277                         mask |= RA_MASK_SUBCCK_RATES;
 278                 ra_mask &= mask;
 279         } else if (mode & RTW89_RA_MODE_OFDM) {
 280                 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES);
 281         }
 282
 283         if (mode != RTW89_RA_MODE_CCK)
 284                 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0);
 285
 286         ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak);
 287         ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta);
 288
 289         switch (sta->bandwidth) {
 290         case IEEE80211_STA_RX_BW_80:
 291                 bw_mode = RTW89_CHANNEL_WIDTH_80;
 292                 sgi = sta->vht_cap.vht_supported &&
 293                       (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
 294                 break;
 295         case IEEE80211_STA_RX_BW_40:
 296                 bw_mode = RTW89_CHANNEL_WIDTH_40;
 297                 sgi = sta->ht_cap.ht_supported &&
 298                       (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
 299                 break;
 300         default:
 301                 bw_mode = RTW89_CHANNEL_WIDTH_20;
 302                 sgi = sta->ht_cap.ht_supported &&
 303                       (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
 304                 break;
 305         }
 306
 307         if (sta->he_cap.he_cap_elem.phy_cap_info[3] &
 308             IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM)
 309                 ra->dcm_cap = 1;
 310
 311         if (rate_pattern->enable) {
 312                 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta);
 313                 ra_mask &= rate_pattern->ra_mask;
 314                 mode = rate_pattern->ra_mode;
 315         }
 316
 317         ra->bw_cap = bw_mode;
 318         ra->mode_ctrl = mode;
 319         ra->macid = rtwsta->mac_id;
 320         ra->stbc_cap = stbc_en;
 321         ra->ldpc_cap = ldpc_en;
 322         ra->ss_num = min(sta->rx_nss, rtwdev->hal.tx_nss) - 1;
 323         ra->en_sgi = sgi;
 324         ra->ra_mask = ra_mask;
 325
 326         if (!csi)
 327                 return;
 328
 329         ra->fixed_csi_rate_en = false;
 330         ra->ra_csi_rate_en = true;
 331         ra->cr_tbl_sel = false;
 332         ra->band_num = rtwvif->phy_idx;
 333         ra->csi_bw = bw_mode;
 334         ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32;
 335         ra->csi_mcs_ss_idx = 5;
 336         ra->csi_mode = csi_mode;
 337 }
 338
 339 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta)
 340 {
 341         struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
 342         struct rtw89_ra_info *ra = &rtwsta->ra;
 343
 344         rtw89_phy_ra_sta_update(rtwdev, sta, false);
 345         ra->upd_mask = 1;
 346         rtw89_debug(rtwdev, RTW89_DBG_RA,
 347                     "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d",
 348                     ra->macid,
 349                     ra->bw_cap,
 350                     ra->ss_num,
 351                     ra->en_sgi,
 352                     ra->giltf);
 353
 354         rtw89_fw_h2c_ra(rtwdev, ra, false);
 355 }
 356
 357 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next,
 358                                  u16 rate_base, u64 ra_mask, u8 ra_mode,
 359                                  u32 rate_ctrl, u32 ctrl_skip, bool force)
 360 {
 361         u8 n, c;
 362
 363         if (rate_ctrl == ctrl_skip)
 364                 return true;
 365
 366         n = hweight32(rate_ctrl);
 367         if (n == 0)
 368                 return true;
 369
 370         if (force && n != 1)
 371                 return false;
 372
 373         if (next->enable)
 374                 return false;
 375
 376         c = __fls(rate_ctrl);
 377         next->rate = rate_base + c;
 378         next->ra_mode = ra_mode;
 379         next->ra_mask = ra_mask;
 380         next->enable = true;
 381
 382         return true;
 383 }
 384
 385 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
 386                                 struct ieee80211_vif *vif,
 387                                 const struct cfg80211_bitrate_mask *mask)
 388 {
 389         struct ieee80211_supported_band *sband;
 390         struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
 391         struct rtw89_phy_rate_pattern next_pattern = {0};
 392         static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0,
 393                                          RTW89_HW_RATE_HE_NSS2_MCS0,
 394                                          RTW89_HW_RATE_HE_NSS3_MCS0,
 395                                          RTW89_HW_RATE_HE_NSS4_MCS0};
 396         static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0,
 397                                           RTW89_HW_RATE_VHT_NSS2_MCS0,
 398                                           RTW89_HW_RATE_VHT_NSS3_MCS0,
 399                                           RTW89_HW_RATE_VHT_NSS4_MCS0};
 400         static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0,
 401                                          RTW89_HW_RATE_MCS8,
 402                                          RTW89_HW_RATE_MCS16,
 403                                          RTW89_HW_RATE_MCS24};
 404         u8 band = rtwdev->hal.current_band_type;
 405         u8 tx_nss = rtwdev->hal.tx_nss;
 406         u8 i;
 407
 408         for (i = 0; i < tx_nss; i++)
 409                 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i],
 410                                           RA_MASK_HE_RATES, RTW89_RA_MODE_HE,
 411                                           mask->control[band].he_mcs[i],
 412                                           0, true))
 413                         goto out;
 414
 415         for (i = 0; i < tx_nss; i++)
 416                 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i],
 417                                           RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT,
 418                                           mask->control[band].vht_mcs[i],
 419                                           0, true))
 420                         goto out;
 421
 422         for (i = 0; i < tx_nss; i++)
 423                 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i],
 424                                           RA_MASK_HT_RATES, RTW89_RA_MODE_HT,
 425                                           mask->control[band].ht_mcs[i],
 426                                           0, true))
 427                         goto out;
 428
 429         /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and
 430          * require at least one basic rate for ieee80211_set_bitrate_mask,
 431          * so the decision just depends on if all bitrates are set or not.
 432          */
 433         sband = rtwdev->hw->wiphy->bands[band];
 434         if (band == RTW89_BAND_2G) {
 435                 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1,
 436                                           RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES,
 437                                           RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM,
 438                                           mask->control[band].legacy,
 439                                           BIT(sband->n_bitrates) - 1, false))
 440                         goto out;
 441         } else {
 442                 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6,
 443                                           RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM,
 444                                           mask->control[band].legacy,
 445                                           BIT(sband->n_bitrates) - 1, false))
 446                         goto out;
 447         }
 448
 449         if (!next_pattern.enable)
 450                 goto out;
 451
 452         rtwvif->rate_pattern = next_pattern;
 453         rtw89_debug(rtwdev, RTW89_DBG_RA,
 454                     "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n",
 455                     next_pattern.rate,
 456                     next_pattern.ra_mask,
 457                     next_pattern.ra_mode);
 458         return;
 459
 460 out:
 461         rtwvif->rate_pattern.enable = false;
 462         rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n");
 463 }
 464
 465 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta)
 466 {
 467         struct rtw89_dev *rtwdev = (struct rtw89_dev *)data;
 468
 469         rtw89_phy_ra_updata_sta(rtwdev, sta);
 470 }
 471
 472 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev)
 473 {
 474         ieee80211_iterate_stations_atomic(rtwdev->hw,
 475                                           rtw89_phy_ra_updata_sta_iter,
 476                                           rtwdev);
 477 }
 478
 479 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta)
 480 {
 481         struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
 482         struct rtw89_ra_info *ra = &rtwsta->ra;
 483         u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR;
 484         bool csi = rtw89_sta_has_beamformer_cap(sta);
 485
 486         rtw89_phy_ra_sta_update(rtwdev, sta, csi);
 487
 488         if (rssi > 40)
 489                 ra->init_rate_lv = 1;
 490         else if (rssi > 20)
 491                 ra->init_rate_lv = 2;
 492         else if (rssi > 1)
 493                 ra->init_rate_lv = 3;
 494         else
 495                 ra->init_rate_lv = 0;
 496         ra->upd_all = 1;
 497         rtw89_debug(rtwdev, RTW89_DBG_RA,
 498                     "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d",
 499                     ra->macid,
 500                     ra->mode_ctrl,
 501                     ra->bw_cap,
 502                     ra->ss_num,
 503                     ra->init_rate_lv);
 504         rtw89_debug(rtwdev, RTW89_DBG_RA,
 505                     "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d",
 506                     ra->dcm_cap,
 507                     ra->er_cap,
 508                     ra->ldpc_cap,
 509                     ra->stbc_cap,
 510                     ra->en_sgi,
 511                     ra->giltf);
 512
 513         rtw89_fw_h2c_ra(rtwdev, ra, csi);
 514 }
 515
 516 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
 517                       struct rtw89_channel_params *param,
 518                       enum rtw89_bandwidth dbw)
 519 {
 520         enum rtw89_bandwidth cbw = param->bandwidth;
 521         u8 pri_ch = param->primary_chan;
 522         u8 central_ch = param->center_chan;
 523         u8 txsc_idx = 0;
 524         u8 tmp = 0;
 525
 526         if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
 527                 return txsc_idx;
 528
 529         switch (cbw) {
 530         case RTW89_CHANNEL_WIDTH_40:
 531                 txsc_idx = pri_ch > central_ch ? 1 : 2;
 532                 break;
 533         case RTW89_CHANNEL_WIDTH_80:
 534                 if (dbw == RTW89_CHANNEL_WIDTH_20) {
 535                         if (pri_ch > central_ch)
 536                                 txsc_idx = (pri_ch - central_ch) >> 1;
 537                         else
 538                                 txsc_idx = ((central_ch - pri_ch) >> 1) + 1;
 539                 } else {
 540                         txsc_idx = pri_ch > central_ch ? 9 : 10;
 541                 }
 542                 break;
 543         case RTW89_CHANNEL_WIDTH_160:
 544                 if (pri_ch > central_ch)
 545                         tmp = (pri_ch - central_ch) >> 1;
 546                 else
 547                         tmp = ((central_ch - pri_ch) >> 1) + 1;
 548
 549                 if (dbw == RTW89_CHANNEL_WIDTH_20) {
 550                         txsc_idx = tmp;
 551                 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
 552                         if (tmp == 1 || tmp == 3)
 553                                 txsc_idx = 9;
 554                         else if (tmp == 5 || tmp == 7)
 555                                 txsc_idx = 11;
 556                         else if (tmp == 2 || tmp == 4)
 557                                 txsc_idx = 10;
 558                         else if (tmp == 6 || tmp == 8)
 559                                 txsc_idx = 12;
 560                         else
 561                                 return 0xff;
 562                 } else {
 563                         txsc_idx = pri_ch > central_ch ? 13 : 14;
 564                 }
 565                 break;
 566         case RTW89_CHANNEL_WIDTH_80_80:
 567                 if (dbw == RTW89_CHANNEL_WIDTH_20) {
 568                         if (pri_ch > central_ch)
 569                                 txsc_idx = (10 - (pri_ch - central_ch)) >> 1;
 570                         else
 571                                 txsc_idx = ((central_ch - pri_ch) >> 1) + 5;
 572                 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
 573                         txsc_idx = pri_ch > central_ch ? 10 : 12;
 574                 } else {
 575                         txsc_idx = 14;
 576                 }
 577                 break;
 578         default:
 579                 break;
 580         }
 581
 582         return txsc_idx;
 583 }
 584 EXPORT_SYMBOL(rtw89_phy_get_txsc);
 585
 586 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
 587                       u32 addr, u32 mask)
 588 {
 589         const struct rtw89_chip_info *chip = rtwdev->chip;
 590         const u32 *base_addr = chip->rf_base_addr;
 591         u32 val, direct_addr;
 592
 593         if (rf_path >= rtwdev->chip->rf_path_num) {
 594                 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
 595                 return INV_RF_DATA;
 596         }
 597
 598         addr &= 0xff;
 599         direct_addr = base_addr[rf_path] + (addr << 2);
 600         mask &= RFREG_MASK;
 601
 602         val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask);
 603
 604         return val;
 605 }
 606 EXPORT_SYMBOL(rtw89_phy_read_rf);
 607
 608 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
 609                         u32 addr, u32 mask, u32 data)
 610 {
 611         const struct rtw89_chip_info *chip = rtwdev->chip;
 612         const u32 *base_addr = chip->rf_base_addr;
 613         u32 direct_addr;
 614
 615         if (rf_path >= rtwdev->chip->rf_path_num) {
 616                 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
 617                 return false;
 618         }
 619
 620         addr &= 0xff;
 621         direct_addr = base_addr[rf_path] + (addr << 2);
 622         mask &= RFREG_MASK;
 623
 624         rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data);
 625
 626         /* delay to ensure writing properly */
 627         udelay(1);
 628
 629         return true;
 630 }
 631 EXPORT_SYMBOL(rtw89_phy_write_rf);
 632
 633 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev,
 634                                enum rtw89_phy_idx phy_idx)
 635 {
 636         const struct rtw89_chip_info *chip = rtwdev->chip;
 637
 638         chip->ops->bb_reset(rtwdev, phy_idx);
 639 }
 640
 641 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev,
 642                                     const struct rtw89_reg2_def *reg,
 643                                     enum rtw89_rf_path rf_path,
 644                                     void *extra_data)
 645 {
 646         if (reg->addr == 0xfe)
 647                 mdelay(50);
 648         else if (reg->addr == 0xfd)
 649                 mdelay(5);
 650         else if (reg->addr == 0xfc)
 651                 mdelay(1);
 652         else if (reg->addr == 0xfb)
 653                 udelay(50);
 654         else if (reg->addr == 0xfa)
 655                 udelay(5);
 656         else if (reg->addr == 0xf9)
 657                 udelay(1);
 658         else
 659                 rtw89_phy_write32(rtwdev, reg->addr, reg->data);
 660 }
 661
 662 static void
 663 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev,
 664                              const struct rtw89_reg2_def *reg,
 665                              enum rtw89_rf_path rf_path,
 666                              struct rtw89_fw_h2c_rf_reg_info *info)
 667 {
 668         u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE;
 669         u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE;
 670
 671         if (page >= RTW89_H2C_RF_PAGE_NUM) {
 672                 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d",
 673                            rf_path, info->curr_idx);
 674                 return;
 675         }
 676
 677         info->rtw89_phy_config_rf_h2c[page][idx] =
 678                 cpu_to_le32((reg->addr << 20) | reg->data);
 679         info->curr_idx++;
 680 }
 681
 682 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev,
 683                                       struct rtw89_fw_h2c_rf_reg_info *info)
 684 {
 685         u16 remain = info->curr_idx;
 686         u16 len = 0;
 687         u8 i;
 688         int ret = 0;
 689
 690         if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) {
 691                 rtw89_warn(rtwdev,
 692                            "rf reg h2c total len %d larger than %d\n",
 693                            remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE);
 694                 ret = -EINVAL;
 695                 goto out;
 696         }
 697
 698         for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) {
 699                 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain;
 700                 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i);
 701                 if (ret)
 702                         goto out;
 703         }
 704 out:
 705         info->curr_idx = 0;
 706
 707         return ret;
 708 }
 709
 710 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
 711                                     const struct rtw89_reg2_def *reg,
 712                                     enum rtw89_rf_path rf_path,
 713                                     void *extra_data)
 714 {
 715         if (reg->addr == 0xfe) {
 716                 mdelay(50);
 717         } else if (reg->addr == 0xfd) {
 718                 mdelay(5);
 719         } else if (reg->addr == 0xfc) {
 720                 mdelay(1);
 721         } else if (reg->addr == 0xfb) {
 722                 udelay(50);
 723         } else if (reg->addr == 0xfa) {
 724                 udelay(5);
 725         } else if (reg->addr == 0xf9) {
 726                 udelay(1);
 727         } else {
 728                 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data);
 729                 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
 730                                              (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
 731         }
 732 }
 733
 734 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev,
 735                                   const struct rtw89_phy_table *table,
 736                                   u32 *headline_size, u32 *headline_idx,
 737                                   u8 rfe, u8 cv)
 738 {
 739         const struct rtw89_reg2_def *reg;
 740         u32 headline;
 741         u32 compare, target;
 742         u8 rfe_para, cv_para;
 743         u8 cv_max = 0;
 744         bool case_matched = false;
 745         u32 i;
 746
 747         for (i = 0; i < table->n_regs; i++) {
 748                 reg = &table->regs[i];
 749                 headline = get_phy_headline(reg->addr);
 750                 if (headline != PHY_HEADLINE_VALID)
 751                         break;
 752         }
 753         *headline_size = i;
 754         if (*headline_size == 0)
 755                 return 0;
 756
 757         /* case 1: RFE match, CV match */
 758         compare = get_phy_compare(rfe, cv);
 759         for (i = 0; i < *headline_size; i++) {
 760                 reg = &table->regs[i];
 761                 target = get_phy_target(reg->addr);
 762                 if (target == compare) {
 763                         *headline_idx = i;
 764                         return 0;
 765                 }
 766         }
 767
 768         /* case 2: RFE match, CV don't care */
 769         compare = get_phy_compare(rfe, PHY_COND_DONT_CARE);
 770         for (i = 0; i < *headline_size; i++) {
 771                 reg = &table->regs[i];
 772                 target = get_phy_target(reg->addr);
 773                 if (target == compare) {
 774                         *headline_idx = i;
 775                         return 0;
 776                 }
 777         }
 778
 779         /* case 3: RFE match, CV max in table */
 780         for (i = 0; i < *headline_size; i++) {
 781                 reg = &table->regs[i];
 782                 rfe_para = get_phy_cond_rfe(reg->addr);
 783                 cv_para = get_phy_cond_cv(reg->addr);
 784                 if (rfe_para == rfe) {
 785                         if (cv_para >= cv_max) {
 786                                 cv_max = cv_para;
 787                                 *headline_idx = i;
 788                                 case_matched = true;
 789                         }
 790                 }
 791         }
 792
 793         if (case_matched)
 794                 return 0;
 795
 796         /* case 4: RFE don't care, CV max in table */
 797         for (i = 0; i < *headline_size; i++) {
 798                 reg = &table->regs[i];
 799                 rfe_para = get_phy_cond_rfe(reg->addr);
 800                 cv_para = get_phy_cond_cv(reg->addr);
 801                 if (rfe_para == PHY_COND_DONT_CARE) {
 802                         if (cv_para >= cv_max) {
 803                                 cv_max = cv_para;
 804                                 *headline_idx = i;
 805                                 case_matched = true;
 806                         }
 807                 }
 808         }
 809
 810         if (case_matched)
 811                 return 0;
 812
 813         return -EINVAL;
 814 }
 815
 816 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,
 817                                const struct rtw89_phy_table *table,
 818                                void (*config)(struct rtw89_dev *rtwdev,
 819                                               const struct rtw89_reg2_def *reg,
 820                                               enum rtw89_rf_path rf_path,
 821                                               void *data),
 822                                void *extra_data)
 823 {
 824         const struct rtw89_reg2_def *reg;
 825         enum rtw89_rf_path rf_path = table->rf_path;
 826         u8 rfe = rtwdev->efuse.rfe_type;
 827         u8 cv = rtwdev->hal.cv;
 828         u32 i;
 829         u32 headline_size = 0, headline_idx = 0;
 830         u32 target = 0, cfg_target;
 831         u8 cond;
 832         bool is_matched = true;
 833         bool target_found = false;
 834         int ret;
 835
 836         ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size,
 837                                      &headline_idx, rfe, cv);
 838         if (ret) {
 839                 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv);
 840                 return;
 841         }
 842
 843         cfg_target = get_phy_target(table->regs[headline_idx].addr);
 844         for (i = headline_size; i < table->n_regs; i++) {
 845                 reg = &table->regs[i];
 846                 cond = get_phy_cond(reg->addr);
 847                 switch (cond) {
 848                 case PHY_COND_BRANCH_IF:
 849                 case PHY_COND_BRANCH_ELIF:
 850                         target = get_phy_target(reg->addr);
 851                         break;
 852                 case PHY_COND_BRANCH_ELSE:
 853                         is_matched = false;
 854                         if (!target_found) {
 855                                 rtw89_warn(rtwdev, "failed to load CR %x/%x\n",
 856                                            reg->addr, reg->data);
 857                                 return;
 858                         }
 859                         break;
 860                 case PHY_COND_BRANCH_END:
 861                         is_matched = true;
 862                         target_found = false;
 863                         break;
 864                 case PHY_COND_CHECK:
 865                         if (target_found) {
 866                                 is_matched = false;
 867                                 break;
 868                         }
 869
 870                         if (target == cfg_target) {
 871                                 is_matched = true;
 872                                 target_found = true;
 873                         } else {
 874                                 is_matched = false;
 875                                 target_found = false;
 876                         }
 877                         break;
 878                 default:
 879                         if (is_matched)
 880                                 config(rtwdev, reg, rf_path, extra_data);
 881                         break;
 882                 }
 883         }
 884 }
 885
 886 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev)
 887 {
 888         const struct rtw89_chip_info *chip = rtwdev->chip;
 889         const struct rtw89_phy_table *bb_table = chip->bb_table;
 890
 891         rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL);
 892         rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0);
 893         rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0);
 894 }
 895
 896 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev)
 897 {
 898         rtw89_phy_write32(rtwdev, 0x8080, 0x4);
 899         udelay(1);
 900         return rtw89_phy_read32(rtwdev, 0x8080);
 901 }
 902
 903 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev)
 904 {
 905         const struct rtw89_chip_info *chip = rtwdev->chip;
 906         const struct rtw89_phy_table *rf_table;
 907         struct rtw89_fw_h2c_rf_reg_info *rf_reg_info;
 908         u8 path;
 909
 910         rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL);
 911         if (!rf_reg_info)
 912                 return;
 913
 914         for (path = RF_PATH_A; path < chip->rf_path_num; path++) {
 915                 rf_reg_info->rf_path = path;
 916                 rf_table = chip->rf_table[path];
 917                 rtw89_phy_init_reg(rtwdev, rf_table, rtw89_phy_config_rf_reg,
 918                                    (void *)rf_reg_info);
 919                 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
 920                         rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
 921                                    path);
 922         }
 923         kfree(rf_reg_info);
 924 }
 925
 926 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
 927 {
 928         const struct rtw89_chip_info *chip = rtwdev->chip;
 929         const struct rtw89_phy_table *nctl_table;
 930         u32 val;
 931         int ret;
 932
 933         /* IQK/DPK clock & reset */
 934         rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3);
 935         rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1);
 936         rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000);
 937         rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000);
 938
 939         /* check 0x8080 */
 940         rtw89_phy_write32(rtwdev, 0x8000, 0x8);
 941
 942         ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
 943                                 1000, false, rtwdev);
 944         if (ret)
 945                 rtw89_err(rtwdev, "failed to poll nctl block\n");
 946
 947         nctl_table = chip->nctl_table;
 948         rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL);
 949 }
 950
 951 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
 952 {
 953         u32 phy_page = addr >> 8;
 954         u32 ofst = 0;
 955
 956         switch (phy_page) {
 957         case 0x6:
 958         case 0x7:
 959         case 0x8:
 960         case 0x9:
 961         case 0xa:
 962         case 0xb:
 963         case 0xc:
 964         case 0xd:
 965         case 0x19:
 966         case 0x1a:
 967         case 0x1b:
 968                 ofst = 0x2000;
 969                 break;
 970         default:
 971                 /* warning case */
 972                 ofst = 0;
 973                 break;
 974         }
 975
 976         if (phy_page >= 0x40 && phy_page <= 0x4f)
 977                 ofst = 0x2000;
 978
 979         return ofst;
 980 }
 981
 982 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
 983                            u32 data, enum rtw89_phy_idx phy_idx)
 984 {
 985         if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
 986                 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
 987         rtw89_phy_write32_mask(rtwdev, addr, mask, data);
 988 }
 989 EXPORT_SYMBOL(rtw89_phy_write32_idx);
 990
 991 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
 992                             u32 val)
 993 {
 994         rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
 995
 996         if (!rtwdev->dbcc_en)
 997                 return;
 998
 999         rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1);
1000 }
1001
1002 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
1003                               const struct rtw89_phy_reg3_tbl *tbl)
1004 {
1005         const struct rtw89_reg3_def *reg3;
1006         int i;
1007
1008         for (i = 0; i < tbl->size; i++) {
1009                 reg3 = &tbl->reg3[i];
1010                 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
1011         }
1012 }
1013 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
1014
1015 const u8 rtw89_rs_idx_max[] = {
1016         [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX,
1017         [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX,
1018         [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX,
1019         [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX,
1020         [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX,
1021 };
1022 EXPORT_SYMBOL(rtw89_rs_idx_max);
1023
1024 const u8 rtw89_rs_nss_max[] = {
1025         [RTW89_RS_CCK] = 1,
1026         [RTW89_RS_OFDM] = 1,
1027         [RTW89_RS_MCS] = RTW89_NSS_MAX,
1028         [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX,
1029         [RTW89_RS_OFFSET] = 1,
1030 };
1031 EXPORT_SYMBOL(rtw89_rs_nss_max);
1032
1033 static const u8 _byr_of_rs[] = {
1034         [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck),
1035         [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm),
1036         [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs),
1037         [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm),
1038         [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset),
1039 };
1040
1041 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs])
1042 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx))
1043 #define _byr_chk(rs, nss, idx) \
1044         ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs])
1045
1046 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
1047                                  const struct rtw89_txpwr_table *tbl)
1048 {
1049         const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data;
1050         const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size;
1051         s8 *byr;
1052         u32 data;
1053         u8 i, idx;
1054
1055         for (; cfg < end; cfg++) {
1056                 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]);
1057                 data = cfg->data;
1058
1059                 for (i = 0; i < cfg->len; i++, data >>= 8) {
1060                         idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i));
1061                         byr[idx] = (s8)(data & 0xff);
1062                 }
1063         }
1064 }
1065 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate);
1066
1067 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf)                          \
1068 ({                                                                      \
1069         const struct rtw89_chip_info *__c = (rtwdev)->chip;             \
1070         (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac);   \
1071 })
1072
1073 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev,
1074                                const struct rtw89_rate_desc *rate_desc)
1075 {
1076         enum rtw89_band band = rtwdev->hal.current_band_type;
1077         s8 *byr;
1078         u8 idx;
1079
1080         if (rate_desc->rs == RTW89_RS_CCK)
1081                 band = RTW89_BAND_2G;
1082
1083         if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) {
1084                 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1085                             "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n",
1086                             rate_desc->rs, rate_desc->nss, rate_desc->idx);
1087
1088                 return 0;
1089         }
1090
1091         byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]);
1092         idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx);
1093
1094         return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]);
1095 }
1096 EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate);
1097
1098 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 channel)
1099 {
1100         switch (channel) {
1101         case 1 ... 14:
1102                 return channel - 1;
1103         case 36 ... 64:
1104                 return (channel - 36) / 2;
1105         case 100 ... 144:
1106                 return ((channel - 100) / 2) + 15;
1107         case 149 ... 177:
1108                 return ((channel - 149) / 2) + 38;
1109         default:
1110                 rtw89_warn(rtwdev, "unknown channel: %d\n", channel);
1111                 return 0;
1112         }
1113 }
1114
1115 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev,
1116                               u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch)
1117 {
1118         const struct rtw89_chip_info *chip = rtwdev->chip;
1119         u8 ch_idx = rtw89_channel_to_idx(rtwdev, ch);
1120         u8 band = rtwdev->hal.current_band_type;
1121         u8 regd = rtw89_regd_get(rtwdev, band);
1122         s8 lmt = 0, sar;
1123
1124         switch (band) {
1125         case RTW89_BAND_2G:
1126                 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx];
1127                 if (!lmt)
1128                         lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf]
1129                                                    [RTW89_WW][ch_idx];
1130                 break;
1131         case RTW89_BAND_5G:
1132                 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx];
1133                 if (!lmt)
1134                         lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf]
1135                                                    [RTW89_WW][ch_idx];
1136                 break;
1137         default:
1138                 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
1139                 return 0;
1140         }
1141
1142         lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt);
1143         sar = rtw89_query_sar(rtwdev);
1144
1145         return min(lmt, sar);
1146 }
1147 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit);
1148
1149 #define __fill_txpwr_limit_nonbf_bf(ptr, bw, ntx, rs, ch)               \
1150         do {                                                            \
1151                 u8 __i;                                                 \
1152                 for (__i = 0; __i < RTW89_BF_NUM; __i++)                \
1153                         ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev,   \
1154                                                               bw, ntx,  \
1155                                                               rs, __i,  \
1156                                                               (ch));    \
1157         } while (0)
1158
1159 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev,
1160                                            struct rtw89_txpwr_limit *lmt,
1161                                            u8 ntx, u8 ch)
1162 {
1163         __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20,
1164                                     ntx, RTW89_RS_CCK, ch);
1165         __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40,
1166                                     ntx, RTW89_RS_CCK, ch);
1167         __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20,
1168                                     ntx, RTW89_RS_OFDM, ch);
1169         __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20,
1170                                     ntx, RTW89_RS_MCS, ch);
1171 }
1172
1173 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev,
1174                                            struct rtw89_txpwr_limit *lmt,
1175                                            u8 ntx, u8 ch)
1176 {
1177         __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20,
1178                                     ntx, RTW89_RS_CCK, ch - 2);
1179         __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40,
1180                                     ntx, RTW89_RS_CCK, ch);
1181         __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20,
1182                                     ntx, RTW89_RS_OFDM, ch - 2);
1183         __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20,
1184                                     ntx, RTW89_RS_MCS, ch - 2);
1185         __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20,
1186                                     ntx, RTW89_RS_MCS, ch + 2);
1187         __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40,
1188                                     ntx, RTW89_RS_MCS, ch);
1189 }
1190
1191 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev,
1192                                            struct rtw89_txpwr_limit *lmt,
1193                                            u8 ntx, u8 ch)
1194 {
1195         s8 val_0p5_n[RTW89_BF_NUM];
1196         s8 val_0p5_p[RTW89_BF_NUM];
1197         u8 i;
1198
1199         __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20,
1200                                     ntx, RTW89_RS_OFDM, ch - 6);
1201         __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20,
1202                                     ntx, RTW89_RS_MCS, ch - 6);
1203         __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20,
1204                                     ntx, RTW89_RS_MCS, ch - 2);
1205         __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], RTW89_CHANNEL_WIDTH_20,
1206                                     ntx, RTW89_RS_MCS, ch + 2);
1207         __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], RTW89_CHANNEL_WIDTH_20,
1208                                     ntx, RTW89_RS_MCS, ch + 6);
1209         __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40,
1210                                     ntx, RTW89_RS_MCS, ch - 4);
1211         __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], RTW89_CHANNEL_WIDTH_40,
1212                                     ntx, RTW89_RS_MCS, ch + 4);
1213         __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], RTW89_CHANNEL_WIDTH_80,
1214                                     ntx, RTW89_RS_MCS, ch);
1215
1216         __fill_txpwr_limit_nonbf_bf(val_0p5_n, RTW89_CHANNEL_WIDTH_40,
1217                                     ntx, RTW89_RS_MCS, ch - 4);
1218         __fill_txpwr_limit_nonbf_bf(val_0p5_p, RTW89_CHANNEL_WIDTH_40,
1219                                     ntx, RTW89_RS_MCS, ch + 4);
1220
1221         for (i = 0; i < RTW89_BF_NUM; i++)
1222                 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
1223 }
1224
1225 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
1226                                 struct rtw89_txpwr_limit *lmt,
1227                                 u8 ntx)
1228 {
1229         u8 ch = rtwdev->hal.current_channel;
1230         u8 bw = rtwdev->hal.current_band_width;
1231
1232         memset(lmt, 0, sizeof(*lmt));
1233
1234         switch (bw) {
1235         case RTW89_CHANNEL_WIDTH_20:
1236                 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, ntx, ch);
1237                 break;
1238         case RTW89_CHANNEL_WIDTH_40:
1239                 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, ntx, ch);
1240                 break;
1241         case RTW89_CHANNEL_WIDTH_80:
1242                 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, ntx, ch);
1243                 break;
1244         }
1245 }
1246 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit);
1247
1248 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev,
1249                                         u8 ru, u8 ntx, u8 ch)
1250 {
1251         const struct rtw89_chip_info *chip = rtwdev->chip;
1252         u8 ch_idx = rtw89_channel_to_idx(rtwdev, ch);
1253         u8 band = rtwdev->hal.current_band_type;
1254         u8 regd = rtw89_regd_get(rtwdev, band);
1255         s8 lmt_ru = 0, sar;
1256
1257         switch (band) {
1258         case RTW89_BAND_2G:
1259                 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx];
1260                 if (!lmt_ru)
1261                         lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx]
1262                                                          [RTW89_WW][ch_idx];
1263                 break;
1264         case RTW89_BAND_5G:
1265                 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx];
1266                 if (!lmt_ru)
1267                         lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx]
1268                                                          [RTW89_WW][ch_idx];
1269                 break;
1270         default:
1271                 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
1272                 return 0;
1273         }
1274
1275         lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru);
1276         sar = rtw89_query_sar(rtwdev);
1277
1278         return min(lmt_ru, sar);
1279 }
1280
1281 static void
1282 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev,
1283                                   struct rtw89_txpwr_limit_ru *lmt_ru,
1284                                   u8 ntx, u8 ch)
1285 {
1286         lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1287                                                         ntx, ch);
1288         lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1289                                                         ntx, ch);
1290         lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1291                                                          ntx, ch);
1292 }
1293
1294 static void
1295 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev,
1296                                   struct rtw89_txpwr_limit_ru *lmt_ru,
1297                                   u8 ntx, u8 ch)
1298 {
1299         lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1300                                                         ntx, ch - 2);
1301         lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1302                                                         ntx, ch + 2);
1303         lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1304                                                         ntx, ch - 2);
1305         lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1306                                                         ntx, ch + 2);
1307         lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1308                                                          ntx, ch - 2);
1309         lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1310                                                          ntx, ch + 2);
1311 }
1312
1313 static void
1314 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev,
1315                                   struct rtw89_txpwr_limit_ru *lmt_ru,
1316                                   u8 ntx, u8 ch)
1317 {
1318         lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1319                                                         ntx, ch - 6);
1320         lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1321                                                         ntx, ch - 2);
1322         lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1323                                                         ntx, ch + 2);
1324         lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26,
1325                                                         ntx, ch + 6);
1326         lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1327                                                         ntx, ch - 6);
1328         lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1329                                                         ntx, ch - 2);
1330         lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1331                                                         ntx, ch + 2);
1332         lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52,
1333                                                         ntx, ch + 6);
1334         lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1335                                                          ntx, ch - 6);
1336         lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1337                                                          ntx, ch - 2);
1338         lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1339                                                          ntx, ch + 2);
1340         lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106,
1341                                                          ntx, ch + 6);
1342 }
1343
1344 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
1345                                    struct rtw89_txpwr_limit_ru *lmt_ru,
1346                                    u8 ntx)
1347 {
1348         u8 ch = rtwdev->hal.current_channel;
1349         u8 bw = rtwdev->hal.current_band_width;
1350
1351         memset(lmt_ru, 0, sizeof(*lmt_ru));
1352
1353         switch (bw) {
1354         case RTW89_CHANNEL_WIDTH_20:
1355                 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, ntx, ch);
1356                 break;
1357         case RTW89_CHANNEL_WIDTH_40:
1358                 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, ntx, ch);
1359                 break;
1360         case RTW89_CHANNEL_WIDTH_80:
1361                 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, ntx, ch);
1362                 break;
1363         }
1364 }
1365 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit_ru);
1366
1367 struct rtw89_phy_iter_ra_data {
1368         struct rtw89_dev *rtwdev;
1369         struct sk_buff *c2h;
1370 };
1371
1372 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
1373 {
1374         struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data;
1375         struct rtw89_dev *rtwdev = ra_data->rtwdev;
1376         struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
1377         struct rtw89_ra_report *ra_report = &rtwsta->ra_report;
1378         struct sk_buff *c2h = ra_data->c2h;
1379         u8 mode, rate, bw, giltf, mac_id;
1380
1381         mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data);
1382         if (mac_id != rtwsta->mac_id)
1383                 return;
1384
1385         memset(ra_report, 0, sizeof(*ra_report));
1386
1387         rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data);
1388         bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data);
1389         giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data);
1390         mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data);
1391
1392         switch (mode) {
1393         case RTW89_RA_RPT_MODE_LEGACY:
1394                 ra_report->txrate.legacy = rtw89_ra_report_to_bitrate(rtwdev, rate);
1395                 break;
1396         case RTW89_RA_RPT_MODE_HT:
1397                 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS;
1398                 if (rtwdev->fw.old_ht_ra_format)
1399                         rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate),
1400                                                 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate));
1401                 else
1402                         rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate);
1403                 ra_report->txrate.mcs = rate;
1404                 if (giltf)
1405                         ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1406                 break;
1407         case RTW89_RA_RPT_MODE_VHT:
1408                 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS;
1409                 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate);
1410                 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1;
1411                 if (giltf)
1412                         ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1413                 break;
1414         case RTW89_RA_RPT_MODE_HE:
1415                 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS;
1416                 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate);
1417                 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1;
1418                 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
1419                         ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8;
1420                 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
1421                         ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6;
1422                 else
1423                         ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2;
1424                 break;
1425         }
1426
1427         if (bw == RTW89_CHANNEL_WIDTH_80)
1428                 ra_report->txrate.bw = RATE_INFO_BW_80;
1429         else if (bw == RTW89_CHANNEL_WIDTH_40)
1430                 ra_report->txrate.bw = RATE_INFO_BW_40;
1431         else
1432                 ra_report->txrate.bw = RATE_INFO_BW_20;
1433
1434         ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate);
1435         ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) |
1436                              FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate);
1437         sta->max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
1438         rtwsta->max_agg_wait = sta->max_rc_amsdu_len / 1500 - 1;
1439 }
1440
1441 static void
1442 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
1443 {
1444         struct rtw89_phy_iter_ra_data ra_data;
1445
1446         ra_data.rtwdev = rtwdev;
1447         ra_data.c2h = c2h;
1448         ieee80211_iterate_stations_atomic(rtwdev->hw,
1449                                           rtw89_phy_c2h_ra_rpt_iter,
1450                                           &ra_data);
1451 }
1452
1453 static
1454 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev,
1455                                           struct sk_buff *c2h, u32 len) = {
1456         [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt,
1457         [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL,
1458         [RTW89_PHY_C2H_FUNC_TXSTS] = NULL,
1459 };
1460
1461 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1462                           u32 len, u8 class, u8 func)
1463 {
1464         void (*handler)(struct rtw89_dev *rtwdev,
1465                         struct sk_buff *c2h, u32 len) = NULL;
1466
1467         switch (class) {
1468         case RTW89_PHY_C2H_CLASS_RA:
1469                 if (func < RTW89_PHY_C2H_FUNC_RA_MAX)
1470                         handler = rtw89_phy_c2h_ra_handler[func];
1471                 break;
1472         default:
1473                 rtw89_info(rtwdev, "c2h class %d not support\n", class);
1474                 return;
1475         }
1476         if (!handler) {
1477                 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class,
1478                            func);
1479                 return;
1480         }
1481         handler(rtwdev, skb, len);
1482 }
1483
1484 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo)
1485 {
1486         u32 reg_mask;
1487
1488         if (sc_xo)
1489                 reg_mask = B_AX_XTAL_SC_XO_MASK;
1490         else
1491                 reg_mask = B_AX_XTAL_SC_XI_MASK;
1492
1493         return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask);
1494 }
1495
1496 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo,
1497                                        u8 val)
1498 {
1499         u32 reg_mask;
1500
1501         if (sc_xo)
1502                 reg_mask = B_AX_XTAL_SC_XO_MASK;
1503         else
1504                 reg_mask = B_AX_XTAL_SC_XI_MASK;
1505
1506         rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val);
1507 }
1508
1509 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
1510                                           u8 crystal_cap, bool force)
1511 {
1512         struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
1513         u8 sc_xi_val, sc_xo_val;
1514
1515         if (!force && cfo->crystal_cap == crystal_cap)
1516                 return;
1517         crystal_cap = clamp_t(u8, crystal_cap, 0, 127);
1518         rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap);
1519         rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap);
1520         sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true);
1521         sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false);
1522         cfo->crystal_cap = sc_xi_val;
1523         cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap);
1524
1525         rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val);
1526         rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val);
1527         rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n",
1528                     cfo->x_cap_ofst);
1529         rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n");
1530 }
1531
1532 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev)
1533 {
1534         struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
1535         u8 cap;
1536
1537         cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK;
1538         cfo->is_adjust = false;
1539         if (cfo->crystal_cap == cfo->def_x_cap)
1540                 return;
1541         cap = cfo->crystal_cap;
1542         cap += (cap > cfo->def_x_cap ? -1 : 1);
1543         rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false);
1544         rtw89_debug(rtwdev, RTW89_DBG_CFO,
1545                     "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap,
1546                     cfo->def_x_cap);
1547 }
1548
1549 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo)
1550 {
1551         bool is_linked = rtwdev->total_sta_assoc > 0;
1552         s32 cfo_avg_312;
1553         s32 dcfo_comp;
1554         int sign;
1555
1556         if (!is_linked) {
1557                 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n",
1558                             is_linked);
1559                 return;
1560         }
1561         rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo);
1562         if (curr_cfo == 0)
1563                 return;
1564         dcfo_comp = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO);
1565         sign = curr_cfo > 0 ? 1 : -1;
1566         cfo_avg_312 = (curr_cfo << 3) / 5 + sign * dcfo_comp;
1567         rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312);
1568         if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV)
1569                 cfo_avg_312 = -cfo_avg_312;
1570         rtw89_phy_set_phy_regs(rtwdev, R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK,
1571                                cfo_avg_312);
1572 }
1573
1574 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev)
1575 {
1576         rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1);
1577         rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8);
1578         rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK);
1579 }
1580
1581 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev)
1582 {
1583         struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
1584         struct rtw89_efuse *efuse = &rtwdev->efuse;
1585
1586         cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK;
1587         cfo->crystal_cap = cfo->crystal_cap_default;
1588         cfo->def_x_cap = cfo->crystal_cap;
1589         cfo->is_adjust = false;
1590         cfo->x_cap_ofst = 0;
1591         cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE;
1592         cfo->apply_compensation = false;
1593         cfo->residual_cfo_acc = 0;
1594         rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n",
1595                     cfo->crystal_cap_default);
1596         rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true);
1597         rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1);
1598         rtw89_dcfo_comp_init(rtwdev);
1599         cfo->cfo_timer_ms = 2000;
1600         cfo->cfo_trig_by_timer_en = false;
1601         cfo->phy_cfo_trk_cnt = 0;
1602         cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
1603 }
1604
1605 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev,
1606                                              s32 curr_cfo)
1607 {
1608         struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
1609         s8 crystal_cap = cfo->crystal_cap;
1610         s32 cfo_abs = abs(curr_cfo);
1611         int sign;
1612
1613         if (!cfo->is_adjust) {
1614                 if (cfo_abs > CFO_TRK_ENABLE_TH)
1615                         cfo->is_adjust = true;
1616         } else {
1617                 if (cfo_abs < CFO_TRK_STOP_TH)
1618                         cfo->is_adjust = false;
1619         }
1620         if (!cfo->is_adjust) {
1621                 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n");
1622                 return;
1623         }
1624         sign = curr_cfo > 0 ? 1 : -1;
1625         if (cfo_abs > CFO_TRK_STOP_TH_4)
1626                 crystal_cap += 7 * sign;
1627         else if (cfo_abs > CFO_TRK_STOP_TH_3)
1628                 crystal_cap += 5 * sign;
1629         else if (cfo_abs > CFO_TRK_STOP_TH_2)
1630                 crystal_cap += 3 * sign;
1631         else if (cfo_abs > CFO_TRK_STOP_TH_1)
1632                 crystal_cap += 1 * sign;
1633         else
1634                 return;
1635         rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false);
1636         rtw89_debug(rtwdev, RTW89_DBG_CFO,
1637                     "X_cap{Curr,Default}={0x%x,0x%x}\n",
1638                     cfo->crystal_cap, cfo->def_x_cap);
1639 }
1640
1641 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev)
1642 {
1643         struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
1644         s32 cfo_khz_all = 0;
1645         s32 cfo_cnt_all = 0;
1646         s32 cfo_all_avg = 0;
1647         u8 i;
1648
1649         if (rtwdev->total_sta_assoc != 1)
1650                 return 0;
1651         rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n");
1652         for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
1653                 if (cfo->cfo_cnt[i] == 0)
1654                         continue;
1655                 cfo_khz_all += cfo->cfo_tail[i];
1656                 cfo_cnt_all += cfo->cfo_cnt[i];
1657                 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all);
1658                 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
1659         }
1660         rtw89_debug(rtwdev, RTW89_DBG_CFO,
1661                     "CFO track for macid = %d\n", i);
1662         rtw89_debug(rtwdev, RTW89_DBG_CFO,
1663                     "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n",
1664                     cfo_khz_all, cfo_cnt_all, cfo_all_avg);
1665         return cfo_all_avg;
1666 }
1667
1668 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev)
1669 {
1670         struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
1671         struct rtw89_traffic_stats *stats = &rtwdev->stats;
1672         s32 target_cfo = 0;
1673         s32 cfo_khz_all = 0;
1674         s32 cfo_khz_all_tp_wgt = 0;
1675         s32 cfo_avg = 0;
1676         s32 max_cfo_lb = BIT(31);
1677         s32 min_cfo_ub = GENMASK(30, 0);
1678         u16 cfo_cnt_all = 0;
1679         u8 active_entry_cnt = 0;
1680         u8 sta_cnt = 0;
1681         u32 tp_all = 0;
1682         u8 i;
1683         u8 cfo_tol = 0;
1684
1685         rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n");
1686         if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) {
1687                 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n");
1688                 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
1689                         if (cfo->cfo_cnt[i] == 0)
1690                                 continue;
1691                         cfo_khz_all += cfo->cfo_tail[i];
1692                         cfo_cnt_all += cfo->cfo_cnt[i];
1693                         cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all);
1694                         rtw89_debug(rtwdev, RTW89_DBG_CFO,
1695                                     "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n",
1696                                     cfo_khz_all, cfo_cnt_all, cfo_avg);
1697                         target_cfo = cfo_avg;
1698                 }
1699         } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) {
1700                 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n");
1701                 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
1702                         if (cfo->cfo_cnt[i] == 0)
1703                                 continue;
1704                         cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
1705                                                   (s32)cfo->cfo_cnt[i]);
1706                         cfo_khz_all += cfo->cfo_avg[i];
1707                         rtw89_debug(rtwdev, RTW89_DBG_CFO,
1708                                     "Macid=%d, cfo_avg=%d\n", i,
1709                                     cfo->cfo_avg[i]);
1710                 }
1711                 sta_cnt = rtwdev->total_sta_assoc;
1712                 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt);
1713                 rtw89_debug(rtwdev, RTW89_DBG_CFO,
1714                             "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n",
1715                             cfo_khz_all, sta_cnt, cfo_avg);
1716                 target_cfo = cfo_avg;
1717         } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) {
1718                 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n");
1719                 cfo_tol = cfo->sta_cfo_tolerance;
1720                 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
1721                         sta_cnt++;
1722                         if (cfo->cfo_cnt[i] != 0) {
1723                                 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
1724                                                           (s32)cfo->cfo_cnt[i]);
1725                                 active_entry_cnt++;
1726                         } else {
1727                                 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i];
1728                         }
1729                         max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb);
1730                         min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub);
1731                         cfo_khz_all += cfo->cfo_avg[i];
1732                         /* need tp for each entry */
1733                         rtw89_debug(rtwdev, RTW89_DBG_CFO,
1734                                     "[%d] cfo_avg=%d, tp=tbd\n",
1735                                     i, cfo->cfo_avg[i]);
1736                         if (sta_cnt >= rtwdev->total_sta_assoc)
1737                                 break;
1738                 }
1739                 tp_all = stats->rx_throughput; /* need tp for each entry */
1740                 cfo_avg =  phy_div(cfo_khz_all_tp_wgt, (s32)tp_all);
1741
1742                 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n",
1743                             sta_cnt);
1744                 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n",
1745                             active_entry_cnt);
1746                 rtw89_debug(rtwdev, RTW89_DBG_CFO,
1747                             "Msta cfo with tp_wgt=%d, avg_cfo=%d\n",
1748                             cfo_khz_all_tp_wgt, cfo_avg);
1749                 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n",
1750                             max_cfo_lb, min_cfo_ub);
1751                 if (max_cfo_lb <= min_cfo_ub) {
1752                         rtw89_debug(rtwdev, RTW89_DBG_CFO,
1753                                     "cfo win_size=%d\n",
1754                                     min_cfo_ub - max_cfo_lb);
1755                         target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub);
1756                 } else {
1757                         rtw89_debug(rtwdev, RTW89_DBG_CFO,
1758                                     "No intersection of cfo tolerance windows\n");
1759                         target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt);
1760                 }
1761                 for (i = 0; i < CFO_TRACK_MAX_USER; i++)
1762                         cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
1763         }
1764         rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo);
1765         return target_cfo;
1766 }
1767
1768 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev)
1769 {
1770         struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
1771
1772         memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail));
1773         memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt));
1774         cfo->packet_count = 0;
1775         cfo->packet_count_pre = 0;
1776         cfo->cfo_avg_pre = 0;
1777 }
1778
1779 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev)
1780 {
1781         struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
1782         s32 new_cfo = 0;
1783         bool x_cap_update = false;
1784         u8 pre_x_cap = cfo->crystal_cap;
1785
1786         rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n",
1787                     rtwdev->total_sta_assoc);
1788         if (rtwdev->total_sta_assoc == 0) {
1789                 rtw89_phy_cfo_reset(rtwdev);
1790                 return;
1791         }
1792         if (cfo->packet_count == 0) {
1793                 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n");
1794                 return;
1795         }
1796         if (cfo->packet_count == cfo->packet_count_pre) {
1797                 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n");
1798                 return;
1799         }
1800         if (rtwdev->total_sta_assoc == 1)
1801                 new_cfo = rtw89_phy_average_cfo_calc(rtwdev);
1802         else
1803                 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev);
1804         if (new_cfo == 0) {
1805                 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n");
1806                 return;
1807         }
1808         rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo);
1809         cfo->cfo_avg_pre = new_cfo;
1810         x_cap_update =  cfo->crystal_cap != pre_x_cap;
1811         rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update);
1812         rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n",
1813                     cfo->def_x_cap, pre_x_cap, cfo->crystal_cap,
1814                     cfo->x_cap_ofst);
1815         if (x_cap_update) {
1816                 if (new_cfo > 0)
1817                         new_cfo -= CFO_SW_COMP_FINE_TUNE;
1818                 else
1819                         new_cfo += CFO_SW_COMP_FINE_TUNE;
1820         }
1821         rtw89_dcfo_comp(rtwdev, new_cfo);
1822         rtw89_phy_cfo_statistics_reset(rtwdev);
1823 }
1824
1825 void rtw89_phy_cfo_track_work(struct work_struct *work)
1826 {
1827         struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
1828                                                 cfo_track_work.work);
1829         struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
1830
1831         mutex_lock(&rtwdev->mutex);
1832         if (!cfo->cfo_trig_by_timer_en)
1833                 goto out;
1834         rtw89_leave_ps_mode(rtwdev);
1835         rtw89_phy_cfo_dm(rtwdev);
1836         ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
1837                                      msecs_to_jiffies(cfo->cfo_timer_ms));
1838 out:
1839         mutex_unlock(&rtwdev->mutex);
1840 }
1841
1842 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev)
1843 {
1844         struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
1845
1846         ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
1847                                      msecs_to_jiffies(cfo->cfo_timer_ms));
1848 }
1849
1850 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev)
1851 {
1852         struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
1853         struct rtw89_traffic_stats *stats = &rtwdev->stats;
1854
1855         switch (cfo->phy_cfo_status) {
1856         case RTW89_PHY_DCFO_STATE_NORMAL:
1857                 if (stats->tx_throughput >= CFO_TP_UPPER) {
1858                         cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE;
1859                         cfo->cfo_trig_by_timer_en = true;
1860                         cfo->cfo_timer_ms = CFO_COMP_PERIOD;
1861                         rtw89_phy_cfo_start_work(rtwdev);
1862                 }
1863                 break;
1864         case RTW89_PHY_DCFO_STATE_ENHANCE:
1865                 if (cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) {
1866                         cfo->phy_cfo_trk_cnt = 0;
1867                         cfo->cfo_trig_by_timer_en = false;
1868                 }
1869                 if (cfo->cfo_trig_by_timer_en == 1)
1870                         cfo->phy_cfo_trk_cnt++;
1871                 if (stats->tx_throughput <= CFO_TP_LOWER) {
1872                         cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
1873                         cfo->phy_cfo_trk_cnt = 0;
1874                         cfo->cfo_trig_by_timer_en = false;
1875                 }
1876                 break;
1877         default:
1878                 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
1879                 cfo->phy_cfo_trk_cnt = 0;
1880                 break;
1881         }
1882         rtw89_debug(rtwdev, RTW89_DBG_CFO,
1883                     "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n",
1884                     stats->tx_throughput, cfo->phy_cfo_status,
1885                     cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt,
1886                     ewma_thermal_read(&rtwdev->phystat.avg_thermal[0]));
1887         if (cfo->cfo_trig_by_timer_en)
1888                 return;
1889         rtw89_phy_cfo_dm(rtwdev);
1890 }
1891
1892 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
1893                          struct rtw89_rx_phy_ppdu *phy_ppdu)
1894 {
1895         struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
1896         u8 macid = phy_ppdu->mac_id;
1897
1898         cfo->cfo_tail[macid] += cfo_val;
1899         cfo->cfo_cnt[macid]++;
1900         cfo->packet_count++;
1901 }
1902
1903 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
1904 {
1905         struct rtw89_phy_stat *phystat = &rtwdev->phystat;
1906         int i;
1907         u8 th;
1908
1909         for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
1910                 th = rtw89_chip_get_thermal(rtwdev, i);
1911                 if (th)
1912                         ewma_thermal_add(&phystat->avg_thermal[i], th);
1913
1914                 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
1915                             "path(%d) thermal cur=%u avg=%ld", i, th,
1916                             ewma_thermal_read(&phystat->avg_thermal[i]));
1917         }
1918 }
1919
1920 struct rtw89_phy_iter_rssi_data {
1921         struct rtw89_dev *rtwdev;
1922         struct rtw89_phy_ch_info *ch_info;
1923         bool rssi_changed;
1924 };
1925
1926 static void rtw89_phy_stat_rssi_update_iter(void *data,
1927                                             struct ieee80211_sta *sta)
1928 {
1929         struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
1930         struct rtw89_phy_iter_rssi_data *rssi_data =
1931                                         (struct rtw89_phy_iter_rssi_data *)data;
1932         struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info;
1933         unsigned long rssi_curr;
1934
1935         rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi);
1936
1937         if (rssi_curr < ch_info->rssi_min) {
1938                 ch_info->rssi_min = rssi_curr;
1939                 ch_info->rssi_min_macid = rtwsta->mac_id;
1940         }
1941
1942         if (rtwsta->prev_rssi == 0) {
1943                 rtwsta->prev_rssi = rssi_curr;
1944         } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) {
1945                 rtwsta->prev_rssi = rssi_curr;
1946                 rssi_data->rssi_changed = true;
1947         }
1948 }
1949
1950 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev)
1951 {
1952         struct rtw89_phy_iter_rssi_data rssi_data = {0};
1953
1954         rssi_data.rtwdev = rtwdev;
1955         rssi_data.ch_info = &rtwdev->ch_info;
1956         rssi_data.ch_info->rssi_min = U8_MAX;
1957         ieee80211_iterate_stations_atomic(rtwdev->hw,
1958                                           rtw89_phy_stat_rssi_update_iter,
1959                                           &rssi_data);
1960         if (rssi_data.rssi_changed)
1961                 rtw89_btc_ntfy_wl_sta(rtwdev);
1962 }
1963
1964 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
1965 {
1966         struct rtw89_phy_stat *phystat = &rtwdev->phystat;
1967         int i;
1968
1969         for (i = 0; i < rtwdev->chip->rf_path_num; i++)
1970                 ewma_thermal_init(&phystat->avg_thermal[i]);
1971
1972         rtw89_phy_stat_thermal_update(rtwdev);
1973
1974         memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
1975         memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat));
1976 }
1977
1978 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
1979 {
1980         struct rtw89_phy_stat *phystat = &rtwdev->phystat;
1981
1982         rtw89_phy_stat_thermal_update(rtwdev);
1983         rtw89_phy_stat_rssi_update(rtwdev);
1984
1985         phystat->last_pkt_stat = phystat->cur_pkt_stat;
1986         memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
1987 }
1988
1989 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us)
1990 {
1991         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
1992
1993         return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
1994 }
1995
1996 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx)
1997 {
1998         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
1999
2000         return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
2001 }
2002
2003 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev)
2004 {
2005         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2006
2007         env->ccx_manual_ctrl = false;
2008         env->ccx_ongoing = false;
2009         env->ccx_rac_lv = RTW89_RAC_RELEASE;
2010         env->ccx_rpt_stamp = 0;
2011         env->ccx_period = 0;
2012         env->ccx_unit_idx = RTW89_CCX_32_US;
2013         env->ccx_trigger_time = 0;
2014         env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0;
2015
2016         rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1);
2017         rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1);
2018         rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1);
2019         rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK,
2020                                RTW89_CCX_EDCCA_BW20_0);
2021 }
2022
2023 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report,
2024                                     u16 score)
2025 {
2026         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2027         u32 numer = 0;
2028         u16 ret = 0;
2029
2030         numer = report * score + (env->ccx_period >> 1);
2031         if (env->ccx_period)
2032                 ret = numer / env->ccx_period;
2033
2034         return ret >= score ? score - 1 : ret;
2035 }
2036
2037 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev,
2038                                             u16 time_ms, u32 *period,
2039                                             u32 *unit_idx)
2040 {
2041         u32 idx;
2042         u8 quotient;
2043
2044         if (time_ms >= CCX_MAX_PERIOD)
2045                 time_ms = CCX_MAX_PERIOD;
2046
2047         quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD;
2048
2049         if (quotient < 4)
2050                 idx = RTW89_CCX_4_US;
2051         else if (quotient < 8)
2052                 idx = RTW89_CCX_8_US;
2053         else if (quotient < 16)
2054                 idx = RTW89_CCX_16_US;
2055         else
2056                 idx = RTW89_CCX_32_US;
2057
2058         *unit_idx = idx;
2059         *period = (time_ms * MS_TO_4US_RATIO) >> idx;
2060
2061         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2062                     "[Trigger Time] period:%d, unit_idx:%d\n",
2063                     *period, *unit_idx);
2064 }
2065
2066 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev)
2067 {
2068         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2069
2070         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2071                     "lv:(%d)->(0)\n", env->ccx_rac_lv);
2072
2073         env->ccx_ongoing = false;
2074         env->ccx_rac_lv = RTW89_RAC_RELEASE;
2075         env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
2076 }
2077
2078 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev,
2079                                               struct rtw89_ccx_para_info *para)
2080 {
2081         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2082         bool is_update = env->ifs_clm_app != para->ifs_clm_app;
2083         u8 i = 0;
2084         u16 *ifs_th_l = env->ifs_clm_th_l;
2085         u16 *ifs_th_h = env->ifs_clm_th_h;
2086         u32 ifs_th0_us = 0, ifs_th_times = 0;
2087         u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0};
2088
2089         if (!is_update)
2090                 goto ifs_update_finished;
2091
2092         switch (para->ifs_clm_app) {
2093         case RTW89_IFS_CLM_INIT:
2094         case RTW89_IFS_CLM_BACKGROUND:
2095         case RTW89_IFS_CLM_ACS:
2096         case RTW89_IFS_CLM_DBG:
2097         case RTW89_IFS_CLM_DIG:
2098         case RTW89_IFS_CLM_TDMA_DIG:
2099                 ifs_th0_us = IFS_CLM_TH0_UPPER;
2100                 ifs_th_times = IFS_CLM_TH_MUL;
2101                 break;
2102         case RTW89_IFS_CLM_DBG_MANUAL:
2103                 ifs_th0_us = para->ifs_clm_manual_th0;
2104                 ifs_th_times = para->ifs_clm_manual_th_times;
2105                 break;
2106         default:
2107                 break;
2108         }
2109
2110         /* Set sampling threshold for 4 different regions, unit in idx_cnt.
2111          * low[i] = high[i-1] + 1
2112          * high[i] = high[i-1] * ifs_th_times
2113          */
2114         ifs_th_l[IFS_CLM_TH_START_IDX] = 0;
2115         ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us;
2116         ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev,
2117                                                                  ifs_th0_us);
2118         for (i = 1; i < RTW89_IFS_CLM_NUM; i++) {
2119                 ifs_th_l[i] = ifs_th_h[i - 1] + 1;
2120                 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times;
2121                 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]);
2122         }
2123
2124 ifs_update_finished:
2125         if (!is_update)
2126                 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2127                             "No need to update IFS_TH\n");
2128
2129         return is_update;
2130 }
2131
2132 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev)
2133 {
2134         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2135         u8 i = 0;
2136
2137         rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK,
2138                                env->ifs_clm_th_l[0]);
2139         rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK,
2140                                env->ifs_clm_th_l[1]);
2141         rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK,
2142                                env->ifs_clm_th_l[2]);
2143         rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK,
2144                                env->ifs_clm_th_l[3]);
2145
2146         rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK,
2147                                env->ifs_clm_th_h[0]);
2148         rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK,
2149                                env->ifs_clm_th_h[1]);
2150         rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK,
2151                                env->ifs_clm_th_h[2]);
2152         rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK,
2153                                env->ifs_clm_th_h[3]);
2154
2155         for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
2156                 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2157                             "Update IFS_T%d_th{low, high} : {%d, %d}\n",
2158                             i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]);
2159 }
2160
2161 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev)
2162 {
2163         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2164         struct rtw89_ccx_para_info para = {0};
2165
2166         env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
2167         env->ifs_clm_mntr_time = 0;
2168
2169         para.ifs_clm_app = RTW89_IFS_CLM_INIT;
2170         if (rtw89_phy_ifs_clm_th_update_check(rtwdev, &para))
2171                 rtw89_phy_ifs_clm_set_th_reg(rtwdev);
2172
2173         rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN,
2174                                true);
2175         rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true);
2176         rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true);
2177         rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true);
2178         rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true);
2179 }
2180
2181 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev,
2182                                      enum rtw89_env_racing_lv level)
2183 {
2184         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2185         int ret = 0;
2186
2187         if (level >= RTW89_RAC_MAX_NUM) {
2188                 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2189                             "[WARNING] Wrong LV=%d\n", level);
2190                 return -EINVAL;
2191         }
2192
2193         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2194                     "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing,
2195                     env->ccx_rac_lv, level);
2196
2197         if (env->ccx_ongoing) {
2198                 if (level <= env->ccx_rac_lv)
2199                         ret = -EINVAL;
2200                 else
2201                         env->ccx_ongoing = false;
2202         }
2203
2204         if (ret == 0)
2205                 env->ccx_rac_lv = level;
2206
2207         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n",
2208                     !ret);
2209
2210         return ret;
2211 }
2212
2213 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev)
2214 {
2215         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2216
2217         rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0);
2218         rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0);
2219         rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1);
2220         rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1);
2221
2222         env->ccx_rpt_stamp++;
2223         env->ccx_ongoing = true;
2224 }
2225
2226 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev)
2227 {
2228         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2229         u8 i = 0;
2230         u32 res = 0;
2231
2232         env->ifs_clm_tx_ratio =
2233                 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT);
2234         env->ifs_clm_edcca_excl_cca_ratio =
2235                 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca,
2236                                          PERCENT);
2237         env->ifs_clm_cck_fa_ratio =
2238                 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT);
2239         env->ifs_clm_ofdm_fa_ratio =
2240                 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT);
2241         env->ifs_clm_cck_cca_excl_fa_ratio =
2242                 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa,
2243                                          PERCENT);
2244         env->ifs_clm_ofdm_cca_excl_fa_ratio =
2245                 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa,
2246                                          PERCENT);
2247         env->ifs_clm_cck_fa_permil =
2248                 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL);
2249         env->ifs_clm_ofdm_fa_permil =
2250                 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL);
2251
2252         for (i = 0; i < RTW89_IFS_CLM_NUM; i++) {
2253                 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) {
2254                         env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD;
2255                 } else {
2256                         env->ifs_clm_ifs_avg[i] =
2257                                 rtw89_phy_ccx_idx_to_us(rtwdev,
2258                                                         env->ifs_clm_avg[i]);
2259                 }
2260
2261                 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]);
2262                 res += env->ifs_clm_his[i] >> 1;
2263                 if (env->ifs_clm_his[i])
2264                         res /= env->ifs_clm_his[i];
2265                 else
2266                         res = 0;
2267                 env->ifs_clm_cca_avg[i] = res;
2268         }
2269
2270         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2271                     "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n",
2272                     env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio);
2273         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2274                     "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n",
2275                     env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio);
2276         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2277                     "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n",
2278                     env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil);
2279         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2280                     "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n",
2281                     env->ifs_clm_cck_cca_excl_fa_ratio,
2282                     env->ifs_clm_ofdm_cca_excl_fa_ratio);
2283         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2284                     "Time:[his, ifs_avg(us), cca_avg(us)]\n");
2285         for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
2286                 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n",
2287                             i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i],
2288                             env->ifs_clm_cca_avg[i]);
2289 }
2290
2291 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev)
2292 {
2293         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2294         u8 i = 0;
2295
2296         if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) {
2297                 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2298                             "Get IFS_CLM report Fail\n");
2299                 return false;
2300         }
2301
2302         env->ifs_clm_tx =
2303                 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT,
2304                                       B_IFS_CLM_TX_CNT_MSK);
2305         env->ifs_clm_edcca_excl_cca =
2306                 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT,
2307                                       B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK);
2308         env->ifs_clm_cckcca_excl_fa =
2309                 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA,
2310                                       B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK);
2311         env->ifs_clm_ofdmcca_excl_fa =
2312                 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA,
2313                                       B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK);
2314         env->ifs_clm_cckfa =
2315                 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA,
2316                                       B_IFS_CLM_CCK_FA_MSK);
2317         env->ifs_clm_ofdmfa =
2318                 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA,
2319                                       B_IFS_CLM_OFDM_FA_MSK);
2320
2321         env->ifs_clm_his[0] =
2322                 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK);
2323         env->ifs_clm_his[1] =
2324                 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK);
2325         env->ifs_clm_his[2] =
2326                 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK);
2327         env->ifs_clm_his[3] =
2328                 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK);
2329
2330         env->ifs_clm_avg[0] =
2331                 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK);
2332         env->ifs_clm_avg[1] =
2333                 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK);
2334         env->ifs_clm_avg[2] =
2335                 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK);
2336         env->ifs_clm_avg[3] =
2337                 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK);
2338
2339         env->ifs_clm_cca[0] =
2340                 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK);
2341         env->ifs_clm_cca[1] =
2342                 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK);
2343         env->ifs_clm_cca[2] =
2344                 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK);
2345         env->ifs_clm_cca[3] =
2346                 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK);
2347
2348         env->ifs_clm_total_ifs =
2349                 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK);
2350
2351         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n",
2352                     env->ifs_clm_total_ifs);
2353         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2354                     "{Tx, EDCCA_exclu_cca} = {%d, %d}\n",
2355                     env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca);
2356         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2357                     "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n",
2358                     env->ifs_clm_cckfa, env->ifs_clm_ofdmfa);
2359         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2360                     "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n",
2361                     env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa);
2362
2363         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n");
2364         for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
2365                 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2366                             "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i],
2367                             env->ifs_clm_avg[i], env->ifs_clm_cca[i]);
2368
2369         rtw89_phy_ifs_clm_get_utility(rtwdev);
2370
2371         return true;
2372 }
2373
2374 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev,
2375                                  struct rtw89_ccx_para_info *para)
2376 {
2377         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2378         u32 period = 0;
2379         u32 unit_idx = 0;
2380
2381         if (para->mntr_time == 0) {
2382                 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2383                             "[WARN] MNTR_TIME is 0\n");
2384                 return -EINVAL;
2385         }
2386
2387         if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv))
2388                 return -EINVAL;
2389
2390         if (para->mntr_time != env->ifs_clm_mntr_time) {
2391                 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
2392                                                 &period, &unit_idx);
2393                 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER,
2394                                        B_IFS_CLM_PERIOD_MSK, period);
2395                 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER,
2396                                        B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx);
2397
2398                 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2399                             "Update IFS-CLM time ((%d)) -> ((%d))\n",
2400                             env->ifs_clm_mntr_time, para->mntr_time);
2401
2402                 env->ifs_clm_mntr_time = para->mntr_time;
2403                 env->ccx_period = (u16)period;
2404                 env->ccx_unit_idx = (u8)unit_idx;
2405         }
2406
2407         if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) {
2408                 env->ifs_clm_app = para->ifs_clm_app;
2409                 rtw89_phy_ifs_clm_set_th_reg(rtwdev);
2410         }
2411
2412         return 0;
2413 }
2414
2415 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev)
2416 {
2417         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2418         struct rtw89_ccx_para_info para = {0};
2419         u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL;
2420
2421         env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL;
2422         if (env->ccx_manual_ctrl) {
2423                 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2424                             "CCX in manual ctrl\n");
2425                 return;
2426         }
2427
2428         /* only ifs_clm for now */
2429         if (rtw89_phy_ifs_clm_get_result(rtwdev))
2430                 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM;
2431
2432         rtw89_phy_ccx_racing_release(rtwdev);
2433         para.mntr_time = 1900;
2434         para.rac_lv = RTW89_RAC_LV_1;
2435         para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
2436
2437         if (rtw89_phy_ifs_clm_set(rtwdev, &para) == 0)
2438                 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM;
2439         if (chk_result)
2440                 rtw89_phy_ccx_trigger(rtwdev);
2441
2442         rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2443                     "get_result=0x%x, chk_result:0x%x\n",
2444                     env->ccx_watchdog_result, chk_result);
2445 }
2446
2447 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page)
2448 {
2449         if (*ie_page > RTW89_PHYSTS_BITMAP_NUM ||
2450             *ie_page == RTW89_RSVD_9)
2451                 return false;
2452         else if (*ie_page > RTW89_RSVD_9)
2453                 *ie_page -= 1;
2454
2455         return true;
2456 }
2457
2458 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)
2459 {
2460         static const u8 ie_page_shift = 2;
2461
2462         return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift);
2463 }
2464
2465 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev,
2466                                       enum rtw89_phy_status_bitmap ie_page)
2467 {
2468         u32 addr;
2469
2470         if (!rtw89_physts_ie_page_valid(&ie_page))
2471                 return 0;
2472
2473         addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
2474
2475         return rtw89_phy_read32(rtwdev, addr);
2476 }
2477
2478 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev,
2479                                        enum rtw89_phy_status_bitmap ie_page,
2480                                        u32 val)
2481 {
2482         const struct rtw89_chip_info *chip = rtwdev->chip;
2483         u32 addr;
2484
2485         if (!rtw89_physts_ie_page_valid(&ie_page))
2486                 return;
2487
2488         if (chip->chip_id == RTL8852A)
2489                 val &= B_PHY_STS_BITMAP_MSK_52A;
2490
2491         addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
2492         rtw89_phy_write32(rtwdev, addr, val);
2493 }
2494
2495 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev,
2496                                           enum rtw89_phy_status_bitmap bitmap,
2497                                           enum rtw89_phy_status_ie_type ie,
2498                                           bool enable)
2499 {
2500         u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap);
2501
2502         if (enable)
2503                 val |= BIT(ie);
2504         else
2505                 val &= ~BIT(ie);
2506
2507         rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val);
2508 }
2509
2510 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev,
2511                                             bool enable,
2512                                             enum rtw89_phy_idx phy_idx)
2513 {
2514         if (enable) {
2515                 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM,
2516                                       B_STS_DIS_TRIG_BY_FAIL);
2517                 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM,
2518                                       B_STS_DIS_TRIG_BY_BRK);
2519         } else {
2520                 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM,
2521                                       B_STS_DIS_TRIG_BY_FAIL);
2522                 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM,
2523                                       B_STS_DIS_TRIG_BY_BRK);
2524         }
2525 }
2526
2527 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev)
2528 {
2529         const struct rtw89_chip_info *chip = rtwdev->chip;
2530         u8 i;
2531
2532         if (chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV)
2533                 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0);
2534
2535         for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) {
2536                 if (i >= RTW89_CCK_PKT)
2537                         rtw89_physts_enable_ie_bitmap(rtwdev, i,
2538                                                       RTW89_PHYSTS_IE09_FTR_0,
2539                                                       true);
2540                 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) ||
2541                     (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT))
2542                         continue;
2543                 rtw89_physts_enable_ie_bitmap(rtwdev, i,
2544                                               RTW89_PHYSTS_IE24_OFDM_TD_PATH_A,
2545                                               true);
2546         }
2547         rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT,
2548                                       RTW89_PHYSTS_IE13_DL_MU_DEF, true);
2549         rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT,
2550                                       RTW89_PHYSTS_IE13_DL_MU_DEF, true);
2551
2552         /* force IE01 for channel index, only channel field is valid */
2553         rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT,
2554                                       RTW89_PHYSTS_IE01_CMN_OFDM, true);
2555 }
2556
2557 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type)
2558 {
2559         const struct rtw89_chip_info *chip = rtwdev->chip;
2560         struct rtw89_dig_info *dig = &rtwdev->dig;
2561         const struct rtw89_phy_dig_gain_cfg *cfg;
2562         const char *msg;
2563         u8 i;
2564         s8 gain_base;
2565         s8 *gain_arr;
2566         u32 tmp;
2567
2568         switch (type) {
2569         case RTW89_DIG_GAIN_LNA_G:
2570                 gain_arr = dig->lna_gain_g;
2571                 gain_base = LNA0_GAIN;
2572                 cfg = chip->dig_table->cfg_lna_g;
2573                 msg = "lna_gain_g";
2574                 break;
2575         case RTW89_DIG_GAIN_TIA_G:
2576                 gain_arr = dig->tia_gain_g;
2577                 gain_base = TIA0_GAIN_G;
2578                 cfg = chip->dig_table->cfg_tia_g;
2579                 msg = "tia_gain_g";
2580                 break;
2581         case RTW89_DIG_GAIN_LNA_A:
2582                 gain_arr = dig->lna_gain_a;
2583                 gain_base = LNA0_GAIN;
2584                 cfg = chip->dig_table->cfg_lna_a;
2585                 msg = "lna_gain_a";
2586                 break;
2587         case RTW89_DIG_GAIN_TIA_A:
2588                 gain_arr = dig->tia_gain_a;
2589                 gain_base = TIA0_GAIN_A;
2590                 cfg = chip->dig_table->cfg_tia_a;
2591                 msg = "tia_gain_a";
2592                 break;
2593         default:
2594                 return;
2595         }
2596
2597         for (i = 0; i < cfg->size; i++) {
2598                 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr,
2599                                             cfg->table[i].mask);
2600                 tmp >>= DIG_GAIN_SHIFT;
2601                 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base;
2602                 gain_base += DIG_GAIN;
2603
2604                 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n",
2605                             msg, i, gain_arr[i]);
2606         }
2607 }
2608
2609 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev)
2610 {
2611         struct rtw89_dig_info *dig = &rtwdev->dig;
2612         u32 tmp;
2613         u8 i;
2614
2615         tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW,
2616                                     B_PATH0_IB_PKPW_MSK);
2617         dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT);
2618         dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK,
2619                                             B_PATH0_IB_PBK_MSK);
2620         rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n",
2621                     dig->ib_pkpwr, dig->ib_pbk);
2622
2623         for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++)
2624                 rtw89_phy_dig_read_gain_table(rtwdev, i);
2625 }
2626
2627 static const u8 rssi_nolink = 22;
2628 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104};
2629 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88};
2630 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16};
2631 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528};
2632
2633 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev)
2634 {
2635         struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info;
2636         struct rtw89_dig_info *dig = &rtwdev->dig;
2637         bool is_linked = rtwdev->total_sta_assoc > 0;
2638
2639         if (is_linked) {
2640                 dig->igi_rssi = ch_info->rssi_min >> 1;
2641         } else {
2642                 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n");
2643                 dig->igi_rssi = rssi_nolink;
2644         }
2645 }
2646
2647 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev)
2648 {
2649         struct rtw89_dig_info *dig = &rtwdev->dig;
2650         bool is_linked = rtwdev->total_sta_assoc > 0;
2651         const u16 *fa_th_src = NULL;
2652
2653         switch (rtwdev->hal.current_band_type) {
2654         case RTW89_BAND_2G:
2655                 dig->lna_gain = dig->lna_gain_g;
2656                 dig->tia_gain = dig->tia_gain_g;
2657                 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink;
2658                 dig->force_gaincode_idx_en = false;
2659                 dig->dyn_pd_th_en = true;
2660                 break;
2661         case RTW89_BAND_5G:
2662         default:
2663                 dig->lna_gain = dig->lna_gain_a;
2664                 dig->tia_gain = dig->tia_gain_a;
2665                 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink;
2666                 dig->force_gaincode_idx_en = true;
2667                 dig->dyn_pd_th_en = true;
2668                 break;
2669         }
2670         memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th));
2671         memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th));
2672 }
2673
2674 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20;
2675 static const u8 igi_max_performance_mode = 0x5a;
2676 static const u8 dynamic_pd_threshold_max;
2677
2678 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev)
2679 {
2680         struct rtw89_dig_info *dig = &rtwdev->dig;
2681
2682         dig->cur_gaincode.lna_idx = LNA_IDX_MAX;
2683         dig->cur_gaincode.tia_idx = TIA_IDX_MAX;
2684         dig->cur_gaincode.rxb_idx = RXB_IDX_MAX;
2685         dig->force_gaincode.lna_idx = LNA_IDX_MAX;
2686         dig->force_gaincode.tia_idx = TIA_IDX_MAX;
2687         dig->force_gaincode.rxb_idx = RXB_IDX_MAX;
2688
2689         dig->dyn_igi_max = igi_max_performance_mode;
2690         dig->dyn_igi_min = dynamic_igi_min;
2691         dig->dyn_pd_th_max = dynamic_pd_threshold_max;
2692         dig->pd_low_th_ofst = pd_low_th_offset;
2693         dig->is_linked_pre = false;
2694 }
2695
2696 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev)
2697 {
2698         rtw89_phy_dig_update_gain_para(rtwdev);
2699         rtw89_phy_dig_reset(rtwdev);
2700 }
2701
2702 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)
2703 {
2704         struct rtw89_dig_info *dig = &rtwdev->dig;
2705         u8 lna_idx;
2706
2707         if (rssi < dig->igi_rssi_th[0])
2708                 lna_idx = RTW89_DIG_GAIN_LNA_IDX6;
2709         else if (rssi < dig->igi_rssi_th[1])
2710                 lna_idx = RTW89_DIG_GAIN_LNA_IDX5;
2711         else if (rssi < dig->igi_rssi_th[2])
2712                 lna_idx = RTW89_DIG_GAIN_LNA_IDX4;
2713         else if (rssi < dig->igi_rssi_th[3])
2714                 lna_idx = RTW89_DIG_GAIN_LNA_IDX3;
2715         else if (rssi < dig->igi_rssi_th[4])
2716                 lna_idx = RTW89_DIG_GAIN_LNA_IDX2;
2717         else
2718                 lna_idx = RTW89_DIG_GAIN_LNA_IDX1;
2719
2720         return lna_idx;
2721 }
2722
2723 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)
2724 {
2725         struct rtw89_dig_info *dig = &rtwdev->dig;
2726         u8 tia_idx;
2727
2728         if (rssi < dig->igi_rssi_th[0])
2729                 tia_idx = RTW89_DIG_GAIN_TIA_IDX1;
2730         else
2731                 tia_idx = RTW89_DIG_GAIN_TIA_IDX0;
2732
2733         return tia_idx;
2734 }
2735
2736 #define IB_PBK_BASE 110
2737 #define WB_RSSI_BASE 10
2738 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,
2739                                         struct rtw89_agc_gaincode_set *set)
2740 {
2741         struct rtw89_dig_info *dig = &rtwdev->dig;
2742         s8 lna_gain = dig->lna_gain[set->lna_idx];
2743         s8 tia_gain = dig->tia_gain[set->tia_idx];
2744         s32 wb_rssi = rssi + lna_gain + tia_gain;
2745         s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE;
2746         u8 rxb_idx;
2747
2748         rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi;
2749         rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX);
2750
2751         rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n",
2752                     wb_rssi, rxb_idx_tmp);
2753
2754         return rxb_idx;
2755 }
2756
2757 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,
2758                                            struct rtw89_agc_gaincode_set *set)
2759 {
2760         set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi);
2761         set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi);
2762         set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set);
2763
2764         rtw89_debug(rtwdev, RTW89_DBG_DIG,
2765                     "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n",
2766                     rssi, set->lna_idx, set->tia_idx, set->rxb_idx);
2767 }
2768
2769 #define IGI_OFFSET_MAX 25
2770 #define IGI_OFFSET_MUL 2
2771 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev)
2772 {
2773         struct rtw89_dig_info *dig = &rtwdev->dig;
2774         struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2775         enum rtw89_dig_noisy_level noisy_lv;
2776         u8 igi_offset = dig->fa_rssi_ofst;
2777         u16 fa_ratio = 0;
2778
2779         fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil;
2780
2781         if (fa_ratio < dig->fa_th[0])
2782                 noisy_lv = RTW89_DIG_NOISY_LEVEL0;
2783         else if (fa_ratio < dig->fa_th[1])
2784                 noisy_lv = RTW89_DIG_NOISY_LEVEL1;
2785         else if (fa_ratio < dig->fa_th[2])
2786                 noisy_lv = RTW89_DIG_NOISY_LEVEL2;
2787         else if (fa_ratio < dig->fa_th[3])
2788                 noisy_lv = RTW89_DIG_NOISY_LEVEL3;
2789         else
2790                 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX;
2791
2792         if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2)
2793                 igi_offset = 0;
2794         else
2795                 igi_offset += noisy_lv * IGI_OFFSET_MUL;
2796
2797         igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX);
2798         dig->fa_rssi_ofst = igi_offset;
2799
2800         rtw89_debug(rtwdev, RTW89_DBG_DIG,
2801                     "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n",
2802                     dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]);
2803
2804         rtw89_debug(rtwdev, RTW89_DBG_DIG,
2805                     "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n",
2806                     env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil,
2807                     env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil,
2808                     noisy_lv, igi_offset);
2809 }
2810
2811 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx)
2812 {
2813         rtw89_phy_write32_mask(rtwdev, R_PATH0_LNA_INIT,
2814                                B_PATH0_LNA_INIT_IDX_MSK, lna_idx);
2815         rtw89_phy_write32_mask(rtwdev, R_PATH1_LNA_INIT,
2816                                B_PATH1_LNA_INIT_IDX_MSK, lna_idx);
2817 }
2818
2819 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx)
2820 {
2821         rtw89_phy_write32_mask(rtwdev, R_PATH0_TIA_INIT,
2822                                B_PATH0_TIA_INIT_IDX_MSK, tia_idx);
2823         rtw89_phy_write32_mask(rtwdev, R_PATH1_TIA_INIT,
2824                                B_PATH1_TIA_INIT_IDX_MSK, tia_idx);
2825 }
2826
2827 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx)
2828 {
2829         rtw89_phy_write32_mask(rtwdev, R_PATH0_RXB_INIT,
2830                                B_PATH0_RXB_INIT_IDX_MSK, rxb_idx);
2831         rtw89_phy_write32_mask(rtwdev, R_PATH1_RXB_INIT,
2832                                B_PATH1_RXB_INIT_IDX_MSK, rxb_idx);
2833 }
2834
2835 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev,
2836                                      const struct rtw89_agc_gaincode_set set)
2837 {
2838         rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx);
2839         rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx);
2840         rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx);
2841
2842         rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n",
2843                     set.lna_idx, set.tia_idx, set.rxb_idx);
2844 }
2845
2846 static const struct rtw89_reg_def sdagc_config[4] = {
2847         {R_PATH0_P20_FOLLOW_BY_PAGCUGC, B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
2848         {R_PATH0_S20_FOLLOW_BY_PAGCUGC, B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
2849         {R_PATH1_P20_FOLLOW_BY_PAGCUGC, B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
2850         {R_PATH1_S20_FOLLOW_BY_PAGCUGC, B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
2851 };
2852
2853 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev,
2854                                                    bool enable)
2855 {
2856         u8 i = 0;
2857
2858         for (i = 0; i < ARRAY_SIZE(sdagc_config); i++)
2859                 rtw89_phy_write32_mask(rtwdev, sdagc_config[i].addr,
2860                                        sdagc_config[i].mask, enable);
2861
2862         rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable);
2863 }
2864
2865 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi,
2866                                     bool enable)
2867 {
2868         enum rtw89_bandwidth cbw = rtwdev->hal.current_band_width;
2869         struct rtw89_dig_info *dig = &rtwdev->dig;
2870         u8 final_rssi = 0, under_region = dig->pd_low_th_ofst;
2871         u8 ofdm_cca_th;
2872         s8 cck_cca_th;
2873         u32 pd_val = 0;
2874
2875         under_region += PD_TH_SB_FLTR_CMP_VAL;
2876
2877         switch (cbw) {
2878         case RTW89_CHANNEL_WIDTH_40:
2879                 under_region += PD_TH_BW40_CMP_VAL;
2880                 break;
2881         case RTW89_CHANNEL_WIDTH_80:
2882                 under_region += PD_TH_BW80_CMP_VAL;
2883                 break;
2884         case RTW89_CHANNEL_WIDTH_160:
2885                 under_region += PD_TH_BW160_CMP_VAL;
2886                 break;
2887         case RTW89_CHANNEL_WIDTH_20:
2888                 fallthrough;
2889         default:
2890                 under_region += PD_TH_BW20_CMP_VAL;
2891                 break;
2892         }
2893
2894         dig->dyn_pd_th_max = dig->igi_rssi;
2895
2896         final_rssi = min_t(u8, rssi, dig->igi_rssi);
2897         ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region,
2898                               PD_TH_MAX_RSSI + under_region);
2899
2900         if (enable) {
2901                 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1;
2902                 rtw89_debug(rtwdev, RTW89_DBG_DIG,
2903                             "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n",
2904                             final_rssi, ofdm_cca_th, under_region, pd_val);
2905         } else {
2906                 rtw89_debug(rtwdev, RTW89_DBG_DIG,
2907                             "Dynamic PD th disabled, Set PD_low_bd=0\n");
2908         }
2909
2910         rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK,
2911                                pd_val);
2912         rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD,
2913                                B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, enable);
2914
2915         if (!rtwdev->hal.support_cckpd)
2916                 return;
2917
2918         cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI);
2919         pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX);
2920
2921         rtw89_debug(rtwdev, RTW89_DBG_DIG,
2922                     "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n",
2923                     final_rssi, cck_cca_th, under_region, pd_val);
2924
2925         rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1,
2926                                B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable);
2927         rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1,
2928                                B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val);
2929 }
2930
2931 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev)
2932 {
2933         struct rtw89_dig_info *dig = &rtwdev->dig;
2934
2935         dig->bypass_dig = false;
2936         rtw89_phy_dig_para_reset(rtwdev);
2937         rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
2938         rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false);
2939         rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false);
2940         rtw89_phy_dig_update_para(rtwdev);
2941 }
2942
2943 #define IGI_RSSI_MIN 10
2944 void rtw89_phy_dig(struct rtw89_dev *rtwdev)
2945 {
2946         struct rtw89_dig_info *dig = &rtwdev->dig;
2947         bool is_linked = rtwdev->total_sta_assoc > 0;
2948
2949         if (unlikely(dig->bypass_dig)) {
2950                 dig->bypass_dig = false;
2951                 return;
2952         }
2953
2954         if (!dig->is_linked_pre && is_linked) {
2955                 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n");
2956                 rtw89_phy_dig_update_para(rtwdev);
2957         } else if (dig->is_linked_pre && !is_linked) {
2958                 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n");
2959                 rtw89_phy_dig_update_para(rtwdev);
2960         }
2961         dig->is_linked_pre = is_linked;
2962
2963         rtw89_phy_dig_igi_offset_by_env(rtwdev);
2964         rtw89_phy_dig_update_rssi_info(rtwdev);
2965
2966         dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ?
2967                             dig->igi_rssi - IGI_RSSI_MIN : 0;
2968         dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX;
2969         dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst;
2970
2971         dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min,
2972                                  dig->dyn_igi_max);
2973
2974         rtw89_debug(rtwdev, RTW89_DBG_DIG,
2975                     "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n",
2976                     dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min,
2977                     dig->igi_fa_rssi);
2978
2979         if (dig->force_gaincode_idx_en) {
2980                 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
2981                 rtw89_debug(rtwdev, RTW89_DBG_DIG,
2982                             "Force gaincode index enabled.\n");
2983         } else {
2984                 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi,
2985                                                &dig->cur_gaincode);
2986                 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode);
2987         }
2988
2989         rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en);
2990
2991         if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max)
2992                 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true);
2993         else
2994                 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false);
2995 }
2996
2997 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)
2998 {
2999         rtw89_phy_ccx_top_setting_init(rtwdev);
3000         rtw89_phy_ifs_clm_setting_init(rtwdev);
3001 }
3002
3003 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)
3004 {
3005         const struct rtw89_chip_info *chip = rtwdev->chip;
3006
3007         rtw89_phy_stat_init(rtwdev);
3008
3009         rtw89_chip_bb_sethw(rtwdev);
3010
3011         rtw89_phy_env_monitor_init(rtwdev);
3012         rtw89_physts_parsing_init(rtwdev);
3013         rtw89_phy_dig_init(rtwdev);
3014         rtw89_phy_cfo_init(rtwdev);
3015
3016         rtw89_phy_init_rf_nctl(rtwdev);
3017         rtw89_chip_rfk_init(rtwdev);
3018         rtw89_load_txpwr_table(rtwdev, chip->byr_table);
3019         rtw89_chip_set_txpwr_ctrl(rtwdev);
3020         rtw89_chip_power_trim(rtwdev);
3021 }
3022
3023 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif)
3024 {
3025         enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
3026         u8 bss_color;
3027
3028         if (!vif->bss_conf.he_support || !vif->bss_conf.assoc)
3029                 return;
3030
3031         bss_color = vif->bss_conf.he_bss_color.color;
3032
3033         rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1,
3034                               phy_idx);
3035         rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color,
3036                               phy_idx);
3037         rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID,
3038                               vif->bss_conf.aid, phy_idx);
3039 }