drivers/net/wireless/realtek/rtw88/rtw8821c.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /* Copyright(c) 2018-2019  Realtek Corporation
   3  */
   4
   5 #include "main.h"
   6 #include "coex.h"
   7 #include "fw.h"
   8 #include "tx.h"
   9 #include "rx.h"
  10 #include "phy.h"
  11 #include "rtw8821c.h"
  12 #include "rtw8821c_table.h"
  13 #include "mac.h"
  14 #include "reg.h"
  15 #include "debug.h"
  16 #include "bf.h"
  17
  18 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse,
  19                                     struct rtw8821c_efuse *map)
  20 {
  21         ether_addr_copy(efuse->addr, map->e.mac_addr);
  22 }
  23
  24 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
  25 {
  26         struct rtw_efuse *efuse = &rtwdev->efuse;
  27         struct rtw8821c_efuse *map;
  28         int i;
  29
  30         map = (struct rtw8821c_efuse *)log_map;
  31
  32         efuse->rfe_option = map->rfe_option;
  33         efuse->rf_board_option = map->rf_board_option;
  34         efuse->crystal_cap = map->xtal_k;
  35         efuse->pa_type_2g = map->pa_type;
  36         efuse->pa_type_5g = map->pa_type;
  37         efuse->lna_type_2g = map->lna_type_2g[0];
  38         efuse->lna_type_5g = map->lna_type_5g[0];
  39         efuse->channel_plan = map->channel_plan;
  40         efuse->country_code[0] = map->country_code[0];
  41         efuse->country_code[1] = map->country_code[1];
  42         efuse->bt_setting = map->rf_bt_setting;
  43         efuse->regd = map->rf_board_option & 0x7;
  44         efuse->thermal_meter[0] = map->thermal_meter;
  45         efuse->thermal_meter_k = map->thermal_meter;
  46         efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
  47         efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
  48
  49         for (i = 0; i < 4; i++)
  50                 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
  51
  52         switch (rtw_hci_type(rtwdev)) {
  53         case RTW_HCI_TYPE_PCIE:
  54                 rtw8821ce_efuse_parsing(efuse, map);
  55                 break;
  56         default:
  57                 /* unsupported now */
  58                 return -ENOTSUPP;
  59         }
  60
  61         return 0;
  62 }
  63
  64 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
  65 {
  66         u8 crystal_cap, val;
  67
  68         /* power on BB/RF domain */
  69         val = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
  70         val |= BIT_FEN_PCIEA;
  71         rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
  72
  73         /* toggle BB reset */
  74         val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
  75         rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
  76         val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
  77         rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
  78         val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
  79         rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
  80
  81         rtw_write8(rtwdev, REG_RF_CTRL,
  82                    BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
  83         usleep_range(10, 11);
  84         rtw_write8(rtwdev, REG_WLRF1 + 3,
  85                    BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
  86         usleep_range(10, 11);
  87
  88         /* pre init before header files config */
  89         rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
  90
  91         rtw_phy_load_tables(rtwdev);
  92
  93         crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
  94         rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
  95         rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
  96         rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0);
  97
  98         /* post init after header files config */
  99         rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
 100         rtwdev->chip->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);
 101         rtwdev->chip->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD);
 102         rtwdev->chip->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);
 103
 104         rtw_phy_init(rtwdev);
 105         rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
 106 }
 107
 108 static int rtw8821c_mac_init(struct rtw_dev *rtwdev)
 109 {
 110         u32 value32;
 111         u16 pre_txcnt;
 112
 113         /* protocol configuration */
 114         rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
 115         rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
 116         pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
 117         rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
 118         rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
 119         value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
 120                   (WLAN_MAX_AGG_PKT_LIMIT << 16) |
 121                   (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
 122         rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
 123         rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
 124                     WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
 125         rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
 126         rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
 127         rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
 128         rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
 129         rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5));
 130
 131         /* EDCA configuration */
 132         rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
 133         rtw_write16(rtwdev, REG_TXPAUSE, 0);
 134         rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
 135         rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
 136         rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
 137         rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
 138         rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
 139         rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
 140         rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
 141
 142         /* Set beacon cotnrol - enable TSF and other related functions */
 143         rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
 144
 145         /* Set send beacon related registers */
 146         rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
 147         rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
 148         rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
 149         rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
 150
 151         /* WMAC configuration */
 152         rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
 153         rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
 154         rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
 155         rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
 156         rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
 157         rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
 158         rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40);
 159         rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1));
 160         rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, BIT(6));
 161         rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
 162         rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
 163
 164         return 0;
 165 }
 166
 167 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
 168 {
 169         u8 ldo_pwr;
 170
 171         ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
 172         ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7);
 173         rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
 174 }
 175
 176 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
 177 {
 178         u32 rf_reg18;
 179
 180         rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
 181
 182         rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
 183                       RF18_BW_MASK);
 184
 185         rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
 186         rf_reg18 |= (channel & RF18_CHANNEL_MASK);
 187
 188         if (channel >= 100 && channel <= 140)
 189                 rf_reg18 |= RF18_RFSI_GE;
 190         else if (channel > 140)
 191                 rf_reg18 |= RF18_RFSI_GT;
 192
 193         switch (bw) {
 194         case RTW_CHANNEL_WIDTH_5:
 195         case RTW_CHANNEL_WIDTH_10:
 196         case RTW_CHANNEL_WIDTH_20:
 197         default:
 198                 rf_reg18 |= RF18_BW_20M;
 199                 break;
 200         case RTW_CHANNEL_WIDTH_40:
 201                 rf_reg18 |= RF18_BW_40M;
 202                 break;
 203         case RTW_CHANNEL_WIDTH_80:
 204                 rf_reg18 |= RF18_BW_80M;
 205                 break;
 206         }
 207
 208         if (channel <= 14) {
 209                 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1);
 210                 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf);
 211         } else {
 212                 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0);
 213         }
 214
 215         rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
 216
 217         rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
 218         rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
 219 }
 220
 221 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
 222 {
 223         if (bw == RTW_CHANNEL_WIDTH_40) {
 224                 /* RX DFIR for BW40 */
 225                 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
 226                 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
 227                 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
 228                 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
 229         } else if (bw == RTW_CHANNEL_WIDTH_80) {
 230                 /* RX DFIR for BW80 */
 231                 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
 232                 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
 233                 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
 234                 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1);
 235         } else {
 236                 /* RX DFIR for BW20, BW10 and BW5 */
 237                 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
 238                 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
 239                 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
 240                 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
 241         }
 242 }
 243
 244 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
 245                                     u8 primary_ch_idx)
 246 {
 247         u32 val32;
 248
 249         if (channel <= 14) {
 250                 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
 251                 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
 252                 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
 253                 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
 254
 255                 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0);
 256                 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
 257                 if (channel == 14) {
 258                         rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
 259                         rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
 260                         rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
 261                 } else {
 262                         rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
 263                                          rtwdev->chip->ch_param[0]);
 264                         rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
 265                                          rtwdev->chip->ch_param[1] & MASKLWORD);
 266                         rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
 267                                          rtwdev->chip->ch_param[2]);
 268                 }
 269         } else if (channel > 35) {
 270                 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
 271                 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
 272                 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
 273                 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
 274
 275                 if (channel >= 36 && channel <= 64)
 276                         rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1);
 277                 else if (channel >= 100 && channel <= 144)
 278                         rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2);
 279                 else if (channel >= 149)
 280                         rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3);
 281
 282                 if (channel >= 36 && channel <= 48)
 283                         rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
 284                 else if (channel >= 52 && channel <= 64)
 285                         rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
 286                 else if (channel >= 100 && channel <= 116)
 287                         rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
 288                 else if (channel >= 118 && channel <= 177)
 289                         rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
 290         }
 291
 292         switch (bw) {
 293         case RTW_CHANNEL_WIDTH_20:
 294         default:
 295                 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
 296                 val32 &= 0xffcffc00;
 297                 val32 |= 0x10010000;
 298                 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
 299
 300                 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
 301                 break;
 302         case RTW_CHANNEL_WIDTH_40:
 303                 if (primary_ch_idx == 1)
 304                         rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
 305                 else
 306                         rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
 307
 308                 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
 309                 val32 &= 0xff3ff300;
 310                 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) |
 311                          RTW_CHANNEL_WIDTH_40;
 312                 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
 313
 314                 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
 315                 break;
 316         case RTW_CHANNEL_WIDTH_80:
 317                 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
 318                 val32 &= 0xfcffcf00;
 319                 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) |
 320                          RTW_CHANNEL_WIDTH_80;
 321                 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
 322
 323                 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
 324                 break;
 325         case RTW_CHANNEL_WIDTH_5:
 326                 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
 327                 val32 &= 0xefcefc00;
 328                 val32 |= 0x200240;
 329                 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
 330
 331                 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
 332                 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
 333                 break;
 334         case RTW_CHANNEL_WIDTH_10:
 335                 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
 336                 val32 &= 0xefcefc00;
 337                 val32 |= 0x300380;
 338                 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
 339
 340                 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
 341                 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
 342                 break;
 343         }
 344 }
 345
 346 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel)
 347 {
 348         struct rtw_efuse efuse = rtwdev->efuse;
 349         u8 tx_bb_swing;
 350         u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
 351
 352         tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g :
 353                                       efuse.tx_bb_swing_setting_5g;
 354         if (tx_bb_swing > 9)
 355                 tx_bb_swing = 0;
 356
 357         return swing2setting[(tx_bb_swing / 3)];
 358 }
 359
 360 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel,
 361                                           u8 bw, u8 primary_ch_idx)
 362 {
 363         rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
 364                          rtw8821c_get_bb_swing(rtwdev, channel));
 365 }
 366
 367 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
 368                                  u8 primary_chan_idx)
 369 {
 370         rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
 371         rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx);
 372         rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
 373         rtw8821c_set_channel_rf(rtwdev, channel, bw);
 374         rtw8821c_set_channel_rxdfir(rtwdev, bw);
 375 }
 376
 377 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
 378                                    struct rtw_rx_pkt_stat *pkt_stat)
 379 {
 380         s8 min_rx_power = -120;
 381         u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status);
 382
 383         pkt_stat->rx_power[RF_PATH_A] = pwdb - 100;
 384         pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
 385         pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
 386         pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
 387                                      min_rx_power);
 388 }
 389
 390 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
 391                                    struct rtw_rx_pkt_stat *pkt_stat)
 392 {
 393         u8 rxsc, bw;
 394         s8 min_rx_power = -120;
 395
 396         if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
 397                 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
 398         else
 399                 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
 400
 401         if (rxsc >= 1 && rxsc <= 8)
 402                 bw = RTW_CHANNEL_WIDTH_20;
 403         else if (rxsc >= 9 && rxsc <= 12)
 404                 bw = RTW_CHANNEL_WIDTH_40;
 405         else if (rxsc >= 13)
 406                 bw = RTW_CHANNEL_WIDTH_80;
 407         else
 408                 bw = GET_PHY_STAT_P1_RF_MODE(phy_status);
 409
 410         pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
 411         pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
 412         pkt_stat->bw = bw;
 413         pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
 414                                      min_rx_power);
 415 }
 416
 417 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
 418                              struct rtw_rx_pkt_stat *pkt_stat)
 419 {
 420         u8 page;
 421
 422         page = *phy_status & 0xf;
 423
 424         switch (page) {
 425         case 0:
 426                 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
 427                 break;
 428         case 1:
 429                 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
 430                 break;
 431         default:
 432                 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
 433                 return;
 434         }
 435 }
 436
 437 static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
 438                                    struct rtw_rx_pkt_stat *pkt_stat,
 439                                    struct ieee80211_rx_status *rx_status)
 440 {
 441         struct ieee80211_hdr *hdr;
 442         u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
 443         u8 *phy_status = NULL;
 444
 445         memset(pkt_stat, 0, sizeof(*pkt_stat));
 446
 447         pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
 448         pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
 449         pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
 450         pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc);
 451         pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
 452         pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
 453         pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
 454         pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
 455         pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
 456         pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
 457         pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
 458         pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
 459
 460         /* drv_info_sz is in unit of 8-bytes */
 461         pkt_stat->drv_info_sz *= 8;
 462
 463         /* c2h cmd pkt's rx/phy status is not interested */
 464         if (pkt_stat->is_c2h)
 465                 return;
 466
 467         hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
 468                                        pkt_stat->drv_info_sz);
 469         if (pkt_stat->phy_status) {
 470                 phy_status = rx_desc + desc_sz + pkt_stat->shift;
 471                 query_phy_status(rtwdev, phy_status, pkt_stat);
 472         }
 473
 474         rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
 475 }
 476
 477 static void
 478 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
 479 {
 480         struct rtw_hal *hal = &rtwdev->hal;
 481         static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
 482         static u32 phy_pwr_idx;
 483         u8 rate, rate_idx, pwr_index, shift;
 484         int j;
 485
 486         for (j = 0; j < rtw_rate_size[rs]; j++) {
 487                 rate = rtw_rate_section[rs][j];
 488                 pwr_index = hal->tx_pwr_tbl[path][rate];
 489                 shift = rate & 0x3;
 490                 phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
 491                 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) {
 492                         rate_idx = rate & 0xfc;
 493                         rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
 494                                     phy_pwr_idx);
 495                         phy_pwr_idx = 0;
 496                 }
 497         }
 498 }
 499
 500 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev)
 501 {
 502         struct rtw_hal *hal = &rtwdev->hal;
 503         int rs, path;
 504
 505         for (path = 0; path < hal->rf_path_num; path++) {
 506                 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
 507                         if (rs == RTW_RATE_SECTION_HT_2S ||
 508                             rs == RTW_RATE_SECTION_VHT_2S)
 509                                 continue;
 510                         rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs);
 511                 }
 512         }
 513 }
 514
 515 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev)
 516 {
 517         struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 518         u32 cck_enable;
 519         u32 cck_fa_cnt;
 520         u32 ofdm_fa_cnt;
 521         u32 crc32_cnt;
 522         u32 cca32_cnt;
 523
 524         cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);
 525         cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK);
 526         ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM);
 527
 528         dm_info->cck_fa_cnt = cck_fa_cnt;
 529         dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
 530         if (cck_enable)
 531                 dm_info->total_fa_cnt += cck_fa_cnt;
 532         dm_info->total_fa_cnt = ofdm_fa_cnt;
 533
 534         crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK);
 535         dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
 536         dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
 537
 538         crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM);
 539         dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
 540         dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
 541
 542         crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT);
 543         dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
 544         dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
 545
 546         crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT);
 547         dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
 548         dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
 549
 550         cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM);
 551         dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt);
 552         dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
 553         if (cck_enable) {
 554                 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK);
 555                 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt);
 556                 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
 557         }
 558
 559         rtw_write32_set(rtwdev, REG_FAS, BIT(17));
 560         rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
 561         rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15));
 562         rtw_write32_set(rtwdev, REG_RXDESC, BIT(15));
 563         rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
 564         rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
 565 }
 566
 567 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev)
 568 {
 569         static int do_iqk_cnt;
 570         struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
 571         u32 rf_reg, iqk_fail_mask;
 572         int counter;
 573         bool reload;
 574
 575         if (rtw_is_assoc(rtwdev))
 576                 para.segment_iqk = 1;
 577
 578         rtw_fw_do_iqk(rtwdev, &para);
 579
 580         for (counter = 0; counter < 300; counter++) {
 581                 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
 582                 if (rf_reg == 0xabcde)
 583                         break;
 584                 msleep(20);
 585         }
 586         rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
 587
 588         reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
 589         iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
 590         rtw_dbg(rtwdev, RTW_DBG_PHY,
 591                 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
 592                 counter, reload, ++do_iqk_cnt, iqk_fail_mask);
 593 }
 594
 595 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev)
 596 {
 597         rtw8821c_do_iqk(rtwdev);
 598 }
 599
 600 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
 601 {
 602         struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 603         u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13};
 604
 605         if (dm_info->min_rssi > 60) {
 606                 new_lvl = 4;
 607                 pd[4] = 0x1d;
 608                 goto set_cck_pd;
 609         }
 610
 611         if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
 612                 return;
 613
 614         dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
 615
 616 set_cck_pd:
 617         dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
 618         rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
 619         rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
 620                          dm_info->cck_pd_default + new_lvl * 2);
 621 }
 622
 623 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = {
 624         {0x0086,
 625          RTW_PWR_CUT_ALL_MSK,
 626          RTW_PWR_INTF_SDIO_MSK,
 627          RTW_PWR_ADDR_SDIO,
 628          RTW_PWR_CMD_WRITE, BIT(0), 0},
 629         {0x0086,
 630          RTW_PWR_CUT_ALL_MSK,
 631          RTW_PWR_INTF_SDIO_MSK,
 632          RTW_PWR_ADDR_SDIO,
 633          RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
 634         {0x004A,
 635          RTW_PWR_CUT_ALL_MSK,
 636          RTW_PWR_INTF_USB_MSK,
 637          RTW_PWR_ADDR_MAC,
 638          RTW_PWR_CMD_WRITE, BIT(0), 0},
 639         {0x0005,
 640          RTW_PWR_CUT_ALL_MSK,
 641          RTW_PWR_INTF_ALL_MSK,
 642          RTW_PWR_ADDR_MAC,
 643          RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
 644         {0x0300,
 645          RTW_PWR_CUT_ALL_MSK,
 646          RTW_PWR_INTF_PCI_MSK,
 647          RTW_PWR_ADDR_MAC,
 648          RTW_PWR_CMD_WRITE, 0xFF, 0},
 649         {0x0301,
 650          RTW_PWR_CUT_ALL_MSK,
 651          RTW_PWR_INTF_PCI_MSK,
 652          RTW_PWR_ADDR_MAC,
 653          RTW_PWR_CMD_WRITE, 0xFF, 0},
 654         {0xFFFF,
 655          RTW_PWR_CUT_ALL_MSK,
 656          RTW_PWR_INTF_ALL_MSK,
 657          0,
 658          RTW_PWR_CMD_END, 0, 0},
 659 };
 660
 661 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = {
 662         {0x0020,
 663          RTW_PWR_CUT_ALL_MSK,
 664          RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
 665          RTW_PWR_ADDR_MAC,
 666          RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
 667         {0x0001,
 668          RTW_PWR_CUT_ALL_MSK,
 669          RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
 670          RTW_PWR_ADDR_MAC,
 671          RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
 672         {0x0000,
 673          RTW_PWR_CUT_ALL_MSK,
 674          RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
 675          RTW_PWR_ADDR_MAC,
 676          RTW_PWR_CMD_WRITE, BIT(5), 0},
 677         {0x0005,
 678          RTW_PWR_CUT_ALL_MSK,
 679          RTW_PWR_INTF_ALL_MSK,
 680          RTW_PWR_ADDR_MAC,
 681          RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
 682         {0x0075,
 683          RTW_PWR_CUT_ALL_MSK,
 684          RTW_PWR_INTF_PCI_MSK,
 685          RTW_PWR_ADDR_MAC,
 686          RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
 687         {0x0006,
 688          RTW_PWR_CUT_ALL_MSK,
 689          RTW_PWR_INTF_ALL_MSK,
 690          RTW_PWR_ADDR_MAC,
 691          RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
 692         {0x0075,
 693          RTW_PWR_CUT_ALL_MSK,
 694          RTW_PWR_INTF_PCI_MSK,
 695          RTW_PWR_ADDR_MAC,
 696          RTW_PWR_CMD_WRITE, BIT(0), 0},
 697         {0x0006,
 698          RTW_PWR_CUT_ALL_MSK,
 699          RTW_PWR_INTF_ALL_MSK,
 700          RTW_PWR_ADDR_MAC,
 701          RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
 702         {0x0005,
 703          RTW_PWR_CUT_ALL_MSK,
 704          RTW_PWR_INTF_ALL_MSK,
 705          RTW_PWR_ADDR_MAC,
 706          RTW_PWR_CMD_WRITE, BIT(7), 0},
 707         {0x0005,
 708          RTW_PWR_CUT_ALL_MSK,
 709          RTW_PWR_INTF_ALL_MSK,
 710          RTW_PWR_ADDR_MAC,
 711          RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
 712         {0x10C3,
 713          RTW_PWR_CUT_ALL_MSK,
 714          RTW_PWR_INTF_USB_MSK,
 715          RTW_PWR_ADDR_MAC,
 716          RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
 717         {0x0005,
 718          RTW_PWR_CUT_ALL_MSK,
 719          RTW_PWR_INTF_ALL_MSK,
 720          RTW_PWR_ADDR_MAC,
 721          RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
 722         {0x0005,
 723          RTW_PWR_CUT_ALL_MSK,
 724          RTW_PWR_INTF_ALL_MSK,
 725          RTW_PWR_ADDR_MAC,
 726          RTW_PWR_CMD_POLLING, BIT(0), 0},
 727         {0x0020,
 728          RTW_PWR_CUT_ALL_MSK,
 729          RTW_PWR_INTF_ALL_MSK,
 730          RTW_PWR_ADDR_MAC,
 731          RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
 732         {0x0074,
 733          RTW_PWR_CUT_ALL_MSK,
 734          RTW_PWR_INTF_PCI_MSK,
 735          RTW_PWR_ADDR_MAC,
 736          RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
 737         {0x0022,
 738          RTW_PWR_CUT_ALL_MSK,
 739          RTW_PWR_INTF_PCI_MSK,
 740          RTW_PWR_ADDR_MAC,
 741          RTW_PWR_CMD_WRITE, BIT(1), 0},
 742         {0x0062,
 743          RTW_PWR_CUT_ALL_MSK,
 744          RTW_PWR_INTF_PCI_MSK,
 745          RTW_PWR_ADDR_MAC,
 746          RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
 747          (BIT(7) | BIT(6) | BIT(5))},
 748         {0x0061,
 749          RTW_PWR_CUT_ALL_MSK,
 750          RTW_PWR_INTF_PCI_MSK,
 751          RTW_PWR_ADDR_MAC,
 752          RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
 753         {0x007C,
 754          RTW_PWR_CUT_ALL_MSK,
 755          RTW_PWR_INTF_ALL_MSK,
 756          RTW_PWR_ADDR_MAC,
 757          RTW_PWR_CMD_WRITE, BIT(1), 0},
 758         {0xFFFF,
 759          RTW_PWR_CUT_ALL_MSK,
 760          RTW_PWR_INTF_ALL_MSK,
 761          0,
 762          RTW_PWR_CMD_END, 0, 0},
 763 };
 764
 765 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = {
 766         {0x0093,
 767          RTW_PWR_CUT_ALL_MSK,
 768          RTW_PWR_INTF_ALL_MSK,
 769          RTW_PWR_ADDR_MAC,
 770          RTW_PWR_CMD_WRITE, BIT(3), 0},
 771         {0x001F,
 772          RTW_PWR_CUT_ALL_MSK,
 773          RTW_PWR_INTF_ALL_MSK,
 774          RTW_PWR_ADDR_MAC,
 775          RTW_PWR_CMD_WRITE, 0xFF, 0},
 776         {0x0049,
 777          RTW_PWR_CUT_ALL_MSK,
 778          RTW_PWR_INTF_ALL_MSK,
 779          RTW_PWR_ADDR_MAC,
 780          RTW_PWR_CMD_WRITE, BIT(1), 0},
 781         {0x0006,
 782          RTW_PWR_CUT_ALL_MSK,
 783          RTW_PWR_INTF_ALL_MSK,
 784          RTW_PWR_ADDR_MAC,
 785          RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
 786         {0x0002,
 787          RTW_PWR_CUT_ALL_MSK,
 788          RTW_PWR_INTF_ALL_MSK,
 789          RTW_PWR_ADDR_MAC,
 790          RTW_PWR_CMD_WRITE, BIT(1), 0},
 791         {0x10C3,
 792          RTW_PWR_CUT_ALL_MSK,
 793          RTW_PWR_INTF_USB_MSK,
 794          RTW_PWR_ADDR_MAC,
 795          RTW_PWR_CMD_WRITE, BIT(0), 0},
 796         {0x0005,
 797          RTW_PWR_CUT_ALL_MSK,
 798          RTW_PWR_INTF_ALL_MSK,
 799          RTW_PWR_ADDR_MAC,
 800          RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
 801         {0x0005,
 802          RTW_PWR_CUT_ALL_MSK,
 803          RTW_PWR_INTF_ALL_MSK,
 804          RTW_PWR_ADDR_MAC,
 805          RTW_PWR_CMD_POLLING, BIT(1), 0},
 806         {0x0020,
 807          RTW_PWR_CUT_ALL_MSK,
 808          RTW_PWR_INTF_ALL_MSK,
 809          RTW_PWR_ADDR_MAC,
 810          RTW_PWR_CMD_WRITE, BIT(3), 0},
 811         {0x0000,
 812          RTW_PWR_CUT_ALL_MSK,
 813          RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
 814          RTW_PWR_ADDR_MAC,
 815          RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
 816         {0xFFFF,
 817          RTW_PWR_CUT_ALL_MSK,
 818          RTW_PWR_INTF_ALL_MSK,
 819          0,
 820          RTW_PWR_CMD_END, 0, 0},
 821 };
 822
 823 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = {
 824         {0x0007,
 825          RTW_PWR_CUT_ALL_MSK,
 826          RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
 827          RTW_PWR_ADDR_MAC,
 828          RTW_PWR_CMD_WRITE, 0xFF, 0x20},
 829         {0x0067,
 830          RTW_PWR_CUT_ALL_MSK,
 831          RTW_PWR_INTF_ALL_MSK,
 832          RTW_PWR_ADDR_MAC,
 833          RTW_PWR_CMD_WRITE, BIT(5), 0},
 834         {0x0005,
 835          RTW_PWR_CUT_ALL_MSK,
 836          RTW_PWR_INTF_PCI_MSK,
 837          RTW_PWR_ADDR_MAC,
 838          RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
 839         {0x004A,
 840          RTW_PWR_CUT_ALL_MSK,
 841          RTW_PWR_INTF_USB_MSK,
 842          RTW_PWR_ADDR_MAC,
 843          RTW_PWR_CMD_WRITE, BIT(0), 0},
 844         {0x0067,
 845          RTW_PWR_CUT_ALL_MSK,
 846          RTW_PWR_INTF_SDIO_MSK,
 847          RTW_PWR_ADDR_MAC,
 848          RTW_PWR_CMD_WRITE, BIT(5), 0},
 849         {0x0067,
 850          RTW_PWR_CUT_ALL_MSK,
 851          RTW_PWR_INTF_SDIO_MSK,
 852          RTW_PWR_ADDR_MAC,
 853          RTW_PWR_CMD_WRITE, BIT(4), 0},
 854         {0x004F,
 855          RTW_PWR_CUT_ALL_MSK,
 856          RTW_PWR_INTF_SDIO_MSK,
 857          RTW_PWR_ADDR_MAC,
 858          RTW_PWR_CMD_WRITE, BIT(0), 0},
 859         {0x0067,
 860          RTW_PWR_CUT_ALL_MSK,
 861          RTW_PWR_INTF_SDIO_MSK,
 862          RTW_PWR_ADDR_MAC,
 863          RTW_PWR_CMD_WRITE, BIT(1), 0},
 864         {0x0046,
 865          RTW_PWR_CUT_ALL_MSK,
 866          RTW_PWR_INTF_SDIO_MSK,
 867          RTW_PWR_ADDR_MAC,
 868          RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
 869         {0x0067,
 870          RTW_PWR_CUT_ALL_MSK,
 871          RTW_PWR_INTF_SDIO_MSK,
 872          RTW_PWR_ADDR_MAC,
 873          RTW_PWR_CMD_WRITE, BIT(2), 0},
 874         {0x0046,
 875          RTW_PWR_CUT_ALL_MSK,
 876          RTW_PWR_INTF_SDIO_MSK,
 877          RTW_PWR_ADDR_MAC,
 878          RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
 879         {0x0062,
 880          RTW_PWR_CUT_ALL_MSK,
 881          RTW_PWR_INTF_SDIO_MSK,
 882          RTW_PWR_ADDR_MAC,
 883          RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
 884         {0x0081,
 885          RTW_PWR_CUT_ALL_MSK,
 886          RTW_PWR_INTF_ALL_MSK,
 887          RTW_PWR_ADDR_MAC,
 888          RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
 889         {0x0005,
 890          RTW_PWR_CUT_ALL_MSK,
 891          RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
 892          RTW_PWR_ADDR_MAC,
 893          RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
 894         {0x0086,
 895          RTW_PWR_CUT_ALL_MSK,
 896          RTW_PWR_INTF_SDIO_MSK,
 897          RTW_PWR_ADDR_SDIO,
 898          RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
 899         {0x0086,
 900          RTW_PWR_CUT_ALL_MSK,
 901          RTW_PWR_INTF_SDIO_MSK,
 902          RTW_PWR_ADDR_SDIO,
 903          RTW_PWR_CMD_POLLING, BIT(1), 0},
 904         {0x0090,
 905          RTW_PWR_CUT_ALL_MSK,
 906          RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK,
 907          RTW_PWR_ADDR_MAC,
 908          RTW_PWR_CMD_WRITE, BIT(1), 0},
 909         {0x0044,
 910          RTW_PWR_CUT_ALL_MSK,
 911          RTW_PWR_INTF_SDIO_MSK,
 912          RTW_PWR_ADDR_SDIO,
 913          RTW_PWR_CMD_WRITE, 0xFF, 0},
 914         {0x0040,
 915          RTW_PWR_CUT_ALL_MSK,
 916          RTW_PWR_INTF_SDIO_MSK,
 917          RTW_PWR_ADDR_SDIO,
 918          RTW_PWR_CMD_WRITE, 0xFF, 0x90},
 919         {0x0041,
 920          RTW_PWR_CUT_ALL_MSK,
 921          RTW_PWR_INTF_SDIO_MSK,
 922          RTW_PWR_ADDR_SDIO,
 923          RTW_PWR_CMD_WRITE, 0xFF, 0x00},
 924         {0x0042,
 925          RTW_PWR_CUT_ALL_MSK,
 926          RTW_PWR_INTF_SDIO_MSK,
 927          RTW_PWR_ADDR_SDIO,
 928          RTW_PWR_CMD_WRITE, 0xFF, 0x04},
 929         {0xFFFF,
 930          RTW_PWR_CUT_ALL_MSK,
 931          RTW_PWR_INTF_ALL_MSK,
 932          0,
 933          RTW_PWR_CMD_END, 0, 0},
 934 };
 935
 936 static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = {
 937         trans_carddis_to_cardemu_8821c,
 938         trans_cardemu_to_act_8821c,
 939         NULL
 940 };
 941
 942 static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = {
 943         trans_act_to_cardemu_8821c,
 944         trans_cardemu_to_carddis_8821c,
 945         NULL
 946 };
 947
 948 static const struct rtw_intf_phy_para usb2_param_8821c[] = {
 949         {0xFFFF, 0x00,
 950          RTW_IP_SEL_PHY,
 951          RTW_INTF_PHY_CUT_ALL,
 952          RTW_INTF_PHY_PLATFORM_ALL},
 953 };
 954
 955 static const struct rtw_intf_phy_para usb3_param_8821c[] = {
 956         {0xFFFF, 0x0000,
 957          RTW_IP_SEL_PHY,
 958          RTW_INTF_PHY_CUT_ALL,
 959          RTW_INTF_PHY_PLATFORM_ALL},
 960 };
 961
 962 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = {
 963         {0x0009, 0x6380,
 964          RTW_IP_SEL_PHY,
 965          RTW_INTF_PHY_CUT_ALL,
 966          RTW_INTF_PHY_PLATFORM_ALL},
 967         {0xFFFF, 0x0000,
 968          RTW_IP_SEL_PHY,
 969          RTW_INTF_PHY_CUT_ALL,
 970          RTW_INTF_PHY_PLATFORM_ALL},
 971 };
 972
 973 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = {
 974         {0xFFFF, 0x0000,
 975          RTW_IP_SEL_PHY,
 976          RTW_INTF_PHY_CUT_ALL,
 977          RTW_INTF_PHY_PLATFORM_ALL},
 978 };
 979
 980 static const struct rtw_intf_phy_para_table phy_para_table_8821c = {
 981         .usb2_para      = usb2_param_8821c,
 982         .usb3_para      = usb3_param_8821c,
 983         .gen1_para      = pcie_gen1_param_8821c,
 984         .gen2_para      = pcie_gen2_param_8821c,
 985         .n_usb2_para    = ARRAY_SIZE(usb2_param_8821c),
 986         .n_usb3_para    = ARRAY_SIZE(usb2_param_8821c),
 987         .n_gen1_para    = ARRAY_SIZE(pcie_gen1_param_8821c),
 988         .n_gen2_para    = ARRAY_SIZE(pcie_gen2_param_8821c),
 989 };
 990
 991 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = {
 992         [0] = RTW_DEF_RFE(8821c, 0, 0),
 993 };
 994
 995 static struct rtw_hw_reg rtw8821c_dig[] = {
 996         [0] = { .addr = 0xc50, .mask = 0x7f },
 997 };
 998
 999 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = {
1000         .ctrl = LTECOEX_ACCESS_CTRL,
1001         .wdata = LTECOEX_WRITE_DATA,
1002         .rdata = LTECOEX_READ_DATA,
1003 };
1004
1005 static struct rtw_page_table page_table_8821c[] = {
1006         /* not sure what [0] stands for */
1007         {16, 16, 16, 14, 1},
1008         {16, 16, 16, 14, 1},
1009         {16, 16, 0, 0, 1},
1010         {16, 16, 16, 0, 1},
1011         {16, 16, 16, 14, 1},
1012 };
1013
1014 static struct rtw_rqpn rqpn_table_8821c[] = {
1015         /* not sure what [0] stands for */
1016         {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1017          RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1018          RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1019         {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1020          RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1021          RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1022         {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1023          RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
1024          RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1025         {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1026          RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1027          RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1028         {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1029          RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1030          RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1031 };
1032
1033 static struct rtw_prioq_addrs prioq_addrs_8821c = {
1034         .prio[RTW_DMA_MAPPING_EXTRA] = {
1035                 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
1036         },
1037         .prio[RTW_DMA_MAPPING_LOW] = {
1038                 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
1039         },
1040         .prio[RTW_DMA_MAPPING_NORMAL] = {
1041                 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
1042         },
1043         .prio[RTW_DMA_MAPPING_HIGH] = {
1044                 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
1045         },
1046         .wsize = true,
1047 };
1048
1049 static struct rtw_chip_ops rtw8821c_ops = {
1050         .phy_set_param          = rtw8821c_phy_set_param,
1051         .read_efuse             = rtw8821c_read_efuse,
1052         .query_rx_desc          = rtw8821c_query_rx_desc,
1053         .set_channel            = rtw8821c_set_channel,
1054         .mac_init               = rtw8821c_mac_init,
1055         .read_rf                = rtw_phy_read_rf,
1056         .write_rf               = rtw_phy_write_rf_reg_sipi,
1057         .set_antenna            = NULL,
1058         .set_tx_power_index     = rtw8821c_set_tx_power_index,
1059         .cfg_ldo25              = rtw8821c_cfg_ldo25,
1060         .false_alarm_statistics = rtw8821c_false_alarm_statistics,
1061         .phy_calibration        = rtw8821c_phy_calibration,
1062         .cck_pd_set             = rtw8821c_phy_cck_pd_set,
1063 };
1064
1065 struct rtw_chip_info rtw8821c_hw_spec = {
1066         .ops = &rtw8821c_ops,
1067         .id = RTW_CHIP_TYPE_8821C,
1068         .fw_name = "rtw88/rtw8821c_fw.bin",
1069         .wlan_cpu = RTW_WCPU_11AC,
1070         .tx_pkt_desc_sz = 48,
1071         .tx_buf_desc_sz = 16,
1072         .rx_pkt_desc_sz = 24,
1073         .rx_buf_desc_sz = 8,
1074         .phy_efuse_size = 512,
1075         .log_efuse_size = 512,
1076         .ptct_efuse_size = 96,
1077         .txff_size = 65536,
1078         .rxff_size = 16384,
1079         .txgi_factor = 1,
1080         .is_pwr_by_rate_dec = true,
1081         .max_power_index = 0x3f,
1082         .csi_buf_pg_num = 0,
1083         .band = RTW_BAND_2G | RTW_BAND_5G,
1084         .page_size = 128,
1085         .dig_min = 0x1c,
1086         .ht_supported = true,
1087         .vht_supported = true,
1088         .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
1089         .sys_func_en = 0xD8,
1090         .pwr_on_seq = card_enable_flow_8821c,
1091         .pwr_off_seq = card_disable_flow_8821c,
1092         .page_table = page_table_8821c,
1093         .rqpn_table = rqpn_table_8821c,
1094         .prioq_addrs = &prioq_addrs_8821c,
1095         .intf_table = &phy_para_table_8821c,
1096         .dig = rtw8821c_dig,
1097         .rf_base_addr = {0x2800, 0x2c00},
1098         .rf_sipi_addr = {0xc90, 0xe90},
1099         .ltecoex_addr = &rtw8821c_ltecoex_addr,
1100         .mac_tbl = &rtw8821c_mac_tbl,
1101         .agc_tbl = &rtw8821c_agc_tbl,
1102         .bb_tbl = &rtw8821c_bb_tbl,
1103         .rf_tbl = {&rtw8821c_rf_a_tbl},
1104         .rfe_defs = rtw8821c_rfe_defs,
1105         .rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs),
1106         .rx_ldpc = false,
1107 };
1108 EXPORT_SYMBOL(rtw8821c_hw_spec);
1109
1110 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin");
1111
1112 MODULE_AUTHOR("Realtek Corporation");
1113 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver");
1114 MODULE_LICENSE("Dual BSD/GPL");