1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
5 #ifndef __RTW_REG_DEF_H__
6 #define __RTW_REG_DEF_H__
8 #define REG_SYS_FUNC_EN 0x0002
9 #define BIT_FEN_EN_25_1 BIT(13)
10 #define BIT_FEN_ELDR BIT(12)
11 #define BIT_FEN_CPUEN BIT(2)
12 #define BIT_FEN_BB_GLB_RST BIT(1)
13 #define BIT_FEN_BB_RSTB BIT(0)
14 #define BIT_R_DIS_PRST BIT(6)
15 #define BIT_WLOCK_1C_B6 BIT(5)
16 #define REG_SYS_PW_CTRL 0x0004
17 #define BIT_PFM_WOWL BIT(3)
18 #define REG_SYS_CLK_CTRL 0x0008
19 #define BIT_CPU_CLK_EN BIT(14)
21 #define REG_SYS_CLKR 0x0008
22 #define BIT_ANA8M BIT(1)
23 #define BIT_WAKEPAD_EN BIT(3)
24 #define BIT_LOADER_CLK_EN BIT(5)
26 #define REG_RSV_CTRL 0x001C
27 #define DISABLE_PI 0x3
29 #define BITS_RFC_DIRECT (BIT(31) | BIT(30))
30 #define BIT_WLMCU_IOIF BIT(0)
31 #define REG_RF_CTRL 0x001F
32 #define BIT_RF_SDM_RSTB BIT(2)
33 #define BIT_RF_RSTB BIT(1)
34 #define BIT_RF_EN BIT(0)
36 #define REG_AFE_CTRL1 0x0024
37 #define BIT_MAC_CLK_SEL (BIT(20) | BIT(21))
38 #define REG_EFUSE_CTRL 0x0030
39 #define BIT_EF_FLAG BIT(31)
40 #define BIT_SHIFT_EF_ADDR 8
41 #define BIT_MASK_EF_ADDR 0x3ff
42 #define BIT_MASK_EF_DATA 0xff
43 #define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)
46 #define REG_AFE_CTRL3 0x2c
47 #define BIT_MASK_XTAL 0x00FFF000
48 #define BIT_XTAL_GMP_BIT4 BIT(28)
50 #define REG_LDO_EFUSE_CTRL 0x0034
51 #define BIT_MASK_EFUSE_BANK_SEL (BIT(8) | BIT(9))
53 #define BIT_LDO25_VOLTAGE_V25 0x03
54 #define BIT_MASK_LDO25_VOLTAGE GENMASK(6, 4)
55 #define BIT_SHIFT_LDO25_VOLTAGE 4
56 #define BIT_LDO25_EN BIT(7)
58 #define REG_GPIO_MUXCFG 0x0040
59 #define BIT_FSPI_EN BIT(19)
60 #define BIT_EN_SIC BIT(12)
61 #define BIT_BT_AOD_GPIO3 BIT(9)
62 #define BIT_BT_PTA_EN BIT(5)
63 #define BIT_WLRFE_4_5_EN BIT(2)
65 #define REG_LED_CFG 0x004C
66 #define BIT_LNAON_SEL_EN BIT(26)
67 #define BIT_PAPE_SEL_EN BIT(25)
68 #define BIT_DPDT_WL_SEL BIT(24)
69 #define BIT_DPDT_SEL_EN BIT(23)
70 #define REG_LEDCFG2 0x004E
71 #define REG_PAD_CTRL1 0x0064
72 #define BIT_BT_BTG_SEL BIT(31)
73 #define BIT_PAPE_WLBT_SEL BIT(29)
74 #define BIT_LNAON_WLBT_SEL BIT(28)
75 #define BIT_BTGP_JTAG_EN BIT(24)
76 #define BIT_BTGP_SPI_EN BIT(20)
77 #define BIT_LED1DIS BIT(15)
78 #define BIT_SW_DPDT_SEL_DATA BIT(0)
79 #define REG_WL_BT_PWR_CTRL 0x0068
80 #define BIT_BT_FUNC_EN BIT(18)
81 #define BIT_BT_DIG_CLK_EN BIT(8)
82 #define REG_SYS_SDIO_CTRL 0x0070
83 #define BIT_DBG_GNT_WL_BT BIT(27)
84 #define BIT_LTE_MUX_CTRL_PATH BIT(26)
85 #define REG_HCI_OPT_CTRL 0x0074
86 #define BIT_USB_SUS_DIS BIT(8)
88 #define REG_AFE_CTRL_4 0x0078
89 #define BIT_CK320M_AFE_EN BIT(4)
90 #define BIT_EN_SYN BIT(15)
92 #define REG_LDO_SWR_CTRL 0x007C
95 #define BIT_XTA1 BIT(29)
96 #define BIT_XTA0 BIT(28)
98 #define REG_MCUFW_CTRL 0x0080
99 #define BIT_ANA_PORT_EN BIT(22)
100 #define BIT_MAC_PORT_EN BIT(21)
101 #define BIT_BOOT_FSPI_EN BIT(20)
102 #define BIT_ROM_DLEN BIT(19)
103 #define BIT_ROM_PGE GENMASK(18, 16) /* legacy only */
104 #define BIT_SHIFT_ROM_PGE 16
105 #define BIT_FW_INIT_RDY BIT(15)
106 #define BIT_FW_DW_RDY BIT(14)
107 #define BIT_RPWM_TOGGLE BIT(7)
108 #define BIT_RAM_DL_SEL BIT(7) /* legacy only */
109 #define BIT_DMEM_CHKSUM_OK BIT(6)
110 #define BIT_WINTINI_RDY BIT(6) /* legacy only */
111 #define BIT_DMEM_DW_OK BIT(5)
112 #define BIT_IMEM_CHKSUM_OK BIT(4)
113 #define BIT_IMEM_DW_OK BIT(3)
114 #define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2)
115 #define BIT_FWDL_CHK_RPT BIT(2) /* legacy only */
116 #define BIT_MCUFWDL_RDY BIT(1) /* legacy only */
117 #define BIT_MCUFWDL_EN BIT(0)
118 #define BIT_CHECK_SUM_OK (BIT(4) | BIT(6))
119 #define FW_READY (BIT_FW_INIT_RDY | BIT_FW_DW_RDY | \
120 BIT_IMEM_DW_OK | BIT_DMEM_DW_OK | \
122 #define FW_READY_LEGACY (BIT_MCUFWDL_RDY | BIT_FWDL_CHK_RPT | \
123 BIT_WINTINI_RDY | BIT_RAM_DL_SEL)
124 #define FW_READY_MASK 0xffff
126 #define REG_EFUSE_ACCESS 0x00CF
127 #define EFUSE_ACCESS_ON 0x69
128 #define EFUSE_ACCESS_OFF 0x00
130 #define REG_WLRF1 0x00EC
131 #define REG_WIFI_BT_INFO 0x00AA
132 #define BIT_BT_INT_EN BIT(15)
133 #define REG_SYS_CFG1 0x00F0
134 #define BIT_RTL_ID BIT(23)
135 #define BIT_LDO BIT(24)
136 #define BIT_RF_TYPE_ID BIT(27)
137 #define BIT_SHIFT_VENDOR_ID 16
138 #define BIT_MASK_VENDOR_ID 0xf
139 #define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID)
140 #define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID)
141 #define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID))
142 #define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID)
143 #define BIT_SHIFT_CHIP_VER 12
144 #define BIT_MASK_CHIP_VER 0xf
145 #define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER)
146 #define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER)
147 #define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER))
148 #define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER)
149 #define REG_SYS_STATUS1 0x00F4
150 #define REG_SYS_STATUS2 0x00F8
151 #define REG_SYS_CFG2 0x00FC
152 #define REG_WLRF1 0x00EC
153 #define BIT_WLRF1_BBRF_EN (BIT(24) | BIT(25) | BIT(26))
154 #define REG_CR 0x0100
155 #define BIT_32K_CAL_TMR_EN BIT(10)
156 #define BIT_MAC_SEC_EN BIT(9)
157 #define BIT_ENSWBCN BIT(8)
158 #define BIT_MACRXEN BIT(7)
159 #define BIT_MACTXEN BIT(6)
160 #define BIT_SCHEDULE_EN BIT(5)
161 #define BIT_PROTOCOL_EN BIT(4)
162 #define BIT_RXDMA_EN BIT(3)
163 #define BIT_TXDMA_EN BIT(2)
164 #define BIT_HCI_RXDMA_EN BIT(1)
165 #define BIT_HCI_TXDMA_EN BIT(0)
166 #define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \
167 BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \
168 BIT_MACTXEN | BIT_MACRXEN)
169 #define BIT_SHIFT_TXDMA_VOQ_MAP 4
170 #define BIT_MASK_TXDMA_VOQ_MAP 0x3
171 #define BIT_TXDMA_VOQ_MAP(x) \
172 (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP)
173 #define BIT_SHIFT_TXDMA_VIQ_MAP 6
174 #define BIT_MASK_TXDMA_VIQ_MAP 0x3
175 #define BIT_TXDMA_VIQ_MAP(x) \
176 (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP)
177 #define REG_TXDMA_PQ_MAP 0x010C
178 #define BIT_SHIFT_TXDMA_BEQ_MAP 8
179 #define BIT_MASK_TXDMA_BEQ_MAP 0x3
180 #define BIT_TXDMA_BEQ_MAP(x) \
181 (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP)
182 #define BIT_SHIFT_TXDMA_BKQ_MAP 10
183 #define BIT_MASK_TXDMA_BKQ_MAP 0x3
184 #define BIT_TXDMA_BKQ_MAP(x) \
185 (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP)
186 #define BIT_SHIFT_TXDMA_MGQ_MAP 12
187 #define BIT_MASK_TXDMA_MGQ_MAP 0x3
188 #define BIT_TXDMA_MGQ_MAP(x) \
189 (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP)
190 #define BIT_SHIFT_TXDMA_HIQ_MAP 14
191 #define BIT_MASK_TXDMA_HIQ_MAP 0x3
192 #define BIT_TXDMA_HIQ_MAP(x) \
193 (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP)
194 #define BIT_SHIFT_TXSC_40M 4
195 #define BIT_MASK_TXSC_40M 0xf
196 #define BIT_TXSC_40M(x) \
197 (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M)
198 #define BIT_SHIFT_TXSC_20M 0
199 #define BIT_MASK_TXSC_20M 0xf
200 #define BIT_TXSC_20M(x) \
201 (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M)
202 #define BIT_SHIFT_MAC_CLK_SEL 20
203 #define MAC_CLK_HW_DEF_80M 0
204 #define MAC_CLK_HW_DEF_40M 1
205 #define MAC_CLK_HW_DEF_20M 2
206 #define MAC_CLK_SPEED 80
208 #define REG_CR 0x0100
209 #define REG_TRXFF_BNDY 0x0114
210 #define REG_RXFF_BNDY 0x011C
211 #define REG_FE1IMR 0x0120
212 #define BIT_FS_RXDONE BIT(16)
213 #define REG_PKTBUF_DBG_CTRL 0x0140
214 #define REG_C2HEVT 0x01A0
215 #define REG_MCUTST_1 0x01C0
216 #define REG_MCUTST_II 0x01C4
217 #define REG_WOWLAN_WAKE_REASON 0x01C7
218 #define REG_HMETFR 0x01CC
219 #define REG_HMEBOX0 0x01D0
220 #define REG_HMEBOX1 0x01D4
221 #define REG_HMEBOX2 0x01D8
222 #define REG_HMEBOX3 0x01DC
223 #define REG_HMEBOX0_EX 0x01F0
224 #define REG_HMEBOX1_EX 0x01F4
225 #define REG_HMEBOX2_EX 0x01F8
226 #define REG_HMEBOX3_EX 0x01FC
228 #define REG_RQPN 0x0200
229 #define BIT_MASK_HPQ 0xff
230 #define BIT_SHIFT_HPQ 0
231 #define BIT_RQPN_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ)
232 #define BIT_MASK_LPQ 0xff
233 #define BIT_SHIFT_LPQ 8
234 #define BIT_RQPN_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ)
235 #define BIT_MASK_PUBQ 0xff
236 #define BIT_SHIFT_PUBQ 16
237 #define BIT_RQPN_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ)
238 #define BIT_RQPN_HLP(h, l, p) (BIT_LD_RQPN | BIT_RQPN_HPQ(h) | \
239 BIT_RQPN_LPQ(l) | BIT_RQPN_PUBQ(p))
241 #define REG_FIFOPAGE_CTRL_2 0x0204
242 #define BIT_BCN_VALID_V1 BIT(15)
243 #define BIT_MASK_BCN_HEAD_1_V1 0xfff
244 #define REG_AUTO_LLT_V1 0x0208
245 #define BIT_AUTO_INIT_LLT_V1 BIT(0)
246 #define REG_DWBCN0_CTRL 0x0208
247 #define BIT_BCN_VALID BIT(16)
248 #define REG_TXDMA_OFFSET_CHK 0x020C
249 #define BIT_DROP_DATA_EN BIT(9)
250 #define REG_TXDMA_STATUS 0x0210
251 #define BTI_PAGE_OVF BIT(2)
253 #define REG_RQPN_NPQ 0x0214
254 #define BIT_MASK_NPQ 0xff
255 #define BIT_SHIFT_NPQ 0
256 #define BIT_MASK_EPQ 0xff
257 #define BIT_SHIFT_EPQ 16
258 #define BIT_RQPN_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ)
259 #define BIT_RQPN_EPQ(x) (((x) & BIT_MASK_EPQ) << BIT_SHIFT_EPQ)
260 #define BIT_RQPN_NE(n, e) (BIT_RQPN_NPQ(n) | BIT_RQPN_EPQ(e))
262 #define REG_AUTO_LLT 0x0224
263 #define BIT_AUTO_INIT_LLT BIT(16)
264 #define REG_RQPN_CTRL_1 0x0228
265 #define REG_RQPN_CTRL_2 0x022C
266 #define BIT_LD_RQPN BIT(31)
267 #define REG_FIFOPAGE_INFO_1 0x0230
268 #define REG_FIFOPAGE_INFO_2 0x0234
269 #define REG_FIFOPAGE_INFO_3 0x0238
270 #define REG_FIFOPAGE_INFO_4 0x023C
271 #define REG_FIFOPAGE_INFO_5 0x0240
272 #define REG_H2C_HEAD 0x0244
273 #define REG_H2C_TAIL 0x0248
274 #define REG_H2C_READ_ADDR 0x024C
275 #define REG_H2C_INFO 0x0254
276 #define REG_RXPKT_NUM 0x0284
277 #define BIT_RXDMA_REQ BIT(19)
278 #define BIT_RW_RELEASE BIT(18)
279 #define BIT_RXDMA_IDLE BIT(17)
280 #define REG_RXPKTNUM 0x02B0
282 #define REG_INT_MIG 0x0304
283 #define REG_HCI_MIX_CFG 0x03FC
284 #define BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK BIT(26)
286 #define REG_BCNQ_INFO 0x0418
287 #define BIT_MGQ_CPU_EMPTY BIT(24)
288 #define REG_FWHW_TXQ_CTRL 0x0420
289 #define BIT_EN_BCNQ_DL BIT(22)
290 #define BIT_EN_WR_FREE_TAIL BIT(20)
291 #define REG_HWSEQ_CTRL 0x0423
293 #define REG_BCNQ_BDNY_V1 0x0424
294 #define REG_BCNQ_BDNY 0x0424
295 #define REG_MGQ_BDNY 0x0425
296 #define REG_LIFETIME_EN 0x0426
297 #define BIT_BA_PARSER_EN BIT(5)
298 #define REG_SPEC_SIFS 0x0428
299 #define REG_RETRY_LIMIT 0x042a
300 #define REG_DARFRC 0x0430
301 #define REG_DARFRCH 0x0434
302 #define REG_RARFRCH 0x043C
303 #define REG_ARFR0 0x0444
304 #define REG_ARFRH0 0x0448
305 #define REG_ARFR1_V1 0x044C
306 #define REG_ARFRH1_V1 0x0450
307 #define REG_CCK_CHECK 0x0454
308 #define BIT_CHECK_CCK_EN BIT(7)
309 #define REG_AMPDU_MAX_TIME_V1 0x0455
310 #define REG_BCNQ1_BDNY_V1 0x0456
311 #define REG_AMPDU_MAX_TIME 0x0456
312 #define REG_WMAC_LBK_BF_HD 0x045D
313 #define REG_TX_HANG_CTRL 0x045E
314 #define BIT_EN_GNT_BT_AWAKE BIT(3)
315 #define BIT_EN_EOF_V1 BIT(2)
316 #define REG_DATA_SC 0x0483
317 #define REG_ARFR4 0x049C
318 #define BIT_WL_RFK BIT(0)
319 #define REG_ARFRH4 0x04A0
320 #define REG_ARFR5 0x04A4
321 #define REG_ARFRH5 0x04A8
322 #define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
323 #define BIT_PRE_TX_CMD BIT(6)
324 #define REG_QUEUE_CTRL 0x04C6
325 #define BIT_PTA_WL_TX_EN BIT(4)
326 #define BIT_PTA_EDCCA_EN BIT(5)
327 #define REG_SINGLE_AMPDU_CTRL 0x04C7
328 #define BIT_EN_SINGLE_APMDU BIT(7)
329 #define REG_PROT_MODE_CTRL 0x04C8
330 #define REG_MAX_AGGR_NUM 0x04CA
331 #define REG_BAR_MODE_CTRL 0x04CC
332 #define REG_PRECNT_CTRL 0x04E5
333 #define BIT_BTCCA_CTRL (BIT(0) | BIT(1))
334 #define BIT_EN_PRECNT BIT(11)
335 #define REG_DUMMY_PAGE4_V1 0x04FC
337 #define REG_EDCA_VO_PARAM 0x0500
338 #define REG_EDCA_VI_PARAM 0x0504
339 #define REG_EDCA_BE_PARAM 0x0508
340 #define REG_EDCA_BK_PARAM 0x050C
341 #define BIT_MASK_TXOP_LMT GENMASK(26, 16)
342 #define BIT_MASK_CWMAX GENMASK(15, 12)
343 #define BIT_MASK_CWMIN GENMASK(11, 8)
344 #define BIT_MASK_AIFS GENMASK(7, 0)
345 #define REG_PIFS 0x0512
346 #define REG_SIFS 0x0514
347 #define BIT_SHIFT_SIFS_OFDM_CTX 8
348 #define BIT_SHIFT_SIFS_CCK_TRX 16
349 #define BIT_SHIFT_SIFS_OFDM_TRX 24
350 #define REG_AGGR_BREAK_TIME 0x051A
351 #define REG_SLOT 0x051B
352 #define REG_TX_PTCL_CTRL 0x0520
353 #define BIT_SIFS_BK_EN BIT(12)
354 #define REG_TXPAUSE 0x0522
355 #define REG_RD_CTRL 0x0524
356 #define BIT_DIS_TXOP_CFE BIT(10)
357 #define BIT_DIS_LSIG_CFE BIT(9)
358 #define BIT_DIS_STBC_CFE BIT(8)
359 #define REG_TBTT_PROHIBIT 0x0540
360 #define BIT_SHIFT_TBTT_HOLD_TIME_AP 8
361 #define REG_RD_NAV_NXT 0x0544
362 #define REG_NAV_PROT_LEN 0x0546
363 #define REG_BCN_CTRL 0x0550
364 #define BIT_DIS_TSF_UDT BIT(4)
365 #define BIT_EN_BCN_FUNCTION BIT(3)
366 #define BIT_EN_TXBCN_RPT BIT(2)
367 #define REG_BCN_CTRL_CLINT0 0x0551
368 #define REG_DRVERLYINT 0x0558
369 #define REG_BCNDMATIM 0x0559
370 #define REG_ATIMWND 0x055A
371 #define REG_USTIME_TSF 0x055C
372 #define REG_BCN_MAX_ERR 0x055D
373 #define REG_RXTSF_OFFSET_CCK 0x055E
374 #define REG_MISC_CTRL 0x0577
375 #define BIT_EN_FREE_CNT BIT(3)
376 #define BIT_DIS_SECOND_CCA (BIT(0) | BIT(1))
377 #define REG_HIQ_NO_LMT_EN 0x5A7
378 #define BIT_HIQ_NO_LMT_EN_ROOT BIT(0)
379 #define REG_TIMER0_SRC_SEL 0x05B4
380 #define BIT_TSFT_SEL_TIMER0 (BIT(4) | BIT(5) | BIT(6))
382 #define REG_TCR 0x0604
383 #define BIT_PWRMGT_HWDATA_EN BIT(7)
384 #define REG_RCR 0x0608
385 #define BIT_APP_FCS BIT(31)
386 #define BIT_APP_MIC BIT(30)
387 #define BIT_APP_ICV BIT(29)
388 #define BIT_APP_PHYSTS BIT(28)
389 #define BIT_APP_BASSN BIT(27)
390 #define BIT_VHT_DACK BIT(26)
391 #define BIT_TCPOFLD_EN BIT(25)
392 #define BIT_ENMBID BIT(24)
393 #define BIT_LSIGEN BIT(23)
394 #define BIT_MFBEN BIT(22)
395 #define BIT_DISCHKPPDLLEN BIT(21)
396 #define BIT_PKTCTL_DLEN BIT(20)
397 #define BIT_TIM_PARSER_EN BIT(18)
398 #define BIT_BC_MD_EN BIT(17)
399 #define BIT_UC_MD_EN BIT(16)
400 #define BIT_RXSK_PERPKT BIT(15)
401 #define BIT_HTC_LOC_CTRL BIT(14)
402 #define BIT_RPFM_CAM_ENABLE BIT(12)
403 #define BIT_TA_BCN BIT(11)
404 #define BIT_RCR_ADF BIT(11)
405 #define BIT_DISDECMYPKT BIT(10)
406 #define BIT_AICV BIT(9)
407 #define BIT_ACRC32 BIT(8)
408 #define BIT_CBSSID_BCN BIT(7)
409 #define BIT_CBSSID_DATA BIT(6)
410 #define BIT_APWRMGT BIT(5)
411 #define BIT_ADD3 BIT(4)
412 #define BIT_AB BIT(3)
413 #define BIT_AM BIT(2)
414 #define BIT_APM BIT(1)
415 #define BIT_AAP BIT(0)
416 #define REG_RX_PKT_LIMIT 0x060C
417 #define REG_RX_DRVINFO_SZ 0x060F
418 #define BIT_APP_PHYSTS BIT(28)
419 #define REG_MAR 0x0620
420 #define REG_USTIME_EDCA 0x0638
421 #define REG_ACKTO_CCK 0x0639
422 #define REG_MAC_SPEC_SIFS 0x063A
423 #define REG_RESP_SIFS_CCK 0x063C
424 #define REG_RESP_SIFS_OFDM 0x063E
425 #define REG_ACKTO 0x0640
426 #define REG_EIFS 0x0642
427 #define REG_NAV_CTRL 0x0650
428 #define REG_WMAC_TRXPTCL_CTL 0x0668
429 #define BIT_RFMOD (BIT(7) | BIT(8))
430 #define BIT_RFMOD_80M BIT(8)
431 #define BIT_RFMOD_40M BIT(7)
432 #define REG_WMAC_TRXPTCL_CTL_H 0x066C
433 #define REG_WKFMCAM_CMD 0x0698
434 #define BIT_WKFCAM_POLLING_V1 BIT(31)
435 #define BIT_WKFCAM_CLR_V1 BIT(30)
436 #define BIT_WKFCAM_WE BIT(16)
437 #define BIT_SHIFT_WKFCAM_ADDR_V2 8
438 #define BIT_MASK_WKFCAM_ADDR_V2 0xff
439 #define BIT_WKFCAM_ADDR_V2(x) \
440 (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)
441 #define REG_WKFMCAM_RWD 0x069C
442 #define BIT_WKFMCAM_VALID BIT(31)
443 #define BIT_WKFMCAM_BC BIT(26)
444 #define BIT_WKFMCAM_MC BIT(25)
445 #define BIT_WKFMCAM_UC BIT(24)
447 #define REG_RXFLTMAP0 0x06A0
448 #define REG_RXFLTMAP1 0x06A2
449 #define REG_RXFLTMAP2 0x06A4
450 #define REG_RXFLTMAP4 0x068A
451 #define REG_BT_COEX_TABLE0 0x06C0
452 #define REG_BT_COEX_TABLE1 0x06C4
453 #define REG_BT_COEX_BRK_TABLE 0x06C8
454 #define REG_BT_COEX_TABLE_H 0x06CC
455 #define REG_BT_COEX_TABLE_H1 0x06CD
456 #define REG_BT_COEX_TABLE_H2 0x06CE
457 #define REG_BT_COEX_TABLE_H3 0x06CF
458 #define REG_BBPSF_CTRL 0x06DC
460 #define REG_BT_COEX_V2 0x0763
461 #define BIT_GNT_BT_POLARITY BIT(4)
462 #define BIT_LTE_COEX_EN BIT(7)
463 #define REG_BT_STAT_CTRL 0x0778
464 #define REG_BT_TDMA_TIME 0x0790
465 #define REG_LTR_IDLE_LATENCY 0x0798
466 #define REG_LTR_ACTIVE_LATENCY 0x079C
467 #define REG_LTR_CTRL_BASIC 0x07A4
468 #define REG_WMAC_OPTION_FUNCTION 0x07D0
469 #define REG_WMAC_OPTION_FUNCTION_1 0x07D4
471 #define REG_FPGA0_RFMOD 0x0800
472 #define BIT_CCKEN BIT(24)
473 #define BIT_OFDMEN BIT(25)
474 #define REG_RX_GAIN_EN 0x081c
476 #define REG_RFE_CTRL_E 0x0974
477 #define REG_2ND_CCA_CTRL 0x0976
479 #define REG_DIS_DPD 0x0a70
480 #define DIS_DPD_MASK GENMASK(9, 0)
481 #define DIS_DPD_RATE6M BIT(0)
482 #define DIS_DPD_RATE9M BIT(1)
483 #define DIS_DPD_RATEMCS0 BIT(2)
484 #define DIS_DPD_RATEMCS1 BIT(3)
485 #define DIS_DPD_RATEMCS8 BIT(4)
486 #define DIS_DPD_RATEMCS9 BIT(5)
487 #define DIS_DPD_RATEVHT1SS_MCS0 BIT(6)
488 #define DIS_DPD_RATEVHT1SS_MCS1 BIT(7)
489 #define DIS_DPD_RATEVHT2SS_MCS0 BIT(8)
490 #define DIS_DPD_RATEVHT2SS_MCS1 BIT(9)
491 #define DIS_DPD_RATEALL GENMASK(9, 0)
493 #define REG_RFE_CTRL8 0x0cb4
494 #define BIT_MASK_RFE_SEL89 GENMASK(7, 0)
495 #define REG_RFE_INV8 0x0cbd
496 #define BIT_MASK_RFE_INV89 GENMASK(1, 0)
497 #define REG_RFE_INV16 0x0cbe
498 #define BIT_RFE_BUF_EN BIT(3)
500 #define REG_ANAPAR_XTAL_0 0x1040
501 #define REG_CPU_DMEM_CON 0x1080
502 #define BIT_WL_PLATFORM_RST BIT(16)
503 #define BIT_WL_SECURITY_CLK BIT(15)
504 #define BIT_DDMA_EN BIT(8)
506 #define REG_H2C_PKT_READADDR 0x10D0
507 #define REG_H2C_PKT_WRITEADDR 0x10D4
508 #define REG_FW_DBG7 0x10FC
509 #define FW_KEY_MASK 0xffffff00
511 #define REG_CR_EXT 0x1100
513 #define REG_DDMA_CH0SA 0x1200
514 #define REG_DDMA_CH0DA 0x1204
515 #define REG_DDMA_CH0CTRL 0x1208
516 #define BIT_DDMACH0_OWN BIT(31)
517 #define BIT_DDMACH0_CHKSUM_EN BIT(29)
518 #define BIT_DDMACH0_CHKSUM_STS BIT(27)
519 #define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25)
520 #define BIT_DDMACH0_CHKSUM_CONT BIT(24)
521 #define BIT_MASK_DDMACH0_DLEN 0x3ffff
523 #define REG_H2CQ_CSR 0x1330
524 #define BIT_H2CQ_FULL BIT(31)
525 #define REG_FAST_EDCA_VOVI_SETTING 0x1448
526 #define REG_FAST_EDCA_BEBK_SETTING 0x144C
528 #define REG_RXPSF_CTRL 0x1610
529 #define BIT_RXGCK_FIFOTHR_EN BIT(28)
531 #define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26
532 #define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3
533 #define BIT_RXGCK_VHT_FIFOTHR(x) \
534 (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
535 #define BITS_RXGCK_VHT_FIFOTHR \
536 (BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
538 #define BIT_SHIFT_RXGCK_HT_FIFOTHR 24
539 #define BIT_MASK_RXGCK_HT_FIFOTHR 0x3
540 #define BIT_RXGCK_HT_FIFOTHR(x) \
541 (((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR)
542 #define BITS_RXGCK_HT_FIFOTHR \
543 (BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR)
545 #define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22
546 #define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3
547 #define BIT_RXGCK_OFDM_FIFOTHR(x) \
548 (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
549 #define BITS_RXGCK_OFDM_FIFOTHR \
550 (BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
552 #define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20
553 #define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3
554 #define BIT_RXGCK_CCK_FIFOTHR(x) \
555 (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
556 #define BITS_RXGCK_CCK_FIFOTHR \
557 (BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
559 #define BIT_RXGCK_OFDMCCA_EN BIT(16)
561 #define BIT_SHIFT_RXPSF_PKTLENTHR 13
562 #define BIT_MASK_RXPSF_PKTLENTHR 0x7
563 #define BIT_RXPSF_PKTLENTHR(x) \
564 (((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR)
565 #define BITS_RXPSF_PKTLENTHR \
566 (BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR)
567 #define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR))
568 #define BIT_SET_RXPSF_PKTLENTHR(x, v) \
569 (BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v))
571 #define BIT_RXPSF_CTRLEN BIT(12)
572 #define BIT_RXPSF_VHTCHKEN BIT(11)
573 #define BIT_RXPSF_HTCHKEN BIT(10)
574 #define BIT_RXPSF_OFDMCHKEN BIT(9)
575 #define BIT_RXPSF_CCKCHKEN BIT(8)
576 #define BIT_RXPSF_OFDMRST BIT(7)
577 #define BIT_RXPSF_CCKRST BIT(6)
578 #define BIT_RXPSF_MHCHKEN BIT(5)
579 #define BIT_RXPSF_CONT_ERRCHKEN BIT(4)
580 #define BIT_RXPSF_ALL_ERRCHKEN BIT(3)
582 #define BIT_SHIFT_RXPSF_ERRTHR 0
583 #define BIT_MASK_RXPSF_ERRTHR 0x7
584 #define BIT_RXPSF_ERRTHR(x) \
585 (((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR)
586 #define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR)
587 #define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR))
588 #define BIT_GET_RXPSF_ERRTHR(x) \
589 (((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR)
590 #define BIT_SET_RXPSF_ERRTHR(x, v) \
591 (BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v))
593 #define REG_RXPSF_TYPE_CTRL 0x1614
594 #define REG_GENERAL_OPTION 0x1664
595 #define BIT_DUMMY_FCS_READY_MASK_EN BIT(9)
597 #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700
598 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704
599 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708
600 #define LTECOEX_READY BIT(29)
601 #define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1
602 #define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1
603 #define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1
605 #define REG_IGN_GNT_BT1 0x1860
607 #define REG_RFESEL_CTRL 0x1990
609 #define REG_NOMASK_TXBT 0x1ca7
610 #define REG_ANAPAR 0x1c30
611 #define BIT_ANAPAR_BTPS BIT(22)
612 #define REG_RSTB_SEL 0x1c38
614 #define REG_IGN_GNTBT4 0x4160
617 #define RF_MODOPT 0x01
618 #define RF_WLINT 0x01
619 #define RF_WLSEL 0x02
620 #define RF_DTXLOK 0x08
621 #define RF_CFGCH 0x18
623 #define RF_LUTWA 0x33
624 #define RF_LUTWD1 0x3e
625 #define RF_LUTWD0 0x3f
626 #define RF_T_METER 0x42
627 #define RF_BSPAD 0x54
628 #define RF_GAINTX 0x56
629 #define RF_TXATANK 0x64
630 #define RF_TRXIQ 0x66
631 #define RF_RXIQGEN 0x8d
632 #define RF_XTALX2 0xb8
633 #define RF_MALSEL 0xbe
635 #define RF_TXADBG 0xde
636 #define RF_LUTDBG 0xdf
637 #define RF_LUTWE2 0xee
638 #define RF_LUTWE 0xef
640 #define LTE_COEX_CTRL 0x38
641 #define LTE_WL_TRX_CTRL 0xa0
642 #define LTE_BT_TRX_CTRL 0xa4