drivers/net/wireless/realtek/rtw88/mac.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /* Copyright(c) 2018-2019  Realtek Corporation
   3  */
   4
   5 #include "main.h"
   6 #include "mac.h"
   7 #include "reg.h"
   8 #include "fw.h"
   9 #include "debug.h"
  10
  11 void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw,
  12                          u8 primary_ch_idx)
  13 {
  14         u8 txsc40 = 0, txsc20 = 0;
  15         u32 value32;
  16         u8 value8;
  17
  18         txsc20 = primary_ch_idx;
  19         if (txsc20 == 1 || txsc20 == 3)
  20                 txsc40 = 9;
  21         else
  22                 txsc40 = 10;
  23         rtw_write8(rtwdev, REG_DATA_SC,
  24                    BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40));
  25
  26         value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL);
  27         value32 &= ~BIT_RFMOD;
  28         switch (bw) {
  29         case RTW_CHANNEL_WIDTH_80:
  30                 value32 |= BIT_RFMOD_80M;
  31                 break;
  32         case RTW_CHANNEL_WIDTH_40:
  33                 value32 |= BIT_RFMOD_40M;
  34                 break;
  35         case RTW_CHANNEL_WIDTH_20:
  36         default:
  37                 break;
  38         }
  39         rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32);
  40
  41         value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL);
  42         value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
  43         rtw_write32(rtwdev, REG_AFE_CTRL1, value32);
  44
  45         rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
  46         rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
  47
  48         value8 = rtw_read8(rtwdev, REG_CCK_CHECK);
  49         value8 = value8 & ~BIT_CHECK_CCK_EN;
  50         if (channel > 35)
  51                 value8 |= BIT_CHECK_CCK_EN;
  52         rtw_write8(rtwdev, REG_CCK_CHECK, value8);
  53 }
  54
  55 static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev)
  56 {
  57         u32 value32;
  58         u8 value8;
  59
  60         rtw_write8(rtwdev, REG_RSV_CTRL, 0);
  61
  62         switch (rtw_hci_type(rtwdev)) {
  63         case RTW_HCI_TYPE_PCIE:
  64                 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_BT_DIG_CLK_EN);
  65                 break;
  66         case RTW_HCI_TYPE_USB:
  67                 break;
  68         default:
  69                 return -EINVAL;
  70         }
  71
  72         /* config PIN Mux */
  73         value32 = rtw_read32(rtwdev, REG_PAD_CTRL1);
  74         value32 |= BIT_PAPE_WLBT_SEL | BIT_LNAON_WLBT_SEL;
  75         rtw_write32(rtwdev, REG_PAD_CTRL1, value32);
  76
  77         value32 = rtw_read32(rtwdev, REG_LED_CFG);
  78         value32 &= ~(BIT_PAPE_SEL_EN | BIT_LNAON_SEL_EN);
  79         rtw_write32(rtwdev, REG_LED_CFG, value32);
  80
  81         value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG);
  82         value32 |= BIT_WLRFE_4_5_EN;
  83         rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32);
  84
  85         /* disable BB/RF */
  86         value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
  87         value8 &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
  88         rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8);
  89
  90         value8 = rtw_read8(rtwdev, REG_RF_CTRL);
  91         value8 &= ~(BIT_RF_SDM_RSTB | BIT_RF_RSTB | BIT_RF_EN);
  92         rtw_write8(rtwdev, REG_RF_CTRL, value8);
  93
  94         value32 = rtw_read32(rtwdev, REG_WLRF1);
  95         value32 &= ~BIT_WLRF1_BBRF_EN;
  96         rtw_write32(rtwdev, REG_WLRF1, value32);
  97
  98         return 0;
  99 }
 100
 101 static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev,
 102                                struct rtw_pwr_seq_cmd *cmd)
 103 {
 104         u8 value;
 105         u8 flag = 0;
 106         u32 offset;
 107         u32 cnt = RTW_PWR_POLLING_CNT;
 108
 109         if (cmd->base == RTW_PWR_ADDR_SDIO)
 110                 offset = cmd->offset | SDIO_LOCAL_OFFSET;
 111         else
 112                 offset = cmd->offset;
 113
 114         do {
 115                 cnt--;
 116                 value = rtw_read8(rtwdev, offset);
 117                 value &= cmd->mask;
 118                 if (value == (cmd->value & cmd->mask))
 119                         return 0;
 120                 if (cnt == 0) {
 121                         if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE &&
 122                             flag == 0) {
 123                                 value = rtw_read8(rtwdev, REG_SYS_PW_CTRL);
 124                                 value |= BIT(3);
 125                                 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value);
 126                                 value &= ~BIT(3);
 127                                 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value);
 128                                 cnt = RTW_PWR_POLLING_CNT;
 129                                 flag = 1;
 130                         } else {
 131                                 return -EBUSY;
 132                         }
 133                 } else {
 134                         udelay(50);
 135                 }
 136         } while (1);
 137 }
 138
 139 static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask,
 140                                   u8 cut_mask, struct rtw_pwr_seq_cmd *cmd)
 141 {
 142         struct rtw_pwr_seq_cmd *cur_cmd;
 143         u32 offset;
 144         u8 value;
 145
 146         for (cur_cmd = cmd; cur_cmd->cmd != RTW_PWR_CMD_END; cur_cmd++) {
 147                 if (!(cur_cmd->intf_mask & intf_mask) ||
 148                     !(cur_cmd->cut_mask & cut_mask))
 149                         continue;
 150
 151                 switch (cur_cmd->cmd) {
 152                 case RTW_PWR_CMD_WRITE:
 153                         offset = cur_cmd->offset;
 154
 155                         if (cur_cmd->base == RTW_PWR_ADDR_SDIO)
 156                                 offset |= SDIO_LOCAL_OFFSET;
 157
 158                         value = rtw_read8(rtwdev, offset);
 159                         value &= ~cur_cmd->mask;
 160                         value |= (cur_cmd->value & cur_cmd->mask);
 161                         rtw_write8(rtwdev, offset, value);
 162                         break;
 163                 case RTW_PWR_CMD_POLLING:
 164                         if (rtw_pwr_cmd_polling(rtwdev, cur_cmd))
 165                                 return -EBUSY;
 166                         break;
 167                 case RTW_PWR_CMD_DELAY:
 168                         if (cur_cmd->value == RTW_PWR_DELAY_US)
 169                                 udelay(cur_cmd->offset);
 170                         else
 171                                 mdelay(cur_cmd->offset);
 172                         break;
 173                 case RTW_PWR_CMD_READ:
 174                         break;
 175                 default:
 176                         return -EINVAL;
 177                 }
 178         }
 179
 180         return 0;
 181 }
 182
 183 static int rtw_pwr_seq_parser(struct rtw_dev *rtwdev,
 184                               struct rtw_pwr_seq_cmd **cmd_seq)
 185 {
 186         u8 cut_mask;
 187         u8 intf_mask;
 188         u8 cut;
 189         u32 idx = 0;
 190         struct rtw_pwr_seq_cmd *cmd;
 191         int ret;
 192
 193         cut = rtwdev->hal.cut_version;
 194         cut_mask = cut_version_to_mask(cut);
 195         switch (rtw_hci_type(rtwdev)) {
 196         case RTW_HCI_TYPE_PCIE:
 197                 intf_mask = BIT(2);
 198                 break;
 199         case RTW_HCI_TYPE_USB:
 200                 intf_mask = BIT(1);
 201                 break;
 202         default:
 203                 return -EINVAL;
 204         }
 205
 206         do {
 207                 cmd = cmd_seq[idx];
 208                 if (!cmd)
 209                         break;
 210
 211                 ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd);
 212                 if (ret)
 213                         return -EBUSY;
 214
 215                 idx++;
 216         } while (1);
 217
 218         return 0;
 219 }
 220
 221 static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on)
 222 {
 223         struct rtw_chip_info *chip = rtwdev->chip;
 224         struct rtw_pwr_seq_cmd **pwr_seq;
 225         u8 rpwm;
 226         bool cur_pwr;
 227
 228         rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr);
 229
 230         /* Check FW still exist or not */
 231         if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) {
 232                 rpwm = (rpwm ^ BIT_RPWM_TOGGLE) & BIT_RPWM_TOGGLE;
 233                 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm);
 234         }
 235
 236         if (rtw_read8(rtwdev, REG_CR) == 0xea)
 237                 cur_pwr = false;
 238         else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
 239                  (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0)))
 240                 cur_pwr = false;
 241         else
 242                 cur_pwr = true;
 243
 244         if (pwr_on && cur_pwr)
 245                 return -EALREADY;
 246
 247         pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq;
 248         if (rtw_pwr_seq_parser(rtwdev, pwr_seq))
 249                 return -EINVAL;
 250
 251         return 0;
 252 }
 253
 254 static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev)
 255 {
 256         u8 sys_func_en = rtwdev->chip->sys_func_en;
 257         u8 value8;
 258         u32 value, tmp;
 259
 260         value = rtw_read32(rtwdev, REG_CPU_DMEM_CON);
 261         value |= BIT_WL_PLATFORM_RST | BIT_DDMA_EN;
 262         rtw_write32(rtwdev, REG_CPU_DMEM_CON, value);
 263
 264         rtw_write8(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en);
 265         value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C;
 266         rtw_write8(rtwdev, REG_CR_EXT + 3, value8);
 267
 268         /* disable boot-from-flash for driver's DL FW */
 269         tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL);
 270         if (tmp & BIT_BOOT_FSPI_EN) {
 271                 rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));
 272                 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
 273                 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value);
 274         }
 275
 276         return 0;
 277 }
 278
 279 int rtw_mac_power_on(struct rtw_dev *rtwdev)
 280 {
 281         int ret = 0;
 282
 283         ret = rtw_mac_pre_system_cfg(rtwdev);
 284         if (ret)
 285                 goto err;
 286
 287         ret = rtw_mac_power_switch(rtwdev, true);
 288         if (ret == -EALREADY) {
 289                 rtw_mac_power_switch(rtwdev, false);
 290                 ret = rtw_mac_power_switch(rtwdev, true);
 291                 if (ret)
 292                         goto err;
 293         } else if (ret) {
 294                 goto err;
 295         }
 296
 297         ret = rtw_mac_init_system_cfg(rtwdev);
 298         if (ret)
 299                 goto err;
 300
 301         return 0;
 302
 303 err:
 304         rtw_err(rtwdev, "mac power on failed");
 305         return ret;
 306 }
 307
 308 void rtw_mac_power_off(struct rtw_dev *rtwdev)
 309 {
 310         rtw_mac_power_switch(rtwdev, false);
 311 }
 312
 313 static bool check_firmware_size(const u8 *data, u32 size)
 314 {
 315         u32 dmem_size;
 316         u32 imem_size;
 317         u32 emem_size;
 318         u32 real_size;
 319
 320         dmem_size = le32_to_cpu(*((__le32 *)(data + FW_HDR_DMEM_SIZE)));
 321         imem_size = le32_to_cpu(*((__le32 *)(data + FW_HDR_IMEM_SIZE)));
 322         emem_size = ((*(data + FW_HDR_MEM_USAGE)) & BIT(4)) ?
 323                     le32_to_cpu(*((__le32 *)(data + FW_HDR_EMEM_SIZE))) : 0;
 324
 325         dmem_size += FW_HDR_CHKSUM_SIZE;
 326         imem_size += FW_HDR_CHKSUM_SIZE;
 327         emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0;
 328         real_size = FW_HDR_SIZE + dmem_size + imem_size + emem_size;
 329         if (real_size != size)
 330                 return false;
 331
 332         return true;
 333 }
 334
 335 static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable)
 336 {
 337         if (enable) {
 338                 /* cpu io interface enable */
 339                 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
 340
 341                 /* cpu enable */
 342                 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
 343         } else {
 344                 /* cpu io interface disable */
 345                 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
 346
 347                 /* cpu disable */
 348                 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
 349         }
 350 }
 351
 352 #define DLFW_RESTORE_REG_NUM 6
 353
 354 static void download_firmware_reg_backup(struct rtw_dev *rtwdev,
 355                                          struct rtw_backup_info *bckp)
 356 {
 357         u8 tmp;
 358         u8 bckp_idx = 0;
 359
 360         /* set HIQ to hi priority */
 361         bckp[bckp_idx].len = 1;
 362         bckp[bckp_idx].reg = REG_TXDMA_PQ_MAP + 1;
 363         bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1);
 364         bckp_idx++;
 365         tmp = RTW_DMA_MAPPING_HIGH << 6;
 366         rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp);
 367
 368         /* DLFW only use HIQ, map HIQ to hi priority */
 369         bckp[bckp_idx].len = 1;
 370         bckp[bckp_idx].reg = REG_CR;
 371         bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR);
 372         bckp_idx++;
 373         bckp[bckp_idx].len = 4;
 374         bckp[bckp_idx].reg = REG_H2CQ_CSR;
 375         bckp[bckp_idx].val = BIT_H2CQ_FULL;
 376         bckp_idx++;
 377         tmp = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN;
 378         rtw_write8(rtwdev, REG_CR, tmp);
 379         rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
 380
 381         /* Config hi priority queue and public priority queue page number */
 382         bckp[bckp_idx].len = 2;
 383         bckp[bckp_idx].reg = REG_FIFOPAGE_INFO_1;
 384         bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1);
 385         bckp_idx++;
 386         bckp[bckp_idx].len = 4;
 387         bckp[bckp_idx].reg = REG_RQPN_CTRL_2;
 388         bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN;
 389         bckp_idx++;
 390         rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200);
 391         rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val);
 392
 393         /* Disable beacon related functions */
 394         tmp = rtw_read8(rtwdev, REG_BCN_CTRL);
 395         bckp[bckp_idx].len = 1;
 396         bckp[bckp_idx].reg = REG_BCN_CTRL;
 397         bckp[bckp_idx].val = tmp;
 398         bckp_idx++;
 399         tmp = (u8)((tmp & (~BIT_EN_BCN_FUNCTION)) | BIT_DIS_TSF_UDT);
 400         rtw_write8(rtwdev, REG_BCN_CTRL, tmp);
 401
 402         WARN(bckp_idx != DLFW_RESTORE_REG_NUM, "wrong backup number\n");
 403 }
 404
 405 static void download_firmware_reset_platform(struct rtw_dev *rtwdev)
 406 {
 407         rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
 408         rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
 409         rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
 410         rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
 411 }
 412
 413 static void download_firmware_reg_restore(struct rtw_dev *rtwdev,
 414                                           struct rtw_backup_info *bckp,
 415                                           u8 bckp_num)
 416 {
 417         rtw_restore_reg(rtwdev, bckp, bckp_num);
 418 }
 419
 420 #define TX_DESC_SIZE 48
 421
 422 static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
 423                                        const u8 *data, u32 size)
 424 {
 425         u8 *buf;
 426         int ret;
 427
 428         buf = kmemdup(data, size, GFP_KERNEL);
 429         if (!buf)
 430                 return -ENOMEM;
 431
 432         ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size);
 433         kfree(buf);
 434         return ret;
 435 }
 436
 437 static int
 438 send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size)
 439 {
 440         int ret;
 441
 442         if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
 443             !((size + TX_DESC_SIZE) & (512 - 1)))
 444                 size += 1;
 445
 446         ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size);
 447         if (ret)
 448                 rtw_err(rtwdev, "failed to download rsvd page\n");
 449
 450         return ret;
 451 }
 452
 453 static int
 454 iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl)
 455 {
 456         rtw_write32(rtwdev, REG_DDMA_CH0SA, src);
 457         rtw_write32(rtwdev, REG_DDMA_CH0DA, dst);
 458         rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl);
 459
 460         if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
 461                 return -EBUSY;
 462
 463         return 0;
 464 }
 465
 466 static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst,
 467                                    u32 len, u8 first)
 468 {
 469         u32 ch0_ctrl = BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN;
 470
 471         if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
 472                 return -EBUSY;
 473
 474         ch0_ctrl |= len & BIT_MASK_DDMACH0_DLEN;
 475         if (!first)
 476                 ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT;
 477
 478         if (iddma_enable(rtwdev, src, dst, ch0_ctrl))
 479                 return -EBUSY;
 480
 481         return 0;
 482 }
 483
 484 static bool
 485 check_fw_checksum(struct rtw_dev *rtwdev, u32 addr)
 486 {
 487         u8 fw_ctrl;
 488
 489         fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL);
 490
 491         if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) {
 492                 if (addr < OCPBASE_DMEM_88XX) {
 493                         fw_ctrl |= BIT_IMEM_DW_OK;
 494                         fw_ctrl &= ~BIT_IMEM_CHKSUM_OK;
 495                         rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
 496                 } else {
 497                         fw_ctrl |= BIT_DMEM_DW_OK;
 498                         fw_ctrl &= ~BIT_DMEM_CHKSUM_OK;
 499                         rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
 500                 }
 501
 502                 rtw_err(rtwdev, "invalid fw checksum\n");
 503
 504                 return false;
 505         }
 506
 507         if (addr < OCPBASE_DMEM_88XX) {
 508                 fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK);
 509                 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
 510         } else {
 511                 fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK);
 512                 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
 513         }
 514
 515         return true;
 516 }
 517
 518 static int
 519 download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data,
 520                          u32 src, u32 dst, u32 size)
 521 {
 522         struct rtw_chip_info *chip = rtwdev->chip;
 523         u32 desc_size = chip->tx_pkt_desc_sz;
 524         u8 first_part;
 525         u32 mem_offset;
 526         u32 residue_size;
 527         u32 pkt_size;
 528         u32 max_size = 0x1000;
 529         u32 val;
 530         int ret;
 531
 532         mem_offset = 0;
 533         first_part = 1;
 534         residue_size = size;
 535
 536         val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL);
 537         val |= BIT_DDMACH0_RESET_CHKSUM_STS;
 538         rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val);
 539
 540         while (residue_size) {
 541                 if (residue_size >= max_size)
 542                         pkt_size = max_size;
 543                 else
 544                         pkt_size = residue_size;
 545
 546                 ret = send_firmware_pkt(rtwdev, (u16)(src >> 7),
 547                                         data + mem_offset, pkt_size);
 548                 if (ret)
 549                         return ret;
 550
 551                 ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX +
 552                                               src + desc_size,
 553                                               dst + mem_offset, pkt_size,
 554                                               first_part);
 555                 if (ret)
 556                         return ret;
 557
 558                 first_part = 0;
 559                 mem_offset += pkt_size;
 560                 residue_size -= pkt_size;
 561         }
 562
 563         if (!check_fw_checksum(rtwdev, dst))
 564                 return -EINVAL;
 565
 566         return 0;
 567 }
 568
 569 static void update_firmware_info(struct rtw_dev *rtwdev,
 570                                  struct rtw_fw_state *fw)
 571 {
 572         const u8 *data = fw->firmware->data;
 573
 574         fw->h2c_version =
 575                 le16_to_cpu(*((__le16 *)(data + FW_HDR_H2C_FMT_VER)));
 576         fw->version =
 577                 le16_to_cpu(*((__le16 *)(data + FW_HDR_VERSION)));
 578         fw->sub_version = *(data + FW_HDR_SUBVERSION);
 579         fw->sub_index = *(data + FW_HDR_SUBINDEX);
 580
 581         rtw_dbg(rtwdev, RTW_DBG_FW, "fw h2c version: %x\n", fw->h2c_version);
 582         rtw_dbg(rtwdev, RTW_DBG_FW, "fw version:     %x\n", fw->version);
 583         rtw_dbg(rtwdev, RTW_DBG_FW, "fw sub version: %x\n", fw->sub_version);
 584         rtw_dbg(rtwdev, RTW_DBG_FW, "fw sub index:   %x\n", fw->sub_index);
 585 }
 586
 587 static int
 588 start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size)
 589 {
 590         const u8 *cur_fw;
 591         u16 val;
 592         u32 imem_size;
 593         u32 dmem_size;
 594         u32 emem_size;
 595         u32 addr;
 596         int ret;
 597
 598         dmem_size = le32_to_cpu(*((__le32 *)(data + FW_HDR_DMEM_SIZE)));
 599         imem_size = le32_to_cpu(*((__le32 *)(data + FW_HDR_IMEM_SIZE)));
 600         emem_size = ((*(data + FW_HDR_MEM_USAGE)) & BIT(4)) ?
 601                     le32_to_cpu(*((__le32 *)(data + FW_HDR_EMEM_SIZE))) : 0;
 602         dmem_size += FW_HDR_CHKSUM_SIZE;
 603         imem_size += FW_HDR_CHKSUM_SIZE;
 604         emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0;
 605
 606         val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800);
 607         val |= BIT_MCUFWDL_EN;
 608         rtw_write16(rtwdev, REG_MCUFW_CTRL, val);
 609
 610         cur_fw = data + FW_HDR_SIZE;
 611         addr = le32_to_cpu(*((__le32 *)(data + FW_HDR_DMEM_ADDR)));
 612         addr &= ~BIT(31);
 613         ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size);
 614         if (ret)
 615                 return ret;
 616
 617         cur_fw = data + FW_HDR_SIZE + dmem_size;
 618         addr = le32_to_cpu(*((__le32 *)(data + FW_HDR_IMEM_ADDR)));
 619         addr &= ~BIT(31);
 620         ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size);
 621         if (ret)
 622                 return ret;
 623
 624         if (emem_size) {
 625                 cur_fw = data + FW_HDR_SIZE + dmem_size + imem_size;
 626                 addr = le32_to_cpu(*((__le32 *)(data + FW_HDR_EMEM_ADDR)));
 627                 addr &= ~BIT(31);
 628                 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr,
 629                                                emem_size);
 630                 if (ret)
 631                         return ret;
 632         }
 633
 634         return 0;
 635 }
 636
 637 static int download_firmware_validate(struct rtw_dev *rtwdev)
 638 {
 639         u32 fw_key;
 640
 641         if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) {
 642                 fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK;
 643                 if (fw_key == ILLEGAL_KEY_GROUP)
 644                         rtw_err(rtwdev, "invalid fw key\n");
 645                 return -EINVAL;
 646         }
 647
 648         return 0;
 649 }
 650
 651 static void download_firmware_end_flow(struct rtw_dev *rtwdev)
 652 {
 653         u16 fw_ctrl;
 654
 655         rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF);
 656
 657         /* Check IMEM & DMEM checksum is OK or not */
 658         fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL);
 659         if ((fw_ctrl & BIT_CHECK_SUM_OK) != BIT_CHECK_SUM_OK)
 660                 return;
 661
 662         fw_ctrl = (fw_ctrl | BIT_FW_DW_RDY) & ~BIT_MCUFWDL_EN;
 663         rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
 664 }
 665
 666 int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw)
 667 {
 668         struct rtw_backup_info bckp[DLFW_RESTORE_REG_NUM];
 669         const u8 *data = fw->firmware->data;
 670         u32 size = fw->firmware->size;
 671         u32 ltecoex_bckp;
 672         int ret;
 673
 674         if (!check_firmware_size(data, size))
 675                 return -EINVAL;
 676
 677         if (!ltecoex_read_reg(rtwdev, 0x38, &ltecoex_bckp))
 678                 return -EBUSY;
 679
 680         wlan_cpu_enable(rtwdev, false);
 681
 682         download_firmware_reg_backup(rtwdev, bckp);
 683         download_firmware_reset_platform(rtwdev);
 684
 685         ret = start_download_firmware(rtwdev, data, size);
 686         if (ret)
 687                 goto dlfw_fail;
 688
 689         download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM);
 690
 691         download_firmware_end_flow(rtwdev);
 692
 693         wlan_cpu_enable(rtwdev, true);
 694
 695         if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp))
 696                 return -EBUSY;
 697
 698         ret = download_firmware_validate(rtwdev);
 699         if (ret)
 700                 goto dlfw_fail;
 701
 702         update_firmware_info(rtwdev, fw);
 703
 704         /* reset desc and index */
 705         rtw_hci_setup(rtwdev);
 706
 707         rtwdev->h2c.last_box_num = 0;
 708         rtwdev->h2c.seq = 0;
 709
 710         rtw_flag_set(rtwdev, RTW_FLAG_FW_RUNNING);
 711
 712         return 0;
 713
 714 dlfw_fail:
 715         /* Disable FWDL_EN */
 716         rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
 717         rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
 718
 719         return ret;
 720 }
 721
 722 static int txdma_queue_mapping(struct rtw_dev *rtwdev)
 723 {
 724         struct rtw_chip_info *chip = rtwdev->chip;
 725         struct rtw_rqpn *rqpn = NULL;
 726         u16 txdma_pq_map = 0;
 727
 728         switch (rtw_hci_type(rtwdev)) {
 729         case RTW_HCI_TYPE_PCIE:
 730                 rqpn = &chip->rqpn_table[1];
 731                 break;
 732         case RTW_HCI_TYPE_USB:
 733                 if (rtwdev->hci.bulkout_num == 2)
 734                         rqpn = &chip->rqpn_table[2];
 735                 else if (rtwdev->hci.bulkout_num == 3)
 736                         rqpn = &chip->rqpn_table[3];
 737                 else if (rtwdev->hci.bulkout_num == 4)
 738                         rqpn = &chip->rqpn_table[4];
 739                 else
 740                         return -EINVAL;
 741                 break;
 742         default:
 743                 return -EINVAL;
 744         }
 745
 746         txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi);
 747         txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg);
 748         txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk);
 749         txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be);
 750         txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi);
 751         txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo);
 752         rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map);
 753
 754         rtw_write8(rtwdev, REG_CR, 0);
 755         rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE);
 756         rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
 757
 758         return 0;
 759 }
 760
 761 static int set_trx_fifo_info(struct rtw_dev *rtwdev)
 762 {
 763         struct rtw_fifo_conf *fifo = &rtwdev->fifo;
 764         struct rtw_chip_info *chip = rtwdev->chip;
 765         u16 cur_pg_addr;
 766         u8 csi_buf_pg_num = chip->csi_buf_pg_num;
 767
 768         /* config rsvd page num */
 769         fifo->rsvd_drv_pg_num = 8;
 770         fifo->txff_pg_num = chip->txff_size >> 7;
 771         fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num +
 772                            RSVD_PG_H2C_EXTRAINFO_NUM +
 773                            RSVD_PG_H2C_STATICINFO_NUM +
 774                            RSVD_PG_H2CQ_NUM +
 775                            RSVD_PG_CPU_INSTRUCTION_NUM +
 776                            RSVD_PG_FW_TXBUF_NUM +
 777                            csi_buf_pg_num;
 778
 779         if (fifo->rsvd_pg_num > fifo->txff_pg_num)
 780                 return -ENOMEM;
 781
 782         fifo->acq_pg_num = fifo->txff_pg_num - fifo->rsvd_pg_num;
 783         fifo->rsvd_boundary = fifo->txff_pg_num - fifo->rsvd_pg_num;
 784
 785         cur_pg_addr = fifo->txff_pg_num;
 786         cur_pg_addr -= csi_buf_pg_num;
 787         fifo->rsvd_csibuf_addr = cur_pg_addr;
 788         cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM;
 789         fifo->rsvd_fw_txbuf_addr = cur_pg_addr;
 790         cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM;
 791         fifo->rsvd_cpu_instr_addr = cur_pg_addr;
 792         cur_pg_addr -= RSVD_PG_H2CQ_NUM;
 793         fifo->rsvd_h2cq_addr = cur_pg_addr;
 794         cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM;
 795         fifo->rsvd_h2c_sta_info_addr = cur_pg_addr;
 796         cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM;
 797         fifo->rsvd_h2c_info_addr = cur_pg_addr;
 798         cur_pg_addr -= fifo->rsvd_drv_pg_num;
 799         fifo->rsvd_drv_addr = cur_pg_addr;
 800
 801         if (fifo->rsvd_boundary != fifo->rsvd_drv_addr) {
 802                 rtw_err(rtwdev, "wrong rsvd driver address\n");
 803                 return -EINVAL;
 804         }
 805
 806         return 0;
 807 }
 808
 809 static int priority_queue_cfg(struct rtw_dev *rtwdev)
 810 {
 811         struct rtw_fifo_conf *fifo = &rtwdev->fifo;
 812         struct rtw_chip_info *chip = rtwdev->chip;
 813         struct rtw_page_table *pg_tbl = NULL;
 814         u16 pubq_num;
 815         int ret;
 816
 817         ret = set_trx_fifo_info(rtwdev);
 818         if (ret)
 819                 return ret;
 820
 821         switch (rtw_hci_type(rtwdev)) {
 822         case RTW_HCI_TYPE_PCIE:
 823                 pg_tbl = &chip->page_table[1];
 824                 break;
 825         case RTW_HCI_TYPE_USB:
 826                 if (rtwdev->hci.bulkout_num == 2)
 827                         pg_tbl = &chip->page_table[2];
 828                 else if (rtwdev->hci.bulkout_num == 3)
 829                         pg_tbl = &chip->page_table[3];
 830                 else if (rtwdev->hci.bulkout_num == 4)
 831                         pg_tbl = &chip->page_table[4];
 832                 else
 833                         return -EINVAL;
 834                 break;
 835         default:
 836                 return -EINVAL;
 837         }
 838
 839         pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num -
 840                    pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num;
 841         rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num);
 842         rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num);
 843         rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num);
 844         rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num);
 845         rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num);
 846         rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN);
 847
 848         rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary);
 849         rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16);
 850
 851         rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary);
 852         rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary);
 853         rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary);
 854         rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1);
 855         rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);
 856
 857         if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0))
 858                 return -EBUSY;
 859
 860         rtw_write8(rtwdev, REG_CR + 3, 0);
 861
 862         return 0;
 863 }
 864
 865 static int init_h2c(struct rtw_dev *rtwdev)
 866 {
 867         struct rtw_fifo_conf *fifo = &rtwdev->fifo;
 868         u8 value8;
 869         u32 value32;
 870         u32 h2cq_addr;
 871         u32 h2cq_size;
 872         u32 h2cq_free;
 873         u32 wp, rp;
 874
 875         h2cq_addr = fifo->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT;
 876         h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT;
 877
 878         value32 = rtw_read32(rtwdev, REG_H2C_HEAD);
 879         value32 = (value32 & 0xFFFC0000) | h2cq_addr;
 880         rtw_write32(rtwdev, REG_H2C_HEAD, value32);
 881
 882         value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR);
 883         value32 = (value32 & 0xFFFC0000) | h2cq_addr;
 884         rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32);
 885
 886         value32 = rtw_read32(rtwdev, REG_H2C_TAIL);
 887         value32 &= 0xFFFC0000;
 888         value32 |= (h2cq_addr + h2cq_size);
 889         rtw_write32(rtwdev, REG_H2C_TAIL, value32);
 890
 891         value8 = rtw_read8(rtwdev, REG_H2C_INFO);
 892         value8 = (u8)((value8 & 0xFC) | 0x01);
 893         rtw_write8(rtwdev, REG_H2C_INFO, value8);
 894
 895         value8 = rtw_read8(rtwdev, REG_H2C_INFO);
 896         value8 = (u8)((value8 & 0xFB) | 0x04);
 897         rtw_write8(rtwdev, REG_H2C_INFO, value8);
 898
 899         value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1);
 900         value8 = (u8)((value8 & 0x7f) | 0x80);
 901         rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8);
 902
 903         wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF;
 904         rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF;
 905         h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp;
 906
 907         if (h2cq_size != h2cq_free) {
 908                 rtw_err(rtwdev, "H2C queue mismatch\n");
 909                 return -EINVAL;
 910         }
 911
 912         return 0;
 913 }
 914
 915 static int rtw_init_trx_cfg(struct rtw_dev *rtwdev)
 916 {
 917         int ret;
 918
 919         ret = txdma_queue_mapping(rtwdev);
 920         if (ret)
 921                 return ret;
 922
 923         ret = priority_queue_cfg(rtwdev);
 924         if (ret)
 925                 return ret;
 926
 927         ret = init_h2c(rtwdev);
 928         if (ret)
 929                 return ret;
 930
 931         return 0;
 932 }
 933
 934 static int rtw_drv_info_cfg(struct rtw_dev *rtwdev)
 935 {
 936         u8 value8;
 937
 938         rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE);
 939         value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1);
 940         value8 &= 0xF0;
 941         /* For rxdesc len = 0 issue */
 942         value8 |= 0xF;
 943         rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8);
 944         rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS);
 945         rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9));
 946
 947         return 0;
 948 }
 949
 950 int rtw_mac_init(struct rtw_dev *rtwdev)
 951 {
 952         struct rtw_chip_info *chip = rtwdev->chip;
 953         int ret;
 954
 955         ret = rtw_init_trx_cfg(rtwdev);
 956         if (ret)
 957                 return ret;
 958
 959         ret = chip->ops->mac_init(rtwdev);
 960         if (ret)
 961                 return ret;
 962
 963         ret = rtw_drv_info_cfg(rtwdev);
 964         if (ret)
 965                 return ret;
 966
 967         return 0;
 968 }