drivers/net/wireless/realtek/rtlwifi/rtl8723be/rf.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
   3
   4 #include "../wifi.h"
   5 #include "reg.h"
   6 #include "def.h"
   7 #include "phy.h"
   8 #include "rf.h"
   9 #include "dm.h"
  10
  11 static bool _rtl8723be_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
  12
  13 void rtl8723be_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
  14 {
  15         struct rtl_priv *rtlpriv = rtl_priv(hw);
  16         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  17
  18         switch (bandwidth) {
  19         case HT_CHANNEL_WIDTH_20:
  20                 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
  21                                              0xfffff3ff) | BIT(10) | BIT(11));
  22                 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
  23                               rtlphy->rfreg_chnlval[0]);
  24                 break;
  25         case HT_CHANNEL_WIDTH_20_40:
  26                 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
  27                                              0xfffff3ff) | BIT(10));
  28                 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
  29                               rtlphy->rfreg_chnlval[0]);
  30                 break;
  31         default:
  32                 pr_err("unknown bandwidth: %#X\n", bandwidth);
  33                 break;
  34         }
  35 }
  36
  37 void rtl8723be_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
  38                                           u8 *ppowerlevel)
  39 {
  40         struct rtl_priv *rtlpriv = rtl_priv(hw);
  41         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  42         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  43         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  44         u32 tx_agc[2] = {0, 0}, tmpval;
  45         bool turbo_scanoff = false;
  46         u8 idx1, idx2;
  47         u8 *ptr;
  48         u8 direction;
  49         u32 pwrtrac_value;
  50
  51         if (rtlefuse->eeprom_regulatory != 0)
  52                 turbo_scanoff = true;
  53
  54         if (mac->act_scanning) {
  55                 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
  56                 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
  57
  58                 if (turbo_scanoff) {
  59                         for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  60                                 tx_agc[idx1] = ppowerlevel[idx1] |
  61                                                (ppowerlevel[idx1] << 8) |
  62                                                (ppowerlevel[idx1] << 16) |
  63                                                (ppowerlevel[idx1] << 24);
  64                         }
  65                 }
  66         } else {
  67                 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  68                         tx_agc[idx1] = ppowerlevel[idx1] |
  69                                        (ppowerlevel[idx1] << 8) |
  70                                        (ppowerlevel[idx1] << 16) |
  71                                        (ppowerlevel[idx1] << 24);
  72                 }
  73
  74                 if (rtlefuse->eeprom_regulatory == 0) {
  75                         tmpval =
  76                             (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
  77                             (rtlphy->mcs_txpwrlevel_origoffset[0][7] << 8);
  78                         tx_agc[RF90_PATH_A] += tmpval;
  79
  80                         tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
  81                                  (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
  82                                   24);
  83                         tx_agc[RF90_PATH_B] += tmpval;
  84                 }
  85         }
  86
  87         for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  88                 ptr = (u8 *)(&(tx_agc[idx1]));
  89                 for (idx2 = 0; idx2 < 4; idx2++) {
  90                         if (*ptr > RF6052_MAX_TX_PWR)
  91                                 *ptr = RF6052_MAX_TX_PWR;
  92                         ptr++;
  93                 }
  94         }
  95         rtl8723be_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
  96         if (direction == 1) {
  97                 tx_agc[0] += pwrtrac_value;
  98                 tx_agc[1] += pwrtrac_value;
  99         } else if (direction == 2) {
 100                 tx_agc[0] -= pwrtrac_value;
 101                 tx_agc[1] -= pwrtrac_value;
 102         }
 103         tmpval = tx_agc[RF90_PATH_A] & 0xff;
 104         rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
 105
 106         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 107                 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
 108                  RTXAGC_A_CCK1_MCS32);
 109
 110         tmpval = tx_agc[RF90_PATH_A] >> 8;
 111
 112         /*tmpval = tmpval & 0xff00ffff;*/
 113
 114         rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
 115
 116         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 117                 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
 118                  RTXAGC_B_CCK11_A_CCK2_11);
 119
 120         tmpval = tx_agc[RF90_PATH_B] >> 24;
 121         rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
 122
 123         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 124                 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
 125                  RTXAGC_B_CCK11_A_CCK2_11);
 126
 127         tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
 128         rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
 129
 130         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 131                 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
 132                  RTXAGC_B_CCK1_55_MCS32);
 133 }
 134
 135 static void rtl8723be_phy_get_power_base(struct ieee80211_hw *hw,
 136                                          u8 *ppowerlevel_ofdm,
 137                                          u8 *ppowerlevel_bw20,
 138                                          u8 *ppowerlevel_bw40,
 139                                          u8 channel, u32 *ofdmbase,
 140                                          u32 *mcsbase)
 141 {
 142         struct rtl_priv *rtlpriv = rtl_priv(hw);
 143         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 144         u32 powerbase0, powerbase1;
 145         u8 i, powerlevel[2];
 146
 147         for (i = 0; i < 2; i++) {
 148                 powerbase0 = ppowerlevel_ofdm[i];
 149
 150                 powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
 151                     (powerbase0 << 8) | powerbase0;
 152                 *(ofdmbase + i) = powerbase0;
 153                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 154                         " [OFDM power base index rf(%c) = 0x%x]\n",
 155                          ((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
 156         }
 157
 158         for (i = 0; i < 2; i++) {
 159                 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
 160                         powerlevel[i] = ppowerlevel_bw20[i];
 161                 else
 162                         powerlevel[i] = ppowerlevel_bw40[i];
 163
 164                 powerbase1 = powerlevel[i];
 165                 powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) |
 166                              (powerbase1 << 8) | powerbase1;
 167
 168                 *(mcsbase + i) = powerbase1;
 169
 170                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 171                         " [MCS power base index rf(%c) = 0x%x]\n",
 172                          ((i == 0) ? 'A' : 'B'), *(mcsbase + i));
 173         }
 174 }
 175
 176 static void _rtl8723be_get_txpower_writeval_by_regulatory(
 177                                                         struct ieee80211_hw *hw,
 178                                                         u8 channel, u8 index,
 179                                                         u32 *powerbase0,
 180                                                         u32 *powerbase1,
 181                                                         u32 *p_outwriteval)
 182 {
 183         struct rtl_priv *rtlpriv = rtl_priv(hw);
 184         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 185         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 186         u8 i, chnlgroup = 0, pwr_diff_limit[4], pwr_diff = 0, customer_pwr_diff;
 187         u32 writeval, customer_limit, rf;
 188
 189         for (rf = 0; rf < 2; rf++) {
 190                 switch (rtlefuse->eeprom_regulatory) {
 191                 case 0:
 192                         chnlgroup = 0;
 193
 194                         writeval =
 195                             rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
 196                                                                 (rf ? 8 : 0)]
 197                             + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
 198
 199                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 200                                 "RTK better performance, writeval(%c) = 0x%x\n",
 201                                 ((rf == 0) ? 'A' : 'B'), writeval);
 202                         break;
 203                 case 1:
 204                         if (rtlphy->pwrgroup_cnt == 1) {
 205                                 chnlgroup = 0;
 206                         } else {
 207                                 if (channel < 3)
 208                                         chnlgroup = 0;
 209                                 else if (channel < 6)
 210                                         chnlgroup = 1;
 211                                 else if (channel < 9)
 212                                         chnlgroup = 2;
 213                                 else if (channel < 12)
 214                                         chnlgroup = 3;
 215                                 else if (channel < 14)
 216                                         chnlgroup = 4;
 217                                 else if (channel == 14)
 218                                         chnlgroup = 5;
 219                         }
 220
 221                         writeval =
 222                             rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
 223                             [index + (rf ? 8 : 0)] + ((index < 2) ?
 224                                                       powerbase0[rf] :
 225                                                       powerbase1[rf]);
 226
 227                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 228                                 "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
 229                                 ((rf == 0) ? 'A' : 'B'), writeval);
 230
 231                         break;
 232                 case 2:
 233                         writeval =
 234                             ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
 235
 236                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 237                                 "Better regulatory, writeval(%c) = 0x%x\n",
 238                                 ((rf == 0) ? 'A' : 'B'), writeval);
 239                         break;
 240                 case 3:
 241                         chnlgroup = 0;
 242
 243                         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
 244                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 245                                         "customer's limit, 40MHz rf(%c) = 0x%x\n",
 246                                         ((rf == 0) ? 'A' : 'B'),
 247                                         rtlefuse->pwrgroup_ht40
 248                                         [rf][channel - 1]);
 249                         } else {
 250                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 251                                         "customer's limit, 20MHz rf(%c) = 0x%x\n",
 252                                         ((rf == 0) ? 'A' : 'B'),
 253                                         rtlefuse->pwrgroup_ht20
 254                                         [rf][channel - 1]);
 255                         }
 256
 257                         if (index < 2)
 258                                 pwr_diff =
 259                                     rtlefuse->txpwr_legacyhtdiff[rf][channel-1];
 260                         else if (rtlphy->current_chan_bw ==
 261                                  HT_CHANNEL_WIDTH_20)
 262                                 pwr_diff =
 263                                     rtlefuse->txpwr_ht20diff[rf][channel-1];
 264
 265                         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
 266                                 customer_pwr_diff =
 267                                         rtlefuse->pwrgroup_ht40[rf][channel-1];
 268                         else
 269                                 customer_pwr_diff =
 270                                         rtlefuse->pwrgroup_ht20[rf][channel-1];
 271
 272                         if (pwr_diff > customer_pwr_diff)
 273                                 pwr_diff = 0;
 274                         else
 275                                 pwr_diff = customer_pwr_diff - pwr_diff;
 276
 277                         for (i = 0; i < 4; i++) {
 278                                 pwr_diff_limit[i] =
 279                                     (u8)((rtlphy->mcs_txpwrlevel_origoffset
 280                                            [chnlgroup][index + (rf ? 8 : 0)] &
 281                                               (0x7f << (i * 8))) >> (i * 8));
 282
 283                                 if (pwr_diff_limit[i] > pwr_diff)
 284                                         pwr_diff_limit[i] = pwr_diff;
 285                         }
 286
 287                         customer_limit = (pwr_diff_limit[3] << 24) |
 288                                          (pwr_diff_limit[2] << 16) |
 289                                          (pwr_diff_limit[1] << 8) |
 290                                          (pwr_diff_limit[0]);
 291
 292                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 293                                 "Customer's limit rf(%c) = 0x%x\n",
 294                                  ((rf == 0) ? 'A' : 'B'), customer_limit);
 295
 296                         writeval = customer_limit + ((index < 2) ?
 297                                                       powerbase0[rf] :
 298                                                       powerbase1[rf]);
 299
 300                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 301                                 "Customer, writeval rf(%c)= 0x%x\n",
 302                                  ((rf == 0) ? 'A' : 'B'), writeval);
 303                         break;
 304                 default:
 305                         chnlgroup = 0;
 306                         writeval =
 307                             rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
 308                             [index + (rf ? 8 : 0)]
 309                             + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
 310
 311                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 312                                 "RTK better performance, writeval rf(%c) = 0x%x\n",
 313                                 ((rf == 0) ? 'A' : 'B'), writeval);
 314                         break;
 315                 }
 316
 317                 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
 318                         writeval = writeval - 0x06060606;
 319                 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
 320                          TXHIGHPWRLEVEL_BT2)
 321                         writeval = writeval - 0x0c0c0c0c;
 322                 *(p_outwriteval + rf) = writeval;
 323         }
 324 }
 325
 326 static void _rtl8723be_write_ofdm_power_reg(struct ieee80211_hw *hw,
 327                                          u8 index, u32 *pvalue)
 328 {
 329         struct rtl_priv *rtlpriv = rtl_priv(hw);
 330         u16 regoffset_a[6] = {
 331                 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
 332                 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
 333                 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
 334         };
 335         u16 regoffset_b[6] = {
 336                 RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
 337                 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
 338                 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
 339         };
 340         u8 i, rf, pwr_val[4];
 341         u32 writeval;
 342         u16 regoffset;
 343
 344         for (rf = 0; rf < 2; rf++) {
 345                 writeval = pvalue[rf];
 346                 for (i = 0; i < 4; i++) {
 347                         pwr_val[i] = (u8)((writeval & (0x7f <<
 348                                                         (i * 8))) >> (i * 8));
 349
 350                         if (pwr_val[i] > RF6052_MAX_TX_PWR)
 351                                 pwr_val[i] = RF6052_MAX_TX_PWR;
 352                 }
 353                 writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
 354                     (pwr_val[1] << 8) | pwr_val[0];
 355
 356                 if (rf == 0)
 357                         regoffset = regoffset_a[index];
 358                 else
 359                         regoffset = regoffset_b[index];
 360                 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
 361
 362                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 363                         "Set 0x%x = %08x\n", regoffset, writeval);
 364         }
 365 }
 366
 367 void rtl8723be_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
 368                                            u8 *ppowerlevel_ofdm,
 369                                            u8 *ppowerlevel_bw20,
 370                                            u8 *ppowerlevel_bw40, u8 channel)
 371 {
 372         u32 writeval[2], powerbase0[2], powerbase1[2];
 373         u8 index;
 374         u8 direction;
 375         u32 pwrtrac_value;
 376
 377         rtl8723be_phy_get_power_base(hw, ppowerlevel_ofdm, ppowerlevel_bw20,
 378                                      ppowerlevel_bw40, channel,
 379                                      &powerbase0[0], &powerbase1[0]);
 380
 381         rtl8723be_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
 382
 383         for (index = 0; index < 6; index++) {
 384                 _rtl8723be_get_txpower_writeval_by_regulatory(hw,
 385                                                               channel, index,
 386                                                               &powerbase0[0],
 387                                                               &powerbase1[0],
 388                                                               &writeval[0]);
 389                 if (direction == 1) {
 390                         writeval[0] += pwrtrac_value;
 391                         writeval[1] += pwrtrac_value;
 392                 } else if (direction == 2) {
 393                         writeval[0] -= pwrtrac_value;
 394                         writeval[1] -= pwrtrac_value;
 395                 }
 396                 _rtl8723be_write_ofdm_power_reg(hw, index, &writeval[0]);
 397         }
 398 }
 399
 400 bool rtl8723be_phy_rf6052_config(struct ieee80211_hw *hw)
 401 {
 402         struct rtl_priv *rtlpriv = rtl_priv(hw);
 403         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 404
 405         if (rtlphy->rf_type == RF_1T1R)
 406                 rtlphy->num_total_rfpath = 1;
 407         else
 408                 rtlphy->num_total_rfpath = 2;
 409
 410         return _rtl8723be_phy_rf6052_config_parafile(hw);
 411
 412 }
 413
 414 static bool _rtl8723be_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
 415 {
 416         struct rtl_priv *rtlpriv = rtl_priv(hw);
 417         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 418         u32 u4_regvalue = 0;
 419         u8 rfpath;
 420         bool rtstatus = true;
 421         struct bb_reg_def *pphyreg;
 422
 423         for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
 424                 pphyreg = &rtlphy->phyreg_def[rfpath];
 425
 426                 switch (rfpath) {
 427                 case RF90_PATH_A:
 428                 case RF90_PATH_C:
 429                         u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
 430                                                     BRFSI_RFENV);
 431                         break;
 432                 case RF90_PATH_B:
 433                 case RF90_PATH_D:
 434                         u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
 435                                                     BRFSI_RFENV << 16);
 436                         break;
 437                 }
 438
 439                 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
 440                 udelay(1);
 441
 442                 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
 443                 udelay(1);
 444
 445                 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
 446                               B3WIREADDREAALENGTH, 0x0);
 447                 udelay(1);
 448
 449                 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
 450                 udelay(1);
 451
 452                 switch (rfpath) {
 453                 case RF90_PATH_A:
 454                         rtstatus = rtl8723be_phy_config_rf_with_headerfile(hw,
 455                                                       (enum radio_path)rfpath);
 456                         break;
 457                 case RF90_PATH_B:
 458                         rtstatus = rtl8723be_phy_config_rf_with_headerfile(hw,
 459                                                       (enum radio_path)rfpath);
 460                         break;
 461                 case RF90_PATH_C:
 462                         break;
 463                 case RF90_PATH_D:
 464                         break;
 465                 }
 466
 467                 switch (rfpath) {
 468                 case RF90_PATH_A:
 469                 case RF90_PATH_C:
 470                         rtl_set_bbreg(hw, pphyreg->rfintfs,
 471                                       BRFSI_RFENV, u4_regvalue);
 472                         break;
 473                 case RF90_PATH_B:
 474                 case RF90_PATH_D:
 475                         rtl_set_bbreg(hw, pphyreg->rfintfs,
 476                                       BRFSI_RFENV << 16, u4_regvalue);
 477                         break;
 478                 }
 479
 480                 if (!rtstatus) {
 481                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 482                                  "Radio[%d] Fail!!\n", rfpath);
 483                         return false;
 484                 }
 485         }
 486
 487         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
 488         return rtstatus;
 489 }