drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
   3
   4 #include "../wifi.h"
   5 #include "../pci.h"
   6 #include "../ps.h"
   7 #include "../core.h"
   8 #include "reg.h"
   9 #include "def.h"
  10 #include "phy.h"
  11 #include "rf.h"
  12 #include "dm.h"
  13 #include "fw.h"
  14 #include "hw.h"
  15 #include "table.h"
  16
  17 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask)
  18 {
  19         u32 i;
  20
  21         for (i = 0; i <= 31; i++) {
  22                 if (((bitmask >> i) & 0x1) == 1)
  23                         break;
  24         }
  25
  26         return i;
  27 }
  28
  29 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
  30 {
  31         struct rtl_priv *rtlpriv = rtl_priv(hw);
  32         u32 returnvalue = 0, originalvalue, bitshift;
  33
  34         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
  35                 regaddr, bitmask);
  36
  37         originalvalue = rtl_read_dword(rtlpriv, regaddr);
  38         bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
  39         returnvalue = (originalvalue & bitmask) >> bitshift;
  40
  41         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
  42                 bitmask, regaddr, originalvalue);
  43
  44         return returnvalue;
  45
  46 }
  47
  48 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
  49                            u32 data)
  50 {
  51         struct rtl_priv *rtlpriv = rtl_priv(hw);
  52         u32 originalvalue, bitshift;
  53
  54         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
  55                 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  56                 regaddr, bitmask, data);
  57
  58         if (bitmask != MASKDWORD) {
  59                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
  60                 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
  61                 data = ((originalvalue & (~bitmask)) | (data << bitshift));
  62         }
  63
  64         rtl_write_dword(rtlpriv, regaddr, data);
  65
  66         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
  67                 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  68                 regaddr, bitmask, data);
  69
  70 }
  71
  72 static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw,
  73                                       enum radio_path rfpath, u32 offset)
  74 {
  75
  76         struct rtl_priv *rtlpriv = rtl_priv(hw);
  77         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  78         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
  79         u32 newoffset;
  80         u32 tmplong, tmplong2;
  81         u8 rfpi_enable = 0;
  82         u32 retvalue = 0;
  83
  84         offset &= 0x3f;
  85         newoffset = offset;
  86
  87         tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
  88
  89         if (rfpath == RF90_PATH_A)
  90                 tmplong2 = tmplong;
  91         else
  92                 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
  93
  94         tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) |
  95                         BLSSI_READEDGE;
  96
  97         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
  98                       tmplong & (~BLSSI_READEDGE));
  99
 100         mdelay(1);
 101
 102         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
 103         mdelay(1);
 104
 105         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |
 106                       BLSSI_READEDGE);
 107         mdelay(1);
 108
 109         if (rfpath == RF90_PATH_A)
 110                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 111                                                 BIT(8));
 112         else if (rfpath == RF90_PATH_B)
 113                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 114                                                 BIT(8));
 115
 116         if (rfpi_enable)
 117                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
 118                                          BLSSI_READBACK_DATA);
 119         else
 120                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 121                                          BLSSI_READBACK_DATA);
 122
 123         retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 124                                  BLSSI_READBACK_DATA);
 125
 126         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
 127                 rfpath, pphyreg->rf_rb, retvalue);
 128
 129         return retvalue;
 130
 131 }
 132
 133 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw,
 134                                         enum radio_path rfpath, u32 offset,
 135                                         u32 data)
 136 {
 137         struct rtl_priv *rtlpriv = rtl_priv(hw);
 138         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 139         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 140         u32 data_and_addr = 0;
 141         u32 newoffset;
 142
 143         offset &= 0x3f;
 144         newoffset = offset;
 145
 146         data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 147         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 148
 149         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
 150                 rfpath, pphyreg->rf3wire_offset, data_and_addr);
 151 }
 152
 153
 154 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
 155                             u32 regaddr, u32 bitmask)
 156 {
 157         struct rtl_priv *rtlpriv = rtl_priv(hw);
 158         u32 original_value, readback_value, bitshift;
 159
 160         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 161                 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
 162                  regaddr, rfpath, bitmask);
 163
 164         spin_lock(&rtlpriv->locks.rf_lock);
 165
 166         original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr);
 167
 168         bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
 169         readback_value = (original_value & bitmask) >> bitshift;
 170
 171         spin_unlock(&rtlpriv->locks.rf_lock);
 172
 173         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 174                 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
 175                 regaddr, rfpath, bitmask, original_value);
 176
 177         return readback_value;
 178 }
 179
 180 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
 181                            u32 regaddr, u32 bitmask, u32 data)
 182 {
 183         struct rtl_priv *rtlpriv = rtl_priv(hw);
 184         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 185         u32 original_value, bitshift;
 186
 187         if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
 188                 return;
 189
 190         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 191                 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 192                 regaddr, bitmask, data, rfpath);
 193
 194         spin_lock(&rtlpriv->locks.rf_lock);
 195
 196         if (bitmask != RFREG_OFFSET_MASK) {
 197                 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath,
 198                                                             regaddr);
 199                 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
 200                 data = ((original_value & (~bitmask)) | (data << bitshift));
 201         }
 202
 203         _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data);
 204
 205         spin_unlock(&rtlpriv->locks.rf_lock);
 206
 207         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 208                 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 209                 regaddr, bitmask, data, rfpath);
 210
 211 }
 212
 213 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw,
 214                                       u8 operation)
 215 {
 216         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 217
 218         if (!is_hal_stop(rtlhal)) {
 219                 switch (operation) {
 220                 case SCAN_OPT_BACKUP:
 221                         rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN);
 222                         break;
 223                 case SCAN_OPT_RESTORE:
 224                         rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN);
 225                         break;
 226                 default:
 227                         pr_err("Unknown operation\n");
 228                         break;
 229                 }
 230         }
 231 }
 232
 233 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
 234                             enum nl80211_channel_type ch_type)
 235 {
 236         struct rtl_priv *rtlpriv = rtl_priv(hw);
 237         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 238         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 239         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 240         u8 reg_bw_opmode;
 241
 242         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
 243                 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 244                 "20MHz" : "40MHz");
 245
 246         if (rtlphy->set_bwmode_inprogress)
 247                 return;
 248         if (is_hal_stop(rtlhal))
 249                 return;
 250
 251         rtlphy->set_bwmode_inprogress = true;
 252
 253         reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE);
 254         /* dummy read */
 255         rtl_read_byte(rtlpriv, RRSR + 2);
 256
 257         switch (rtlphy->current_chan_bw) {
 258         case HT_CHANNEL_WIDTH_20:
 259                 reg_bw_opmode |= BW_OPMODE_20MHZ;
 260                 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 261                 break;
 262         case HT_CHANNEL_WIDTH_20_40:
 263                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 264                 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 265                 break;
 266         default:
 267                 pr_err("unknown bandwidth: %#X\n",
 268                        rtlphy->current_chan_bw);
 269                 break;
 270         }
 271
 272         switch (rtlphy->current_chan_bw) {
 273         case HT_CHANNEL_WIDTH_20:
 274                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
 275                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
 276
 277                 if (rtlhal->version >= VERSION_8192S_BCUT)
 278                         rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58);
 279                 break;
 280         case HT_CHANNEL_WIDTH_20_40:
 281                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
 282                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
 283
 284                 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
 285                                 (mac->cur_40_prime_sc >> 1));
 286                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
 287
 288                 if (rtlhal->version >= VERSION_8192S_BCUT)
 289                         rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18);
 290                 break;
 291         default:
 292                 pr_err("unknown bandwidth: %#X\n",
 293                        rtlphy->current_chan_bw);
 294                 break;
 295         }
 296
 297         rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
 298         rtlphy->set_bwmode_inprogress = false;
 299         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
 300 }
 301
 302 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
 303                 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
 304                 u32 para1, u32 para2, u32 msdelay)
 305 {
 306         struct swchnlcmd *pcmd;
 307
 308         if (cmdtable == NULL) {
 309                 WARN_ONCE(true, "rtl8192se: cmdtable cannot be NULL\n");
 310                 return false;
 311         }
 312
 313         if (cmdtableidx >= cmdtablesz)
 314                 return false;
 315
 316         pcmd = cmdtable + cmdtableidx;
 317         pcmd->cmdid = cmdid;
 318         pcmd->para1 = para1;
 319         pcmd->para2 = para2;
 320         pcmd->msdelay = msdelay;
 321
 322         return true;
 323 }
 324
 325 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
 326              u8 channel, u8 *stage, u8 *step, u32 *delay)
 327 {
 328         struct rtl_priv *rtlpriv = rtl_priv(hw);
 329         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 330         struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
 331         u32 precommoncmdcnt;
 332         struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
 333         u32 postcommoncmdcnt;
 334         struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
 335         u32 rfdependcmdcnt;
 336         struct swchnlcmd *currentcmd = NULL;
 337         u8 rfpath;
 338         u8 num_total_rfpath = rtlphy->num_total_rfpath;
 339
 340         precommoncmdcnt = 0;
 341         _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 342                         MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
 343         _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 344                         MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
 345
 346         postcommoncmdcnt = 0;
 347
 348         _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
 349                         MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
 350
 351         rfdependcmdcnt = 0;
 352
 353         WARN_ONCE((channel < 1 || channel > 14),
 354                   "rtl8192se: invalid channel for Zebra: %d\n", channel);
 355
 356         _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 357                                          MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
 358                                          RF_CHNLBW, channel, 10);
 359
 360         _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 361                         MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
 362
 363         do {
 364                 switch (*stage) {
 365                 case 0:
 366                         currentcmd = &precommoncmd[*step];
 367                         break;
 368                 case 1:
 369                         currentcmd = &rfdependcmd[*step];
 370                         break;
 371                 case 2:
 372                         currentcmd = &postcommoncmd[*step];
 373                         break;
 374                 default:
 375                         return true;
 376                 }
 377
 378                 if (currentcmd->cmdid == CMDID_END) {
 379                         if ((*stage) == 2) {
 380                                 return true;
 381                         } else {
 382                                 (*stage)++;
 383                                 (*step) = 0;
 384                                 continue;
 385                         }
 386                 }
 387
 388                 switch (currentcmd->cmdid) {
 389                 case CMDID_SET_TXPOWEROWER_LEVEL:
 390                         rtl92s_phy_set_txpower(hw, channel);
 391                         break;
 392                 case CMDID_WRITEPORT_ULONG:
 393                         rtl_write_dword(rtlpriv, currentcmd->para1,
 394                                         currentcmd->para2);
 395                         break;
 396                 case CMDID_WRITEPORT_USHORT:
 397                         rtl_write_word(rtlpriv, currentcmd->para1,
 398                                        (u16)currentcmd->para2);
 399                         break;
 400                 case CMDID_WRITEPORT_UCHAR:
 401                         rtl_write_byte(rtlpriv, currentcmd->para1,
 402                                        (u8)currentcmd->para2);
 403                         break;
 404                 case CMDID_RF_WRITEREG:
 405                         for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
 406                                 rtlphy->rfreg_chnlval[rfpath] =
 407                                          ((rtlphy->rfreg_chnlval[rfpath] &
 408                                          0xfffffc00) | currentcmd->para2);
 409                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
 410                                               currentcmd->para1,
 411                                               RFREG_OFFSET_MASK,
 412                                               rtlphy->rfreg_chnlval[rfpath]);
 413                         }
 414                         break;
 415                 default:
 416                         pr_err("switch case %#x not processed\n",
 417                                currentcmd->cmdid);
 418                         break;
 419                 }
 420
 421                 break;
 422         } while (true);
 423
 424         (*delay) = currentcmd->msdelay;
 425         (*step)++;
 426         return false;
 427 }
 428
 429 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw)
 430 {
 431         struct rtl_priv *rtlpriv = rtl_priv(hw);
 432         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 433         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 434         u32 delay;
 435         bool ret;
 436
 437         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
 438                 rtlphy->current_channel);
 439
 440         if (rtlphy->sw_chnl_inprogress)
 441                 return 0;
 442
 443         if (rtlphy->set_bwmode_inprogress)
 444                 return 0;
 445
 446         if (is_hal_stop(rtlhal))
 447                 return 0;
 448
 449         rtlphy->sw_chnl_inprogress = true;
 450         rtlphy->sw_chnl_stage = 0;
 451         rtlphy->sw_chnl_step = 0;
 452
 453         do {
 454                 if (!rtlphy->sw_chnl_inprogress)
 455                         break;
 456
 457                 ret = _rtl92s_phy_sw_chnl_step_by_step(hw,
 458                                  rtlphy->current_channel,
 459                                  &rtlphy->sw_chnl_stage,
 460                                  &rtlphy->sw_chnl_step, &delay);
 461                 if (!ret) {
 462                         if (delay > 0)
 463                                 mdelay(delay);
 464                         else
 465                                 continue;
 466                 } else {
 467                         rtlphy->sw_chnl_inprogress = false;
 468                 }
 469                 break;
 470         } while (true);
 471
 472         rtlphy->sw_chnl_inprogress = false;
 473
 474         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
 475
 476         return 1;
 477 }
 478
 479 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw)
 480 {
 481         struct rtl_priv *rtlpriv = rtl_priv(hw);
 482         u8 u1btmp;
 483
 484         u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
 485         u1btmp |= BIT(0);
 486
 487         rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
 488         rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
 489         rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
 490         rtl_write_word(rtlpriv, CMDR, 0x57FC);
 491         udelay(100);
 492
 493         rtl_write_word(rtlpriv, CMDR, 0x77FC);
 494         rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
 495         udelay(10);
 496
 497         rtl_write_word(rtlpriv, CMDR, 0x37FC);
 498         udelay(10);
 499
 500         rtl_write_word(rtlpriv, CMDR, 0x77FC);
 501         udelay(10);
 502
 503         rtl_write_word(rtlpriv, CMDR, 0x57FC);
 504
 505         /* we should chnge GPIO to input mode
 506          * this will drop away current about 25mA*/
 507         rtl8192se_gpiobit3_cfg_inputmode(hw);
 508 }
 509
 510 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
 511                                    enum rf_pwrstate rfpwr_state)
 512 {
 513         struct rtl_priv *rtlpriv = rtl_priv(hw);
 514         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 515         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 516         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 517         bool bresult = true;
 518         u8 i, queue_id;
 519         struct rtl8192_tx_ring *ring = NULL;
 520
 521         if (rfpwr_state == ppsc->rfpwr_state)
 522                 return false;
 523
 524         switch (rfpwr_state) {
 525         case ERFON:{
 526                         if ((ppsc->rfpwr_state == ERFOFF) &&
 527                             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
 528
 529                                 bool rtstatus;
 530                                 u32 initializecount = 0;
 531                                 do {
 532                                         initializecount++;
 533                                         rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
 534                                                 "IPS Set eRf nic enable\n");
 535                                         rtstatus = rtl_ps_enable_nic(hw);
 536                                 } while (!rtstatus && (initializecount < 10));
 537
 538                                 RT_CLEAR_PS_LEVEL(ppsc,
 539                                                   RT_RF_OFF_LEVL_HALT_NIC);
 540                         } else {
 541                                 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
 542                                         "awake, slept:%d ms state_inap:%x\n",
 543                                         jiffies_to_msecs(jiffies -
 544                                         ppsc->last_sleep_jiffies),
 545                                         rtlpriv->psc.state_inap);
 546                                 ppsc->last_awake_jiffies = jiffies;
 547                                 rtl_write_word(rtlpriv, CMDR, 0x37FC);
 548                                 rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
 549                                 rtl_write_byte(rtlpriv, PHY_CCA, 0x3);
 550                         }
 551
 552                         if (mac->link_state == MAC80211_LINKED)
 553                                 rtlpriv->cfg->ops->led_control(hw,
 554                                                          LED_CTL_LINK);
 555                         else
 556                                 rtlpriv->cfg->ops->led_control(hw,
 557                                                          LED_CTL_NO_LINK);
 558                         break;
 559                 }
 560         case ERFOFF:{
 561                         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
 562                                 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
 563                                         "IPS Set eRf nic disable\n");
 564                                 rtl_ps_disable_nic(hw);
 565                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 566                         } else {
 567                                 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 568                                         rtlpriv->cfg->ops->led_control(hw,
 569                                                          LED_CTL_NO_LINK);
 570                                 else
 571                                         rtlpriv->cfg->ops->led_control(hw,
 572                                                          LED_CTL_POWER_OFF);
 573                         }
 574                         break;
 575                 }
 576         case ERFSLEEP:
 577                         if (ppsc->rfpwr_state == ERFOFF)
 578                                 return false;
 579
 580                         for (queue_id = 0, i = 0;
 581                              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 582                                 ring = &pcipriv->dev.tx_ring[queue_id];
 583                                 if (skb_queue_len(&ring->queue) == 0 ||
 584                                         queue_id == BEACON_QUEUE) {
 585                                         queue_id++;
 586                                         continue;
 587                                 } else {
 588                                         rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
 589                                                 "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
 590                                                 i + 1, queue_id,
 591                                                 skb_queue_len(&ring->queue));
 592
 593                                         udelay(10);
 594                                         i++;
 595                                 }
 596
 597                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 598                                         rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
 599                                                 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
 600                                                 MAX_DOZE_WAITING_TIMES_9x,
 601                                                 queue_id,
 602                                                 skb_queue_len(&ring->queue));
 603                                         break;
 604                                 }
 605                         }
 606
 607                         rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
 608                                 "Set ERFSLEEP awaked:%d ms\n",
 609                                 jiffies_to_msecs(jiffies -
 610                                                  ppsc->last_awake_jiffies));
 611
 612                         rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
 613                                 "sleep awaked:%d ms state_inap:%x\n",
 614                                 jiffies_to_msecs(jiffies -
 615                                                  ppsc->last_awake_jiffies),
 616                                  rtlpriv->psc.state_inap);
 617                         ppsc->last_sleep_jiffies = jiffies;
 618                         _rtl92se_phy_set_rf_sleep(hw);
 619                         break;
 620         default:
 621                 pr_err("switch case %#x not processed\n",
 622                        rfpwr_state);
 623                 bresult = false;
 624                 break;
 625         }
 626
 627         if (bresult)
 628                 ppsc->rfpwr_state = rfpwr_state;
 629
 630         return bresult;
 631 }
 632
 633 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw,
 634                                                  enum radio_path rfpath)
 635 {
 636         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 637         bool rtstatus = true;
 638         u32 tmpval = 0;
 639
 640         /* If inferiority IC, we have to increase the PA bias current */
 641         if (rtlhal->ic_class != IC_INFERIORITY_A) {
 642                 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf);
 643                 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1);
 644         }
 645
 646         return rtstatus;
 647 }
 648
 649 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
 650                 u32 reg_addr, u32 bitmask, u32 data)
 651 {
 652         struct rtl_priv *rtlpriv = rtl_priv(hw);
 653         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 654         int index;
 655
 656         if (reg_addr == RTXAGC_RATE18_06)
 657                 index = 0;
 658         else if (reg_addr == RTXAGC_RATE54_24)
 659                 index = 1;
 660         else if (reg_addr == RTXAGC_CCK_MCS32)
 661                 index = 6;
 662         else if (reg_addr == RTXAGC_MCS03_MCS00)
 663                 index = 2;
 664         else if (reg_addr == RTXAGC_MCS07_MCS04)
 665                 index = 3;
 666         else if (reg_addr == RTXAGC_MCS11_MCS08)
 667                 index = 4;
 668         else if (reg_addr == RTXAGC_MCS15_MCS12)
 669                 index = 5;
 670         else
 671                 return;
 672
 673         rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
 674         if (index == 5)
 675                 rtlphy->pwrgroup_cnt++;
 676 }
 677
 678 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw)
 679 {
 680         struct rtl_priv *rtlpriv = rtl_priv(hw);
 681         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 682
 683         /*RF Interface Sowrtware Control */
 684         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 685         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 686         rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 687         rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 688
 689         /* RF Interface Readback Value */
 690         rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 691         rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 692         rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 693         rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 694
 695         /* RF Interface Output (and Enable) */
 696         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
 697         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
 698         rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;
 699         rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE;
 700
 701         /* RF Interface (Output and)  Enable */
 702         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
 703         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
 704         rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;
 705         rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE;
 706
 707         /* Addr of LSSI. Wirte RF register by driver */
 708         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
 709                                                  RFPGA0_XA_LSSIPARAMETER;
 710         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
 711                                                  RFPGA0_XB_LSSIPARAMETER;
 712         rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =
 713                                                  RFPGA0_XC_LSSIPARAMETER;
 714         rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset =
 715                                                  RFPGA0_XD_LSSIPARAMETER;
 716
 717         /* RF parameter */
 718         rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 719         rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 720         rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 721         rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 722
 723         /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
 724         rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 725         rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 726         rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 727         rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 728
 729         /* Tranceiver A~D HSSI Parameter-1 */
 730         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
 731         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
 732         rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;
 733         rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1;
 734
 735         /* Tranceiver A~D HSSI Parameter-2 */
 736         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
 737         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
 738         rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;
 739         rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2;
 740
 741         /* RF switch Control */
 742         rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 743         rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 744         rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 745         rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 746
 747         /* AGC control 1  */
 748         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
 749         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
 750         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
 751         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
 752
 753         /* AGC control 2  */
 754         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
 755         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
 756         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
 757         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
 758
 759         /* RX AFE control 1  */
 760         rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
 761         rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
 762         rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
 763         rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
 764
 765         /* RX AFE control 1   */
 766         rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
 767         rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
 768         rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
 769         rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
 770
 771         /* Tx AFE control 1  */
 772         rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
 773         rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
 774         rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
 775         rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
 776
 777         /* Tx AFE control 2  */
 778         rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
 779         rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
 780         rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
 781         rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
 782
 783         /* Tranceiver LSSI Readback */
 784         rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
 785         rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
 786         rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
 787         rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
 788
 789         /* Tranceiver LSSI Readback PI mode  */
 790         rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
 791         rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
 792 }
 793
 794
 795 static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
 796 {
 797         int i;
 798         u32 *phy_reg_table;
 799         u32 *agc_table;
 800         u16 phy_reg_len, agc_len;
 801
 802         agc_len = AGCTAB_ARRAYLENGTH;
 803         agc_table = rtl8192seagctab_array;
 804         /* Default RF_type: 2T2R */
 805         phy_reg_len = PHY_REG_2T2RARRAYLENGTH;
 806         phy_reg_table = rtl8192sephy_reg_2t2rarray;
 807
 808         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 809                 for (i = 0; i < phy_reg_len; i = i + 2) {
 810                         rtl_addr_delay(phy_reg_table[i]);
 811
 812                         /* Add delay for ECS T20 & LG malow platform, */
 813                         udelay(1);
 814
 815                         rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD,
 816                                         phy_reg_table[i + 1]);
 817                 }
 818         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 819                 for (i = 0; i < agc_len; i = i + 2) {
 820                         rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD,
 821                                         agc_table[i + 1]);
 822
 823                         /* Add delay for ECS T20 & LG malow platform */
 824                         udelay(1);
 825                 }
 826         }
 827
 828         return true;
 829 }
 830
 831 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
 832                                           u8 configtype)
 833 {
 834         struct rtl_priv *rtlpriv = rtl_priv(hw);
 835         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 836         u32 *phy_regarray2xtxr_table;
 837         u16 phy_regarray2xtxr_len;
 838         int i;
 839
 840         if (rtlphy->rf_type == RF_1T1R) {
 841                 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray;
 842                 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH;
 843         } else if (rtlphy->rf_type == RF_1T2R) {
 844                 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray;
 845                 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH;
 846         } else {
 847                 return false;
 848         }
 849
 850         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 851                 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
 852                         rtl_addr_delay(phy_regarray2xtxr_table[i]);
 853
 854                         rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
 855                                 phy_regarray2xtxr_table[i + 1],
 856                                 phy_regarray2xtxr_table[i + 2]);
 857                 }
 858         }
 859
 860         return true;
 861 }
 862
 863 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
 864                                           u8 configtype)
 865 {
 866         int i;
 867         u32 *phy_table_pg;
 868         u16 phy_pg_len;
 869
 870         phy_pg_len = PHY_REG_ARRAY_PGLENGTH;
 871         phy_table_pg = rtl8192sephy_reg_array_pg;
 872
 873         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 874                 for (i = 0; i < phy_pg_len; i = i + 3) {
 875                         rtl_addr_delay(phy_table_pg[i]);
 876
 877                         _rtl92s_store_pwrindex_diffrate_offset(hw,
 878                                         phy_table_pg[i],
 879                                         phy_table_pg[i + 1],
 880                                         phy_table_pg[i + 2]);
 881                         rtl92s_phy_set_bb_reg(hw, phy_table_pg[i],
 882                                         phy_table_pg[i + 1],
 883                                         phy_table_pg[i + 2]);
 884                 }
 885         }
 886
 887         return true;
 888 }
 889
 890 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw)
 891 {
 892         struct rtl_priv *rtlpriv = rtl_priv(hw);
 893         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 894         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 895         bool rtstatus = true;
 896
 897         /* 1. Read PHY_REG.TXT BB INIT!! */
 898         /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */
 899         if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R ||
 900             rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) {
 901                 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG);
 902
 903                 if (rtlphy->rf_type != RF_2T2R &&
 904                     rtlphy->rf_type != RF_2T2R_GREEN)
 905                         /* so we should reconfig BB reg with the right
 906                          * PHY parameters. */
 907                         rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw,
 908                                                 BASEBAND_CONFIG_PHY_REG);
 909         } else {
 910                 rtstatus = false;
 911         }
 912
 913         if (!rtstatus) {
 914                 pr_err("Write BB Reg Fail!!\n");
 915                 goto phy_bb8190_config_parafile_fail;
 916         }
 917
 918         /* 2. If EEPROM or EFUSE autoload OK, We must config by
 919          *    PHY_REG_PG.txt */
 920         if (rtlefuse->autoload_failflag == false) {
 921                 rtlphy->pwrgroup_cnt = 0;
 922
 923                 rtstatus = _rtl92s_phy_config_bb_with_pg(hw,
 924                                                  BASEBAND_CONFIG_PHY_REG);
 925         }
 926         if (!rtstatus) {
 927                 pr_err("_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
 928                 goto phy_bb8190_config_parafile_fail;
 929         }
 930
 931         /* 3. BB AGC table Initialization */
 932         rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
 933
 934         if (!rtstatus) {
 935                 pr_err("%s(): AGC Table Fail\n", __func__);
 936                 goto phy_bb8190_config_parafile_fail;
 937         }
 938
 939         /* Check if the CCK HighPower is turned ON. */
 940         /* This is used to calculate PWDB. */
 941         rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
 942                         RFPGA0_XA_HSSIPARAMETER2, 0x200));
 943
 944 phy_bb8190_config_parafile_fail:
 945         return rtstatus;
 946 }
 947
 948 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
 949 {
 950         struct rtl_priv *rtlpriv = rtl_priv(hw);
 951         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 952         int i;
 953         bool rtstatus = true;
 954         u32 *radio_a_table;
 955         u32 *radio_b_table;
 956         u16 radio_a_tblen, radio_b_tblen;
 957
 958         radio_a_tblen = RADIOA_1T_ARRAYLENGTH;
 959         radio_a_table = rtl8192seradioa_1t_array;
 960
 961         /* Using Green mode array table for RF_2T2R_GREEN */
 962         if (rtlphy->rf_type == RF_2T2R_GREEN) {
 963                 radio_b_table = rtl8192seradiob_gm_array;
 964                 radio_b_tblen = RADIOB_GM_ARRAYLENGTH;
 965         } else {
 966                 radio_b_table = rtl8192seradiob_array;
 967                 radio_b_tblen = RADIOB_ARRAYLENGTH;
 968         }
 969
 970         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
 971         rtstatus = true;
 972
 973         switch (rfpath) {
 974         case RF90_PATH_A:
 975                 for (i = 0; i < radio_a_tblen; i = i + 2) {
 976                         rtl_rfreg_delay(hw, rfpath, radio_a_table[i],
 977                                         MASK20BITS, radio_a_table[i + 1]);
 978
 979                 }
 980
 981                 /* PA Bias current for inferiority IC */
 982                 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath);
 983                 break;
 984         case RF90_PATH_B:
 985                 for (i = 0; i < radio_b_tblen; i = i + 2) {
 986                         rtl_rfreg_delay(hw, rfpath, radio_b_table[i],
 987                                         MASK20BITS, radio_b_table[i + 1]);
 988                 }
 989                 break;
 990         case RF90_PATH_C:
 991                 ;
 992                 break;
 993         case RF90_PATH_D:
 994                 ;
 995                 break;
 996         default:
 997                 break;
 998         }
 999
1000         return rtstatus;
1001 }
1002
1003
1004 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw)
1005 {
1006         struct rtl_priv *rtlpriv = rtl_priv(hw);
1007         u32 i;
1008         u32 arraylength;
1009         u32 *ptrarray;
1010
1011         arraylength = MAC_2T_ARRAYLENGTH;
1012         ptrarray = rtl8192semac_2t_array;
1013
1014         for (i = 0; i < arraylength; i = i + 2)
1015                 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
1016
1017         return true;
1018 }
1019
1020
1021 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw)
1022 {
1023         struct rtl_priv *rtlpriv = rtl_priv(hw);
1024         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1025         bool rtstatus = true;
1026         u8 pathmap, index, rf_num = 0;
1027         u8 path1, path2;
1028
1029         _rtl92s_phy_init_register_definition(hw);
1030
1031         /* Config BB and AGC */
1032         rtstatus = _rtl92s_phy_bb_config_parafile(hw);
1033
1034
1035         /* Check BB/RF confiuration setting. */
1036         /* We only need to configure RF which is turned on. */
1037         path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf));
1038         mdelay(10);
1039         path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
1040         pathmap = path1 | path2;
1041
1042         rtlphy->rf_pathmap = pathmap;
1043         for (index = 0; index < 4; index++) {
1044                 if ((pathmap >> index) & 0x1)
1045                         rf_num++;
1046         }
1047
1048         if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) ||
1049             (rtlphy->rf_type == RF_1T2R && rf_num != 2) ||
1050             (rtlphy->rf_type == RF_2T2R && rf_num != 2) ||
1051             (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) {
1052                 pr_err("RF_Type(%x) does not match RF_Num(%x)!!\n",
1053                        rtlphy->rf_type, rf_num);
1054                 pr_err("path1 0x%x, path2 0x%x, pathmap 0x%x\n",
1055                        path1, path2, pathmap);
1056         }
1057
1058         return rtstatus;
1059 }
1060
1061 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw)
1062 {
1063         struct rtl_priv *rtlpriv = rtl_priv(hw);
1064         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1065
1066         /* Initialize general global value */
1067         if (rtlphy->rf_type == RF_1T1R)
1068                 rtlphy->num_total_rfpath = 1;
1069         else
1070                 rtlphy->num_total_rfpath = 2;
1071
1072         /* Config BB and RF */
1073         return rtl92s_phy_rf6052_config(hw);
1074 }
1075
1076 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1077 {
1078         struct rtl_priv *rtlpriv = rtl_priv(hw);
1079         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1080
1081         /* read rx initial gain */
1082         rtlphy->default_initialgain[0] = rtl_get_bbreg(hw,
1083                         ROFDM0_XAAGCCORE1, MASKBYTE0);
1084         rtlphy->default_initialgain[1] = rtl_get_bbreg(hw,
1085                         ROFDM0_XBAGCCORE1, MASKBYTE0);
1086         rtlphy->default_initialgain[2] = rtl_get_bbreg(hw,
1087                         ROFDM0_XCAGCCORE1, MASKBYTE0);
1088         rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
1089                         ROFDM0_XDAGCCORE1, MASKBYTE0);
1090         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1091                 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1092                 rtlphy->default_initialgain[0],
1093                 rtlphy->default_initialgain[1],
1094                 rtlphy->default_initialgain[2],
1095                 rtlphy->default_initialgain[3]);
1096
1097         /* read framesync */
1098         rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
1099         rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1100                                               MASKDWORD);
1101         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1102                 "Default framesync (0x%x) = 0x%x\n",
1103                 ROFDM0_RXDETECTOR3, rtlphy->framesync);
1104
1105 }
1106
1107 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1108                                           u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1109 {
1110         struct rtl_priv *rtlpriv = rtl_priv(hw);
1111         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1112         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1113         u8 index = (channel - 1);
1114
1115         /* 1. CCK */
1116         /* RF-A */
1117         cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index];
1118         /* RF-B */
1119         cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index];
1120
1121         /* 2. OFDM for 1T or 2T */
1122         if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1123                 /* Read HT 40 OFDM TX power */
1124                 ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1125                 ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
1126         } else if (rtlphy->rf_type == RF_2T2R) {
1127                 /* Read HT 40 OFDM TX power */
1128                 ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1129                 ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1130         } else {
1131                 ofdmpowerlevel[0] = 0;
1132                 ofdmpowerlevel[1] = 0;
1133         }
1134 }
1135
1136 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw,
1137                 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1138 {
1139         struct rtl_priv *rtlpriv = rtl_priv(hw);
1140         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1141
1142         rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1143         rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1144 }
1145
1146 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel)
1147 {
1148         struct rtl_priv *rtlpriv = rtl_priv(hw);
1149         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1150         /* [0]:RF-A, [1]:RF-B */
1151         u8 cckpowerlevel[2], ofdmpowerlevel[2];
1152
1153         if (!rtlefuse->txpwr_fromeprom)
1154                 return;
1155
1156         /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1157          * but the RF-B Tx Power must be calculated by the antenna diff.
1158          * So we have to rewrite Antenna gain offset register here.
1159          * Please refer to BB register 0x80c
1160          * 1. For CCK.
1161          * 2. For OFDM 1T or 2T */
1162         _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
1163                         &ofdmpowerlevel[0]);
1164
1165         rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1166                 "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1167                 channel, cckpowerlevel[0], cckpowerlevel[1],
1168                 ofdmpowerlevel[0], ofdmpowerlevel[1]);
1169
1170         _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1171                         &ofdmpowerlevel[0]);
1172
1173         rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
1174         rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerlevel[0], channel);
1175
1176 }
1177
1178 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw)
1179 {
1180         struct rtl_priv *rtlpriv = rtl_priv(hw);
1181         u16 pollingcnt = 10000;
1182         u32 tmpvalue;
1183
1184         /* Make sure that CMD IO has be accepted by FW. */
1185         do {
1186                 udelay(10);
1187
1188                 tmpvalue = rtl_read_dword(rtlpriv, WFM5);
1189                 if (tmpvalue == 0)
1190                         break;
1191         } while (--pollingcnt);
1192
1193         if (pollingcnt == 0)
1194                 pr_err("Set FW Cmd fail!!\n");
1195 }
1196
1197
1198 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1199 {
1200         struct rtl_priv *rtlpriv = rtl_priv(hw);
1201         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1202         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1203         u32 input, current_aid = 0;
1204
1205         if (is_hal_stop(rtlhal))
1206                 return;
1207
1208         if (hal_get_firmwareversion(rtlpriv) < 0x34)
1209                 goto skip;
1210         /* We re-map RA related CMD IO to combinational ones */
1211         /* if FW version is v.52 or later. */
1212         switch (rtlhal->current_fwcmd_io) {
1213         case FW_CMD_RA_REFRESH_N:
1214                 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB;
1215                 break;
1216         case FW_CMD_RA_REFRESH_BG:
1217                 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB;
1218                 break;
1219         default:
1220                 break;
1221         }
1222
1223 skip:
1224         switch (rtlhal->current_fwcmd_io) {
1225         case FW_CMD_RA_RESET:
1226                 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
1227                 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1228                 rtl92s_phy_chk_fwcmd_iodone(hw);
1229                 break;
1230         case FW_CMD_RA_ACTIVE:
1231                 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
1232                 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1233                 rtl92s_phy_chk_fwcmd_iodone(hw);
1234                 break;
1235         case FW_CMD_RA_REFRESH_N:
1236                 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
1237                 input = FW_RA_REFRESH;
1238                 rtl_write_dword(rtlpriv, WFM5, input);
1239                 rtl92s_phy_chk_fwcmd_iodone(hw);
1240                 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK);
1241                 rtl92s_phy_chk_fwcmd_iodone(hw);
1242                 break;
1243         case FW_CMD_RA_REFRESH_BG:
1244                 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG,
1245                         "FW_CMD_RA_REFRESH_BG\n");
1246                 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1247                 rtl92s_phy_chk_fwcmd_iodone(hw);
1248                 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
1249                 rtl92s_phy_chk_fwcmd_iodone(hw);
1250                 break;
1251         case FW_CMD_RA_REFRESH_N_COMB:
1252                 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG,
1253                         "FW_CMD_RA_REFRESH_N_COMB\n");
1254                 input = FW_RA_IOT_N_COMB;
1255                 rtl_write_dword(rtlpriv, WFM5, input);
1256                 rtl92s_phy_chk_fwcmd_iodone(hw);
1257                 break;
1258         case FW_CMD_RA_REFRESH_BG_COMB:
1259                 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG,
1260                         "FW_CMD_RA_REFRESH_BG_COMB\n");
1261                 input = FW_RA_IOT_BG_COMB;
1262                 rtl_write_dword(rtlpriv, WFM5, input);
1263                 rtl92s_phy_chk_fwcmd_iodone(hw);
1264                 break;
1265         case FW_CMD_IQK_ENABLE:
1266                 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
1267                 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
1268                 rtl92s_phy_chk_fwcmd_iodone(hw);
1269                 break;
1270         case FW_CMD_PAUSE_DM_BY_SCAN:
1271                 /* Lower initial gain */
1272                 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1273                 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1274                 /* CCA threshold */
1275                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1276                 break;
1277         case FW_CMD_RESUME_DM_BY_SCAN:
1278                 /* CCA threshold */
1279                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1280                 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1281                 break;
1282         case FW_CMD_HIGH_PWR_DISABLE:
1283                 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE)
1284                         break;
1285
1286                 /* Lower initial gain */
1287                 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1288                 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1289                 /* CCA threshold */
1290                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1291                 break;
1292         case FW_CMD_HIGH_PWR_ENABLE:
1293                 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1294                         rtlpriv->dm.dynamic_txpower_enable)
1295                         break;
1296
1297                 /* CCA threshold */
1298                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1299                 break;
1300         case FW_CMD_LPS_ENTER:
1301                 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
1302                 current_aid = rtlpriv->mac80211.assoc_id;
1303                 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
1304                                 ((current_aid | 0xc000) << 8)));
1305                 rtl92s_phy_chk_fwcmd_iodone(hw);
1306                 /* FW set TXOP disable here, so disable EDCA
1307                  * turbo mode until driver leave LPS */
1308                 break;
1309         case FW_CMD_LPS_LEAVE:
1310                 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
1311                 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
1312                 rtl92s_phy_chk_fwcmd_iodone(hw);
1313                 break;
1314         case FW_CMD_ADD_A2_ENTRY:
1315                 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
1316                 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
1317                 rtl92s_phy_chk_fwcmd_iodone(hw);
1318                 break;
1319         case FW_CMD_CTRL_DM_BY_DRIVER:
1320                 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1321                         "FW_CMD_CTRL_DM_BY_DRIVER\n");
1322                 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
1323                 rtl92s_phy_chk_fwcmd_iodone(hw);
1324                 break;
1325
1326         default:
1327                 break;
1328         }
1329
1330         rtl92s_phy_chk_fwcmd_iodone(hw);
1331
1332         /* Clear FW CMD operation flag. */
1333         rtlhal->set_fwcmd_inprogress = false;
1334 }
1335
1336 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1337 {
1338         struct rtl_priv *rtlpriv = rtl_priv(hw);
1339         struct dig_t *digtable = &rtlpriv->dm_digtable;
1340         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1341         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1342         u32     fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv);
1343         u16     fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
1344         bool postprocessing = false;
1345
1346         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1347                 "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1348                 fw_cmdio, rtlhal->set_fwcmd_inprogress);
1349
1350         do {
1351                 /* We re-map to combined FW CMD ones if firmware version */
1352                 /* is v.53 or later. */
1353                 if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1354                         switch (fw_cmdio) {
1355                         case FW_CMD_RA_REFRESH_N:
1356                                 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB;
1357                                 break;
1358                         case FW_CMD_RA_REFRESH_BG:
1359                                 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB;
1360                                 break;
1361                         default:
1362                                 break;
1363                         }
1364                 } else {
1365                         if ((fw_cmdio == FW_CMD_IQK_ENABLE) ||
1366                             (fw_cmdio == FW_CMD_RA_REFRESH_N) ||
1367                             (fw_cmdio == FW_CMD_RA_REFRESH_BG)) {
1368                                 postprocessing = true;
1369                                 break;
1370                         }
1371                 }
1372
1373                 /* If firmware version is v.62 or later,
1374                  * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
1375                 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) {
1376                         if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER)
1377                                 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
1378                 }
1379
1380
1381                 /* We shall revise all FW Cmd IO into Reg0x364
1382                  * DM map table in the future. */
1383                 switch (fw_cmdio) {
1384                 case FW_CMD_RA_INIT:
1385                         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
1386                         fw_cmdmap |= FW_RA_INIT_CTL;
1387                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1388                         /* Clear control flag to sync with FW. */
1389                         FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL);
1390                         break;
1391                 case FW_CMD_DIG_DISABLE:
1392                         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1393                                 "Set DIG disable!!\n");
1394                         fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1395                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1396                         break;
1397                 case FW_CMD_DIG_ENABLE:
1398                 case FW_CMD_DIG_RESUME:
1399                         if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1400                                 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1401                                         "Set DIG enable or resume!!\n");
1402                                 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
1403                                 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1404                         }
1405                         break;
1406                 case FW_CMD_DIG_HALT:
1407                         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1408                                 "Set DIG halt!!\n");
1409                         fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
1410                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1411                         break;
1412                 case FW_CMD_TXPWR_TRACK_THERMAL: {
1413                         u8      thermalval = 0;
1414                         fw_cmdmap |= FW_PWR_TRK_CTL;
1415
1416                         /* Clear FW parameter in terms of thermal parts. */
1417                         fw_param &= FW_PWR_TRK_PARAM_CLR;
1418
1419                         thermalval = rtlpriv->dm.thermalvalue;
1420                         fw_param |= ((thermalval << 24) |
1421                                      (rtlefuse->thermalmeter[0] << 16));
1422
1423                         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1424                                 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1425                                 fw_cmdmap, fw_param);
1426
1427                         FW_CMD_PARA_SET(rtlpriv, fw_param);
1428                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1429
1430                         /* Clear control flag to sync with FW. */
1431                         FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL);
1432                         }
1433                         break;
1434                 /* The following FW CMDs are only compatible to
1435                  * v.53 or later. */
1436                 case FW_CMD_RA_REFRESH_N_COMB:
1437                         fw_cmdmap |= FW_RA_N_CTL;
1438
1439                         /* Clear RA BG mode control. */
1440                         fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL);
1441
1442                         /* Clear FW parameter in terms of RA parts. */
1443                         fw_param &= FW_RA_PARAM_CLR;
1444
1445                         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1446                                 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1447                                 fw_cmdmap, fw_param);
1448
1449                         FW_CMD_PARA_SET(rtlpriv, fw_param);
1450                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1451
1452                         /* Clear control flag to sync with FW. */
1453                         FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL);
1454                         break;
1455                 case FW_CMD_RA_REFRESH_BG_COMB:
1456                         fw_cmdmap |= FW_RA_BG_CTL;
1457
1458                         /* Clear RA n-mode control. */
1459                         fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL);
1460                         /* Clear FW parameter in terms of RA parts. */
1461                         fw_param &= FW_RA_PARAM_CLR;
1462
1463                         FW_CMD_PARA_SET(rtlpriv, fw_param);
1464                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1465
1466                         /* Clear control flag to sync with FW. */
1467                         FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL);
1468                         break;
1469                 case FW_CMD_IQK_ENABLE:
1470                         fw_cmdmap |= FW_IQK_CTL;
1471                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1472                         /* Clear control flag to sync with FW. */
1473                         FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL);
1474                         break;
1475                 /* The following FW CMD is compatible to v.62 or later.  */
1476                 case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
1477                         fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL;
1478                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1479                         break;
1480                 /*  The followed FW Cmds needs post-processing later. */
1481                 case FW_CMD_RESUME_DM_BY_SCAN:
1482                         fw_cmdmap |= (FW_DIG_ENABLE_CTL |
1483                                       FW_HIGH_PWR_ENABLE_CTL |
1484                                       FW_SS_CTL);
1485
1486                         if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE ||
1487                                 !digtable->dig_enable_flag)
1488                                 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1489
1490                         if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1491                             rtlpriv->dm.dynamic_txpower_enable)
1492                                 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1493
1494                         if ((digtable->dig_ext_port_stage ==
1495                             DIG_EXT_PORT_STAGE_0) ||
1496                             (digtable->dig_ext_port_stage ==
1497                             DIG_EXT_PORT_STAGE_1))
1498                                 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1499
1500                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1501                         postprocessing = true;
1502                         break;
1503                 case FW_CMD_PAUSE_DM_BY_SCAN:
1504                         fw_cmdmap &= ~(FW_DIG_ENABLE_CTL |
1505                                        FW_HIGH_PWR_ENABLE_CTL |
1506                                        FW_SS_CTL);
1507                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1508                         postprocessing = true;
1509                         break;
1510                 case FW_CMD_HIGH_PWR_DISABLE:
1511                         fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1512                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1513                         postprocessing = true;
1514                         break;
1515                 case FW_CMD_HIGH_PWR_ENABLE:
1516                         if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
1517                             !rtlpriv->dm.dynamic_txpower_enable) {
1518                                 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL |
1519                                               FW_SS_CTL);
1520                                 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1521                                 postprocessing = true;
1522                         }
1523                         break;
1524                 case FW_CMD_DIG_MODE_FA:
1525                         fw_cmdmap |= FW_FA_CTL;
1526                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1527                         break;
1528                 case FW_CMD_DIG_MODE_SS:
1529                         fw_cmdmap &= ~FW_FA_CTL;
1530                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1531                         break;
1532                 case FW_CMD_PAPE_CONTROL:
1533                         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1534                                 "[FW CMD] Set PAPE Control\n");
1535                         fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
1536
1537                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1538                         break;
1539                 default:
1540                         /* Pass to original FW CMD processing callback
1541                          * routine. */
1542                         postprocessing = true;
1543                         break;
1544                 }
1545         } while (false);
1546
1547         /* We shall post processing these FW CMD if
1548          * variable postprocessing is set.
1549          */
1550         if (postprocessing && !rtlhal->set_fwcmd_inprogress) {
1551                 rtlhal->set_fwcmd_inprogress = true;
1552                 /* Update current FW Cmd for callback use. */
1553                 rtlhal->current_fwcmd_io = fw_cmdio;
1554         } else {
1555                 return false;
1556         }
1557
1558         _rtl92s_phy_set_fwcmd_io(hw);
1559         return true;
1560 }
1561
1562 static  void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw)
1563 {
1564         struct rtl_priv *rtlpriv = rtl_priv(hw);
1565         u32     delay = 100;
1566         u8      regu1;
1567
1568         regu1 = rtl_read_byte(rtlpriv, 0x554);
1569         while ((regu1 & BIT(5)) && (delay > 0)) {
1570                 regu1 = rtl_read_byte(rtlpriv, 0x554);
1571                 delay--;
1572                 /* We delay only 50us to prevent
1573                  * being scheduled out. */
1574                 udelay(50);
1575         }
1576 }
1577
1578 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw)
1579 {
1580         struct rtl_priv *rtlpriv = rtl_priv(hw);
1581         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1582
1583         /* The way to be capable to switch clock request
1584          * when the PG setting does not support clock request.
1585          * This is the backdoor solution to switch clock
1586          * request before ASPM or D3. */
1587         rtl_write_dword(rtlpriv, 0x540, 0x73c11);
1588         rtl_write_dword(rtlpriv, 0x548, 0x2407c);
1589
1590         /* Switch EPHY parameter!!!! */
1591         rtl_write_word(rtlpriv, 0x550, 0x1000);
1592         rtl_write_byte(rtlpriv, 0x554, 0x20);
1593         _rtl92s_phy_check_ephy_switchready(hw);
1594
1595         rtl_write_word(rtlpriv, 0x550, 0xa0eb);
1596         rtl_write_byte(rtlpriv, 0x554, 0x3e);
1597         _rtl92s_phy_check_ephy_switchready(hw);
1598
1599         rtl_write_word(rtlpriv, 0x550, 0xff80);
1600         rtl_write_byte(rtlpriv, 0x554, 0x39);
1601         _rtl92s_phy_check_ephy_switchready(hw);
1602
1603         /* Delay L1 enter time */
1604         if (ppsc->support_aspm && !ppsc->support_backdoor)
1605                 rtl_write_byte(rtlpriv, 0x560, 0x40);
1606         else
1607                 rtl_write_byte(rtlpriv, 0x560, 0x00);
1608
1609 }
1610
1611 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval)
1612 {
1613         struct rtl_priv *rtlpriv = rtl_priv(hw);
1614         u32 new_bcn_num = 0;
1615
1616         if (hal_get_firmwareversion(rtlpriv) >= 0x33) {
1617                 /* Fw v.51 and later. */
1618                 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 |
1619                                 (beaconinterval << 8));
1620         } else {
1621                 new_bcn_num = beaconinterval * 32 - 64;
1622                 rtl_write_dword(rtlpriv, WFM3 + 4, new_bcn_num);
1623                 rtl_write_dword(rtlpriv, WFM3, 0xB026007C);
1624         }
1625 }