1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
4 #ifndef __RTL92DE_TRX_H__
5 #define __RTL92DE_TRX_H__
7 #define TX_DESC_SIZE 64
8 #define TX_DESC_AGGR_SUBFRAME_SIZE 32
10 #define RX_DESC_SIZE 32
11 #define RX_DRV_INFO_SIZE_UNIT 8
13 #define TX_DESC_NEXT_DESC_OFFSET 40
14 #define USB_HWDESC_HEADER_LEN 32
17 /* macros to read/write various fields in RX or TX descriptors */
19 #define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
20 le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(15, 0))
21 #define SET_TX_DESC_OFFSET(__pdesc, __val) \
22 le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(23, 16))
23 #define SET_TX_DESC_HTC(__pdesc, __val) \
24 le32p_replace_bits((__le32 *)__pdesc, __val, BIT(25))
25 #define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
26 le32p_replace_bits((__le32 *)__pdesc, __val, BIT(26))
27 #define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
28 le32p_replace_bits((__le32 *)__pdesc, __val, BIT(27))
29 #define SET_TX_DESC_LINIP(__pdesc, __val) \
30 le32p_replace_bits((__le32 *)__pdesc, __val, BIT(28))
31 #define SET_TX_DESC_OWN(__pdesc, __val) \
32 le32p_replace_bits((__le32 *)__pdesc, __val, BIT(31))
34 #define GET_TX_DESC_OWN(__pdesc) \
35 le32_get_bits(*(__le32 *)__pdesc, BIT(31))
37 #define SET_TX_DESC_MACID(__pdesc, __val) \
38 le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(4, 0))
39 #define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
40 le32p_replace_bits((__le32 *)(__pdesc + 4), __val, BIT(5))
41 #define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
42 le32p_replace_bits((__le32 *)(__pdesc + 4), __val, BIT(7))
43 #define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
44 le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(12, 8))
45 #define SET_TX_DESC_RATE_ID(__pdesc, __val) \
46 le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(19, 16))
47 #define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
48 le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(23, 22))
49 #define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
50 le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(30, 26))
52 #define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
53 le32p_replace_bits((__le32 *)(__pdesc + 8), __val, BIT(17))
54 #define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
55 le32p_replace_bits((__le32 *)(__pdesc + 8), __val, GENMASK(22, 20))
57 #define SET_TX_DESC_SEQ(__pdesc, __val) \
58 le32p_replace_bits((__le32 *)(__pdesc + 12), __val, GENMASK(27, 16))
59 #define SET_TX_DESC_PKT_ID(__pdesc, __val) \
60 le32p_replace_bits((__le32 *)(__pdesc + 12), __val, GENMASK(31, 28))
62 #define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
63 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(4, 0))
64 #define SET_TX_DESC_QOS(__pdesc, __val) \
65 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(6))
66 #define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
67 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(7))
68 #define SET_TX_DESC_USE_RATE(__pdesc, __val) \
69 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(8))
70 #define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
71 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(10))
72 #define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
73 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(11))
74 #define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
75 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(12))
76 #define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
77 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(13))
78 #define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
79 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(21, 20))
80 #define SET_TX_DESC_DATA_BW(__pdesc, __val) \
81 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(25))
82 #define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
83 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(26))
84 #define SET_TX_DESC_RTS_BW(__pdesc, __val) \
85 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(27))
86 #define SET_TX_DESC_RTS_SC(__pdesc, __val) \
87 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(29, 28))
88 #define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
89 le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(31, 30))
91 #define SET_TX_DESC_TX_RATE(__pdesc, __val) \
92 le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(5, 0))
93 #define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
94 le32p_replace_bits((__le32 *)(__pdesc + 20), __val, BIT(6))
95 #define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
96 le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(12, 8))
97 #define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
98 le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(16, 13))
100 #define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
101 le32p_replace_bits((__le32 *)(__pdesc + 24), __val, GENMASK(15, 11))
103 #define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
104 le32p_replace_bits((__le32 *)(__pdesc + 28), __val, GENMASK(15, 0))
106 #define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
107 *(__le32 *)(__pdesc + 32) = cpu_to_le32(__val)
109 #define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
110 le32_to_cpu(*(__le32 *)(__pdesc + 32))
112 #define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
113 *(__le32 *)(__pdesc + 40) = cpu_to_le32(__val)
115 #define GET_RX_DESC_PKT_LEN(__pdesc) \
116 le32_get_bits(*(__le32 *)__pdesc, GENMASK(13, 0))
117 #define GET_RX_DESC_CRC32(__pdesc) \
118 le32_get_bits(*(__le32 *)__pdesc, BIT(14))
119 #define GET_RX_DESC_ICV(__pdesc) \
120 le32_get_bits(*(__le32 *)__pdesc, BIT(15))
121 #define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
122 le32_get_bits(*(__le32 *)__pdesc, GENMASK(19, 16))
123 #define GET_RX_DESC_SHIFT(__pdesc) \
124 le32_get_bits(*(__le32 *)__pdesc, GENMASK(25, 24))
125 #define GET_RX_DESC_PHYST(__pdesc) \
126 le32_get_bits(*(__le32 *)__pdesc, BIT(26))
127 #define GET_RX_DESC_SWDEC(__pdesc) \
128 le32_get_bits(*(__le32 *)__pdesc, BIT(27))
129 #define GET_RX_DESC_OWN(__pdesc) \
130 le32_get_bits(*(__le32 *)__pdesc, BIT(31))
132 #define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
133 le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(13, 0))
134 #define SET_RX_DESC_EOR(__pdesc, __val) \
135 le32p_replace_bits((__le32 *)__pdesc, __val, BIT(30))
136 #define SET_RX_DESC_OWN(__pdesc, __val) \
137 le32p_replace_bits((__le32 *)__pdesc, __val, BIT(31))
139 #define GET_RX_DESC_PAGGR(__pdesc) \
140 le32_get_bits(*(__le32 *)(__pdesc + 4), BIT(14))
141 #define GET_RX_DESC_FAGGR(__pdesc) \
142 le32_get_bits(*(__le32 *)(__pdesc + 4), BIT(15))
144 #define GET_RX_DESC_RXMCS(__pdesc) \
145 le32_get_bits(*(__le32 *)(__pdesc + 12), GENMASK(5, 0))
146 #define GET_RX_DESC_RXHT(__pdesc) \
147 le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(6))
148 #define GET_RX_DESC_SPLCP(__pdesc) \
149 le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(8))
150 #define GET_RX_DESC_BW(__pdesc) \
151 le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(9))
153 #define GET_RX_DESC_TSFL(__pdesc) \
154 le32_to_cpu(*(__le32 *)(__pdesc + 20))
156 #define GET_RX_DESC_BUFF_ADDR(__pdesc) \
157 le32_to_cpu(*(__le32 *)(__pdesc + 24))
158 #define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
159 *(__le32 *)(__pdesc + 24) = cpu_to_le32(__val)
161 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
162 memset((void *)__pdesc, 0, \
163 min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET))
165 /* For 92D early mode */
166 #define SET_EARLYMODE_PKTNUM(__paddr, __value) \
167 le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(2, 0))
168 #define SET_EARLYMODE_LEN0(__paddr, __value) \
169 le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(15, 4))
170 #define SET_EARLYMODE_LEN1(__paddr, __value) \
171 le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(27, 16))
172 #define SET_EARLYMODE_LEN2_1(__paddr, __value) \
173 le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(31, 28))
174 #define SET_EARLYMODE_LEN2_2(__paddr, __value) \
175 le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(7, 0))
176 #define SET_EARLYMODE_LEN3(__paddr, __value) \
177 le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(19, 8))
178 #define SET_EARLYMODE_LEN4(__paddr, __value) \
179 le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(31, 20))
181 struct rx_fwinfo_92d {
273 u32 rtsrate_fb_lmt:4;
291 u32 mcsg15sgimaxlen:4;
296 u32 nextdescaddress64;
298 u32 reserve_pass_pcie_mm_limit[4];
359 void rtl92de_tx_fill_desc(struct ieee80211_hw *hw,
360 struct ieee80211_hdr *hdr, u8 *pdesc,
361 u8 *pbd_desc_tx, struct ieee80211_tx_info *info,
362 struct ieee80211_sta *sta,
363 struct sk_buff *skb, u8 hw_queue,
364 struct rtl_tcb_desc *ptcb_desc);
365 bool rtl92de_rx_query_desc(struct ieee80211_hw *hw,
366 struct rtl_stats *stats,
367 struct ieee80211_rx_status *rx_status,
368 u8 *pdesc, struct sk_buff *skb);
369 void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
370 u8 desc_name, u8 *val);
371 u64 rtl92de_get_desc(struct ieee80211_hw *hw,
372 u8 *p_desc, bool istx, u8 desc_name);
373 bool rtl92de_is_tx_desc_closed(struct ieee80211_hw *hw,
374 u8 hw_queue, u16 index);
375 void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
376 void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
377 bool b_firstseg, bool b_lastseg,
378 struct sk_buff *skb);