drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
   3
   4 #include "../wifi.h"
   5 #include "../pci.h"
   6 #include "../ps.h"
   7 #include "../core.h"
   8 #include "reg.h"
   9 #include "def.h"
  10 #include "phy.h"
  11 #include "rf.h"
  12 #include "dm.h"
  13 #include "table.h"
  14 #include "sw.h"
  15 #include "hw.h"
  16
  17 #define MAX_RF_IMR_INDEX                        12
  18 #define MAX_RF_IMR_INDEX_NORMAL                 13
  19 #define RF_REG_NUM_FOR_C_CUT_5G                 6
  20 #define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA      7
  21 #define RF_REG_NUM_FOR_C_CUT_2G                 5
  22 #define RF_CHNL_NUM_5G                          19
  23 #define RF_CHNL_NUM_5G_40M                      17
  24 #define TARGET_CHNL_NUM_5G                      221
  25 #define TARGET_CHNL_NUM_2G                      14
  26 #define CV_CURVE_CNT                            64
  27
  28 static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
  29         0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
  30 };
  31
  32 static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
  33         RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
  34 };
  35
  36 static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
  37         RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
  38 };
  39
  40 static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
  41         0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
  42 };
  43
  44 static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
  45         BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
  46         BIT(10) | BIT(9),
  47         BIT(18) | BIT(17) | BIT(16) | BIT(1),
  48         BIT(2) | BIT(1),
  49         BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
  50 };
  51
  52 static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
  53         36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
  54         112, 116, 120, 124, 128, 132, 136, 140
  55 };
  56
  57 static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
  58         38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
  59         118, 122, 126, 130, 134, 138
  60 };
  61 static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
  62         {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
  63         {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
  64         {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
  65         {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
  66         {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
  67 };
  68
  69 static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
  70         {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
  71         {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
  72         {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
  73 };
  74
  75 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
  76
  77 static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
  78         {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
  79         {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
  80         {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
  81 };
  82
  83 /* [mode][patha+b][reg] */
  84 static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
  85         {
  86                 /* channel 1-14. */
  87                 {
  88                         0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
  89                         0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
  90                 },
  91                 /* path 36-64 */
  92                 {
  93                         0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
  94                         0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
  95                         0x32c9a
  96                 },
  97                 /* 100 -165 */
  98                 {
  99                         0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
 100                         0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
 101                 }
 102         }
 103 };
 104
 105 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
 106
 107 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
 108
 109 static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
 110         25141, 25116, 25091, 25066, 25041,
 111         25016, 24991, 24966, 24941, 24917,
 112         24892, 24867, 24843, 24818, 24794,
 113         24770, 24765, 24721, 24697, 24672,
 114         24648, 24624, 24600, 24576, 24552,
 115         24528, 24504, 24480, 24457, 24433,
 116         24409, 24385, 24362, 24338, 24315,
 117         24291, 24268, 24245, 24221, 24198,
 118         24175, 24151, 24128, 24105, 24082,
 119         24059, 24036, 24013, 23990, 23967,
 120         23945, 23922, 23899, 23876, 23854,
 121         23831, 23809, 23786, 23764, 23741,
 122         23719, 23697, 23674, 23652, 23630,
 123         23608, 23586, 23564, 23541, 23519,
 124         23498, 23476, 23454, 23432, 23410,
 125         23388, 23367, 23345, 23323, 23302,
 126         23280, 23259, 23237, 23216, 23194,
 127         23173, 23152, 23130, 23109, 23088,
 128         23067, 23046, 23025, 23003, 22982,
 129         22962, 22941, 22920, 22899, 22878,
 130         22857, 22837, 22816, 22795, 22775,
 131         22754, 22733, 22713, 22692, 22672,
 132         22652, 22631, 22611, 22591, 22570,
 133         22550, 22530, 22510, 22490, 22469,
 134         22449, 22429, 22409, 22390, 22370,
 135         22350, 22336, 22310, 22290, 22271,
 136         22251, 22231, 22212, 22192, 22173,
 137         22153, 22134, 22114, 22095, 22075,
 138         22056, 22037, 22017, 21998, 21979,
 139         21960, 21941, 21921, 21902, 21883,
 140         21864, 21845, 21826, 21807, 21789,
 141         21770, 21751, 21732, 21713, 21695,
 142         21676, 21657, 21639, 21620, 21602,
 143         21583, 21565, 21546, 21528, 21509,
 144         21491, 21473, 21454, 21436, 21418,
 145         21400, 21381, 21363, 21345, 21327,
 146         21309, 21291, 21273, 21255, 21237,
 147         21219, 21201, 21183, 21166, 21148,
 148         21130, 21112, 21095, 21077, 21059,
 149         21042, 21024, 21007, 20989, 20972,
 150         25679, 25653, 25627, 25601, 25575,
 151         25549, 25523, 25497, 25471, 25446,
 152         25420, 25394, 25369, 25343, 25318,
 153         25292, 25267, 25242, 25216, 25191,
 154         25166
 155 };
 156
 157 /* channel 1~14 */
 158 static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
 159         26084, 26030, 25976, 25923, 25869, 25816, 25764,
 160         25711, 25658, 25606, 25554, 25502, 25451, 25328
 161 };
 162
 163 static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
 164 {
 165         u32 i = ffs(bitmask);
 166
 167         return i ? i - 1 : 32;
 168 }
 169
 170 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
 171 {
 172         struct rtl_priv *rtlpriv = rtl_priv(hw);
 173         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 174         u32 returnvalue, originalvalue, bitshift;
 175
 176         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
 177                 regaddr, bitmask);
 178         if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
 179                 u8 dbi_direct = 0;
 180
 181                 /* mac1 use phy0 read radio_b. */
 182                 /* mac0 use phy1 read radio_b. */
 183                 if (rtlhal->during_mac1init_radioa)
 184                         dbi_direct = BIT(3);
 185                 else if (rtlhal->during_mac0init_radiob)
 186                         dbi_direct = BIT(3) | BIT(2);
 187                 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
 188                         dbi_direct);
 189         } else {
 190                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
 191         }
 192         bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
 193         returnvalue = (originalvalue & bitmask) >> bitshift;
 194         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 195                 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
 196                 bitmask, regaddr, originalvalue);
 197         return returnvalue;
 198 }
 199
 200 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
 201                            u32 regaddr, u32 bitmask, u32 data)
 202 {
 203         struct rtl_priv *rtlpriv = rtl_priv(hw);
 204         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 205         u8 dbi_direct = 0;
 206         u32 originalvalue, bitshift;
 207
 208         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 209                 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
 210                 regaddr, bitmask, data);
 211         if (rtlhal->during_mac1init_radioa)
 212                 dbi_direct = BIT(3);
 213         else if (rtlhal->during_mac0init_radiob)
 214                 /* mac0 use phy1 write radio_b. */
 215                 dbi_direct = BIT(3) | BIT(2);
 216         if (bitmask != MASKDWORD) {
 217                 if (rtlhal->during_mac1init_radioa ||
 218                     rtlhal->during_mac0init_radiob)
 219                         originalvalue = rtl92de_read_dword_dbi(hw,
 220                                         (u16) regaddr,
 221                                         dbi_direct);
 222                 else
 223                         originalvalue = rtl_read_dword(rtlpriv, regaddr);
 224                 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
 225                 data = ((originalvalue & (~bitmask)) | (data << bitshift));
 226         }
 227         if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
 228                 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
 229         else
 230                 rtl_write_dword(rtlpriv, regaddr, data);
 231         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 232                 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
 233                 regaddr, bitmask, data);
 234 }
 235
 236 static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
 237                                       enum radio_path rfpath, u32 offset)
 238 {
 239
 240         struct rtl_priv *rtlpriv = rtl_priv(hw);
 241         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 242         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 243         u32 newoffset;
 244         u32 tmplong, tmplong2;
 245         u8 rfpi_enable = 0;
 246         u32 retvalue;
 247
 248         newoffset = offset;
 249         tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
 250         if (rfpath == RF90_PATH_A)
 251                 tmplong2 = tmplong;
 252         else
 253                 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
 254         tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
 255                 (newoffset << 23) | BLSSIREADEDGE;
 256         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 257                 tmplong & (~BLSSIREADEDGE));
 258         udelay(10);
 259         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
 260         udelay(50);
 261         udelay(50);
 262         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 263                 tmplong | BLSSIREADEDGE);
 264         udelay(10);
 265         if (rfpath == RF90_PATH_A)
 266                 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 267                               BIT(8));
 268         else if (rfpath == RF90_PATH_B)
 269                 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 270                               BIT(8));
 271         if (rfpi_enable)
 272                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
 273                         BLSSIREADBACKDATA);
 274         else
 275                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 276                         BLSSIREADBACKDATA);
 277         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",
 278                 rfpath, pphyreg->rf_rb, retvalue);
 279         return retvalue;
 280 }
 281
 282 static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
 283                                         enum radio_path rfpath,
 284                                         u32 offset, u32 data)
 285 {
 286         u32 data_and_addr;
 287         u32 newoffset;
 288         struct rtl_priv *rtlpriv = rtl_priv(hw);
 289         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 290         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 291
 292         newoffset = offset;
 293         /* T65 RF */
 294         data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 295         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 296         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
 297                 rfpath, pphyreg->rf3wire_offset, data_and_addr);
 298 }
 299
 300 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
 301                             enum radio_path rfpath, u32 regaddr, u32 bitmask)
 302 {
 303         struct rtl_priv *rtlpriv = rtl_priv(hw);
 304         u32 original_value, readback_value, bitshift;
 305
 306         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 307                 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
 308                 regaddr, rfpath, bitmask);
 309         spin_lock(&rtlpriv->locks.rf_lock);
 310         original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
 311         bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
 312         readback_value = (original_value & bitmask) >> bitshift;
 313         spin_unlock(&rtlpriv->locks.rf_lock);
 314         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 315                 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
 316                 regaddr, rfpath, bitmask, original_value);
 317         return readback_value;
 318 }
 319
 320 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
 321         u32 regaddr, u32 bitmask, u32 data)
 322 {
 323         struct rtl_priv *rtlpriv = rtl_priv(hw);
 324         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 325         u32 original_value, bitshift;
 326
 327         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 328                 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 329                 regaddr, bitmask, data, rfpath);
 330         if (bitmask == 0)
 331                 return;
 332         spin_lock(&rtlpriv->locks.rf_lock);
 333         if (rtlphy->rf_mode != RF_OP_BY_FW) {
 334                 if (bitmask != RFREG_OFFSET_MASK) {
 335                         original_value = _rtl92d_phy_rf_serial_read(hw,
 336                                 rfpath, regaddr);
 337                         bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
 338                         data = ((original_value & (~bitmask)) |
 339                                 (data << bitshift));
 340                 }
 341                 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
 342         }
 343         spin_unlock(&rtlpriv->locks.rf_lock);
 344         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 345                 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 346                 regaddr, bitmask, data, rfpath);
 347 }
 348
 349 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
 350 {
 351         struct rtl_priv *rtlpriv = rtl_priv(hw);
 352         u32 i;
 353         u32 arraylength;
 354         u32 *ptrarray;
 355
 356         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
 357         arraylength = MAC_2T_ARRAYLENGTH;
 358         ptrarray = rtl8192de_mac_2tarray;
 359         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n");
 360         for (i = 0; i < arraylength; i = i + 2)
 361                 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
 362         if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
 363                 /* improve 2-stream TX EVM */
 364                 /* rtl_write_byte(rtlpriv, 0x14,0x71); */
 365                 /* AMPDU aggregation number 9 */
 366                 /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
 367                 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
 368         } else {
 369                 /* 92D need to test to decide the num. */
 370                 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
 371         }
 372         return true;
 373 }
 374
 375 static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
 376 {
 377         struct rtl_priv *rtlpriv = rtl_priv(hw);
 378         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 379
 380         /* RF Interface Sowrtware Control */
 381         /* 16 LSBs if read 32-bit from 0x870 */
 382         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 383         /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 384         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 385         /* 16 LSBs if read 32-bit from 0x874 */
 386         rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 387         /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
 388
 389         rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 390         /* RF Interface Readback Value */
 391         /* 16 LSBs if read 32-bit from 0x8E0 */
 392         rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 393         /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
 394         rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 395         /* 16 LSBs if read 32-bit from 0x8E4 */
 396         rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 397         /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
 398         rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 399
 400         /* RF Interface Output (and Enable) */
 401         /* 16 LSBs if read 32-bit from 0x860 */
 402         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
 403         /* 16 LSBs if read 32-bit from 0x864 */
 404         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
 405
 406         /* RF Interface (Output and)  Enable */
 407         /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 408         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
 409         /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 410         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
 411
 412         /* Addr of LSSI. Wirte RF register by driver */
 413         /* LSSI Parameter */
 414         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
 415                                  RFPGA0_XA_LSSIPARAMETER;
 416         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
 417                                  RFPGA0_XB_LSSIPARAMETER;
 418
 419         /* RF parameter */
 420         /* BB Band Select */
 421         rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 422         rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 423         rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 424         rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 425
 426         /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
 427         /* Tx gain stage */
 428         rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 429         /* Tx gain stage */
 430         rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 431         /* Tx gain stage */
 432         rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 433         /* Tx gain stage */
 434         rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 435
 436         /* Tranceiver A~D HSSI Parameter-1 */
 437         /* wire control parameter1 */
 438         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
 439         /* wire control parameter1 */
 440         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
 441
 442         /* Tranceiver A~D HSSI Parameter-2 */
 443         /* wire control parameter2 */
 444         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
 445         /* wire control parameter2 */
 446         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
 447
 448         /* RF switch Control */
 449         /* TR/Ant switch control */
 450         rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 451         rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 452         rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 453         rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 454
 455         /* AGC control 1 */
 456         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
 457         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
 458         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
 459         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
 460
 461         /* AGC control 2  */
 462         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
 463         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
 464         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
 465         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
 466
 467         /* RX AFE control 1 */
 468         rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
 469         rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
 470         rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
 471         rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
 472
 473         /*RX AFE control 1 */
 474         rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
 475         rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
 476         rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
 477         rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
 478
 479         /* Tx AFE control 1 */
 480         rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
 481         rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
 482         rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
 483         rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
 484
 485         /* Tx AFE control 2 */
 486         rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
 487         rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
 488         rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
 489         rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
 490
 491         /* Tranceiver LSSI Readback SI mode */
 492         rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
 493         rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
 494         rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
 495         rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
 496
 497         /* Tranceiver LSSI Readback PI mode */
 498         rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
 499         rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
 500 }
 501
 502 static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
 503         u8 configtype)
 504 {
 505         int i;
 506         u32 *phy_regarray_table;
 507         u32 *agctab_array_table = NULL;
 508         u32 *agctab_5garray_table;
 509         u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
 510         struct rtl_priv *rtlpriv = rtl_priv(hw);
 511         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 512
 513         /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */
 514         if (rtlhal->interfaceindex == 0) {
 515                 agctab_arraylen = AGCTAB_ARRAYLENGTH;
 516                 agctab_array_table = rtl8192de_agctab_array;
 517                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 518                         " ===> phy:MAC0, Rtl819XAGCTAB_Array\n");
 519         } else {
 520                 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
 521                         agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
 522                         agctab_array_table = rtl8192de_agctab_2garray;
 523                         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 524                                 " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n");
 525                 } else {
 526                         agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
 527                         agctab_5garray_table = rtl8192de_agctab_5garray;
 528                         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 529                                 " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n");
 530
 531                 }
 532         }
 533         phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
 534         phy_regarray_table = rtl8192de_phy_reg_2tarray;
 535         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 536                 " ===> phy:Rtl819XPHY_REG_Array_PG\n");
 537         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 538                 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
 539                         rtl_addr_delay(phy_regarray_table[i]);
 540                         rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
 541                                       phy_regarray_table[i + 1]);
 542                         udelay(1);
 543                         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 544                                 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
 545                                 phy_regarray_table[i],
 546                                 phy_regarray_table[i + 1]);
 547                 }
 548         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 549                 if (rtlhal->interfaceindex == 0) {
 550                         for (i = 0; i < agctab_arraylen; i = i + 2) {
 551                                 rtl_set_bbreg(hw, agctab_array_table[i],
 552                                         MASKDWORD,
 553                                         agctab_array_table[i + 1]);
 554                                 /* Add 1us delay between BB/RF register
 555                                  * setting. */
 556                                 udelay(1);
 557                                 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 558                                         "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
 559                                         agctab_array_table[i],
 560                                         agctab_array_table[i + 1]);
 561                         }
 562                         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 563                                 "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n");
 564                 } else {
 565                         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
 566                                 for (i = 0; i < agctab_arraylen; i = i + 2) {
 567                                         rtl_set_bbreg(hw, agctab_array_table[i],
 568                                                 MASKDWORD,
 569                                                 agctab_array_table[i + 1]);
 570                                         /* Add 1us delay between BB/RF register
 571                                          * setting. */
 572                                         udelay(1);
 573                                         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 574                                                 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
 575                                                 agctab_array_table[i],
 576                                                 agctab_array_table[i + 1]);
 577                                 }
 578                                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 579                                         "Load Rtl819XAGCTAB_2GArray\n");
 580                         } else {
 581                                 for (i = 0; i < agctab_5garraylen; i = i + 2) {
 582                                         rtl_set_bbreg(hw,
 583                                                 agctab_5garray_table[i],
 584                                                 MASKDWORD,
 585                                                 agctab_5garray_table[i + 1]);
 586                                         /* Add 1us delay between BB/RF registeri
 587                                          * setting. */
 588                                         udelay(1);
 589                                         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 590                                                 "The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
 591                                                 agctab_5garray_table[i],
 592                                                 agctab_5garray_table[i + 1]);
 593                                 }
 594                                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 595                                         "Load Rtl819XAGCTAB_5GArray\n");
 596                         }
 597                 }
 598         }
 599         return true;
 600 }
 601
 602 static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
 603                                                    u32 regaddr, u32 bitmask,
 604                                                    u32 data)
 605 {
 606         struct rtl_priv *rtlpriv = rtl_priv(hw);
 607         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 608         int index;
 609
 610         if (regaddr == RTXAGC_A_RATE18_06)
 611                 index = 0;
 612         else if (regaddr == RTXAGC_A_RATE54_24)
 613                 index = 1;
 614         else if (regaddr == RTXAGC_A_CCK1_MCS32)
 615                 index = 6;
 616         else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
 617                 index = 7;
 618         else if (regaddr == RTXAGC_A_MCS03_MCS00)
 619                 index = 2;
 620         else if (regaddr == RTXAGC_A_MCS07_MCS04)
 621                 index = 3;
 622         else if (regaddr == RTXAGC_A_MCS11_MCS08)
 623                 index = 4;
 624         else if (regaddr == RTXAGC_A_MCS15_MCS12)
 625                 index = 5;
 626         else if (regaddr == RTXAGC_B_RATE18_06)
 627                 index = 8;
 628         else if (regaddr == RTXAGC_B_RATE54_24)
 629                 index = 9;
 630         else if (regaddr == RTXAGC_B_CCK1_55_MCS32)
 631                 index = 14;
 632         else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
 633                 index = 15;
 634         else if (regaddr == RTXAGC_B_MCS03_MCS00)
 635                 index = 10;
 636         else if (regaddr == RTXAGC_B_MCS07_MCS04)
 637                 index = 11;
 638         else if (regaddr == RTXAGC_B_MCS11_MCS08)
 639                 index = 12;
 640         else if (regaddr == RTXAGC_B_MCS15_MCS12)
 641                 index = 13;
 642         else
 643                 return;
 644
 645         rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
 646         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 647                 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
 648                 rtlphy->pwrgroup_cnt, index,
 649                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);
 650         if (index == 13)
 651                 rtlphy->pwrgroup_cnt++;
 652 }
 653
 654 static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
 655         u8 configtype)
 656 {
 657         struct rtl_priv *rtlpriv = rtl_priv(hw);
 658         int i;
 659         u32 *phy_regarray_table_pg;
 660         u16 phy_regarray_pg_len;
 661
 662         phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
 663         phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
 664         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 665                 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
 666                         rtl_addr_delay(phy_regarray_table_pg[i]);
 667                         _rtl92d_store_pwrindex_diffrate_offset(hw,
 668                                 phy_regarray_table_pg[i],
 669                                 phy_regarray_table_pg[i + 1],
 670                                 phy_regarray_table_pg[i + 2]);
 671                 }
 672         } else {
 673                 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,
 674                         "configtype != BaseBand_Config_PHY_REG\n");
 675         }
 676         return true;
 677 }
 678
 679 static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
 680 {
 681         struct rtl_priv *rtlpriv = rtl_priv(hw);
 682         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 683         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 684         bool rtstatus = true;
 685
 686         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
 687         rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
 688                 BASEBAND_CONFIG_PHY_REG);
 689         if (!rtstatus) {
 690                 pr_err("Write BB Reg Fail!!\n");
 691                 return false;
 692         }
 693
 694         /* if (rtlphy->rf_type == RF_1T2R) {
 695          *      _rtl92c_phy_bb_config_1t(hw);
 696          *     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
 697          *} */
 698
 699         if (rtlefuse->autoload_failflag == false) {
 700                 rtlphy->pwrgroup_cnt = 0;
 701                 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
 702                         BASEBAND_CONFIG_PHY_REG);
 703         }
 704         if (!rtstatus) {
 705                 pr_err("BB_PG Reg Fail!!\n");
 706                 return false;
 707         }
 708         rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
 709                 BASEBAND_CONFIG_AGC_TAB);
 710         if (!rtstatus) {
 711                 pr_err("AGC Table Fail\n");
 712                 return false;
 713         }
 714         rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
 715                 RFPGA0_XA_HSSIPARAMETER2, 0x200));
 716
 717         return true;
 718 }
 719
 720 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
 721 {
 722         struct rtl_priv *rtlpriv = rtl_priv(hw);
 723         u16 regval;
 724         u32 regvaldw;
 725         u8 value;
 726
 727         _rtl92d_phy_init_bb_rf_register_definition(hw);
 728         regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 729         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
 730                        regval | BIT(13) | BIT(0) | BIT(1));
 731         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
 732         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
 733         /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
 734         value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
 735         rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
 736                 RF_SDMRSTB);
 737         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
 738                 FEN_DIO_PCIE | FEN_BB_GLB_RSTN | FEN_BBRSTB);
 739         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
 740         if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
 741                 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
 742                 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
 743         }
 744
 745         return _rtl92d_phy_bb_config(hw);
 746 }
 747
 748 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
 749 {
 750         return rtl92d_phy_rf6052_config(hw);
 751 }
 752
 753 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 754                                           enum rf_content content,
 755                                           enum radio_path rfpath)
 756 {
 757         int i;
 758         u32 *radioa_array_table;
 759         u32 *radiob_array_table;
 760         u16 radioa_arraylen, radiob_arraylen;
 761         struct rtl_priv *rtlpriv = rtl_priv(hw);
 762
 763         radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
 764         radioa_array_table = rtl8192de_radioa_2tarray;
 765         radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
 766         radiob_array_table = rtl8192de_radiob_2tarray;
 767         if (rtlpriv->efuse.internal_pa_5g[0]) {
 768                 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
 769                 radioa_array_table = rtl8192de_radioa_2t_int_paarray;
 770         }
 771         if (rtlpriv->efuse.internal_pa_5g[1]) {
 772                 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
 773                 radiob_array_table = rtl8192de_radiob_2t_int_paarray;
 774         }
 775         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 776                 "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n");
 777         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 778                 "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n");
 779         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
 780
 781         /* this only happens when DMDP, mac0 start on 2.4G,
 782          * mac1 start on 5G, mac 0 has to set phy0&phy1
 783          * pathA or mac1 has to set phy0&phy1 pathA */
 784         if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
 785                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 786                         " ===> althougth Path A, we load radiob.txt\n");
 787                 radioa_arraylen = radiob_arraylen;
 788                 radioa_array_table = radiob_array_table;
 789         }
 790         switch (rfpath) {
 791         case RF90_PATH_A:
 792                 for (i = 0; i < radioa_arraylen; i = i + 2) {
 793                         rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
 794                                         RFREG_OFFSET_MASK,
 795                                         radioa_array_table[i + 1]);
 796                 }
 797                 break;
 798         case RF90_PATH_B:
 799                 for (i = 0; i < radiob_arraylen; i = i + 2) {
 800                         rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
 801                                         RFREG_OFFSET_MASK,
 802                                         radiob_array_table[i + 1]);
 803                 }
 804                 break;
 805         case RF90_PATH_C:
 806         case RF90_PATH_D:
 807                 pr_err("switch case %#x not processed\n", rfpath);
 808                 break;
 809         }
 810         return true;
 811 }
 812
 813 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
 814 {
 815         struct rtl_priv *rtlpriv = rtl_priv(hw);
 816         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 817
 818         rtlphy->default_initialgain[0] =
 819             (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
 820         rtlphy->default_initialgain[1] =
 821             (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
 822         rtlphy->default_initialgain[2] =
 823             (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
 824         rtlphy->default_initialgain[3] =
 825             (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
 826         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 827                 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
 828                 rtlphy->default_initialgain[0],
 829                 rtlphy->default_initialgain[1],
 830                 rtlphy->default_initialgain[2],
 831                 rtlphy->default_initialgain[3]);
 832         rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
 833                                               MASKBYTE0);
 834         rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
 835                                               MASKDWORD);
 836         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 837                 "Default framesync (0x%x) = 0x%x\n",
 838                 ROFDM0_RXDETECTOR3, rtlphy->framesync);
 839 }
 840
 841 static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
 842         u8 *cckpowerlevel, u8 *ofdmpowerlevel)
 843 {
 844         struct rtl_priv *rtlpriv = rtl_priv(hw);
 845         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 846         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
 847         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 848         u8 index = (channel - 1);
 849
 850         /* 1. CCK */
 851         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
 852                 /* RF-A */
 853                 cckpowerlevel[RF90_PATH_A] =
 854                                  rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
 855                 /* RF-B */
 856                 cckpowerlevel[RF90_PATH_B] =
 857                                  rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
 858         } else {
 859                 cckpowerlevel[RF90_PATH_A] = 0;
 860                 cckpowerlevel[RF90_PATH_B] = 0;
 861         }
 862         /* 2. OFDM for 1S or 2S */
 863         if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
 864                 /*  Read HT 40 OFDM TX power */
 865                 ofdmpowerlevel[RF90_PATH_A] =
 866                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
 867                 ofdmpowerlevel[RF90_PATH_B] =
 868                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
 869         } else if (rtlphy->rf_type == RF_2T2R) {
 870                 /* Read HT 40 OFDM TX power */
 871                 ofdmpowerlevel[RF90_PATH_A] =
 872                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
 873                 ofdmpowerlevel[RF90_PATH_B] =
 874                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
 875         }
 876 }
 877
 878 static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
 879         u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
 880 {
 881         struct rtl_priv *rtlpriv = rtl_priv(hw);
 882         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 883
 884         rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
 885         rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
 886 }
 887
 888 static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
 889 {
 890         u8 place = chnl;
 891
 892         if (chnl > 14) {
 893                 for (place = 14; place < sizeof(channel5g); place++) {
 894                         if (channel5g[place] == chnl) {
 895                                 place++;
 896                                 break;
 897                         }
 898                 }
 899         }
 900         return place;
 901 }
 902
 903 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
 904 {
 905         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 906         struct rtl_priv *rtlpriv = rtl_priv(hw);
 907         u8 cckpowerlevel[2], ofdmpowerlevel[2];
 908
 909         if (!rtlefuse->txpwr_fromeprom)
 910                 return;
 911         channel = _rtl92c_phy_get_rightchnlplace(channel);
 912         _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
 913                 &ofdmpowerlevel[0]);
 914         if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
 915                 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
 916                                 &ofdmpowerlevel[0]);
 917         if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
 918                 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
 919         rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
 920 }
 921
 922 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
 923                             enum nl80211_channel_type ch_type)
 924 {
 925         struct rtl_priv *rtlpriv = rtl_priv(hw);
 926         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 927         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 928         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 929         unsigned long flag = 0;
 930         u8 reg_prsr_rsc;
 931         u8 reg_bw_opmode;
 932
 933         if (rtlphy->set_bwmode_inprogress)
 934                 return;
 935         if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
 936                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
 937                         "FALSE driver sleep or unload\n");
 938                 return;
 939         }
 940         rtlphy->set_bwmode_inprogress = true;
 941         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
 942                 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 943                 "20MHz" : "40MHz");
 944         reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
 945         reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
 946         switch (rtlphy->current_chan_bw) {
 947         case HT_CHANNEL_WIDTH_20:
 948                 reg_bw_opmode |= BW_OPMODE_20MHZ;
 949                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 950                 break;
 951         case HT_CHANNEL_WIDTH_20_40:
 952                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 953                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 954
 955                 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
 956                         (mac->cur_40_prime_sc << 5);
 957                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
 958                 break;
 959         default:
 960                 pr_err("unknown bandwidth: %#X\n",
 961                        rtlphy->current_chan_bw);
 962                 break;
 963         }
 964         switch (rtlphy->current_chan_bw) {
 965         case HT_CHANNEL_WIDTH_20:
 966                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
 967                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
 968                 /* SET BIT10 BIT11  for receive cck */
 969                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
 970                               BIT(11), 3);
 971                 break;
 972         case HT_CHANNEL_WIDTH_20_40:
 973                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
 974                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
 975                 /* Set Control channel to upper or lower.
 976                  * These settings are required only for 40MHz */
 977                 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
 978                         rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
 979                         rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
 980                                 (mac->cur_40_prime_sc >> 1));
 981                         rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
 982                 }
 983                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
 984                 /* SET BIT10 BIT11  for receive cck */
 985                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
 986                               BIT(11), 0);
 987                 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
 988                         (mac->cur_40_prime_sc ==
 989                         HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
 990                 break;
 991         default:
 992                 pr_err("unknown bandwidth: %#X\n",
 993                        rtlphy->current_chan_bw);
 994                 break;
 995
 996         }
 997         rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
 998         rtlphy->set_bwmode_inprogress = false;
 999         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
1000 }
1001
1002 static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1003 {
1004         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1005         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1006         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
1007         rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1008 }
1009
1010 static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1011 {
1012         struct rtl_priv *rtlpriv = rtl_priv(hw);
1013         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1014         u8 value8;
1015
1016         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
1017         rtlhal->bandset = band;
1018         rtlhal->current_bandtype = band;
1019         if (IS_92D_SINGLEPHY(rtlhal->version))
1020                 rtlhal->bandset = BAND_ON_BOTH;
1021         /* stop RX/Tx */
1022         _rtl92d_phy_stop_trx_before_changeband(hw);
1023         /* reconfig BB/RF according to wireless mode */
1024         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1025                 /* BB & RF Config */
1026                 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n");
1027                 if (rtlhal->interfaceindex == 1)
1028                         _rtl92d_phy_config_bb_with_headerfile(hw,
1029                                 BASEBAND_CONFIG_AGC_TAB);
1030         } else {
1031                 /* 5G band */
1032                 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n");
1033                 if (rtlhal->interfaceindex == 1)
1034                         _rtl92d_phy_config_bb_with_headerfile(hw,
1035                                 BASEBAND_CONFIG_AGC_TAB);
1036         }
1037         rtl92d_update_bbrf_configuration(hw);
1038         if (rtlhal->current_bandtype == BAND_ON_2_4G)
1039                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1040         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1041
1042         /* 20M BW. */
1043         /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */
1044         rtlhal->reloadtxpowerindex = true;
1045         /* notice fw know band status  0x81[1]/0x53[1] = 0: 5G, 1: 2G */
1046         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1047                 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1048                         0 ? REG_MAC0 : REG_MAC1));
1049                 value8 |= BIT(1);
1050                 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1051                         0 ? REG_MAC0 : REG_MAC1), value8);
1052         } else {
1053                 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1054                         0 ? REG_MAC0 : REG_MAC1));
1055                 value8 &= (~BIT(1));
1056                 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1057                         0 ? REG_MAC0 : REG_MAC1), value8);
1058         }
1059         mdelay(1);
1060         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n");
1061 }
1062
1063 static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1064         u8 channel, u8 rfpath)
1065 {
1066         struct rtl_priv *rtlpriv = rtl_priv(hw);
1067         u32 imr_num = MAX_RF_IMR_INDEX;
1068         u32 rfmask = RFREG_OFFSET_MASK;
1069         u8 group, i;
1070         unsigned long flag = 0;
1071
1072         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath);
1073         if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1074                 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1075                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1076                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1077                 /* fc area 0xd2c */
1078                 if (channel > 99)
1079                         rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1080                                       BIT(14), 2);
1081                 else
1082                         rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1083                                       BIT(14), 1);
1084                 /* leave 0 for channel1-14. */
1085                 group = channel <= 64 ? 1 : 2;
1086                 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1087                 for (i = 0; i < imr_num; i++)
1088                         rtl_set_rfreg(hw, (enum radio_path)rfpath,
1089                                       rf_reg_for_5g_swchnl_normal[i], rfmask,
1090                                       rf_imr_param_normal[0][group][i]);
1091                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1092                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1093         } else {
1094                 /* G band. */
1095                 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
1096                         "Load RF IMR parameters for G band. IMR already setting %d\n",
1097                         rtlpriv->rtlhal.load_imrandiqk_setting_for2g);
1098                 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1099                 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1100                         rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
1101                                 "Load RF IMR parameters for G band. %d\n",
1102                                 rfpath);
1103                         rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1104                         rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1105                         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1106                                       0x00f00000, 0xf);
1107                         imr_num = MAX_RF_IMR_INDEX_NORMAL;
1108                         for (i = 0; i < imr_num; i++) {
1109                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1110                                               rf_reg_for_5g_swchnl_normal[i],
1111                                               RFREG_OFFSET_MASK,
1112                                               rf_imr_param_normal[0][0][i]);
1113                         }
1114                         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1115                                       0x00f00000, 0);
1116                         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1117                         rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1118                 }
1119         }
1120         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1121 }
1122
1123 static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1124         u8 rfpath, u32 *pu4_regval)
1125 {
1126         struct rtl_priv *rtlpriv = rtl_priv(hw);
1127         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1128         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1129
1130         rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
1131         /*----Store original RFENV control type----*/
1132         switch (rfpath) {
1133         case RF90_PATH_A:
1134         case RF90_PATH_C:
1135                 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1136                 break;
1137         case RF90_PATH_B:
1138         case RF90_PATH_D:
1139                 *pu4_regval =
1140                     rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1141                 break;
1142         }
1143         /*----Set RF_ENV enable----*/
1144         rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1145         udelay(1);
1146         /*----Set RF_ENV output high----*/
1147         rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1148         udelay(1);
1149         /* Set bit number of Address and Data for RF register */
1150         /* Set 1 to 4 bits for 8255 */
1151         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1152         udelay(1);
1153         /*Set 0 to 12 bits for 8255 */
1154         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1155         udelay(1);
1156         rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
1157 }
1158
1159 static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1160                                        u32 *pu4_regval)
1161 {
1162         struct rtl_priv *rtlpriv = rtl_priv(hw);
1163         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1164         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1165
1166         rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n");
1167         /*----Restore RFENV control type----*/
1168         switch (rfpath) {
1169         case RF90_PATH_A:
1170         case RF90_PATH_C:
1171                 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1172                 break;
1173         case RF90_PATH_B:
1174         case RF90_PATH_D:
1175                 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1176                               *pu4_regval);
1177                 break;
1178         }
1179         rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n");
1180 }
1181
1182 static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1183 {
1184         struct rtl_priv *rtlpriv = rtl_priv(hw);
1185         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1186         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1187         u8 path = rtlhal->current_bandtype ==
1188             BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1189         u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1190         bool need_pwr_down = false, internal_pa = false;
1191         u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1192
1193         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n");
1194         /* config path A for 5G */
1195         if (rtlhal->current_bandtype == BAND_ON_5G) {
1196                 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1197                 u4tmp = curveindex_5g[channel - 1];
1198                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1199                         "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
1200                 for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1201                         if (channel == rf_chnl_5g[i] && channel <= 140)
1202                                 index = 0;
1203                 }
1204                 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1205                         if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1206                                 index = 1;
1207                 }
1208                 if (channel == 149 || channel == 155 || channel == 161)
1209                         index = 2;
1210                 else if (channel == 151 || channel == 153 || channel == 163
1211                          || channel == 165)
1212                         index = 3;
1213                 else if (channel == 157 || channel == 159)
1214                         index = 4;
1215
1216                 if (rtlhal->macphymode == DUALMAC_DUALPHY
1217                     && rtlhal->interfaceindex == 1) {
1218                         need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1219                         rtlhal->during_mac1init_radioa = true;
1220                         /* asume no this case */
1221                         if (need_pwr_down)
1222                                 _rtl92d_phy_enable_rf_env(hw, path,
1223                                                           &u4regvalue);
1224                 }
1225                 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1226                         if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1227                                 rtl_set_rfreg(hw, (enum radio_path)path,
1228                                               rf_reg_for_c_cut_5g[i],
1229                                               RFREG_OFFSET_MASK, 0xE439D);
1230                         } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1231                                 u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1232                                      0x7FF) | (u4tmp << 11);
1233                                 if (channel == 36)
1234                                         u4tmp2 &= ~(BIT(7) | BIT(6));
1235                                 rtl_set_rfreg(hw, (enum radio_path)path,
1236                                               rf_reg_for_c_cut_5g[i],
1237                                               RFREG_OFFSET_MASK, u4tmp2);
1238                         } else {
1239                                 rtl_set_rfreg(hw, (enum radio_path)path,
1240                                               rf_reg_for_c_cut_5g[i],
1241                                               RFREG_OFFSET_MASK,
1242                                               rf_reg_pram_c_5g[index][i]);
1243                         }
1244                         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
1245                                 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n",
1246                                 rf_reg_for_c_cut_5g[i],
1247                                 rf_reg_pram_c_5g[index][i],
1248                                 path, index,
1249                                 rtl_get_rfreg(hw, (enum radio_path)path,
1250                                               rf_reg_for_c_cut_5g[i],
1251                                               RFREG_OFFSET_MASK));
1252                 }
1253                 if (need_pwr_down)
1254                         _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1255                 if (rtlhal->during_mac1init_radioa)
1256                         rtl92d_phy_powerdown_anotherphy(hw, false);
1257                 if (channel < 149)
1258                         value = 0x07;
1259                 else if (channel >= 149)
1260                         value = 0x02;
1261                 if (channel >= 36 && channel <= 64)
1262                         index = 0;
1263                 else if (channel >= 100 && channel <= 140)
1264                         index = 1;
1265                 else
1266                         index = 2;
1267                 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1268                         rfpath++) {
1269                         if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1270                                 rtlhal->interfaceindex == 1)    /* MAC 1 5G */
1271                                 internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1272                         else
1273                                 internal_pa =
1274                                          rtlpriv->efuse.internal_pa_5g[rfpath];
1275                         if (internal_pa) {
1276                                 for (i = 0;
1277                                      i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1278                                      i++) {
1279                                         rtl_set_rfreg(hw, rfpath,
1280                                                 rf_for_c_cut_5g_internal_pa[i],
1281                                                 RFREG_OFFSET_MASK,
1282                                                 rf_pram_c_5g_int_pa[index][i]);
1283                                         rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
1284                                                 "offset 0x%x value 0x%x path %d index %d\n",
1285                                                 rf_for_c_cut_5g_internal_pa[i],
1286                                                 rf_pram_c_5g_int_pa[index][i],
1287                                                 rfpath, index);
1288                                 }
1289                         } else {
1290                                 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1291                                               mask, value);
1292                         }
1293                 }
1294         } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1295                 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1296                 u4tmp = curveindex_2g[channel - 1];
1297                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1298                         "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
1299                 if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1300                     || channel == 10 || channel == 11 || channel == 12)
1301                         index = 0;
1302                 else if (channel == 3 || channel == 13 || channel == 14)
1303                         index = 1;
1304                 else if (channel >= 5 && channel <= 8)
1305                         index = 2;
1306                 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1307                         path = RF90_PATH_A;
1308                         if (rtlhal->interfaceindex == 0) {
1309                                 need_pwr_down =
1310                                          rtl92d_phy_enable_anotherphy(hw, true);
1311                                 rtlhal->during_mac0init_radiob = true;
1312
1313                                 if (need_pwr_down)
1314                                         _rtl92d_phy_enable_rf_env(hw, path,
1315                                                                   &u4regvalue);
1316                         }
1317                 }
1318                 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1319                         if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1320                                 rtl_set_rfreg(hw, (enum radio_path)path,
1321                                         rf_reg_for_c_cut_2g[i],
1322                                         RFREG_OFFSET_MASK,
1323                                         (rf_reg_param_for_c_cut_2g[index][i] |
1324                                         BIT(17)));
1325                         else
1326                                 rtl_set_rfreg(hw, (enum radio_path)path,
1327                                               rf_reg_for_c_cut_2g[i],
1328                                               RFREG_OFFSET_MASK,
1329                                               rf_reg_param_for_c_cut_2g
1330                                               [index][i]);
1331                         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
1332                                 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n",
1333                                 rf_reg_for_c_cut_2g[i],
1334                                 rf_reg_param_for_c_cut_2g[index][i],
1335                                 rf_reg_mask_for_c_cut_2g[i], path, index,
1336                                 rtl_get_rfreg(hw, (enum radio_path)path,
1337                                               rf_reg_for_c_cut_2g[i],
1338                                               RFREG_OFFSET_MASK));
1339                 }
1340                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1341                         "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1342                         rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1343
1344                 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1345                               RFREG_OFFSET_MASK,
1346                               rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1347                 if (need_pwr_down)
1348                         _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1349                 if (rtlhal->during_mac0init_radiob)
1350                         rtl92d_phy_powerdown_anotherphy(hw, true);
1351         }
1352         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1353 }
1354
1355 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1356 {
1357         u8 channel_all[59] = {
1358                 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1359                 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1360                 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1361                 114, 116, 118, 120, 122, 124, 126, 128, 130,
1362                 132, 134, 136, 138, 140, 149, 151, 153, 155,
1363                 157, 159, 161, 163, 165
1364         };
1365         u8 place = chnl;
1366
1367         if (chnl > 14) {
1368                 for (place = 14; place < sizeof(channel_all); place++) {
1369                         if (channel_all[place] == chnl)
1370                                 return place - 13;
1371                 }
1372         }
1373
1374         return 0;
1375 }
1376
1377 #define MAX_TOLERANCE           5
1378 #define IQK_DELAY_TIME          1       /* ms */
1379 #define MAX_TOLERANCE_92D       3
1380
1381 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1382 static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1383 {
1384         struct rtl_priv *rtlpriv = rtl_priv(hw);
1385         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1386         u32 regeac, rege94, rege9c, regea4;
1387         u8 result = 0;
1388
1389         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK!\n");
1390         /* path-A IQK setting */
1391         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1392         if (rtlhal->interfaceindex == 0) {
1393                 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1394                 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1395         } else {
1396                 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22);
1397                 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22);
1398         }
1399         rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1400         rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206);
1401         /* path-B IQK setting */
1402         if (configpathb) {
1403                 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1404                 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1405                 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1406                 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206);
1407         }
1408         /* LO calibration setting */
1409         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1410         rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1411         /* One shot, path A LOK & IQK */
1412         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "One shot, path A LOK & IQK!\n");
1413         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1414         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1415         /* delay x ms */
1416         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1417                 "Delay %d ms for One shot, path A LOK & IQK\n",
1418                 IQK_DELAY_TIME);
1419         mdelay(IQK_DELAY_TIME);
1420         /* Check failed */
1421         regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1422         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1423         rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1424         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe94 = 0x%x\n", rege94);
1425         rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1426         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe9c = 0x%x\n", rege9c);
1427         regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1428         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xea4 = 0x%x\n", regea4);
1429         if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1430             (((rege9c & 0x03FF0000) >> 16) != 0x42))
1431                 result |= 0x01;
1432         else                    /* if Tx not OK, ignore Rx */
1433                 return result;
1434         /* if Tx is OK, check whether Rx is OK */
1435         if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1436             (((regeac & 0x03FF0000) >> 16) != 0x36))
1437                 result |= 0x02;
1438         else
1439                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A Rx IQK fail!!\n");
1440         return result;
1441 }
1442
1443 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1444 static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1445                                           bool configpathb)
1446 {
1447         struct rtl_priv *rtlpriv = rtl_priv(hw);
1448         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1449         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1450         u32 regeac, rege94, rege9c, regea4;
1451         u8 result = 0;
1452         u8 i;
1453         u8 retrycount = 2;
1454         u32 TXOKBIT = BIT(28), RXOKBIT = BIT(27);
1455
1456         if (rtlhal->interfaceindex == 1) {      /* PHY1 */
1457                 TXOKBIT = BIT(31);
1458                 RXOKBIT = BIT(30);
1459         }
1460         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK!\n");
1461         /* path-A IQK setting */
1462         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1463         rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1464         rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1465         rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307);
1466         rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960);
1467         /* path-B IQK setting */
1468         if (configpathb) {
1469                 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1470                 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1471                 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000);
1472                 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000);
1473         }
1474         /* LO calibration setting */
1475         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1476         rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1477         /* path-A PA on */
1478         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
1479         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30);
1480         for (i = 0; i < retrycount; i++) {
1481                 /* One shot, path A LOK & IQK */
1482                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1483                         "One shot, path A LOK & IQK!\n");
1484                 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1485                 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1486                 /* delay x ms */
1487                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1488                         "Delay %d ms for One shot, path A LOK & IQK.\n",
1489                         IQK_DELAY_TIME);
1490                 mdelay(IQK_DELAY_TIME * 10);
1491                 /* Check failed */
1492                 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1493                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1494                 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1495                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe94 = 0x%x\n", rege94);
1496                 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1497                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe9c = 0x%x\n", rege9c);
1498                 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1499                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xea4 = 0x%x\n", regea4);
1500                 if (!(regeac & TXOKBIT) &&
1501                      (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1502                         result |= 0x01;
1503                 } else { /* if Tx not OK, ignore Rx */
1504                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1505                                 "Path A Tx IQK fail!!\n");
1506                         continue;
1507                 }
1508
1509                 /* if Tx is OK, check whether Rx is OK */
1510                 if (!(regeac & RXOKBIT) &&
1511                     (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1512                         result |= 0x02;
1513                         break;
1514                 } else {
1515                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1516                                 "Path A Rx IQK fail!!\n");
1517                 }
1518         }
1519         /* path A PA off */
1520         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1521                       rtlphy->iqk_bb_backup[0]);
1522         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD,
1523                       rtlphy->iqk_bb_backup[1]);
1524         return result;
1525 }
1526
1527 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1528 static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1529 {
1530         struct rtl_priv *rtlpriv = rtl_priv(hw);
1531         u32 regeac, regeb4, regebc, regec4, regecc;
1532         u8 result = 0;
1533
1534         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B IQK!\n");
1535         /* One shot, path B LOK & IQK */
1536         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "One shot, path A LOK & IQK!\n");
1537         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1538         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1539         /* delay x ms  */
1540         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1541                 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
1542         mdelay(IQK_DELAY_TIME);
1543         /* Check failed */
1544         regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1545         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1546         regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1547         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeb4 = 0x%x\n", regeb4);
1548         regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1549         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xebc = 0x%x\n", regebc);
1550         regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1551         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xec4 = 0x%x\n", regec4);
1552         regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1553         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xecc = 0x%x\n", regecc);
1554         if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1555             (((regebc & 0x03FF0000) >> 16) != 0x42))
1556                 result |= 0x01;
1557         else
1558                 return result;
1559         if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1560             (((regecc & 0x03FF0000) >> 16) != 0x36))
1561                 result |= 0x02;
1562         else
1563                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B Rx IQK fail!!\n");
1564         return result;
1565 }
1566
1567 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1568 static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1569 {
1570         struct rtl_priv *rtlpriv = rtl_priv(hw);
1571         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1572         u32 regeac, regeb4, regebc, regec4, regecc;
1573         u8 result = 0;
1574         u8 i;
1575         u8 retrycount = 2;
1576
1577         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B IQK!\n");
1578         /* path-A IQK setting */
1579         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1580         rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1581         rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1582         rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000);
1583         rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000);
1584
1585         /* path-B IQK setting */
1586         rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1587         rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1588         rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307);
1589         rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960);
1590
1591         /* LO calibration setting */
1592         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1593         rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1594
1595         /* path-B PA on */
1596         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
1597         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30);
1598
1599         for (i = 0; i < retrycount; i++) {
1600                 /* One shot, path B LOK & IQK */
1601                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1602                         "One shot, path A LOK & IQK!\n");
1603                 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000);
1604                 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1605
1606                 /* delay x ms */
1607                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1608                         "Delay %d ms for One shot, path B LOK & IQK.\n", 10);
1609                 mdelay(IQK_DELAY_TIME * 10);
1610
1611                 /* Check failed */
1612                 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1613                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1614                 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1615                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeb4 = 0x%x\n", regeb4);
1616                 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1617                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xebc = 0x%x\n", regebc);
1618                 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1619                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xec4 = 0x%x\n", regec4);
1620                 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1621                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xecc = 0x%x\n", regecc);
1622                 if (!(regeac & BIT(31)) &&
1623                     (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1624                         result |= 0x01;
1625                 else
1626                         continue;
1627                 if (!(regeac & BIT(30)) &&
1628                     (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1629                         result |= 0x02;
1630                         break;
1631                 } else {
1632                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1633                                 "Path B Rx IQK fail!!\n");
1634                 }
1635         }
1636
1637         /* path B PA off */
1638         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1639                       rtlphy->iqk_bb_backup[0]);
1640         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD,
1641                       rtlphy->iqk_bb_backup[2]);
1642         return result;
1643 }
1644
1645 static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1646                                             u32 *adda_reg, u32 *adda_backup,
1647                                             u32 regnum)
1648 {
1649         struct rtl_priv *rtlpriv = rtl_priv(hw);
1650         u32 i;
1651
1652         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Save ADDA parameters.\n");
1653         for (i = 0; i < regnum; i++)
1654                 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD);
1655 }
1656
1657 static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1658         u32 *macreg, u32 *macbackup)
1659 {
1660         struct rtl_priv *rtlpriv = rtl_priv(hw);
1661         u32 i;
1662
1663         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Save MAC parameters.\n");
1664         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1665                 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1666         macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1667 }
1668
1669 static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1670                                               u32 *adda_reg, u32 *adda_backup,
1671                                               u32 regnum)
1672 {
1673         struct rtl_priv *rtlpriv = rtl_priv(hw);
1674         u32 i;
1675
1676         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1677                 "Reload ADDA power saving parameters !\n");
1678         for (i = 0; i < regnum; i++)
1679                 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]);
1680 }
1681
1682 static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1683                                              u32 *macreg, u32 *macbackup)
1684 {
1685         struct rtl_priv *rtlpriv = rtl_priv(hw);
1686         u32 i;
1687
1688         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Reload MAC parameters !\n");
1689         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1690                 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1691         rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1692 }
1693
1694 static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1695                 u32 *adda_reg, bool patha_on, bool is2t)
1696 {
1697         struct rtl_priv *rtlpriv = rtl_priv(hw);
1698         u32 pathon;
1699         u32 i;
1700
1701         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "ADDA ON.\n");
1702         pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1703         if (patha_on)
1704                 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1705                     0x04db25a4 : 0x0b1b25a4;
1706         for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1707                 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon);
1708 }
1709
1710 static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1711                                                 u32 *macreg, u32 *macbackup)
1712 {
1713         struct rtl_priv *rtlpriv = rtl_priv(hw);
1714         u32 i;
1715
1716         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "MAC settings for Calibration.\n");
1717         rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1718
1719         for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1720                 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1721                                (~BIT(3))));
1722         rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1723 }
1724
1725 static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1726 {
1727         struct rtl_priv *rtlpriv = rtl_priv(hw);
1728         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A standby mode!\n");
1729
1730         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1731         rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000);
1732         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1733 }
1734
1735 static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1736 {
1737         struct rtl_priv *rtlpriv = rtl_priv(hw);
1738         u32 mode;
1739
1740         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1741                 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
1742         mode = pi_mode ? 0x01000100 : 0x01000000;
1743         rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1744         rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1745 }
1746
1747 static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1748                                      u8 t, bool is2t)
1749 {
1750         struct rtl_priv *rtlpriv = rtl_priv(hw);
1751         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1752         u32 i;
1753         u8 patha_ok, pathb_ok;
1754         static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1755                 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1756                 0xe78, 0xe7c, 0xe80, 0xe84,
1757                 0xe88, 0xe8c, 0xed0, 0xed4,
1758                 0xed8, 0xedc, 0xee0, 0xeec
1759         };
1760         static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1761                 0x522, 0x550, 0x551, 0x040
1762         };
1763         static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1764                 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1765                 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1766                 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1767                 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1768                 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1769         };
1770         const u32 retrycount = 2;
1771         u32 bbvalue;
1772
1773         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK for 2.4G :Start!!!\n");
1774         if (t == 0) {
1775                 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1776                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "==>0x%08x\n", bbvalue);
1777                 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1778                         is2t ? "2T2R" : "1T1R");
1779
1780                 /*  Save ADDA parameters, turn Path A ADDA on */
1781                 _rtl92d_phy_save_adda_registers(hw, adda_reg,
1782                         rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1783                 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1784                         rtlphy->iqk_mac_backup);
1785                 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1786                         rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
1787         }
1788         _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1789         if (t == 0)
1790                 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1791                                 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1792
1793         /*  Switch BB to PI mode to do IQ Calibration. */
1794         if (!rtlphy->rfpi_enable)
1795                 _rtl92d_phy_pimode_switch(hw, true);
1796
1797         rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1798         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1799         rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1800         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
1801         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1802         if (is2t) {
1803                 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD,
1804                               0x00010000);
1805                 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD,
1806                               0x00010000);
1807         }
1808         /* MAC settings */
1809         _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1810                                             rtlphy->iqk_mac_backup);
1811         /* Page B init */
1812         rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1813         if (is2t)
1814                 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1815         /* IQ calibration setting */
1816         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK setting!\n");
1817         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1818         rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1819         rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1820         for (i = 0; i < retrycount; i++) {
1821                 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
1822                 if (patha_ok == 0x03) {
1823                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1824                                 "Path A IQK Success!!\n");
1825                         result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1826                                         0x3FF0000) >> 16;
1827                         result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1828                                         0x3FF0000) >> 16;
1829                         result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1830                                         0x3FF0000) >> 16;
1831                         result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1832                                         0x3FF0000) >> 16;
1833                         break;
1834                 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
1835                         /* Tx IQK OK */
1836                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1837                                 "Path A IQK Only  Tx Success!!\n");
1838
1839                         result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1840                                         0x3FF0000) >> 16;
1841                         result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1842                                         0x3FF0000) >> 16;
1843                 }
1844         }
1845         if (0x00 == patha_ok)
1846                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK failed!!\n");
1847         if (is2t) {
1848                 _rtl92d_phy_patha_standby(hw);
1849                 /* Turn Path B ADDA on */
1850                 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
1851                 for (i = 0; i < retrycount; i++) {
1852                         pathb_ok = _rtl92d_phy_pathb_iqk(hw);
1853                         if (pathb_ok == 0x03) {
1854                                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1855                                         "Path B IQK Success!!\n");
1856                                 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1857                                                MASKDWORD) & 0x3FF0000) >> 16;
1858                                 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1859                                                MASKDWORD) & 0x3FF0000) >> 16;
1860                                 result[t][6] = (rtl_get_bbreg(hw, 0xec4,
1861                                                MASKDWORD) & 0x3FF0000) >> 16;
1862                                 result[t][7] = (rtl_get_bbreg(hw, 0xecc,
1863                                                MASKDWORD) & 0x3FF0000) >> 16;
1864                                 break;
1865                         } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1866                                 /* Tx IQK OK */
1867                                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1868                                         "Path B Only Tx IQK Success!!\n");
1869                                 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1870                                                MASKDWORD) & 0x3FF0000) >> 16;
1871                                 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1872                                                MASKDWORD) & 0x3FF0000) >> 16;
1873                         }
1874                 }
1875                 if (0x00 == pathb_ok)
1876                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1877                                 "Path B IQK failed!!\n");
1878         }
1879
1880         /* Back to BB mode, load original value */
1881         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1882                 "IQK:Back to BB mode, load original value!\n");
1883
1884         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1885         if (t != 0) {
1886                 /* Switch back BB to SI mode after finish IQ Calibration. */
1887                 if (!rtlphy->rfpi_enable)
1888                         _rtl92d_phy_pimode_switch(hw, false);
1889                 /* Reload ADDA power saving parameters */
1890                 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
1891                                 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1892                 /* Reload MAC parameters */
1893                 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
1894                                         rtlphy->iqk_mac_backup);
1895                 if (is2t)
1896                         _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1897                                                           rtlphy->iqk_bb_backup,
1898                                                           IQK_BB_REG_NUM);
1899                 else
1900                         _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1901                                                           rtlphy->iqk_bb_backup,
1902                                                           IQK_BB_REG_NUM - 1);
1903                 /* load 0xe30 IQC default value */
1904                 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1905                 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1906         }
1907         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "<==\n");
1908 }
1909
1910 static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
1911                                                long result[][8], u8 t)
1912 {
1913         struct rtl_priv *rtlpriv = rtl_priv(hw);
1914         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1915         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1916         u8 patha_ok, pathb_ok;
1917         static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1918                 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1919                 0xe78, 0xe7c, 0xe80, 0xe84,
1920                 0xe88, 0xe8c, 0xed0, 0xed4,
1921                 0xed8, 0xedc, 0xee0, 0xeec
1922         };
1923         static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1924                 0x522, 0x550, 0x551, 0x040
1925         };
1926         static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1927                 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1928                 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1929                 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1930                 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1931                 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1932         };
1933         u32 bbvalue;
1934         bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
1935
1936         /* Note: IQ calibration must be performed after loading
1937          * PHY_REG.txt , and radio_a, radio_b.txt */
1938
1939         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK for 5G NORMAL:Start!!!\n");
1940         mdelay(IQK_DELAY_TIME * 20);
1941         if (t == 0) {
1942                 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1943                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "==>0x%08x\n", bbvalue);
1944                 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1945                         is2t ? "2T2R" : "1T1R");
1946                 /* Save ADDA parameters, turn Path A ADDA on */
1947                 _rtl92d_phy_save_adda_registers(hw, adda_reg,
1948                                                 rtlphy->adda_backup,
1949                                                 IQK_ADDA_REG_NUM);
1950                 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1951                                                rtlphy->iqk_mac_backup);
1952                 if (is2t)
1953                         _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1954                                                         rtlphy->iqk_bb_backup,
1955                                                         IQK_BB_REG_NUM);
1956                 else
1957                         _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1958                                                         rtlphy->iqk_bb_backup,
1959                                                         IQK_BB_REG_NUM - 1);
1960         }
1961         _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1962         /* MAC settings */
1963         _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1964                         rtlphy->iqk_mac_backup);
1965         if (t == 0)
1966                 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1967                         RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1968         /*  Switch BB to PI mode to do IQ Calibration. */
1969         if (!rtlphy->rfpi_enable)
1970                 _rtl92d_phy_pimode_switch(hw, true);
1971         rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1972         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1973         rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1974         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
1975         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1976
1977         /* Page B init */
1978         rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1979         if (is2t)
1980                 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1981         /* IQ calibration setting  */
1982         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK setting!\n");
1983         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1984         rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00);
1985         rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1986         patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
1987         if (patha_ok == 0x03) {
1988                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK Success!!\n");
1989                 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1990                                 0x3FF0000) >> 16;
1991                 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1992                                 0x3FF0000) >> 16;
1993                 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1994                                 0x3FF0000) >> 16;
1995                 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1996                                 0x3FF0000) >> 16;
1997         } else if (patha_ok == 0x01) {  /* Tx IQK OK */
1998                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1999                         "Path A IQK Only  Tx Success!!\n");
2000
2001                 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2002                                 0x3FF0000) >> 16;
2003                 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2004                                 0x3FF0000) >> 16;
2005         } else {
2006                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK Fail!!\n");
2007         }
2008         if (is2t) {
2009                 /* _rtl92d_phy_patha_standby(hw); */
2010                 /* Turn Path B ADDA on  */
2011                 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2012                 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2013                 if (pathb_ok == 0x03) {
2014                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2015                                 "Path B IQK Success!!\n");
2016                         result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2017                              0x3FF0000) >> 16;
2018                         result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2019                              0x3FF0000) >> 16;
2020                         result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
2021                              0x3FF0000) >> 16;
2022                         result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
2023                              0x3FF0000) >> 16;
2024                 } else if (pathb_ok == 0x01) { /* Tx IQK OK */
2025                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2026                                 "Path B Only Tx IQK Success!!\n");
2027                         result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2028                              0x3FF0000) >> 16;
2029                         result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2030                              0x3FF0000) >> 16;
2031                 } else {
2032                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2033                                 "Path B IQK failed!!\n");
2034                 }
2035         }
2036
2037         /* Back to BB mode, load original value */
2038         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2039                 "IQK:Back to BB mode, load original value!\n");
2040         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
2041         if (t != 0) {
2042                 if (is2t)
2043                         _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2044                                                           rtlphy->iqk_bb_backup,
2045                                                           IQK_BB_REG_NUM);
2046                 else
2047                         _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2048                                                           rtlphy->iqk_bb_backup,
2049                                                           IQK_BB_REG_NUM - 1);
2050                 /* Reload MAC parameters */
2051                 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2052                                 rtlphy->iqk_mac_backup);
2053                 /*  Switch back BB to SI mode after finish IQ Calibration. */
2054                 if (!rtlphy->rfpi_enable)
2055                         _rtl92d_phy_pimode_switch(hw, false);
2056                 /* Reload ADDA power saving parameters */
2057                 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2058                                                   rtlphy->adda_backup,
2059                                                   IQK_ADDA_REG_NUM);
2060         }
2061         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "<==\n");
2062 }
2063
2064 static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2065         long result[][8], u8 c1, u8 c2)
2066 {
2067         struct rtl_priv *rtlpriv = rtl_priv(hw);
2068         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2069         u32 i, j, diff, sim_bitmap, bound;
2070         u8 final_candidate[2] = {0xFF, 0xFF};   /* for path A and path B */
2071         bool bresult = true;
2072         bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2073
2074         if (is2t)
2075                 bound = 8;
2076         else
2077                 bound = 4;
2078         sim_bitmap = 0;
2079         for (i = 0; i < bound; i++) {
2080                 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2081                        result[c2][i]) : (result[c2][i] - result[c1][i]);
2082                 if (diff > MAX_TOLERANCE_92D) {
2083                         if ((i == 2 || i == 6) && !sim_bitmap) {
2084                                 if (result[c1][i] + result[c1][i + 1] == 0)
2085                                         final_candidate[(i / 4)] = c2;
2086                                 else if (result[c2][i] + result[c2][i + 1] == 0)
2087                                         final_candidate[(i / 4)] = c1;
2088                                 else
2089                                         sim_bitmap = sim_bitmap | (1 << i);
2090                         } else {
2091                                 sim_bitmap = sim_bitmap | (1 << i);
2092                         }
2093                 }
2094         }
2095         if (sim_bitmap == 0) {
2096                 for (i = 0; i < (bound / 4); i++) {
2097                         if (final_candidate[i] != 0xFF) {
2098                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2099                                         result[3][j] =
2100                                                  result[final_candidate[i]][j];
2101                                 bresult = false;
2102                         }
2103                 }
2104                 return bresult;
2105         }
2106         if (!(sim_bitmap & 0x0F)) { /* path A OK */
2107                 for (i = 0; i < 4; i++)
2108                         result[3][i] = result[c1][i];
2109         } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */
2110                 for (i = 0; i < 2; i++)
2111                         result[3][i] = result[c1][i];
2112         }
2113         if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */
2114                 for (i = 4; i < 8; i++)
2115                         result[3][i] = result[c1][i];
2116         } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */
2117                 for (i = 4; i < 6; i++)
2118                         result[3][i] = result[c1][i];
2119         }
2120         return false;
2121 }
2122
2123 static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2124                                               bool iqk_ok, long result[][8],
2125                                               u8 final_candidate, bool txonly)
2126 {
2127         struct rtl_priv *rtlpriv = rtl_priv(hw);
2128         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2129         u32 oldval_0, val_x, tx0_a, reg;
2130         long val_y, tx0_c;
2131         bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2132             rtlhal->macphymode == DUALMAC_DUALPHY;
2133
2134         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2135                 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed");
2136         if (final_candidate == 0xFF) {
2137                 return;
2138         } else if (iqk_ok) {
2139                 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2140                         MASKDWORD) >> 22) & 0x3FF;      /* OFDM0_D */
2141                 val_x = result[final_candidate][0];
2142                 if ((val_x & 0x00000200) != 0)
2143                         val_x = val_x | 0xFFFFFC00;
2144                 tx0_a = (val_x * oldval_0) >> 8;
2145                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2146                         "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
2147                         val_x, tx0_a, oldval_0);
2148                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
2149                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2150                               ((val_x * oldval_0 >> 7) & 0x1));
2151                 val_y = result[final_candidate][1];
2152                 if ((val_y & 0x00000200) != 0)
2153                         val_y = val_y | 0xFFFFFC00;
2154                 /* path B IQK result + 3 */
2155                 if (rtlhal->interfaceindex == 1 &&
2156                         rtlhal->current_bandtype == BAND_ON_5G)
2157                         val_y += 3;
2158                 tx0_c = (val_y * oldval_0) >> 8;
2159                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2160                         "Y = 0x%lx, tx0_c = 0x%lx\n",
2161                         val_y, tx0_c);
2162                 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
2163                               ((tx0_c & 0x3C0) >> 6));
2164                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
2165                               (tx0_c & 0x3F));
2166                 if (is2t)
2167                         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2168                                       ((val_y * oldval_0 >> 7) & 0x1));
2169                 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2170                         rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2171                                       MASKDWORD));
2172                 if (txonly) {
2173                         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "only Tx OK\n");
2174                         return;
2175                 }
2176                 reg = result[final_candidate][2];
2177                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2178                 reg = result[final_candidate][3] & 0x3F;
2179                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2180                 reg = (result[final_candidate][3] >> 6) & 0xF;
2181                 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2182         }
2183 }
2184
2185 static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2186         bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2187 {
2188         struct rtl_priv *rtlpriv = rtl_priv(hw);
2189         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2190         u32 oldval_1, val_x, tx1_a, reg;
2191         long val_y, tx1_c;
2192
2193         RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n",
2194                 iqk_ok ? "Success" : "Failed");
2195         if (final_candidate == 0xFF) {
2196                 return;
2197         } else if (iqk_ok) {
2198                 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
2199                                           MASKDWORD) >> 22) & 0x3FF;
2200                 val_x = result[final_candidate][4];
2201                 if ((val_x & 0x00000200) != 0)
2202                         val_x = val_x | 0xFFFFFC00;
2203                 tx1_a = (val_x * oldval_1) >> 8;
2204                 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2205                         val_x, tx1_a);
2206                 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
2207                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2208                               ((val_x * oldval_1 >> 7) & 0x1));
2209                 val_y = result[final_candidate][5];
2210                 if ((val_y & 0x00000200) != 0)
2211                         val_y = val_y | 0xFFFFFC00;
2212                 if (rtlhal->current_bandtype == BAND_ON_5G)
2213                         val_y += 3;
2214                 tx1_c = (val_y * oldval_1) >> 8;
2215                 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2216                         val_y, tx1_c);
2217                 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
2218                               ((tx1_c & 0x3C0) >> 6));
2219                 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
2220                               (tx1_c & 0x3F));
2221                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2222                               ((val_y * oldval_1 >> 7) & 0x1));
2223                 if (txonly)
2224                         return;
2225                 reg = result[final_candidate][6];
2226                 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2227                 reg = result[final_candidate][7] & 0x3F;
2228                 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2229                 reg = (result[final_candidate][7] >> 6) & 0xF;
2230                 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2231         }
2232 }
2233
2234 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2235 {
2236         struct rtl_priv *rtlpriv = rtl_priv(hw);
2237         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2238         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2239         long result[4][8];
2240         u8 i, final_candidate, indexforchannel;
2241         bool patha_ok, pathb_ok;
2242         long rege94, rege9c, regea4, regeac, regeb4;
2243         long regebc, regec4, regecc, regtmp = 0;
2244         bool is12simular, is13simular, is23simular;
2245         unsigned long flag = 0;
2246
2247         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2248                 "IQK:Start!!!channel %d\n", rtlphy->current_channel);
2249         for (i = 0; i < 8; i++) {
2250                 result[0][i] = 0;
2251                 result[1][i] = 0;
2252                 result[2][i] = 0;
2253                 result[3][i] = 0;
2254         }
2255         final_candidate = 0xff;
2256         patha_ok = false;
2257         pathb_ok = false;
2258         is12simular = false;
2259         is23simular = false;
2260         is13simular = false;
2261         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2262                 "IQK !!!currentband %d\n", rtlhal->current_bandtype);
2263         rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2264         for (i = 0; i < 3; i++) {
2265                 if (rtlhal->current_bandtype == BAND_ON_5G) {
2266                         _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2267                 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2268                         if (IS_92D_SINGLEPHY(rtlhal->version))
2269                                 _rtl92d_phy_iq_calibrate(hw, result, i, true);
2270                         else
2271                                 _rtl92d_phy_iq_calibrate(hw, result, i, false);
2272                 }
2273                 if (i == 1) {
2274                         is12simular = _rtl92d_phy_simularity_compare(hw, result,
2275                                                                      0, 1);
2276                         if (is12simular) {
2277                                 final_candidate = 0;
2278                                 break;
2279                         }
2280                 }
2281                 if (i == 2) {
2282                         is13simular = _rtl92d_phy_simularity_compare(hw, result,
2283                                                                      0, 2);
2284                         if (is13simular) {
2285                                 final_candidate = 0;
2286                                 break;
2287                         }
2288                         is23simular = _rtl92d_phy_simularity_compare(hw, result,
2289                                                                      1, 2);
2290                         if (is23simular) {
2291                                 final_candidate = 1;
2292                         } else {
2293                                 for (i = 0; i < 8; i++)
2294                                         regtmp += result[3][i];
2295
2296                                 if (regtmp != 0)
2297                                         final_candidate = 3;
2298                                 else
2299                                         final_candidate = 0xFF;
2300                         }
2301                 }
2302         }
2303         rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2304         for (i = 0; i < 4; i++) {
2305                 rege94 = result[i][0];
2306                 rege9c = result[i][1];
2307                 regea4 = result[i][2];
2308                 regeac = result[i][3];
2309                 regeb4 = result[i][4];
2310                 regebc = result[i][5];
2311                 regec4 = result[i][6];
2312                 regecc = result[i][7];
2313                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2314                         "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2315                         rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2316                         regecc);
2317         }
2318         if (final_candidate != 0xff) {
2319                 rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2320                 rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2321                 regea4 = result[final_candidate][2];
2322                 regeac = result[final_candidate][3];
2323                 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2324                 rtlphy->reg_ebc = regebc = result[final_candidate][5];
2325                 regec4 = result[final_candidate][6];
2326                 regecc = result[final_candidate][7];
2327                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2328                         "IQK: final_candidate is %x\n", final_candidate);
2329                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2330                         "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2331                         rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2332                         regecc);
2333                 patha_ok = pathb_ok = true;
2334         } else {
2335                 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */
2336                 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;   /* Y default value */
2337         }
2338         if ((rege94 != 0) /*&&(regea4 != 0) */)
2339                 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2340                                 final_candidate, (regea4 == 0));
2341         if (IS_92D_SINGLEPHY(rtlhal->version)) {
2342                 if ((regeb4 != 0) /*&&(regec4 != 0) */)
2343                         _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2344                                                 final_candidate, (regec4 == 0));
2345         }
2346         if (final_candidate != 0xFF) {
2347                 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2348                                   rtlphy->current_channel);
2349
2350                 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2351                         rtlphy->iqk_matrix[indexforchannel].
2352                                 value[0][i] = result[final_candidate][i];
2353                 rtlphy->iqk_matrix[indexforchannel].iqk_done =
2354                         true;
2355
2356                 rtl_dbg(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2357                         "IQK OK indexforchannel %d\n", indexforchannel);
2358         }
2359 }
2360
2361 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2362 {
2363         struct rtl_priv *rtlpriv = rtl_priv(hw);
2364         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2365         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2366         u8 indexforchannel;
2367
2368         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel);
2369         /*------Do IQK for normal chip and test chip 5G band------- */
2370         indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2371         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n",
2372                 indexforchannel,
2373                  rtlphy->iqk_matrix[indexforchannel].iqk_done);
2374         if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done &&
2375                 rtlphy->need_iqk) {
2376                 /* Re Do IQK. */
2377                 rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2378                         "Do IQK Matrix reg for channel:%d....\n", channel);
2379                 rtl92d_phy_iq_calibrate(hw);
2380         } else {
2381                 /* Just load the value. */
2382                 /* 2G band just load once. */
2383                 if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2384                     indexforchannel == 0) || indexforchannel > 0) {
2385                         rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
2386                                 "Just Read IQK Matrix reg for channel:%d....\n",
2387                                 channel);
2388                         if ((rtlphy->iqk_matrix[indexforchannel].
2389                              value[0] != NULL)
2390                                 /*&&(regea4 != 0) */)
2391                                 _rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2392                                         rtlphy->iqk_matrix[
2393                                         indexforchannel].value, 0,
2394                                         (rtlphy->iqk_matrix[
2395                                         indexforchannel].value[0][2] == 0));
2396                         if (IS_92D_SINGLEPHY(rtlhal->version)) {
2397                                 if ((rtlphy->iqk_matrix[
2398                                         indexforchannel].value[0][4] != 0)
2399                                         /*&&(regec4 != 0) */)
2400                                         _rtl92d_phy_pathb_fill_iqk_matrix(hw,
2401                                                 true,
2402                                                 rtlphy->iqk_matrix[
2403                                                 indexforchannel].value, 0,
2404                                                 (rtlphy->iqk_matrix[
2405                                                 indexforchannel].value[0][6]
2406                                                 == 0));
2407                         }
2408                 }
2409         }
2410         rtlphy->need_iqk = false;
2411         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2412 }
2413
2414 static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2415 {
2416         u32 ret;
2417
2418         if (val1 >= val2)
2419                 ret = val1 - val2;
2420         else
2421                 ret = val2 - val1;
2422         return ret;
2423 }
2424
2425 static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2426 {
2427
2428         int i;
2429
2430         for (i = 0; i < sizeof(channel5g); i++)
2431                 if (channel == channel5g[i])
2432                         return true;
2433         return false;
2434 }
2435
2436 static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2437                                        u32 *targetchnl, u32 * curvecount_val,
2438                                        bool is5g, u32 *curveindex)
2439 {
2440         struct rtl_priv *rtlpriv = rtl_priv(hw);
2441         u32 smallest_abs_val = 0xffffffff, u4tmp;
2442         u8 i, j;
2443         u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2444
2445         for (i = 0; i < chnl_num; i++) {
2446                 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2447                         continue;
2448                 curveindex[i] = 0;
2449                 for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2450                         u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2451                                 curvecount_val[j]);
2452
2453                         if (u4tmp < smallest_abs_val) {
2454                                 curveindex[i] = j;
2455                                 smallest_abs_val = u4tmp;
2456                         }
2457                 }
2458                 smallest_abs_val = 0xffffffff;
2459                 RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n",
2460                         i, curveindex[i]);
2461         }
2462 }
2463
2464 static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2465                 u8 channel)
2466 {
2467         struct rtl_priv *rtlpriv = rtl_priv(hw);
2468         u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2469                 BAND_ON_5G ? RF90_PATH_A :
2470                 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2471                 RF90_PATH_B : RF90_PATH_A;
2472         u32 u4tmp = 0, u4regvalue = 0;
2473         bool bneed_powerdown_radio = false;
2474
2475         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath);
2476         RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n",
2477                 rtlpriv->rtlhal.current_bandtype);
2478         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "channel = %d\n", channel);
2479         if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2480                 u4tmp = curveindex_5g[channel-1];
2481                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2482                         "ver 1 set RF-A, 5G,    0x28 = 0x%x !!\n", u4tmp);
2483                 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2484                         rtlpriv->rtlhal.interfaceindex == 1) {
2485                         bneed_powerdown_radio =
2486                                 rtl92d_phy_enable_anotherphy(hw, false);
2487                         rtlpriv->rtlhal.during_mac1init_radioa = true;
2488                         /* asume no this case */
2489                         if (bneed_powerdown_radio)
2490                                 _rtl92d_phy_enable_rf_env(hw, erfpath,
2491                                                           &u4regvalue);
2492                 }
2493                 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2494                 if (bneed_powerdown_radio)
2495                         _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2496                 if (rtlpriv->rtlhal.during_mac1init_radioa)
2497                         rtl92d_phy_powerdown_anotherphy(hw, false);
2498         } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2499                 u4tmp = curveindex_2g[channel-1];
2500                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2501                         "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
2502                 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2503                         rtlpriv->rtlhal.interfaceindex == 0) {
2504                         bneed_powerdown_radio =
2505                                 rtl92d_phy_enable_anotherphy(hw, true);
2506                         rtlpriv->rtlhal.during_mac0init_radiob = true;
2507                         if (bneed_powerdown_radio)
2508                                 _rtl92d_phy_enable_rf_env(hw, erfpath,
2509                                                           &u4regvalue);
2510                 }
2511                 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2512                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2513                         "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
2514                         rtl_get_rfreg(hw,  erfpath, RF_SYN_G4, 0x3f800));
2515                 if (bneed_powerdown_radio)
2516                         _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2517                 if (rtlpriv->rtlhal.during_mac0init_radiob)
2518                         rtl92d_phy_powerdown_anotherphy(hw, true);
2519         }
2520         rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2521 }
2522
2523 static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2524 {
2525         struct rtl_priv *rtlpriv = rtl_priv(hw);
2526         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2527         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2528         u8 tmpreg, index, rf_mode[2];
2529         u8 path = is2t ? 2 : 1;
2530         u8 i;
2531         u32 u4tmp, offset;
2532         u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2533         u16 timeout = 800, timecount = 0;
2534
2535         /* Check continuous TX and Packet TX */
2536         tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2537         /* if Deal with contisuous TX case, disable all continuous TX */
2538         /* if Deal with Packet TX case, block all queues */
2539         if ((tmpreg & 0x70) != 0)
2540                 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2541         else
2542                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2543         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2544         for (index = 0; index < path; index++) {
2545                 /* 1. Read original RF mode */
2546                 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2547                 rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2548                 /* 2. Set RF mode = standby mode */
2549                 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2550                               RFREG_OFFSET_MASK, 0x010000);
2551                 if (rtlpci->init_ready) {
2552                         /* switch CV-curve control by LC-calibration */
2553                         rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2554                                       BIT(17), 0x0);
2555                         /* 4. Set LC calibration begin */
2556                         rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2557                                       0x08000, 0x01);
2558                 }
2559                 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2560                                   RFREG_OFFSET_MASK);
2561                 while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2562                         mdelay(50);
2563                         timecount += 50;
2564                         u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2565                                               RF_SYN_G6, RFREG_OFFSET_MASK);
2566                 }
2567                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2568                         "PHY_LCK finish delay for %d ms=2\n", timecount);
2569                 rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK);
2570                 if (index == 0 && rtlhal->interfaceindex == 0) {
2571                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2572                                 "path-A / 5G LCK\n");
2573                 } else {
2574                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2575                                 "path-B / 2.4G LCK\n");
2576                 }
2577                 memset(curvecount_val, 0, sizeof(curvecount_val));
2578                 /* Set LC calibration off */
2579                 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2580                               0x08000, 0x0);
2581                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "set RF 0x18[15] = 0\n");
2582                 /* save Curve-counting number */
2583                 for (i = 0; i < CV_CURVE_CNT; i++) {
2584                         u32 readval = 0, readval2 = 0;
2585                         rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2586                                       0x7f, i);
2587
2588                         rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2589                                 RFREG_OFFSET_MASK, 0x0);
2590                         readval = rtl_get_rfreg(hw, (enum radio_path)index,
2591                                           0x4F, RFREG_OFFSET_MASK);
2592                         curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2593                         /* reg 0x4f [4:0] */
2594                         /* reg 0x50 [19:10] */
2595                         readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2596                                                  0x50, 0xffc00);
2597                         curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2598                                                  readval2);
2599                 }
2600                 if (index == 0 && rtlhal->interfaceindex == 0)
2601                         _rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2602                                                    curvecount_val,
2603                                                    true, curveindex_5g);
2604                 else
2605                         _rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2606                                                    curvecount_val,
2607                                                    false, curveindex_2g);
2608                 /* switch CV-curve control mode */
2609                 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2610                               BIT(17), 0x1);
2611         }
2612
2613         /* Restore original situation  */
2614         for (index = 0; index < path; index++) {
2615                 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2616                 rtl_write_byte(rtlpriv, offset, 0x50);
2617                 rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2618         }
2619         if ((tmpreg & 0x70) != 0)
2620                 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2621         else /*Deal with Packet TX case */
2622                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2623         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2624         _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2625 }
2626
2627 static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2628 {
2629         struct rtl_priv *rtlpriv = rtl_priv(hw);
2630
2631         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "cosa PHY_LCK ver=2\n");
2632         _rtl92d_phy_lc_calibrate_sw(hw, is2t);
2633 }
2634
2635 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2636 {
2637         struct rtl_priv *rtlpriv = rtl_priv(hw);
2638         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2639         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2640         u32 timeout = 2000, timecount = 0;
2641
2642         while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2643                 udelay(50);
2644                 timecount += 50;
2645         }
2646
2647         rtlphy->lck_inprogress = true;
2648         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2649                 "LCK:Start!!! currentband %x delay %d ms\n",
2650                 rtlhal->current_bandtype, timecount);
2651         if (IS_92D_SINGLEPHY(rtlhal->version)) {
2652                 _rtl92d_phy_lc_calibrate(hw, true);
2653         } else {
2654                 /* For 1T1R */
2655                 _rtl92d_phy_lc_calibrate(hw, false);
2656         }
2657         rtlphy->lck_inprogress = false;
2658         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LCK:Finish!!!\n");
2659 }
2660
2661 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
2662 {
2663         return;
2664 }
2665
2666 static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2667                 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2668                 u32 para1, u32 para2, u32 msdelay)
2669 {
2670         struct swchnlcmd *pcmd;
2671
2672         if (cmdtable == NULL) {
2673                 WARN_ONCE(true, "rtl8192de: cmdtable cannot be NULL\n");
2674                 return false;
2675         }
2676         if (cmdtableidx >= cmdtablesz)
2677                 return false;
2678
2679         pcmd = cmdtable + cmdtableidx;
2680         pcmd->cmdid = cmdid;
2681         pcmd->para1 = para1;
2682         pcmd->para2 = para2;
2683         pcmd->msdelay = msdelay;
2684         return true;
2685 }
2686
2687 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2688 {
2689         struct rtl_priv *rtlpriv = rtl_priv(hw);
2690         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2691         u8 i;
2692
2693         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2694                 "settings regs %d default regs %d\n",
2695                 (int)(sizeof(rtlphy->iqk_matrix) /
2696                       sizeof(struct iqk_matrix_regs)),
2697                 IQK_MATRIX_REG_NUM);
2698         /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
2699         for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
2700                 rtlphy->iqk_matrix[i].value[0][0] = 0x100;
2701                 rtlphy->iqk_matrix[i].value[0][2] = 0x100;
2702                 rtlphy->iqk_matrix[i].value[0][4] = 0x100;
2703                 rtlphy->iqk_matrix[i].value[0][6] = 0x100;
2704                 rtlphy->iqk_matrix[i].value[0][1] = 0x0;
2705                 rtlphy->iqk_matrix[i].value[0][3] = 0x0;
2706                 rtlphy->iqk_matrix[i].value[0][5] = 0x0;
2707                 rtlphy->iqk_matrix[i].value[0][7] = 0x0;
2708                 rtlphy->iqk_matrix[i].iqk_done = false;
2709         }
2710 }
2711
2712 static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2713                                              u8 channel, u8 *stage, u8 *step,
2714                                              u32 *delay)
2715 {
2716         struct rtl_priv *rtlpriv = rtl_priv(hw);
2717         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2718         struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2719         u32 precommoncmdcnt;
2720         struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2721         u32 postcommoncmdcnt;
2722         struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
2723         u32 rfdependcmdcnt;
2724         struct swchnlcmd *currentcmd = NULL;
2725         u8 rfpath;
2726         u8 num_total_rfpath = rtlphy->num_total_rfpath;
2727
2728         precommoncmdcnt = 0;
2729         _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2730                                          MAX_PRECMD_CNT,
2731                                          CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
2732         _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2733                                          MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
2734         postcommoncmdcnt = 0;
2735         _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
2736                                          MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
2737         rfdependcmdcnt = 0;
2738         _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2739                                          MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
2740                                          RF_CHNLBW, channel, 0);
2741         _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2742                                          MAX_RFDEPENDCMD_CNT, CMDID_END,
2743                                          0, 0, 0);
2744
2745         do {
2746                 switch (*stage) {
2747                 case 0:
2748                         currentcmd = &precommoncmd[*step];
2749                         break;
2750                 case 1:
2751                         currentcmd = &rfdependcmd[*step];
2752                         break;
2753                 case 2:
2754                         currentcmd = &postcommoncmd[*step];
2755                         break;
2756                 }
2757                 if (currentcmd->cmdid == CMDID_END) {
2758                         if ((*stage) == 2) {
2759                                 return true;
2760                         } else {
2761                                 (*stage)++;
2762                                 (*step) = 0;
2763                                 continue;
2764                         }
2765                 }
2766                 switch (currentcmd->cmdid) {
2767                 case CMDID_SET_TXPOWEROWER_LEVEL:
2768                         rtl92d_phy_set_txpower_level(hw, channel);
2769                         break;
2770                 case CMDID_WRITEPORT_ULONG:
2771                         rtl_write_dword(rtlpriv, currentcmd->para1,
2772                                         currentcmd->para2);
2773                         break;
2774                 case CMDID_WRITEPORT_USHORT:
2775                         rtl_write_word(rtlpriv, currentcmd->para1,
2776                                        (u16)currentcmd->para2);
2777                         break;
2778                 case CMDID_WRITEPORT_UCHAR:
2779                         rtl_write_byte(rtlpriv, currentcmd->para1,
2780                                        (u8)currentcmd->para2);
2781                         break;
2782                 case CMDID_RF_WRITEREG:
2783                         for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
2784                                 rtlphy->rfreg_chnlval[rfpath] =
2785                                         ((rtlphy->rfreg_chnlval[rfpath] &
2786                                         0xffffff00) | currentcmd->para2);
2787                                 if (rtlpriv->rtlhal.current_bandtype ==
2788                                     BAND_ON_5G) {
2789                                         if (currentcmd->para2 > 99)
2790                                                 rtlphy->rfreg_chnlval[rfpath] =
2791                                                     rtlphy->rfreg_chnlval
2792                                                     [rfpath] | (BIT(18));
2793                                         else
2794                                                 rtlphy->rfreg_chnlval[rfpath] =
2795                                                     rtlphy->rfreg_chnlval
2796                                                     [rfpath] & (~BIT(18));
2797                                         rtlphy->rfreg_chnlval[rfpath] |=
2798                                                  (BIT(16) | BIT(8));
2799                                 } else {
2800                                         rtlphy->rfreg_chnlval[rfpath] &=
2801                                                 ~(BIT(8) | BIT(16) | BIT(18));
2802                                 }
2803                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
2804                                               currentcmd->para1,
2805                                               RFREG_OFFSET_MASK,
2806                                               rtlphy->rfreg_chnlval[rfpath]);
2807                                 _rtl92d_phy_reload_imr_setting(hw, channel,
2808                                                                rfpath);
2809                         }
2810                         _rtl92d_phy_switch_rf_setting(hw, channel);
2811                         /* do IQK when all parameters are ready */
2812                         rtl92d_phy_reload_iqk_setting(hw, channel);
2813                         break;
2814                 default:
2815                         pr_err("switch case %#x not processed\n",
2816                                currentcmd->cmdid);
2817                         break;
2818                 }
2819                 break;
2820         } while (true);
2821         (*delay) = currentcmd->msdelay;
2822         (*step)++;
2823         return false;
2824 }
2825
2826 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
2827 {
2828         struct rtl_priv *rtlpriv = rtl_priv(hw);
2829         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2830         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2831         u32 delay;
2832         u32 timeout = 1000, timecount = 0;
2833         u8 channel = rtlphy->current_channel;
2834         u32 ret_value;
2835
2836         if (rtlphy->sw_chnl_inprogress)
2837                 return 0;
2838         if (rtlphy->set_bwmode_inprogress)
2839                 return 0;
2840
2841         if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
2842                 rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
2843                         "sw_chnl_inprogress false driver sleep or unload\n");
2844                 return 0;
2845         }
2846         while (rtlphy->lck_inprogress && timecount < timeout) {
2847                 mdelay(50);
2848                 timecount += 50;
2849         }
2850         if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
2851             rtlhal->bandset == BAND_ON_BOTH) {
2852                 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
2853                                           MASKDWORD);
2854                 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2855                         rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
2856                 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
2857                         rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
2858         }
2859         switch (rtlhal->current_bandtype) {
2860         case BAND_ON_5G:
2861                 /* Get first channel error when change between
2862                  * 5G and 2.4G band. */
2863                 if (channel <= 14)
2864                         return 0;
2865                 WARN_ONCE((channel <= 14), "rtl8192de: 5G but channel<=14\n");
2866                 break;
2867         case BAND_ON_2_4G:
2868                 /* Get first channel error when change between
2869                  * 5G and 2.4G band. */
2870                 if (channel > 14)
2871                         return 0;
2872                 WARN_ONCE((channel > 14), "rtl8192de: 2G but channel>14\n");
2873                 break;
2874         default:
2875                 WARN_ONCE(true, "rtl8192de: Invalid WirelessMode(%#x)!!\n",
2876                           rtlpriv->mac80211.mode);
2877                 break;
2878         }
2879         rtlphy->sw_chnl_inprogress = true;
2880         if (channel == 0)
2881                 channel = 1;
2882         rtlphy->sw_chnl_stage = 0;
2883         rtlphy->sw_chnl_step = 0;
2884         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
2885                 "switch to channel%d\n", rtlphy->current_channel);
2886
2887         do {
2888                 if (!rtlphy->sw_chnl_inprogress)
2889                         break;
2890                 if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
2891                                                       rtlphy->current_channel,
2892                     &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
2893                         if (delay > 0)
2894                                 mdelay(delay);
2895                         else
2896                                 continue;
2897                 } else {
2898                         rtlphy->sw_chnl_inprogress = false;
2899                 }
2900                 break;
2901         } while (true);
2902         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
2903         rtlphy->sw_chnl_inprogress = false;
2904         return 1;
2905 }
2906
2907 static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
2908 {
2909         struct rtl_priv *rtlpriv = rtl_priv(hw);
2910         struct dig_t *de_digtable = &rtlpriv->dm_digtable;
2911         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2912
2913         rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2914                 "--->Cmd(%#x), set_io_inprogress(%d)\n",
2915                 rtlphy->current_io_type, rtlphy->set_io_inprogress);
2916         switch (rtlphy->current_io_type) {
2917         case IO_CMD_RESUME_DM_BY_SCAN:
2918                 de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2919                 rtl92d_dm_write_dig(hw);
2920                 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
2921                 break;
2922         case IO_CMD_PAUSE_DM_BY_SCAN:
2923                 rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue;
2924                 de_digtable->cur_igvalue = 0x37;
2925                 rtl92d_dm_write_dig(hw);
2926                 break;
2927         default:
2928                 pr_err("switch case %#x not processed\n",
2929                        rtlphy->current_io_type);
2930                 break;
2931         }
2932         rtlphy->set_io_inprogress = false;
2933         rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
2934                 rtlphy->current_io_type);
2935 }
2936
2937 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2938 {
2939         struct rtl_priv *rtlpriv = rtl_priv(hw);
2940         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2941         bool postprocessing = false;
2942
2943         rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2944                 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2945                  iotype, rtlphy->set_io_inprogress);
2946         do {
2947                 switch (iotype) {
2948                 case IO_CMD_RESUME_DM_BY_SCAN:
2949                         rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2950                                 "[IO CMD] Resume DM after scan\n");
2951                         postprocessing = true;
2952                         break;
2953                 case IO_CMD_PAUSE_DM_BY_SCAN:
2954                         rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2955                                 "[IO CMD] Pause DM before scan\n");
2956                         postprocessing = true;
2957                         break;
2958                 default:
2959                         pr_err("switch case %#x not processed\n",
2960                                iotype);
2961                         break;
2962                 }
2963         } while (false);
2964         if (postprocessing && !rtlphy->set_io_inprogress) {
2965                 rtlphy->set_io_inprogress = true;
2966                 rtlphy->current_io_type = iotype;
2967         } else {
2968                 return false;
2969         }
2970         rtl92d_phy_set_io(hw);
2971         rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
2972         return true;
2973 }
2974
2975 static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
2976 {
2977         struct rtl_priv *rtlpriv = rtl_priv(hw);
2978
2979         /* a.  SYS_CLKR 0x08[11] = 1  restore MAC clock */
2980         /* b.  SPS_CTRL 0x11[7:0] = 0x2b */
2981         if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
2982                 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2983         /* c.  For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
2984         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2985         /* RF_ON_EXCEP(d~g): */
2986         /* d.  APSD_CTRL 0x600[7:0] = 0x00 */
2987         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2988         /* e.  SYS_FUNC_EN 0x02[7:0] = 0xE2  reset BB TRX function again */
2989         /* f.  SYS_FUNC_EN 0x02[7:0] = 0xE3  enable BB TRX function*/
2990         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2991         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2992         /* g.   txpause 0x522[7:0] = 0x00  enable mac tx queue */
2993         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2994 }
2995
2996 static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
2997 {
2998         struct rtl_priv *rtlpriv = rtl_priv(hw);
2999         u32 u4btmp;
3000         u8 delay = 5;
3001
3002         /* a.   TXPAUSE 0x522[7:0] = 0xFF  Pause MAC TX queue  */
3003         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3004         /* b.   RF path 0 offset 0x00 = 0x00  disable RF  */
3005         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3006         /* c.   APSD_CTRL 0x600[7:0] = 0x40 */
3007         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3008         /* d. APSD_CTRL 0x600[7:0] = 0x00
3009          * APSD_CTRL 0x600[7:0] = 0x00
3010          * RF path 0 offset 0x00 = 0x00
3011          * APSD_CTRL 0x600[7:0] = 0x40
3012          * */
3013         u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3014         while (u4btmp != 0 && delay > 0) {
3015                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3016                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3017                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3018                 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3019                 delay--;
3020         }
3021         if (delay == 0) {
3022                 /* Jump out the LPS turn off sequence to RF_ON_EXCEP */
3023                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3024
3025                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3026                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3027                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3028                 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3029                         "Fail !!! Switch RF timeout\n");
3030                 return;
3031         }
3032         /* e.   For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
3033         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3034         /* f.   SPS_CTRL 0x11[7:0] = 0x22 */
3035         if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3036                 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3037         /* g.    SYS_CLKR 0x08[11] = 0  gated MAC clock */
3038 }
3039
3040 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3041                                    enum rf_pwrstate rfpwr_state)
3042 {
3043
3044         bool bresult = true;
3045         struct rtl_priv *rtlpriv = rtl_priv(hw);
3046         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3047         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3048         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3049         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3050         u8 i, queue_id;
3051         struct rtl8192_tx_ring *ring = NULL;
3052
3053         if (rfpwr_state == ppsc->rfpwr_state)
3054                 return false;
3055         switch (rfpwr_state) {
3056         case ERFON:
3057                 if ((ppsc->rfpwr_state == ERFOFF) &&
3058                     RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3059                         bool rtstatus;
3060                         u32 initializecount = 0;
3061                         do {
3062                                 initializecount++;
3063                                 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3064                                         "IPS Set eRf nic enable\n");
3065                                 rtstatus = rtl_ps_enable_nic(hw);
3066                         } while (!rtstatus && (initializecount < 10));
3067
3068                         RT_CLEAR_PS_LEVEL(ppsc,
3069                                           RT_RF_OFF_LEVL_HALT_NIC);
3070                 } else {
3071                         rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3072                                 "awake, slept:%d ms state_inap:%x\n",
3073                                 jiffies_to_msecs(jiffies -
3074                                                  ppsc->last_sleep_jiffies),
3075                                  rtlpriv->psc.state_inap);
3076                         ppsc->last_awake_jiffies = jiffies;
3077                         _rtl92d_phy_set_rfon(hw);
3078                 }
3079
3080                 if (mac->link_state == MAC80211_LINKED)
3081                         rtlpriv->cfg->ops->led_control(hw,
3082                                          LED_CTL_LINK);
3083                 else
3084                         rtlpriv->cfg->ops->led_control(hw,
3085                                          LED_CTL_NO_LINK);
3086                 break;
3087         case ERFOFF:
3088                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3089                         rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3090                                 "IPS Set eRf nic disable\n");
3091                         rtl_ps_disable_nic(hw);
3092                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3093                 } else {
3094                         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3095                                 rtlpriv->cfg->ops->led_control(hw,
3096                                                  LED_CTL_NO_LINK);
3097                         else
3098                                 rtlpriv->cfg->ops->led_control(hw,
3099                                                  LED_CTL_POWER_OFF);
3100                 }
3101                 break;
3102         case ERFSLEEP:
3103                 if (ppsc->rfpwr_state == ERFOFF)
3104                         return false;
3105
3106                 for (queue_id = 0, i = 0;
3107                      queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3108                         ring = &pcipriv->dev.tx_ring[queue_id];
3109                         if (skb_queue_len(&ring->queue) == 0 ||
3110                             queue_id == BEACON_QUEUE) {
3111                                 queue_id++;
3112                                 continue;
3113                         } else if (rtlpci->pdev->current_state != PCI_D0) {
3114                                 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3115                                         "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n",
3116                                         i + 1, queue_id);
3117                                 break;
3118                         } else {
3119                                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3120                                         "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3121                                         i + 1, queue_id,
3122                                         skb_queue_len(&ring->queue));
3123                                 udelay(10);
3124                                 i++;
3125                         }
3126
3127                         if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3128                                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3129                                         "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
3130                                         MAX_DOZE_WAITING_TIMES_9x, queue_id,
3131                                         skb_queue_len(&ring->queue));
3132                                 break;
3133                         }
3134                 }
3135                 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3136                         "Set rfsleep awakened:%d ms\n",
3137                          jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
3138                 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3139                         "sleep awakened:%d ms state_inap:%x\n",
3140                         jiffies_to_msecs(jiffies -
3141                                          ppsc->last_awake_jiffies),
3142                         rtlpriv->psc.state_inap);
3143                 ppsc->last_sleep_jiffies = jiffies;
3144                 _rtl92d_phy_set_rfsleep(hw);
3145                 break;
3146         default:
3147                 pr_err("switch case %#x not processed\n",
3148                        rfpwr_state);
3149                 bresult = false;
3150                 break;
3151         }
3152         if (bresult)
3153                 ppsc->rfpwr_state = rfpwr_state;
3154         return bresult;
3155 }
3156
3157 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3158 {
3159         struct rtl_priv *rtlpriv = rtl_priv(hw);
3160         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3161         u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3162
3163         switch (rtlhal->macphymode) {
3164         case DUALMAC_DUALPHY:
3165                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3166                         "MacPhyMode: DUALMAC_DUALPHY\n");
3167                 rtl_write_byte(rtlpriv, offset, 0xF3);
3168                 break;
3169         case SINGLEMAC_SINGLEPHY:
3170                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3171                         "MacPhyMode: SINGLEMAC_SINGLEPHY\n");
3172                 rtl_write_byte(rtlpriv, offset, 0xF4);
3173                 break;
3174         case DUALMAC_SINGLEPHY:
3175                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3176                         "MacPhyMode: DUALMAC_SINGLEPHY\n");
3177                 rtl_write_byte(rtlpriv, offset, 0xF1);
3178                 break;
3179         }
3180 }
3181
3182 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3183 {
3184         struct rtl_priv *rtlpriv = rtl_priv(hw);
3185         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3186         struct rtl_phy *rtlphy = &(rtlpriv->phy);
3187
3188         switch (rtlhal->macphymode) {
3189         case DUALMAC_SINGLEPHY:
3190                 rtlphy->rf_type = RF_2T2R;
3191                 rtlhal->version |= RF_TYPE_2T2R;
3192                 rtlhal->bandset = BAND_ON_BOTH;
3193                 rtlhal->current_bandtype = BAND_ON_2_4G;
3194                 break;
3195
3196         case SINGLEMAC_SINGLEPHY:
3197                 rtlphy->rf_type = RF_2T2R;
3198                 rtlhal->version |= RF_TYPE_2T2R;
3199                 rtlhal->bandset = BAND_ON_BOTH;
3200                 rtlhal->current_bandtype = BAND_ON_2_4G;
3201                 break;
3202
3203         case DUALMAC_DUALPHY:
3204                 rtlphy->rf_type = RF_1T1R;
3205                 rtlhal->version &= RF_TYPE_1T1R;
3206                 /* Now we let MAC0 run on 5G band. */
3207                 if (rtlhal->interfaceindex == 0) {
3208                         rtlhal->bandset = BAND_ON_5G;
3209                         rtlhal->current_bandtype = BAND_ON_5G;
3210                 } else {
3211                         rtlhal->bandset = BAND_ON_2_4G;
3212                         rtlhal->current_bandtype = BAND_ON_2_4G;
3213                 }
3214                 break;
3215         default:
3216                 break;
3217         }
3218 }
3219
3220 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3221 {
3222         u8 group;
3223         u8 channel_info[59] = {
3224                 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
3225                 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56,
3226                 58, 60, 62, 64, 100, 102, 104, 106, 108,
3227                 110, 112, 114, 116, 118, 120, 122, 124,
3228                 126, 128, 130, 132, 134, 136, 138, 140,
3229                 149, 151, 153, 155, 157, 159, 161, 163,
3230                 165
3231         };
3232
3233         if (channel_info[chnl] <= 3)
3234                 group = 0;
3235         else if (channel_info[chnl] <= 9)
3236                 group = 1;
3237         else if (channel_info[chnl] <= 14)
3238                 group = 2;
3239         else if (channel_info[chnl] <= 44)
3240                 group = 3;
3241         else if (channel_info[chnl] <= 54)
3242                 group = 4;
3243         else if (channel_info[chnl] <= 64)
3244                 group = 5;
3245         else if (channel_info[chnl] <= 112)
3246                 group = 6;
3247         else if (channel_info[chnl] <= 126)
3248                 group = 7;
3249         else if (channel_info[chnl] <= 140)
3250                 group = 8;
3251         else if (channel_info[chnl] <= 153)
3252                 group = 9;
3253         else if (channel_info[chnl] <= 159)
3254                 group = 10;
3255         else
3256                 group = 11;
3257         return group;
3258 }
3259
3260 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3261 {
3262         struct rtl_priv *rtlpriv = rtl_priv(hw);
3263         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3264         unsigned long flags;
3265         u8 value8;
3266         u16 i;
3267         u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3268
3269         /* notice fw know band status  0x81[1]/0x53[1] = 0: 5G, 1: 2G */
3270         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3271                 value8 = rtl_read_byte(rtlpriv, mac_reg);
3272                 value8 |= BIT(1);
3273                 rtl_write_byte(rtlpriv, mac_reg, value8);
3274         } else {
3275                 value8 = rtl_read_byte(rtlpriv, mac_reg);
3276                 value8 &= (~BIT(1));
3277                 rtl_write_byte(rtlpriv, mac_reg, value8);
3278         }
3279
3280         if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3281                 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3282                 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3283         } else {
3284                 spin_lock_irqsave(&globalmutex_power, flags);
3285                 if (rtlhal->interfaceindex == 0) {
3286                         value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3287                         rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3288                 } else {
3289                         value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3290                         rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3291                 }
3292                 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3293                 spin_unlock_irqrestore(&globalmutex_power, flags);
3294                 for (i = 0; i < 200; i++) {
3295                         if ((value8 & BIT(7)) == 0) {
3296                                 break;
3297                         } else {
3298                                 udelay(500);
3299                                 spin_lock_irqsave(&globalmutex_power, flags);
3300                                 value8 = rtl_read_byte(rtlpriv,
3301                                                     REG_POWER_OFF_IN_PROCESS);
3302                                 spin_unlock_irqrestore(&globalmutex_power,
3303                                                        flags);
3304                         }
3305                 }
3306                 if (i == 200)
3307                         WARN_ONCE(true, "rtl8192de: Another mac power off over time\n");
3308         }
3309 }
3310
3311 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3312 {
3313         struct rtl_priv *rtlpriv = rtl_priv(hw);
3314
3315         switch (rtlpriv->rtlhal.macphymode) {
3316         case DUALMAC_DUALPHY:
3317                 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3318                 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3319                 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3320                 break;
3321         case DUALMAC_SINGLEPHY:
3322                 rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3323                 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3324                 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3325                 break;
3326         case SINGLEMAC_SINGLEPHY:
3327                 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3328                 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3329                 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3330                 break;
3331         default:
3332                 break;
3333         }
3334 }
3335
3336 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3337 {
3338         struct rtl_priv *rtlpriv = rtl_priv(hw);
3339         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3340         struct rtl_phy *rtlphy = &(rtlpriv->phy);
3341         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3342         u8 rfpath, i;
3343
3344         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
3345         /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
3346         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3347                 /* r_select_5G for path_A/B,0x878 */
3348                 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3349                 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3350                 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3351                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3352                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3353                 }
3354                 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3355                 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3356                 /* fc_area  0xd2c */
3357                 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3358                 /* 5G LAN ON */
3359                 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3360                 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3361                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3362                               0x40000100);
3363                 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3364                               0x40000100);
3365                 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3366                         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3367                                       BIT(10) | BIT(6) | BIT(5),
3368                                       ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3369                                       (rtlefuse->eeprom_c9 & BIT(1)) |
3370                                       ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3371                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3372                                       BIT(10) | BIT(6) | BIT(5),
3373                                       ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3374                                       ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3375                                       ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3376                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3377                 } else {
3378                         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3379                                       BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3380                                       BIT(6) | BIT(5),
3381                                       ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3382                                       (rtlefuse->eeprom_c9 & BIT(1)) |
3383                                       ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3384                                       ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3385                                       ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3386                                       ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3387                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3388                                       BIT(10) | BIT(6) | BIT(5),
3389                                       ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3390                                       ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3391                                       ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3392                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3393                                       BIT(10) | BIT(6) | BIT(5),
3394                                       ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3395                                       ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3396                                       ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3397                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3398                                       BIT(31) | BIT(15), 0);
3399                 }
3400                 /* 1.5V_LDO */
3401         } else {
3402                 /* r_select_5G for path_A/B */
3403                 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3404                 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3405                 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3406                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3407                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3408                 }
3409                 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3410                 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3411                 /* fc_area */
3412                 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3413                 /* 5G LAN ON */
3414                 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3415                 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3416                 if (rtlefuse->internal_pa_5g[0])
3417                         rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3418                                       0x2d4000b5);
3419                 else
3420                         rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3421                                       0x20000080);
3422                 if (rtlefuse->internal_pa_5g[1])
3423                         rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3424                                       0x2d4000b5);
3425                 else
3426                         rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3427                                       0x20000080);
3428                 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3429                         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3430                                       BIT(10) | BIT(6) | BIT(5),
3431                                       (rtlefuse->eeprom_cc & BIT(5)));
3432                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3433                                       ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3434                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3435                                       (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3436                 } else {
3437                         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3438                                       BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3439                                       BIT(6) | BIT(5),
3440                                       (rtlefuse->eeprom_cc & BIT(5)) |
3441                                       ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3442                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3443                                       ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3444                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3445                                       ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3446                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3447                                       BIT(31) | BIT(15),
3448                                       ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3449                                       ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3450                 }
3451         }
3452         /* update IQK related settings */
3453         rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
3454         rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
3455         rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00);
3456         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3457                       BIT(26) | BIT(24), 0x00);
3458         rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00);
3459         rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3460         rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3461
3462         /* Update RF */
3463         for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3464              rfpath++) {
3465                 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3466                         /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
3467                         rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3468                                       BIT(18), 0);
3469                         /* RF0x0b[16:14] =3b'111 */
3470                         rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3471                                       0x1c000, 0x07);
3472                 } else {
3473                         /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
3474                         rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3475                                       BIT(16) | BIT(18),
3476                                       (BIT(16) | BIT(8)) >> 8);
3477                 }
3478         }
3479         /* Update for all band. */
3480         /* DMDP */
3481         if (rtlphy->rf_type == RF_1T1R) {
3482                 /* Use antenna 0,0xc04,0xd04 */
3483                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
3484                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3485
3486                 /* enable ad/da clock1 for dual-phy reg0x888 */
3487                 if (rtlhal->interfaceindex == 0) {
3488                         rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3489                                       BIT(13), 0x3);
3490                 } else {
3491                         rtl92d_phy_enable_anotherphy(hw, false);
3492                         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3493                                 "MAC1 use DBI to update 0x888\n");
3494                         /* 0x888 */
3495                         rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3496                                                 rtl92de_read_dword_dbi(hw,
3497                                                 RFPGA0_ADDALLOCKEN,
3498                                                 BIT(3)) | BIT(12) | BIT(13),
3499                                                 BIT(3));
3500                         rtl92d_phy_powerdown_anotherphy(hw, false);
3501                 }
3502         } else {
3503                 /* Single PHY */
3504                 /* Use antenna 0 & 1,0xc04,0xd04 */
3505                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
3506                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3507                 /* disable ad/da clock1,0x888 */
3508                 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3509         }
3510         for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3511              rfpath++) {
3512                 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3513                                                 RF_CHNLBW, RFREG_OFFSET_MASK);
3514                 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3515                         RFREG_OFFSET_MASK);
3516         }
3517         for (i = 0; i < 2; i++)
3518                 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
3519                         rtlphy->rfreg_chnlval[i]);
3520         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n");
3521
3522 }
3523
3524 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3525 {
3526         struct rtl_priv *rtlpriv = rtl_priv(hw);
3527         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3528         u8 u1btmp;
3529         unsigned long flags;
3530
3531         if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3532                 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3533                 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3534                 return true;
3535         }
3536         spin_lock_irqsave(&globalmutex_power, flags);
3537         if (rtlhal->interfaceindex == 0) {
3538                 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3539                 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3540                 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3541                 u1btmp &= MAC1_ON;
3542         } else {
3543                 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3544                 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3545                 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3546                 u1btmp &= MAC0_ON;
3547         }
3548         if (u1btmp) {
3549                 spin_unlock_irqrestore(&globalmutex_power, flags);
3550                 return false;
3551         }
3552         u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3553         u1btmp |= BIT(7);
3554         rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3555         spin_unlock_irqrestore(&globalmutex_power, flags);
3556         return true;
3557 }