1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
8 #include <linux/spi/spi.h>
9 #include <linux/crc7.h>
18 static const struct wilc_hif_func wilc_hif_spi;
20 /********************************************
22 * Spi protocol Function
24 ********************************************/
26 #define CMD_DMA_WRITE 0xc1
27 #define CMD_DMA_READ 0xc2
28 #define CMD_INTERNAL_WRITE 0xc3
29 #define CMD_INTERNAL_READ 0xc4
30 #define CMD_TERMINATE 0xc5
31 #define CMD_REPEAT 0xc6
32 #define CMD_DMA_EXT_WRITE 0xc7
33 #define CMD_DMA_EXT_READ 0xc8
34 #define CMD_SINGLE_WRITE 0xc9
35 #define CMD_SINGLE_READ 0xca
36 #define CMD_RESET 0xcf
38 #define DATA_PKT_SZ_256 256
39 #define DATA_PKT_SZ_512 512
40 #define DATA_PKT_SZ_1K 1024
41 #define DATA_PKT_SZ_4K (4 * 1024)
42 #define DATA_PKT_SZ_8K (8 * 1024)
43 #define DATA_PKT_SZ DATA_PKT_SZ_8K
47 #define WILC_SPI_COMMAND_STAT_SUCCESS 0
48 #define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf)
56 } __packed simple_cmd;
66 } __packed dma_cmd_ext;
71 } __packed internal_w_cmd;
80 struct wilc_spi_read_rsp_data {
88 struct wilc_spi_rsp_data {
93 static int wilc_bus_probe(struct spi_device *spi)
97 struct wilc_spi *spi_priv;
99 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL);
103 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi);
109 spi_set_drvdata(spi, wilc);
110 wilc->dev = &spi->dev;
111 wilc->bus_data = spi_priv;
112 wilc->dev_irq_num = spi->irq;
114 wilc->rtc_clk = devm_clk_get(&spi->dev, "rtc_clk");
115 if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER)
116 return -EPROBE_DEFER;
117 else if (!IS_ERR(wilc->rtc_clk))
118 clk_prepare_enable(wilc->rtc_clk);
123 static int wilc_bus_remove(struct spi_device *spi)
125 struct wilc *wilc = spi_get_drvdata(spi);
127 if (!IS_ERR(wilc->rtc_clk))
128 clk_disable_unprepare(wilc->rtc_clk);
130 wilc_netdev_cleanup(wilc);
134 static const struct of_device_id wilc_of_match[] = {
135 { .compatible = "microchip,wilc1000", },
138 MODULE_DEVICE_TABLE(of, wilc_of_match);
140 static struct spi_driver wilc_spi_driver = {
143 .of_match_table = wilc_of_match,
145 .probe = wilc_bus_probe,
146 .remove = wilc_bus_remove,
148 module_spi_driver(wilc_spi_driver);
149 MODULE_LICENSE("GPL");
151 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
153 struct spi_device *spi = to_spi_device(wilc->dev);
155 struct spi_message msg;
158 struct spi_transfer tr = {
163 .unit = SPI_DELAY_UNIT_USECS
166 char *r_buffer = kzalloc(len, GFP_KERNEL);
171 tr.rx_buf = r_buffer;
172 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
174 memset(&msg, 0, sizeof(msg));
175 spi_message_init(&msg);
177 msg.is_dma_mapped = USE_SPI_DMA;
178 spi_message_add_tail(&tr, &msg);
180 ret = spi_sync(spi, &msg);
182 dev_err(&spi->dev, "SPI transaction failed\n");
187 "can't write data with the following length: %d\n",
195 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
197 struct spi_device *spi = to_spi_device(wilc->dev);
201 struct spi_message msg;
202 struct spi_transfer tr = {
207 .unit = SPI_DELAY_UNIT_USECS
211 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
216 tr.tx_buf = t_buffer;
218 memset(&msg, 0, sizeof(msg));
219 spi_message_init(&msg);
221 msg.is_dma_mapped = USE_SPI_DMA;
222 spi_message_add_tail(&tr, &msg);
224 ret = spi_sync(spi, &msg);
226 dev_err(&spi->dev, "SPI transaction failed\n");
230 "can't read data with the following length: %u\n",
238 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
240 struct spi_device *spi = to_spi_device(wilc->dev);
244 struct spi_message msg;
245 struct spi_transfer tr = {
252 .unit = SPI_DELAY_UNIT_USECS
257 memset(&msg, 0, sizeof(msg));
258 spi_message_init(&msg);
260 msg.is_dma_mapped = USE_SPI_DMA;
262 spi_message_add_tail(&tr, &msg);
263 ret = spi_sync(spi, &msg);
265 dev_err(&spi->dev, "SPI transaction failed\n");
268 "can't read data with the following length: %u\n",
276 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
278 struct spi_device *spi = to_spi_device(wilc->dev);
279 struct wilc_spi *spi_priv = wilc->bus_data;
282 u8 cmd, order, crc[2] = {0};
289 if (sz <= DATA_PKT_SZ) {
293 nbytes = DATA_PKT_SZ;
306 if (wilc_spi_tx(wilc, &cmd, 1)) {
308 "Failed data block cmd write, bus error...\n");
316 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
318 "Failed data block write, bus error...\n");
326 if (!spi_priv->crc_off) {
327 if (wilc_spi_tx(wilc, crc, 2)) {
328 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
335 * No need to wait for response
344 /********************************************
346 * Spi Internal Read/Write Function
348 ********************************************/
349 static u8 wilc_get_crc7(u8 *buffer, u32 len)
351 return crc7_be(0xfe, buffer, len);
354 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b,
357 struct spi_device *spi = to_spi_device(wilc->dev);
358 struct wilc_spi *spi_priv = wilc->bus_data;
360 int cmd_len, resp_len;
362 struct wilc_spi_cmd *c;
363 struct wilc_spi_read_rsp_data *r;
365 memset(wb, 0x0, sizeof(wb));
366 memset(rb, 0x0, sizeof(rb));
367 c = (struct wilc_spi_cmd *)wb;
369 if (cmd == CMD_SINGLE_READ) {
370 c->u.simple_cmd.addr[0] = adr >> 16;
371 c->u.simple_cmd.addr[1] = adr >> 8;
372 c->u.simple_cmd.addr[2] = adr;
373 } else if (cmd == CMD_INTERNAL_READ) {
374 c->u.simple_cmd.addr[0] = adr >> 8;
376 c->u.simple_cmd.addr[0] |= BIT(7);
377 c->u.simple_cmd.addr[1] = adr;
378 c->u.simple_cmd.addr[2] = 0x0;
380 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd);
384 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
385 resp_len = sizeof(*r);
386 if (!spi_priv->crc_off) {
387 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
392 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
394 "spi buffer size too small (%d) (%d) (%zu)\n",
395 cmd_len, resp_len, ARRAY_SIZE(wb));
399 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
400 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
404 r = (struct wilc_spi_read_rsp_data *)&rb[cmd_len];
405 if (r->rsp_cmd_type != cmd) {
407 "Failed cmd response, cmd (%02x), resp (%02x)\n",
408 cmd, r->rsp_cmd_type);
412 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
413 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
418 if (WILC_GET_RESP_HDR_START(r->resp_header) != 0xf) {
419 dev_err(&spi->dev, "Error, data read response (%02x)\n",
425 memcpy(b, r->resp_data, 4);
427 if (!spi_priv->crc_off)
428 memcpy(crc, r->crc, 2);
433 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data,
436 struct spi_device *spi = to_spi_device(wilc->dev);
437 struct wilc_spi *spi_priv = wilc->bus_data;
439 int cmd_len, resp_len;
440 struct wilc_spi_cmd *c;
441 struct wilc_spi_rsp_data *r;
443 memset(wb, 0x0, sizeof(wb));
444 memset(rb, 0x0, sizeof(rb));
445 c = (struct wilc_spi_cmd *)wb;
447 if (cmd == CMD_INTERNAL_WRITE) {
448 c->u.internal_w_cmd.addr[0] = adr >> 8;
450 c->u.internal_w_cmd.addr[0] |= BIT(7);
452 c->u.internal_w_cmd.addr[1] = adr;
453 c->u.internal_w_cmd.data = cpu_to_be32(data);
454 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc);
455 if (!spi_priv->crc_off)
456 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
457 } else if (cmd == CMD_SINGLE_WRITE) {
458 c->u.w_cmd.addr[0] = adr >> 16;
459 c->u.w_cmd.addr[1] = adr >> 8;
460 c->u.w_cmd.addr[2] = adr;
461 c->u.w_cmd.data = cpu_to_be32(data);
462 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc);
463 if (!spi_priv->crc_off)
464 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
466 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd);
470 if (!spi_priv->crc_off)
473 resp_len = sizeof(*r);
475 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
477 "spi buffer size too small (%d) (%d) (%zu)\n",
478 cmd_len, resp_len, ARRAY_SIZE(wb));
482 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
483 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
487 r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
488 if (r->rsp_cmd_type != cmd) {
490 "Failed cmd response, cmd (%02x), resp (%02x)\n",
491 cmd, r->rsp_cmd_type);
495 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
496 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
504 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz)
506 struct spi_device *spi = to_spi_device(wilc->dev);
507 struct wilc_spi *spi_priv = wilc->bus_data;
509 int cmd_len, resp_len;
512 struct wilc_spi_cmd *c;
513 struct wilc_spi_rsp_data *r;
515 memset(wb, 0x0, sizeof(wb));
516 memset(rb, 0x0, sizeof(rb));
517 c = (struct wilc_spi_cmd *)wb;
519 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) {
520 c->u.dma_cmd.addr[0] = adr >> 16;
521 c->u.dma_cmd.addr[1] = adr >> 8;
522 c->u.dma_cmd.addr[2] = adr;
523 c->u.dma_cmd.size[0] = sz >> 8;
524 c->u.dma_cmd.size[1] = sz;
525 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc);
526 if (!spi_priv->crc_off)
527 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
528 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) {
529 c->u.dma_cmd_ext.addr[0] = adr >> 16;
530 c->u.dma_cmd_ext.addr[1] = adr >> 8;
531 c->u.dma_cmd_ext.addr[2] = adr;
532 c->u.dma_cmd_ext.size[0] = sz >> 16;
533 c->u.dma_cmd_ext.size[1] = sz >> 8;
534 c->u.dma_cmd_ext.size[2] = sz;
535 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc);
536 if (!spi_priv->crc_off)
537 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len);
539 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n",
543 if (!spi_priv->crc_off)
546 resp_len = sizeof(*r);
548 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
549 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n",
550 cmd_len, resp_len, ARRAY_SIZE(wb));
554 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
555 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
559 r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
560 if (r->rsp_cmd_type != cmd) {
562 "Failed cmd response, cmd (%02x), resp (%02x)\n",
563 cmd, r->rsp_cmd_type);
567 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
568 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
573 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE)
580 if (sz <= DATA_PKT_SZ)
583 nbytes = DATA_PKT_SZ;
586 * Data Response header
590 if (wilc_spi_rx(wilc, &rsp, 1)) {
592 "Failed resp read, bus err\n");
595 if (WILC_GET_RESP_HDR_START(rsp) == 0xf)
602 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
604 "Failed block read, bus err\n");
611 if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) {
613 "Failed block crc read, bus err\n");
623 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
625 struct spi_device *spi = to_spi_device(wilc->dev);
627 u8 cmd = CMD_SINGLE_READ;
630 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
631 /* Clockless register */
632 cmd = CMD_INTERNAL_READ;
636 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless);
638 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
647 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
649 struct spi_device *spi = to_spi_device(wilc->dev);
655 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size);
657 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
664 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
666 struct spi_device *spi = to_spi_device(wilc->dev);
669 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0);
671 dev_err(&spi->dev, "Failed internal write cmd...\n");
678 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
680 struct spi_device *spi = to_spi_device(wilc->dev);
683 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0);
685 dev_err(&spi->dev, "Failed internal read cmd...\n");
694 /********************************************
698 ********************************************/
700 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
702 struct spi_device *spi = to_spi_device(wilc->dev);
704 u8 cmd = CMD_SINGLE_WRITE;
707 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
708 /* Clockless register */
709 cmd = CMD_INTERNAL_WRITE;
713 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless);
715 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
722 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
724 struct spi_device *spi = to_spi_device(wilc->dev);
728 * has to be greated than 4
733 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size);
736 "Failed cmd, write block (%08x)...\n", addr);
743 result = spi_data_write(wilc, buf, size);
745 dev_err(&spi->dev, "Failed block data write...\n");
752 /********************************************
756 ********************************************/
758 static int wilc_spi_deinit(struct wilc *wilc)
766 static int wilc_spi_init(struct wilc *wilc, bool resume)
768 struct spi_device *spi = to_spi_device(wilc->dev);
769 struct wilc_spi *spi_priv = wilc->bus_data;
776 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
778 dev_err(&spi->dev, "Fail cmd read chip id...\n");
788 * TODO: We can remove the CRC trials if there is a definite
791 /* the SPI to it's initial value. */
792 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®);
795 * Read failed. Try with CRC off. This might happen when module
796 * is removed but chip isn't reset
798 spi_priv->crc_off = 1;
800 "Failed read with CRC on, retrying with CRC off\n");
801 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®);
804 * Read failed with both CRC on and off,
807 dev_err(&spi->dev, "Failed internal read protocol\n");
811 if (spi_priv->crc_off == 0) {
812 reg &= ~0xc; /* disable crc checking */
815 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg);
818 "[wilc spi %d]: Failed internal write reg\n",
822 spi_priv->crc_off = 1;
826 * make sure can read back chip id correctly
828 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
830 dev_err(&spi->dev, "Fail cmd read chip id...\n");
839 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
843 ret = spi_internal_read(wilc,
844 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size);
845 *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size);
850 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
852 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE,
856 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
858 return spi_internal_write(wilc, WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
862 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
864 struct spi_device *spi = to_spi_device(wilc->dev);
868 if (nint > MAX_NUM_INT) {
869 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
874 * interrupt pin mux select
876 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®);
878 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
883 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
885 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
893 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®);
895 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
900 for (i = 0; (i < 5) && (nint > 0); i++, nint--)
901 reg |= (BIT((27 + i)));
903 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
905 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
910 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
912 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
917 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
920 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
922 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
931 /* Global spi HIF function table */
932 static const struct wilc_hif_func wilc_hif_spi = {
933 .hif_init = wilc_spi_init,
934 .hif_deinit = wilc_spi_deinit,
935 .hif_read_reg = wilc_spi_read_reg,
936 .hif_write_reg = wilc_spi_write_reg,
937 .hif_block_rx = wilc_spi_read,
938 .hif_block_tx = wilc_spi_write,
939 .hif_read_int = wilc_spi_read_int,
940 .hif_clear_int_ext = wilc_spi_clear_int_ext,
941 .hif_read_size = wilc_spi_read_size,
942 .hif_block_tx_ext = wilc_spi_write,
943 .hif_block_rx_ext = wilc_spi_read,
944 .hif_sync_ext = wilc_spi_sync_ext,