1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
7 struct mt7915_mcu_txd {
15 u8 set_query; /* FW don't care */
24 } __packed __aligned(4);
28 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
29 MCU_EVENT_FW_START = 0x01,
30 MCU_EVENT_GENERIC = 0x01,
31 MCU_EVENT_ACCESS_REG = 0x02,
32 MCU_EVENT_MT_PATCH_SEM = 0x04,
33 MCU_EVENT_CH_PRIVILEGE = 0x18,
35 MCU_EVENT_RESTART_DL = 0xef,
40 MCU_EXT_EVENT_PS_SYNC = 0x5,
41 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
42 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
43 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
44 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
45 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
46 MCU_EXT_EVENT_RATE_REPORT = 0x87,
50 MCU_ATE_SET_TRX = 0x1,
51 MCU_ATE_SET_FREQ_OFFSET = 0xa,
52 MCU_ATE_SET_SLOT_TIME = 0x13,
53 MCU_ATE_CLEAN_TXQUEUE = 0x1c,
56 struct mt7915_mcu_rxd {
71 struct mt7915_mcu_rdd_report {
72 struct mt7915_mcu_rxd rxd;
76 u8 constant_prf_detected;
77 u8 staggered_prf_detected;
79 u8 periodic_pulse_num;
94 __le32 out_pri_stg[3];
110 } periodic_pulse[32];
123 struct mt7915_mcu_eeprom {
129 struct mt7915_mcu_eeprom_info {
135 struct mt7915_mcu_ra_info {
136 struct mt7915_mcu_rxd rxd;
145 __le32 min_rate; /* for dynamic sounding */
146 __le32 max_rate; /* for dynamic sounding */
147 __le32 init_rate_down_rate;
150 __le16 init_rate_down_total;
151 __le16 init_rate_down_succ;
166 u8 prob_down_pending;
170 struct mt7915_mcu_phy_rx_info {
181 #define MT_RA_RATE_NSS GENMASK(8, 6)
182 #define MT_RA_RATE_MCS GENMASK(3, 0)
183 #define MT_RA_RATE_TX_MODE GENMASK(12, 9)
184 #define MT_RA_RATE_DCM_EN BIT(4)
185 #define MT_RA_RATE_BW GENMASK(14, 13)
196 struct mt7915_mcu_tx {
202 struct edca edca[IEEE80211_NUM_ACS];
205 #define WMM_AIFS_SET BIT(0)
206 #define WMM_CW_MIN_SET BIT(1)
207 #define WMM_CW_MAX_SET BIT(2)
208 #define WMM_TXOP_SET BIT(3)
209 #define WMM_PARAM_SET GENMASK(3, 0)
211 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10))
212 #define MCU_PKT_ID 0xa0
229 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
230 MCU_CMD_FW_START_REQ = 0x02,
231 MCU_CMD_INIT_ACCESS_REG = 0x3,
232 MCU_CMD_NIC_POWER_CTRL = 0x4,
233 MCU_CMD_PATCH_START_REQ = 0x05,
234 MCU_CMD_PATCH_FINISH_REQ = 0x07,
235 MCU_CMD_PATCH_SEM_CONTROL = 0x10,
236 MCU_CMD_EXT_CID = 0xED,
237 MCU_CMD_FW_SCATTER = 0xEE,
238 MCU_CMD_RESTART_DL_REQ = 0xEF,
242 MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
243 MCU_EXT_CMD_RF_TEST = 0x04,
244 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
245 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
246 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
247 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
248 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
249 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
250 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
251 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
252 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
253 MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
254 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
255 MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
256 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
257 MCU_EXT_CMD_ATE_CTRL = 0x3d,
258 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
259 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
260 MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
261 MCU_EXT_CMD_MUAR_UPDATE = 0x48,
262 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
263 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
264 MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
265 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
266 MCU_EXT_CMD_SCS_CTRL = 0x82,
267 MCU_EXT_CMD_RATE_CTRL = 0x87,
268 MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
269 MCU_EXT_CMD_SET_RDD_TH = 0x9d,
270 MCU_EXT_CMD_SET_SPR = 0xa8,
271 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
280 PATCH_NOT_DL_SEM_FAIL,
282 PATCH_NOT_DL_SEM_SUCCESS,
283 PATCH_REL_SEM_SUCCESS
288 FW_STATE_FW_DOWNLOAD,
289 FW_STATE_NORMAL_OPERATION,
291 FW_STATE_WACPU_RDY = 7
306 MCU_PHY_STATE_TX_RATE,
307 MCU_PHY_STATE_RX_RATE,
309 MCU_PHY_STATE_CONTENTION_RX_RATE,
310 MCU_PHY_STATE_OFDMLQ_CNINFO,
313 #define STA_TYPE_STA BIT(0)
314 #define STA_TYPE_AP BIT(1)
315 #define STA_TYPE_ADHOC BIT(2)
316 #define STA_TYPE_WDS BIT(4)
317 #define STA_TYPE_BC BIT(5)
319 #define NETWORK_INFRA BIT(16)
320 #define NETWORK_P2P BIT(17)
321 #define NETWORK_IBSS BIT(18)
322 #define NETWORK_WDS BIT(21)
324 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
325 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
326 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
327 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
328 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
329 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
330 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
332 #define CONN_STATE_DISCONNECT 0
333 #define CONN_STATE_CONNECT 1
334 #define CONN_STATE_PORT_SECURE 2
343 SCS_SET_MANUAL_PD_TH,
348 SCS_GET_GLO_ADDR_EVENT,
352 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20,
353 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40,
354 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80,
355 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160,
371 struct bss_info_omac {
382 struct bss_info_basic {
395 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
396 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
397 u8 bmc_wcid_hi; /* high Byte and version */
401 struct bss_info_rf_ch {
408 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */
409 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */
413 struct bss_info_ext_bss {
416 __le32 mbss_tsf_offset; /* in unit of us */
420 struct bss_info_bmc_rate {
441 u8 has_20_sta; /* Check if any sta support GF. */
442 u8 bss_width_trigger_events;
444 u8 vht_bw_signal; /* not use */
445 u8 vht_force_sgi; /* not use */
450 unsigned short train_up_high_thres;
451 short train_up_rule_rssi;
452 unsigned short low_traffic_thres;
456 __le32 fast_interval;
459 struct bss_info_hw_amsdu {
473 u8 vht_op_info_present;
475 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
479 struct bss_info_bcn {
485 } __packed __aligned(4);
487 struct bss_info_bcn_csa {
492 } __packed __aligned(4);
494 struct bss_info_bcn_bcc {
499 } __packed __aligned(4);
501 struct bss_info_bcn_mbss {
502 #define MAX_BEACON_NUM 32
506 __le16 offset[MAX_BEACON_NUM];
508 } __packed __aligned(4);
510 struct bss_info_bcn_cont {
517 } __packed __aligned(4);
523 BSS_INFO_BCN_CONTENT,
530 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */
531 BSS_INFO_PM, /* sta only */
532 BSS_INFO_UAPSD, /* sta only */
533 BSS_INFO_ROAM_DETECT, /* obsoleted */
534 BSS_INFO_LQ_RM, /* obsoleted */
536 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */
537 BSS_INFO_SYNC_MODE, /* obsoleted */
542 BSS_INFO_PROTECT_INFO,
549 WTBL_RESET_AND_SET = 1,
555 struct wtbl_req_hdr {
563 struct wtbl_generic {
566 u8 peer_addr[ETH_ALEN];
608 struct wtbl_hdr_trans {
619 MT_BA_TYPE_ORIGINATOR,
624 RST_BA_MAC_TID_MATCH,
636 /* originator only */
642 u8 peer_addr[ETH_ALEN];
662 WTBL_PEER_PS, /* not used */
667 WTBL_RDG, /* obsoleted */
668 WTBL_PROTECT, /* not used */
669 WTBL_CLEAR, /* not used */
672 WTBL_RAW_DATA, /* debug only */
678 struct sta_ntlv_hdr {
693 struct sta_rec_basic {
700 u8 peer_addr[ETH_ALEN];
715 __le16 vht_rx_mcs_map;
716 __le16 vht_tx_mcs_map;
721 struct sta_rec_uapsd {
728 __le16 listen_interval;
732 struct sta_rec_muru {
746 bool he_20m_in_40m_2g;
750 bool rx_su_comp_sigb;
751 bool rx_su_non_comp_sigb;
766 bool partial_bw_dl_mimo;
772 bool partial_ul_mimo;
796 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
812 struct sta_rec_amsdu {
836 struct sec_key key[2];
874 __le16 supp_vht_mcs[4];
877 u8 op_vht_chan_width;
879 u8 op_vht_rx_nss_type;
886 struct sta_rec_ra_fixed {
892 u8 op_vht_chan_width;
894 u8 op_vht_rx_nss_type;
904 #define RATE_PARAM_FIXED 3
905 #define RATE_PARAM_AUTO 20
906 #define RATE_CFG_MCS GENMASK(3, 0)
907 #define RATE_CFG_NSS GENMASK(7, 4)
908 #define RATE_CFG_GI GENMASK(11, 8)
909 #define RATE_CFG_BW GENMASK(15, 12)
910 #define RATE_CFG_STBC GENMASK(19, 16)
911 #define RATE_CFG_LDPC GENMASK(23, 20)
912 #define RATE_CFG_PHY_TYPE GENMASK(27, 24)
918 __le16 pfmu; /* 0xffff: no access right for PFMU */
919 bool su_mu; /* 0: SU, 1: MU */
920 u8 bf_cap; /* 0: iBF, 1: eBF */
921 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
925 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
928 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
934 u8 col: 6, row_msb: 2;
939 u8 auto_sounding; /* b7: low traffic indicator
940 * b6: Stop sounding for this entry
941 * b5 ~ b0: postpone sounding
963 struct sta_rec_bfee {
966 bool fb_identity_matrix; /* 1: feedback identity matrix */
967 bool ignore_feedback; /* 1: ignore */
979 STA_REC_RED, /* not used */
980 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
996 enum mt7915_cipher_type {
1007 MT_CIPHER_BIP_CMAC_128,
1011 CH_SWITCH_NORMAL = 0,
1015 CH_SWITCH_BACKGROUND_SCAN_START = 6,
1016 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
1017 CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
1018 CH_SWITCH_SCAN_BYPASS_DPD = 9
1022 THERMAL_SENSOR_TEMP_QUERY,
1023 THERMAL_SENSOR_MANUAL_CTRL,
1024 THERMAL_SENSOR_INFO_QUERY,
1025 THERMAL_SENSOR_TASK_CTRL,
1029 MT_EBF = BIT(0), /* explicit beamforming */
1030 MT_IBF = BIT(1) /* implicit beamforming */
1033 #define MT7915_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
1034 sizeof(struct wtbl_generic) + \
1035 sizeof(struct wtbl_rx) + \
1036 sizeof(struct wtbl_ht) + \
1037 sizeof(struct wtbl_vht) + \
1038 sizeof(struct wtbl_hdr_trans) +\
1039 sizeof(struct wtbl_ba) + \
1040 sizeof(struct wtbl_smps))
1042 #define MT7915_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
1043 sizeof(struct sta_rec_basic) + \
1044 sizeof(struct sta_rec_ht) + \
1045 sizeof(struct sta_rec_he) + \
1046 sizeof(struct sta_rec_ba) + \
1047 sizeof(struct sta_rec_vht) + \
1048 sizeof(struct sta_rec_uapsd) + \
1049 sizeof(struct sta_rec_amsdu) + \
1050 sizeof(struct tlv) + \
1051 MT7915_WTBL_UPDATE_MAX_SIZE)
1053 #define MT7915_WTBL_UPDATE_BA_SIZE (sizeof(struct wtbl_req_hdr) + \
1054 sizeof(struct wtbl_ba))
1056 #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
1057 sizeof(struct bss_info_omac) + \
1058 sizeof(struct bss_info_basic) +\
1059 sizeof(struct bss_info_rf_ch) +\
1060 sizeof(struct bss_info_ra) + \
1061 sizeof(struct bss_info_hw_amsdu) +\
1062 sizeof(struct bss_info_he) + \
1063 sizeof(struct bss_info_bmc_rate) +\
1064 sizeof(struct bss_info_ext_bss))
1066 #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \
1067 sizeof(struct bss_info_bcn_csa) + \
1068 sizeof(struct bss_info_bcn_bcc) + \
1069 sizeof(struct bss_info_bcn_mbss) + \
1070 sizeof(struct bss_info_bcn_cont))
1072 #define PHY_MODE_A BIT(0)
1073 #define PHY_MODE_B BIT(1)
1074 #define PHY_MODE_G BIT(2)
1075 #define PHY_MODE_GN BIT(3)
1076 #define PHY_MODE_AN BIT(4)
1077 #define PHY_MODE_AC BIT(5)
1078 #define PHY_MODE_AX_24G BIT(6)
1079 #define PHY_MODE_AX_5G BIT(7)
1080 #define PHY_MODE_AX_6G BIT(8)
1082 #define MODE_CCK BIT(0)
1083 #define MODE_OFDM BIT(1)
1084 #define MODE_HT BIT(2)
1085 #define MODE_VHT BIT(3)
1086 #define MODE_HE BIT(4)
1088 #define STA_CAP_WMM BIT(0)
1089 #define STA_CAP_SGI_20 BIT(4)
1090 #define STA_CAP_SGI_40 BIT(5)
1091 #define STA_CAP_TX_STBC BIT(6)
1092 #define STA_CAP_RX_STBC BIT(7)
1093 #define STA_CAP_VHT_SGI_80 BIT(16)
1094 #define STA_CAP_VHT_SGI_160 BIT(17)
1095 #define STA_CAP_VHT_TX_STBC BIT(18)
1096 #define STA_CAP_VHT_RX_STBC BIT(19)
1097 #define STA_CAP_VHT_LDPC BIT(23)
1098 #define STA_CAP_LDPC BIT(24)
1099 #define STA_CAP_HT BIT(26)
1100 #define STA_CAP_VHT BIT(27)
1101 #define STA_CAP_HE BIT(28)
1104 #define STA_REC_HE_CAP_HTC BIT(0)
1105 #define STA_REC_HE_CAP_BQR BIT(1)
1106 #define STA_REC_HE_CAP_BSR BIT(2)
1107 #define STA_REC_HE_CAP_OM BIT(3)
1108 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
1110 #define STA_REC_HE_CAP_DUAL_BAND BIT(5)
1111 #define STA_REC_HE_CAP_LDPC BIT(6)
1112 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
1113 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
1115 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
1116 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
1117 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
1118 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
1120 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
1121 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
1122 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
1123 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
1124 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
1126 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
1127 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
1128 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)