1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
18 mt7915_implicit_txbf_set(void *data, u64 val)
20 struct mt7915_dev *dev = data;
22 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state))
27 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE);
31 mt7915_implicit_txbf_get(void *data, u64 *val)
33 struct mt7915_dev *dev = data;
40 DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7915_implicit_txbf_get,
41 mt7915_implicit_txbf_set, "%lld\n");
43 /* test knob of system layer 1/2 error recovery */
44 static int mt7915_ser_trigger_set(void *data, u64 val)
47 SER_SET_RECOVER_L1 = 1,
52 struct mt7915_dev *dev = data;
56 case SER_SET_RECOVER_L1:
57 case SER_SET_RECOVER_L2:
58 ret = mt7915_mcu_set_ser(dev, SER_ENABLE, BIT(val), 0);
62 return mt7915_mcu_set_ser(dev, SER_RECOVER, val, 0);
70 DEFINE_DEBUGFS_ATTRIBUTE(fops_ser_trigger, NULL,
71 mt7915_ser_trigger_set, "%lld\n");
74 mt7915_radar_trigger(void *data, u64 val)
76 struct mt7915_dev *dev = data;
78 return mt7915_mcu_rdd_cmd(dev, RDD_RADAR_EMULATE, 1, 0, 0);
81 DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL,
82 mt7915_radar_trigger, "%lld\n");
85 mt7915_muru_debug_set(void *data, u64 val)
87 struct mt7915_dev *dev = data;
89 dev->muru_debug = val;
90 mt7915_mcu_muru_debug_set(dev, data);
96 mt7915_muru_debug_get(void *data, u64 *val)
98 struct mt7915_dev *dev = data;
100 *val = dev->muru_debug;
105 DEFINE_DEBUGFS_ATTRIBUTE(fops_muru_debug, mt7915_muru_debug_get,
106 mt7915_muru_debug_set, "%lld\n");
108 static int mt7915_muru_stats_show(struct seq_file *file, void *data)
110 struct mt7915_phy *phy = file->private;
111 struct mt7915_dev *dev = phy->dev;
112 struct mt7915_mcu_muru_stats mu_stats = {};
113 static const char * const dl_non_he_type[] = {
114 "CCK", "OFDM", "HT MIX", "HT GF",
115 "VHT SU", "VHT 2MU", "VHT 3MU", "VHT 4MU"
117 static const char * const dl_he_type[] = {
118 "HE SU", "HE EXT", "HE 2MU", "HE 3MU", "HE 4MU",
119 "HE 2RU", "HE 3RU", "HE 4RU", "HE 5-8RU", "HE 9-16RU",
122 static const char * const ul_he_type[] = {
123 "HE 2MU", "HE 3MU", "HE 4MU", "HE SU", "HE 2RU",
124 "HE 3RU", "HE 4RU", "HE 5-8RU", "HE 9-16RU", "HE >16RU"
127 u64 total_ppdu_cnt, sub_total_cnt;
129 if (!dev->muru_debug) {
130 seq_puts(file, "Please enable muru_debug first.\n");
134 mutex_lock(&dev->mt76.mutex);
136 ret = mt7915_mcu_muru_debug_get(phy, &mu_stats);
141 seq_puts(file, "[Non-HE]\nDownlink\nData Type: ");
143 for (i = 0; i < 5; i++)
144 seq_printf(file, "%8s | ", dl_non_he_type[i]);
146 #define __dl_u32(s) le32_to_cpu(mu_stats.dl.s)
147 seq_puts(file, "\nTotal Count:");
148 seq_printf(file, "%8u | %8u | %8u | %8u | %8u | ",
153 __dl_u32(vht_su_cnt));
155 seq_puts(file, "\nDownlink MU-MIMO\nData Type: ");
157 for (i = 5; i < 8; i++)
158 seq_printf(file, "%8s | ", dl_non_he_type[i]);
160 seq_puts(file, "\nTotal Count:");
161 seq_printf(file, "%8u | %8u | %8u | ",
162 __dl_u32(vht_2mu_cnt),
163 __dl_u32(vht_3mu_cnt),
164 __dl_u32(vht_4mu_cnt));
166 sub_total_cnt = __dl_u32(vht_2mu_cnt) +
167 __dl_u32(vht_3mu_cnt) +
168 __dl_u32(vht_4mu_cnt);
170 seq_printf(file, "\nTotal non-HE MU-MIMO DL PPDU count: %lld",
173 total_ppdu_cnt = sub_total_cnt +
176 __dl_u32(htmix_cnt) +
178 __dl_u32(vht_su_cnt);
180 seq_printf(file, "\nAll non-HE DL PPDU count: %lld", total_ppdu_cnt);
183 seq_puts(file, "\n\n[HE]\nDownlink\nData Type: ");
185 for (i = 0; i < 2; i++)
186 seq_printf(file, "%8s | ", dl_he_type[i]);
188 seq_puts(file, "\nTotal Count:");
189 seq_printf(file, "%8u | %8u | ",
191 __dl_u32(he_ext_su_cnt));
193 seq_puts(file, "\nDownlink MU-MIMO\nData Type: ");
195 for (i = 2; i < 5; i++)
196 seq_printf(file, "%8s | ", dl_he_type[i]);
198 seq_puts(file, "\nTotal Count:");
199 seq_printf(file, "%8u | %8u | %8u | ",
200 __dl_u32(he_2mu_cnt),
201 __dl_u32(he_3mu_cnt),
202 __dl_u32(he_4mu_cnt));
204 seq_puts(file, "\nDownlink OFDMA\nData Type: ");
206 for (i = 5; i < 11; i++)
207 seq_printf(file, "%8s | ", dl_he_type[i]);
209 seq_puts(file, "\nTotal Count:");
210 seq_printf(file, "%8u | %8u | %8u | %8u | %9u | %8u | ",
211 __dl_u32(he_2ru_cnt),
212 __dl_u32(he_3ru_cnt),
213 __dl_u32(he_4ru_cnt),
214 __dl_u32(he_5to8ru_cnt),
215 __dl_u32(he_9to16ru_cnt),
216 __dl_u32(he_gtr16ru_cnt));
218 sub_total_cnt = __dl_u32(he_2mu_cnt) +
219 __dl_u32(he_3mu_cnt) +
220 __dl_u32(he_4mu_cnt);
221 total_ppdu_cnt = sub_total_cnt;
223 seq_printf(file, "\nTotal HE MU-MIMO DL PPDU count: %lld",
226 sub_total_cnt = __dl_u32(he_2ru_cnt) +
227 __dl_u32(he_3ru_cnt) +
228 __dl_u32(he_4ru_cnt) +
229 __dl_u32(he_5to8ru_cnt) +
230 __dl_u32(he_9to16ru_cnt) +
231 __dl_u32(he_gtr16ru_cnt);
232 total_ppdu_cnt += sub_total_cnt;
234 seq_printf(file, "\nTotal HE OFDMA DL PPDU count: %lld",
237 total_ppdu_cnt += __dl_u32(he_su_cnt) +
238 __dl_u32(he_ext_su_cnt);
240 seq_printf(file, "\nAll HE DL PPDU count: %lld", total_ppdu_cnt);
244 seq_puts(file, "\n\nUplink");
245 seq_puts(file, "\nTrigger-based Uplink MU-MIMO\nData Type: ");
247 for (i = 0; i < 3; i++)
248 seq_printf(file, "%8s | ", ul_he_type[i]);
250 #define __ul_u32(s) le32_to_cpu(mu_stats.ul.s)
251 seq_puts(file, "\nTotal Count:");
252 seq_printf(file, "%8u | %8u | %8u | ",
253 __ul_u32(hetrig_2mu_cnt),
254 __ul_u32(hetrig_3mu_cnt),
255 __ul_u32(hetrig_4mu_cnt));
257 seq_puts(file, "\nTrigger-based Uplink OFDMA\nData Type: ");
259 for (i = 3; i < 10; i++)
260 seq_printf(file, "%8s | ", ul_he_type[i]);
262 seq_puts(file, "\nTotal Count:");
263 seq_printf(file, "%8u | %8u | %8u | %8u | %8u | %9u | %7u | ",
264 __ul_u32(hetrig_su_cnt),
265 __ul_u32(hetrig_2ru_cnt),
266 __ul_u32(hetrig_3ru_cnt),
267 __ul_u32(hetrig_4ru_cnt),
268 __ul_u32(hetrig_5to8ru_cnt),
269 __ul_u32(hetrig_9to16ru_cnt),
270 __ul_u32(hetrig_gtr16ru_cnt));
272 sub_total_cnt = __ul_u32(hetrig_2mu_cnt) +
273 __ul_u32(hetrig_3mu_cnt) +
274 __ul_u32(hetrig_4mu_cnt);
275 total_ppdu_cnt = sub_total_cnt;
277 seq_printf(file, "\nTotal HE MU-MIMO UL TB PPDU count: %lld",
280 sub_total_cnt = __ul_u32(hetrig_2ru_cnt) +
281 __ul_u32(hetrig_3ru_cnt) +
282 __ul_u32(hetrig_4ru_cnt) +
283 __ul_u32(hetrig_5to8ru_cnt) +
284 __ul_u32(hetrig_9to16ru_cnt) +
285 __ul_u32(hetrig_gtr16ru_cnt);
286 total_ppdu_cnt += sub_total_cnt;
288 seq_printf(file, "\nTotal HE OFDMA UL TB PPDU count: %lld",
291 total_ppdu_cnt += __ul_u32(hetrig_su_cnt);
293 seq_printf(file, "\nAll HE UL TB PPDU count: %lld\n", total_ppdu_cnt);
297 mutex_unlock(&dev->mt76.mutex);
301 DEFINE_SHOW_ATTRIBUTE(mt7915_muru_stats);
304 mt7915_fw_debug_wm_set(void *data, u64 val)
306 struct mt7915_dev *dev = data;
316 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
318 ret = mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, dev->fw_debug_wm);
322 for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RX; debug++) {
323 ret = mt7915_mcu_fw_dbg_ctrl(dev, debug, !!dev->fw_debug_wm);
328 /* WM CPU info record control */
329 mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0));
330 mt76_wr(dev, MT_DIC_CMD_REG_CMD, BIT(2) | BIT(13) | !dev->fw_debug_wm);
331 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5));
332 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5));
338 mt7915_fw_debug_wm_get(void *data, u64 *val)
340 struct mt7915_dev *dev = data;
342 *val = dev->fw_debug_wm;
347 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wm, mt7915_fw_debug_wm_get,
348 mt7915_fw_debug_wm_set, "%lld\n");
351 mt7915_fw_debug_wa_set(void *data, u64 val)
353 struct mt7915_dev *dev = data;
356 dev->fw_debug_wa = val ? MCU_FW_LOG_TO_HOST : 0;
358 ret = mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, dev->fw_debug_wa);
362 return mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), MCU_WA_PARAM_PDMA_RX,
363 !!dev->fw_debug_wa, 0);
367 mt7915_fw_debug_wa_get(void *data, u64 *val)
369 struct mt7915_dev *dev = data;
371 *val = dev->fw_debug_wa;
376 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wa, mt7915_fw_debug_wa_get,
377 mt7915_fw_debug_wa_set, "%lld\n");
380 mt7915_fw_util_wm_show(struct seq_file *file, void *data)
382 struct mt7915_dev *dev = file->private;
384 if (dev->fw_debug_wm) {
385 seq_printf(file, "Busy: %u%% Peak busy: %u%%\n",
386 mt76_rr(dev, MT_CPU_UTIL_BUSY_PCT),
387 mt76_rr(dev, MT_CPU_UTIL_PEAK_BUSY_PCT));
388 seq_printf(file, "Idle count: %u Peak idle count: %u\n",
389 mt76_rr(dev, MT_CPU_UTIL_IDLE_CNT),
390 mt76_rr(dev, MT_CPU_UTIL_PEAK_IDLE_CNT));
396 DEFINE_SHOW_ATTRIBUTE(mt7915_fw_util_wm);
399 mt7915_fw_util_wa_show(struct seq_file *file, void *data)
401 struct mt7915_dev *dev = file->private;
403 if (dev->fw_debug_wa)
404 return mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY),
405 MCU_WA_PARAM_CPU_UTIL, 0, 0);
410 DEFINE_SHOW_ATTRIBUTE(mt7915_fw_util_wa);
413 mt7915_ampdu_stat_read_phy(struct mt7915_phy *phy,
414 struct seq_file *file)
416 struct mt7915_dev *dev = phy->dev;
417 bool ext_phy = phy != &dev->phy;
418 int bound[15], range[4], i, n;
421 for (i = 0; i < ARRAY_SIZE(range); i++)
422 range[i] = mt76_rr(dev, MT_MIB_ARNG(ext_phy, i));
424 for (i = 0; i < ARRAY_SIZE(bound); i++)
425 bound[i] = MT_MIB_ARNCR_RANGE(range[i / 4], i % 4) + 1;
427 seq_printf(file, "\nPhy %d\n", ext_phy);
429 seq_printf(file, "Length: %8d | ", bound[0]);
430 for (i = 0; i < ARRAY_SIZE(bound) - 1; i++)
431 seq_printf(file, "%3d -%3d | ",
432 bound[i] + 1, bound[i + 1]);
434 seq_puts(file, "\nCount: ");
435 n = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
436 for (i = 0; i < ARRAY_SIZE(bound); i++)
437 seq_printf(file, "%8d | ", dev->mt76.aggr_stats[i + n]);
438 seq_puts(file, "\n");
440 seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt);
444 mt7915_txbf_stat_read_phy(struct mt7915_phy *phy, struct seq_file *s)
446 static const char * const bw[] = {
447 "BW20", "BW40", "BW80", "BW160"
449 struct mib_stats *mib = &phy->mib;
451 /* Tx Beamformer monitor */
452 seq_puts(s, "\nTx Beamformer applied PPDU counts: ");
454 seq_printf(s, "iBF: %d, eBF: %d\n",
455 mib->tx_bf_ibf_ppdu_cnt,
456 mib->tx_bf_ebf_ppdu_cnt);
458 /* Tx Beamformer Rx feedback monitor */
459 seq_puts(s, "Tx Beamformer Rx feedback statistics: ");
461 seq_printf(s, "All: %d, HE: %d, VHT: %d, HT: %d, ",
462 mib->tx_bf_rx_fb_all_cnt,
463 mib->tx_bf_rx_fb_he_cnt,
464 mib->tx_bf_rx_fb_vht_cnt,
465 mib->tx_bf_rx_fb_ht_cnt);
467 seq_printf(s, "%s, NC: %d, NR: %d\n",
468 bw[mib->tx_bf_rx_fb_bw],
469 mib->tx_bf_rx_fb_nc_cnt,
470 mib->tx_bf_rx_fb_nr_cnt);
472 /* Tx Beamformee Rx NDPA & Tx feedback report */
473 seq_printf(s, "Tx Beamformee successful feedback frames: %d\n",
474 mib->tx_bf_fb_cpl_cnt);
475 seq_printf(s, "Tx Beamformee feedback triggered counts: %d\n",
476 mib->tx_bf_fb_trig_cnt);
478 /* Tx SU & MU counters */
479 seq_printf(s, "Tx multi-user Beamforming counts: %d\n",
481 seq_printf(s, "Tx multi-user MPDU counts: %d\n", mib->tx_mu_mpdu_cnt);
482 seq_printf(s, "Tx multi-user successful MPDU counts: %d\n",
483 mib->tx_mu_acked_mpdu_cnt);
484 seq_printf(s, "Tx single-user successful MPDU counts: %d\n",
485 mib->tx_su_acked_mpdu_cnt);
491 mt7915_tx_stats_show(struct seq_file *file, void *data)
493 struct mt7915_phy *phy = file->private;
494 struct mt7915_dev *dev = phy->dev;
495 struct mib_stats *mib = &phy->mib;
498 mutex_lock(&dev->mt76.mutex);
500 mt7915_ampdu_stat_read_phy(phy, file);
501 mt7915_mac_update_stats(phy);
502 mt7915_txbf_stat_read_phy(phy, file);
505 seq_puts(file, "Tx MSDU statistics:\n");
506 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) {
507 seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ",
508 i + 1, mib->tx_amsdu[i]);
509 if (mib->tx_amsdu_cnt)
510 seq_printf(file, "(%3d%%)\n",
511 mib->tx_amsdu[i] * 100 / mib->tx_amsdu_cnt);
513 seq_puts(file, "\n");
516 mutex_unlock(&dev->mt76.mutex);
521 DEFINE_SHOW_ATTRIBUTE(mt7915_tx_stats);
524 mt7915_hw_queue_read(struct seq_file *s, u32 base, u32 size,
525 const struct hw_queue_map *map)
527 struct mt7915_phy *phy = s->private;
528 struct mt7915_dev *dev = phy->dev;
531 val = mt76_rr(dev, base + MT_FL_Q_EMPTY);
532 for (i = 0; i < size; i++) {
533 u32 ctrl, head, tail, queued;
535 if (val & BIT(map[i].index))
538 ctrl = BIT(31) | (map[i].pid << 10) | (map[i].qid << 24);
539 mt76_wr(dev, base + MT_FL_Q0_CTRL, ctrl);
541 head = mt76_get_field(dev, base + MT_FL_Q2_CTRL,
543 tail = mt76_get_field(dev, base + MT_FL_Q2_CTRL,
545 queued = mt76_get_field(dev, base + MT_FL_Q3_CTRL,
548 seq_printf(s, "\t%s: ", map[i].name);
549 seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n",
555 mt7915_sta_hw_queue_read(void *data, struct ieee80211_sta *sta)
557 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
558 struct mt7915_dev *dev = msta->vif->phy->dev;
559 struct seq_file *s = data;
562 for (ac = 0; ac < 4; ac++) {
564 u32 idx = msta->wcid.idx >> 5;
565 u8 offs = msta->wcid.idx & GENMASK(4, 0);
567 ctrl = BIT(31) | BIT(11) | (ac << 24);
568 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx));
573 mt76_wr(dev, MT_PLE_BASE + MT_FL_Q0_CTRL, ctrl | msta->wcid.idx);
574 qlen = mt76_get_field(dev, MT_PLE_BASE + MT_FL_Q3_CTRL,
576 seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n",
577 sta->addr, msta->wcid.idx,
578 msta->vif->mt76.wmm_idx, ac, qlen);
583 mt7915_hw_queues_show(struct seq_file *file, void *data)
585 struct mt7915_phy *phy = file->private;
586 struct mt7915_dev *dev = phy->dev;
587 static const struct hw_queue_map ple_queue_map[] = {
588 { "CPU_Q0", 0, 1, MT_CTX0 },
589 { "CPU_Q1", 1, 1, MT_CTX0 + 1 },
590 { "CPU_Q2", 2, 1, MT_CTX0 + 2 },
591 { "CPU_Q3", 3, 1, MT_CTX0 + 3 },
592 { "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 },
593 { "BMC_Q0", 9, 2, MT_LMAC_BMC0 },
594 { "BCN_Q0", 10, 2, MT_LMAC_BCN0 },
595 { "PSMP_Q0", 11, 2, MT_LMAC_PSMP0 },
596 { "ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4 },
597 { "BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4 },
598 { "BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4 },
599 { "PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4 },
601 static const struct hw_queue_map pse_queue_map[] = {
602 { "CPU Q0", 0, 1, MT_CTX0 },
603 { "CPU Q1", 1, 1, MT_CTX0 + 1 },
604 { "CPU Q2", 2, 1, MT_CTX0 + 2 },
605 { "CPU Q3", 3, 1, MT_CTX0 + 3 },
606 { "HIF_Q0", 8, 0, MT_HIF0 },
607 { "HIF_Q1", 9, 0, MT_HIF0 + 1 },
608 { "HIF_Q2", 10, 0, MT_HIF0 + 2 },
609 { "HIF_Q3", 11, 0, MT_HIF0 + 3 },
610 { "HIF_Q4", 12, 0, MT_HIF0 + 4 },
611 { "HIF_Q5", 13, 0, MT_HIF0 + 5 },
612 { "LMAC_Q", 16, 2, 0 },
613 { "MDP_TXQ", 17, 2, 1 },
614 { "MDP_RXQ", 18, 2, 2 },
615 { "SEC_TXQ", 19, 2, 3 },
616 { "SEC_RXQ", 20, 2, 4 },
621 val = mt76_rr(dev, MT_PLE_FREEPG_CNT);
622 head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0));
623 tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16));
624 seq_puts(file, "PLE page info:\n");
626 "\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n",
629 val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP);
630 head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0));
631 tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16));
632 seq_printf(file, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n",
635 seq_puts(file, "PLE non-empty queue info:\n");
636 mt7915_hw_queue_read(file, MT_PLE_BASE, ARRAY_SIZE(ple_queue_map),
639 /* iterate per-sta ple queue */
640 ieee80211_iterate_stations_atomic(phy->mt76->hw,
641 mt7915_sta_hw_queue_read, file);
643 seq_puts(file, "PSE non-empty queue info:\n");
644 mt7915_hw_queue_read(file, MT_PSE_BASE, ARRAY_SIZE(pse_queue_map),
650 DEFINE_SHOW_ATTRIBUTE(mt7915_hw_queues);
653 mt7915_xmit_queues_show(struct seq_file *file, void *data)
655 struct mt7915_phy *phy = file->private;
656 struct mt7915_dev *dev = phy->dev;
658 struct mt76_queue *q;
661 { phy->mt76->q_tx[MT_TXQ_BE], " MAIN" },
662 { dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" },
663 { dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" },
664 { dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" },
668 seq_puts(file, " queue | hw-queued | head | tail |\n");
669 for (i = 0; i < ARRAY_SIZE(queue_map); i++) {
670 struct mt76_queue *q = queue_map[i].q;
675 seq_printf(file, " %s | %9d | %9d | %9d |\n",
676 queue_map[i].queue, q->queued, q->head,
683 DEFINE_SHOW_ATTRIBUTE(mt7915_xmit_queues);
686 mt7915_rate_txpower_show(struct seq_file *file, void *data)
688 static const char * const sku_group_name[] = {
689 "CCK", "OFDM", "HT20", "HT40",
690 "VHT20", "VHT40", "VHT80", "VHT160",
691 "RU26", "RU52", "RU106", "RU242/SU20",
692 "RU484/SU40", "RU996/SU80", "RU2x996/SU160"
694 struct mt7915_phy *phy = file->private;
695 s8 txpower[MT7915_SKU_RATE_NUM], *buf;
698 seq_printf(file, "\nBand %d\n", phy != &phy->dev->phy);
699 mt7915_mcu_get_txpower_sku(phy, txpower, sizeof(txpower));
700 for (i = 0, buf = txpower; i < ARRAY_SIZE(mt7915_sku_group_len); i++) {
701 u8 mcs_num = mt7915_sku_group_len[i];
703 if (i >= SKU_VHT_BW20 && i <= SKU_VHT_BW160)
706 mt76_seq_puts_array(file, sku_group_name[i], buf, mcs_num);
707 buf += mt7915_sku_group_len[i];
713 DEFINE_SHOW_ATTRIBUTE(mt7915_rate_txpower);
716 mt7915_twt_stats(struct seq_file *s, void *data)
718 struct mt7915_dev *dev = dev_get_drvdata(s->private);
719 struct mt7915_twt_flow *iter;
723 seq_puts(s, " wcid | id | flags | exp | mantissa");
724 seq_puts(s, " | duration | tsf |\n");
725 list_for_each_entry_rcu(iter, &dev->twt_list, list)
727 "%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n",
728 iter->wcid, iter->id,
729 iter->sched ? 's' : 'u',
730 iter->protection ? 'p' : '-',
731 iter->trigger ? 't' : '-',
732 iter->flowtype ? '-' : 'a',
733 iter->exp, iter->mantissa,
734 iter->duration, iter->tsf);
741 int mt7915_init_debugfs(struct mt7915_phy *phy)
743 struct mt7915_dev *dev = phy->dev;
744 bool ext_phy = phy != &dev->phy;
747 dir = mt76_register_debugfs_fops(phy->mt76, NULL);
750 debugfs_create_file("muru_debug", 0600, dir, dev, &fops_muru_debug);
751 debugfs_create_file("muru_stats", 0400, dir, phy,
752 &mt7915_muru_stats_fops);
753 debugfs_create_file("hw-queues", 0400, dir, phy,
754 &mt7915_hw_queues_fops);
755 debugfs_create_file("xmit-queues", 0400, dir, phy,
756 &mt7915_xmit_queues_fops);
757 debugfs_create_file("tx_stats", 0400, dir, phy, &mt7915_tx_stats_fops);
758 debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm);
759 debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa);
760 debugfs_create_file("fw_util_wm", 0400, dir, dev,
761 &mt7915_fw_util_wm_fops);
762 debugfs_create_file("fw_util_wa", 0400, dir, dev,
763 &mt7915_fw_util_wa_fops);
764 debugfs_create_file("implicit_txbf", 0600, dir, dev,
765 &fops_implicit_txbf);
766 debugfs_create_file("txpower_sku", 0400, dir, phy,
767 &mt7915_rate_txpower_fops);
768 debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir,
770 debugfs_create_file("ser_trigger", 0200, dir, dev, &fops_ser_trigger);
771 if (!dev->dbdc_support || ext_phy) {
772 debugfs_create_u32("dfs_hw_pattern", 0400, dir,
774 debugfs_create_file("radar_trigger", 0200, dir, dev,
775 &fops_radar_trigger);
781 #ifdef CONFIG_MAC80211_DEBUGFS
782 /** per-station debugfs **/
784 static ssize_t mt7915_sta_fixed_rate_set(struct file *file,
785 const char __user *user_buf,
786 size_t count, loff_t *ppos)
788 struct ieee80211_sta *sta = file->private_data;
789 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
790 struct mt7915_dev *dev = msta->vif->phy->dev;
791 struct ieee80211_vif *vif;
792 struct sta_phy phy = {};
798 if (count >= sizeof(buf))
801 if (copy_from_user(buf, user_buf, count))
804 if (count && buf[count - 1] == '\n')
805 buf[count - 1] = '\0';
809 /* mode - cck: 0, ofdm: 1, ht: 2, gf: 3, vht: 4, he_su: 8, he_er: 9
810 * bw - bw20: 0, bw40: 1, bw80: 2, bw160: 3
811 * nss - vht: 1~4, he: 1~4, others: ignore
812 * mcs - cck: 0~4, ofdm: 0~7, ht: 0~32, vht: 0~9, he_su: 0~11, he_er: 0~2
813 * gi - (ht/vht) lgi: 0, sgi: 1; (he) 0.8us: 0, 1.6us: 1, 3.2us: 2
814 * ldpc - off: 0, on: 1
815 * stbc - off: 0, on: 1
816 * he_ltf - 1xltf: 0, 2xltf: 1, 4xltf: 2
818 if (sscanf(buf, "%hhu %hhu %hhu %hhu %hhu %hhu %hhu %hhu",
819 &phy.type, &phy.bw, &phy.nss, &phy.mcs, &gi,
820 &phy.ldpc, &phy.stbc, &he_ltf) != 8) {
821 dev_warn(dev->mt76.dev,
822 "format: Mode BW NSS MCS (HE)GI LDPC STBC HE_LTF\n");
823 field = RATE_PARAM_AUTO;
827 phy.ldpc = (phy.bw || phy.ldpc) * GENMASK(2, 0);
828 for (i = 0; i <= phy.bw; i++) {
829 phy.sgi |= gi << (i << sta->he_cap.has_he);
830 phy.he_ltf |= he_ltf << (i << sta->he_cap.has_he);
832 field = RATE_PARAM_FIXED;
835 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
836 ret = mt7915_mcu_set_fixed_rate_ctrl(dev, vif, sta, &phy, field);
843 static const struct file_operations fops_fixed_rate = {
844 .write = mt7915_sta_fixed_rate_set,
846 .owner = THIS_MODULE,
847 .llseek = default_llseek,
851 mt7915_queues_show(struct seq_file *s, void *data)
853 struct ieee80211_sta *sta = s->private;
855 mt7915_sta_hw_queue_read(s, sta);
860 DEFINE_SHOW_ATTRIBUTE(mt7915_queues);
862 void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
863 struct ieee80211_sta *sta, struct dentry *dir)
865 debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate);
866 debugfs_create_file("hw-queues", 0400, dir, sta, &mt7915_queues_fops);