2 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/delay.h>
21 #include "../mt76x02_phy.h"
22 #include "../mt76x02_usb.h"
24 static void mt76x2u_init_dma(struct mt76x02_dev *dev)
26 u32 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG));
28 val |= MT_USB_DMA_CFG_RX_DROP_OR_PAD |
29 MT_USB_DMA_CFG_RX_BULK_EN |
30 MT_USB_DMA_CFG_TX_BULK_EN;
32 /* disable AGGR_BULK_RX in order to receive one
33 * frame in each rx urb and avoid copies
35 val &= ~MT_USB_DMA_CFG_RX_BULK_AGG_EN;
36 mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val);
39 static void mt76x2u_power_on_rf_patch(struct mt76x02_dev *dev)
41 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) | BIT(16));
44 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1c), 0xff);
45 mt76_set(dev, MT_VEND_ADDR(CFG, 0x1c), 0x30);
47 mt76_wr(dev, MT_VEND_ADDR(CFG, 0x14), 0x484f);
50 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(17));
51 usleep_range(150, 200);
53 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(16));
54 usleep_range(50, 100);
56 mt76_set(dev, MT_VEND_ADDR(CFG, 0x14c), BIT(19) | BIT(20));
59 static void mt76x2u_power_on_rf(struct mt76x02_dev *dev, int unit)
61 int shift = unit ? 8 : 0;
62 u32 val = (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift;
65 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) << shift);
68 /* Enable RFDIG LDO/AFE/ABB/ADDA */
69 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), val);
72 /* Switch RFDIG power to internal LDO */
73 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(2) << shift);
76 mt76x2u_power_on_rf_patch(dev);
78 mt76_set(dev, 0x530, 0xf);
81 static void mt76x2u_power_on(struct mt76x02_dev *dev)
85 /* Turn on WL MTCMOS */
86 mt76_set(dev, MT_VEND_ADDR(CFG, 0x148),
87 MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
89 val = MT_WLAN_MTC_CTRL_STATE_UP |
90 MT_WLAN_MTC_CTRL_PWR_ACK |
91 MT_WLAN_MTC_CTRL_PWR_ACK_S;
93 mt76_poll(dev, MT_VEND_ADDR(CFG, 0x148), val, val, 1000);
95 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0x7f << 16);
98 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24);
101 mt76_set(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24);
102 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xfff);
104 /* Turn on AD/DA power down */
105 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1204), BIT(3));
107 /* WLAN function enable */
108 mt76_set(dev, MT_VEND_ADDR(CFG, 0x80), BIT(0));
110 /* Release BBP software reset */
111 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x64), BIT(18));
113 mt76x2u_power_on_rf(dev, 0);
114 mt76x2u_power_on_rf(dev, 1);
117 static int mt76x2u_init_eeprom(struct mt76x02_dev *dev)
121 dev->mt76.eeprom.data = devm_kzalloc(dev->mt76.dev,
124 dev->mt76.eeprom.size = MT7612U_EEPROM_SIZE;
125 if (!dev->mt76.eeprom.data)
128 for (i = 0; i + 4 <= MT7612U_EEPROM_SIZE; i += 4) {
129 val = mt76_rr(dev, MT_VEND_ADDR(EEPROM, i));
130 put_unaligned_le32(val, dev->mt76.eeprom.data + i);
133 mt76x02_eeprom_parse_hw_cap(dev);
137 struct mt76x02_dev *mt76x2u_alloc_device(struct device *pdev)
139 static const struct mt76_driver_ops drv_ops = {
140 .tx_prepare_skb = mt76x02u_tx_prepare_skb,
141 .tx_complete_skb = mt76x02u_tx_complete_skb,
142 .tx_status_data = mt76x02_tx_status_data,
143 .rx_skb = mt76x02_queue_rx_skb,
144 .sta_add = mt76x02_sta_add,
145 .sta_remove = mt76x02_sta_remove,
147 struct mt76x02_dev *dev;
148 struct mt76_dev *mdev;
150 mdev = mt76_alloc_device(sizeof(*dev), &mt76x2u_ops);
154 dev = container_of(mdev, struct mt76x02_dev, mt76);
156 mdev->drv = &drv_ops;
161 int mt76x2u_init_hardware(struct mt76x02_dev *dev)
165 mt76x2_reset_wlan(dev, true);
166 mt76x2u_power_on(dev);
168 if (!mt76x02_wait_for_mac(&dev->mt76))
171 err = mt76x2u_mcu_fw_init(dev);
175 if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG,
176 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
177 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100))
180 /* wait for asic ready after fw load. */
181 if (!mt76x02_wait_for_mac(&dev->mt76))
184 mt76x2u_init_dma(dev);
186 err = mt76x2u_mcu_init(dev);
190 err = mt76x2u_mac_reset(dev);
194 mt76x02_mac_setaddr(dev, dev->mt76.eeprom.data + MT_EE_MAC_ADDR);
195 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
197 if (!mt76x02_wait_for_txrx_idle(&dev->mt76))
200 /* reset wcid table */
201 for (i = 0; i < 256; i++)
202 mt76x02_mac_wcid_setup(dev, i, 0, NULL);
204 /* reset shared key table and pairwise key table */
205 for (i = 0; i < 16; i++) {
206 for (k = 0; k < 4; k++)
207 mt76x02_mac_shared_key_setup(dev, i, k, NULL);
210 mt76_clear(dev, MT_BEACON_TIME_CFG,
211 MT_BEACON_TIME_CFG_TIMER_EN |
212 MT_BEACON_TIME_CFG_SYNC_MODE |
213 MT_BEACON_TIME_CFG_TBTT_EN |
214 MT_BEACON_TIME_CFG_BEACON_TX);
216 mt76_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);
217 mt76_wr(dev, MT_TXOP_CTRL_CFG, 0x583f);
219 err = mt76x2_mcu_load_cr(dev, MT_RF_BBP_CR, 0, 0);
223 mt76x02_phy_set_rxpath(dev);
224 mt76x02_phy_set_txdac(dev);
226 return mt76x2u_mac_stop(dev);
229 int mt76x2u_register_device(struct mt76x02_dev *dev)
231 struct ieee80211_hw *hw = mt76_hw(dev);
234 INIT_DELAYED_WORK(&dev->cal_work, mt76x2u_phy_calibrate);
235 mt76x02_init_device(dev);
237 err = mt76x2u_init_eeprom(dev);
241 err = mt76u_alloc_queues(&dev->mt76);
245 err = mt76u_mcu_init_rx(&dev->mt76);
249 err = mt76x2u_init_hardware(dev);
253 err = mt76_register_device(&dev->mt76, true, mt76x02_rates,
254 ARRAY_SIZE(mt76x02_rates));
258 /* check hw sg support in order to enable AMSDU */
259 if (mt76u_check_sg(&dev->mt76))
260 hw->max_tx_fragments = MT_SG_MAX_SIZE;
262 hw->max_tx_fragments = 1;
264 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
266 mt76x02_init_debugfs(dev);
267 mt76x2_init_txpower(dev, &dev->mt76.sband_2g.sband);
268 mt76x2_init_txpower(dev, &dev->mt76.sband_5g.sband);
273 mt76x2u_cleanup(dev);
277 void mt76x2u_stop_hw(struct mt76x02_dev *dev)
279 mt76u_stop_stat_wk(&dev->mt76);
280 cancel_delayed_work_sync(&dev->cal_work);
281 cancel_delayed_work_sync(&dev->mac_work);
282 mt76x2u_mac_stop(dev);
285 void mt76x2u_cleanup(struct mt76x02_dev *dev)
287 mt76x02_mcu_set_radio_state(dev, false);
288 mt76x2u_stop_hw(dev);
289 mt76u_queues_deinit(&dev->mt76);
290 mt76u_mcu_deinit(&dev->mt76);