1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
4 #ifndef __MT76_CONNAC_MCU_H
5 #define __MT76_CONNAC_MCU_H
7 #include "mt76_connac.h"
31 struct sta_rec_basic {
38 u8 peer_addr[ETH_ALEN];
39 #define EXTRA_INFO_VER BIT(0)
40 #define EXTRA_INFO_NEW BIT(1)
55 __le16 vht_rx_mcs_map;
56 __le16 vht_tx_mcs_map;
62 struct sta_rec_uapsd {
69 __le16 listen_interval;
103 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
108 struct sta_rec_amsdu {
117 struct sta_rec_state {
127 #define RA_LEGACY_OFDM GENMASK(13, 6)
128 #define RA_LEGACY_CCK GENMASK(3, 0)
129 #define HT_MCS_MASK_NUM 10
130 struct sta_rec_ra_info {
134 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM];
148 struct sta_rec_he_6g_capa {
157 struct wtbl_req_hdr {
165 struct wtbl_generic {
168 u8 peer_addr[ETH_ALEN];
217 struct wtbl_hdr_trans {
233 /* originator only */
239 u8 peer_addr[ETH_ALEN];
292 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
293 sizeof(struct wtbl_generic) + \
294 sizeof(struct wtbl_rx) + \
295 sizeof(struct wtbl_ht) + \
296 sizeof(struct wtbl_vht) + \
297 sizeof(struct wtbl_tx_ps) + \
298 sizeof(struct wtbl_hdr_trans) +\
299 sizeof(struct wtbl_ba) + \
300 sizeof(struct wtbl_bf) + \
301 sizeof(struct wtbl_smps) + \
302 sizeof(struct wtbl_pn) + \
303 sizeof(struct wtbl_spe))
305 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
306 sizeof(struct sta_rec_basic) + \
307 sizeof(struct sta_rec_ht) + \
308 sizeof(struct sta_rec_he) + \
309 sizeof(struct sta_rec_ba) + \
310 sizeof(struct sta_rec_vht) + \
311 sizeof(struct sta_rec_uapsd) + \
312 sizeof(struct sta_rec_amsdu) + \
313 sizeof(struct sta_rec_he_6g_capa) + \
314 sizeof(struct tlv) + \
315 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE)
326 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
340 STA_REC_HE_6G = 0x17,
349 WTBL_PEER_PS, /* not used */
354 WTBL_RDG, /* obsoleted */
355 WTBL_PROTECT, /* not used */
356 WTBL_CLEAR, /* not used */
359 WTBL_RAW_DATA, /* debug only */
365 #define STA_TYPE_STA BIT(0)
366 #define STA_TYPE_AP BIT(1)
367 #define STA_TYPE_ADHOC BIT(2)
368 #define STA_TYPE_WDS BIT(4)
369 #define STA_TYPE_BC BIT(5)
371 #define NETWORK_INFRA BIT(16)
372 #define NETWORK_P2P BIT(17)
373 #define NETWORK_IBSS BIT(18)
374 #define NETWORK_WDS BIT(21)
376 #define SCAN_FUNC_RANDOM_MAC BIT(0)
377 #define SCAN_FUNC_SPLIT_SCAN BIT(5)
379 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
380 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
381 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
382 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
383 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
384 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
385 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
387 #define CONN_STATE_DISCONNECT 0
388 #define CONN_STATE_CONNECT 1
389 #define CONN_STATE_PORT_SECURE 2
392 #define STA_REC_HE_CAP_HTC BIT(0)
393 #define STA_REC_HE_CAP_BQR BIT(1)
394 #define STA_REC_HE_CAP_BSR BIT(2)
395 #define STA_REC_HE_CAP_OM BIT(3)
396 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
398 #define STA_REC_HE_CAP_DUAL_BAND BIT(5)
399 #define STA_REC_HE_CAP_LDPC BIT(6)
400 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
401 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
403 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
404 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
405 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
406 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
408 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
409 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
410 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
411 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
412 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
414 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
415 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
416 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)
418 #define PHY_MODE_A BIT(0)
419 #define PHY_MODE_B BIT(1)
420 #define PHY_MODE_G BIT(2)
421 #define PHY_MODE_GN BIT(3)
422 #define PHY_MODE_AN BIT(4)
423 #define PHY_MODE_AC BIT(5)
424 #define PHY_MODE_AX_24G BIT(6)
425 #define PHY_MODE_AX_5G BIT(7)
426 #define PHY_MODE_AX_6G BIT(8)
428 #define MODE_CCK BIT(0)
429 #define MODE_OFDM BIT(1)
430 #define MODE_HT BIT(2)
431 #define MODE_VHT BIT(3)
432 #define MODE_HE BIT(4)
435 PHY_TYPE_HR_DSSS_INDEX = 0,
437 PHY_TYPE_ERP_P2P_INDEX,
445 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX)
446 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX)
447 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX)
448 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX)
449 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX)
450 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX)
452 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6)
453 #define MT_WTBL_RATE_MCS GENMASK(5, 0)
454 #define MT_WTBL_RATE_NSS GENMASK(12, 10)
455 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4)
456 #define MT_WTBL_RATE_GI GENMASK(3, 0)
458 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)
459 #define MT_WTBL_W5_SHORT_GI_20 BIT(8)
460 #define MT_WTBL_W5_SHORT_GI_40 BIT(9)
461 #define MT_WTBL_W5_SHORT_GI_80 BIT(10)
462 #define MT_WTBL_W5_SHORT_GI_160 BIT(11)
463 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12)
464 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)
465 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)
466 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)
469 WTBL_RESET_AND_SET = 1,
477 MT_BA_TYPE_ORIGINATOR,
482 RST_BA_MAC_TID_MATCH,
492 #define MCU_CMD_ACK BIT(0)
493 #define MCU_CMD_UNI BIT(1)
494 #define MCU_CMD_QUERY BIT(2)
496 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \
499 #define MCU_FW_PREFIX BIT(31)
500 #define MCU_UNI_PREFIX BIT(30)
501 #define MCU_CE_PREFIX BIT(29)
502 #define MCU_QUERY_PREFIX BIT(28)
503 #define MCU_CMD_MASK ~(MCU_FW_PREFIX | MCU_UNI_PREFIX | \
504 MCU_CE_PREFIX | MCU_QUERY_PREFIX)
506 #define MCU_QUERY_MASK BIT(16)
509 MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
510 MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
511 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
512 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
513 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
514 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
515 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
516 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
517 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
518 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
519 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
520 MCU_EXT_CMD_GET_TEMP = 0x2c,
521 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
522 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
523 MCU_EXT_CMD_ATE_CTRL = 0x3d,
524 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
525 MCU_EXT_CMD_DBDC_CTRL = 0x45,
526 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
527 MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
528 MCU_EXT_CMD_MUAR_UPDATE = 0x48,
529 MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
530 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
531 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
532 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
533 MCU_EXT_CMD_TXDPD_CAL = 0x60,
534 MCU_EXT_CMD_SET_RDD_TH = 0x7c,
535 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
539 MCU_UNI_CMD_DEV_INFO_UPDATE = MCU_UNI_PREFIX | 0x01,
540 MCU_UNI_CMD_BSS_INFO_UPDATE = MCU_UNI_PREFIX | 0x02,
541 MCU_UNI_CMD_STA_REC_UPDATE = MCU_UNI_PREFIX | 0x03,
542 MCU_UNI_CMD_SUSPEND = MCU_UNI_PREFIX | 0x05,
543 MCU_UNI_CMD_OFFLOAD = MCU_UNI_PREFIX | 0x06,
544 MCU_UNI_CMD_HIF_CTRL = MCU_UNI_PREFIX | 0x07,
548 MCU_CMD_TARGET_ADDRESS_LEN_REQ = MCU_FW_PREFIX | 0x01,
549 MCU_CMD_FW_START_REQ = MCU_FW_PREFIX | 0x02,
550 MCU_CMD_INIT_ACCESS_REG = 0x3,
551 MCU_CMD_NIC_POWER_CTRL = MCU_FW_PREFIX | 0x4,
552 MCU_CMD_PATCH_START_REQ = MCU_FW_PREFIX | 0x05,
553 MCU_CMD_PATCH_FINISH_REQ = MCU_FW_PREFIX | 0x07,
554 MCU_CMD_PATCH_SEM_CONTROL = MCU_FW_PREFIX | 0x10,
555 MCU_CMD_EXT_CID = 0xed,
556 MCU_CMD_FW_SCATTER = MCU_FW_PREFIX | 0xee,
557 MCU_CMD_RESTART_DL_REQ = MCU_FW_PREFIX | 0xef,
560 /* offload mcu commands */
562 MCU_CMD_TEST_CTRL = MCU_CE_PREFIX | 0x01,
563 MCU_CMD_START_HW_SCAN = MCU_CE_PREFIX | 0x03,
564 MCU_CMD_SET_PS_PROFILE = MCU_CE_PREFIX | 0x05,
565 MCU_CMD_SET_CHAN_DOMAIN = MCU_CE_PREFIX | 0x0f,
566 MCU_CMD_SET_BSS_CONNECTED = MCU_CE_PREFIX | 0x16,
567 MCU_CMD_SET_BSS_ABORT = MCU_CE_PREFIX | 0x17,
568 MCU_CMD_CANCEL_HW_SCAN = MCU_CE_PREFIX | 0x1b,
569 MCU_CMD_SET_ROC = MCU_CE_PREFIX | 0x1d,
570 MCU_CMD_SET_P2P_OPPPS = MCU_CE_PREFIX | 0x33,
571 MCU_CMD_SET_RATE_TX_POWER = MCU_CE_PREFIX | 0x5d,
572 MCU_CMD_SCHED_SCAN_ENABLE = MCU_CE_PREFIX | 0x61,
573 MCU_CMD_SCHED_SCAN_REQ = MCU_CE_PREFIX | 0x62,
574 MCU_CMD_GET_NIC_CAPAB = MCU_CE_PREFIX | 0x8a,
575 MCU_CMD_SET_MU_EDCA_PARMS = MCU_CE_PREFIX | 0xb0,
576 MCU_CMD_REG_WRITE = MCU_CE_PREFIX | 0xc0,
577 MCU_CMD_REG_READ = MCU_CE_PREFIX | MCU_QUERY_MASK | 0xc0,
578 MCU_CMD_CHIP_CONFIG = MCU_CE_PREFIX | 0xca,
579 MCU_CMD_FWLOG_2_HOST = MCU_CE_PREFIX | 0xc5,
580 MCU_CMD_GET_WTBL = MCU_CE_PREFIX | 0xcd,
581 MCU_CMD_GET_TXPWR = MCU_CE_PREFIX | 0xd0,
590 UNI_BSS_INFO_BASIC = 0,
591 UNI_BSS_INFO_RLM = 2,
592 UNI_BSS_INFO_BSS_COLOR = 4,
593 UNI_BSS_INFO_HE_BASIC = 5,
594 UNI_BSS_INFO_BCN_CONTENT = 7,
595 UNI_BSS_INFO_QBSS = 15,
596 UNI_BSS_INFO_UAPSD = 19,
597 UNI_BSS_INFO_PS = 21,
598 UNI_BSS_INFO_BCNFT = 22,
602 UNI_OFFLOAD_OFFLOAD_ARP,
603 UNI_OFFLOAD_OFFLOAD_ND,
604 UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
605 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
609 MT_NIC_CAP_TX_RESOURCE,
610 MT_NIC_CAP_TX_EFUSE_ADDR,
612 MT_NIC_CAP_SINGLE_SKU,
613 MT_NIC_CAP_CSUM_OFFLOAD,
619 MT_NIC_CAP_FRAME_BUF,
620 MT_NIC_CAP_BEAM_FORM,
623 MT_NIC_CAP_BUFFER_MODE_INFO,
624 MT_NIC_CAP_HW_ADIE_VERSION = 0x14,
625 MT_NIC_CAP_ANTSWP = 0x16,
626 MT_NIC_CAP_WFDMA_REALLOC,
630 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0)
631 #define UNI_WOW_DETECT_TYPE_ANY BIT(1)
632 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2)
633 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3)
634 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4)
635 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5)
636 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6)
639 UNI_SUSPEND_MODE_SETTING,
640 UNI_SUSPEND_WOW_CTRL,
641 UNI_SUSPEND_WOW_GPIO_PARAM,
642 UNI_SUSPEND_WOW_WAKEUP_PORT,
643 UNI_SUSPEND_WOW_PATTERN,
652 struct mt76_connac_bss_basic_tlv {
663 __le16 bmc_tx_wlan_idx;
666 u8 phymode; /* bit(0): A
677 __le16 nonht_basic_phy;
678 u8 phymode_ext; /* bit(0) AX_6G */
682 struct mt76_connac_bss_qos_tlv {
689 struct mt76_connac_beacon_loss_event {
695 struct mt76_connac_mcu_bss_event {
702 struct mt76_connac_mcu_scan_ssid {
704 u8 ssid[IEEE80211_MAX_SSID_LEN];
707 struct mt76_connac_mcu_scan_channel {
708 u8 band; /* 1: 2.4GHz
715 struct mt76_connac_mcu_scan_match {
717 u8 ssid[IEEE80211_MAX_SSID_LEN];
722 struct mt76_connac_hw_scan_req {
725 u8 scan_type; /* 0: PASSIVE SCAN
728 u8 ssid_type; /* BIT(0) wildcard SSID
729 * BIT(1) P2P wildcard SSID
730 * BIT(2) specified SSID + wildcard SSID
731 * BIT(2) + ssid_type_ext BIT(0) specified SSID only
734 u8 probe_req_num; /* Number of probe request for each SSID */
735 u8 scan_func; /* BIT(0) Enable random MAC scan
736 * BIT(1) Disable DBDC scan type 1~3.
737 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan).
739 u8 version; /* 0: Not support fields after ies.
740 * 1: Support fields after ies.
742 struct mt76_connac_mcu_scan_ssid ssids[4];
743 __le16 probe_delay_time;
744 __le16 channel_dwell_time; /* channel Dwell interval */
745 __le16 timeout_value;
746 u8 channel_type; /* 0: Full channels
747 * 1: Only 2.4GHz channels
748 * 2: Only 5GHz channels
749 * 3: P2P social channel only (channel #1, #6 and #11)
750 * 4: Specified channels
753 u8 channels_num; /* valid when channel_type is 4 */
754 /* valid when channels_num is set */
755 struct mt76_connac_mcu_scan_channel channels[32];
757 u8 ies[MT76_CONNAC_SCAN_IE_LEN];
758 /* following fields are valid if version > 0 */
761 __le16 channel_min_dwell_time;
762 struct mt76_connac_mcu_scan_channel ext_channels[32];
763 struct mt76_connac_mcu_scan_ssid ext_ssids[6];
765 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */
770 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64
772 struct mt76_connac_hw_scan_done {
774 u8 sparse_channel_num;
775 struct mt76_connac_mcu_scan_channel sparse_channel;
776 u8 complete_channel_num;
780 __le32 beacon_scan_num;
783 u8 sparse_channel_valid_num;
785 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
786 /* idle format for channel_idle_time
787 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms)
788 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms)
789 * 2: dwell time (16us)
791 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
792 /* beacon and probe response count */
793 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
794 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
795 __le32 beacon_2g_num;
796 __le32 beacon_5g_num;
799 struct mt76_connac_sched_scan_req {
807 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID];
808 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH];
812 u8 scan_func; /* MT7663: BIT(0) eable random mac address */
813 struct mt76_connac_mcu_scan_channel channels[64];
814 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL];
817 u8 random_mac[ETH_ALEN];
825 u8 random_mac[ETH_ALEN];
831 struct mt76_connac_sched_scan_done {
833 u8 status; /* 0: ssid found */
837 struct bss_info_uni_bss_color {
845 struct bss_info_uni_he {
851 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
855 struct mt76_connac_gtk_rekey_tlv {
858 u8 kek[NL80211_KEK_LEN];
859 u8 kck[NL80211_KCK_LEN];
860 u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
861 u8 rekey_mode; /* 0: rekey offload enable
862 * 1: rekey offload disable
866 u8 option; /* 1: rekey data update without enabling offload */
868 __le32 proto; /* WPA-RSN-WAPI-OPSN */
869 __le32 pairwise_cipher;
871 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */
872 __le32 mgmt_group_cipher;
876 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16
877 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128
879 struct mt76_connac_wow_pattern_tlv {
882 u8 index; /* pattern index */
883 u8 enable; /* 0: disable
886 u8 data_len; /* pattern length */
888 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN];
889 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN];
893 struct mt76_connac_wow_ctrl_tlv {
896 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START
897 * 0x2: PM_WOWLAN_REQ_STOP
898 * 0x3: PM_WOWLAN_PARAM_CLEAR
900 u8 trigger; /* 0: NONE
901 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT
902 * BIT(1): NL80211_WOWLAN_TRIG_ANY
903 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT
904 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE
905 * BIT(4): BEACON_LOST
906 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT
908 u8 wakeup_hif; /* 0x0: HIF_SDIO
917 struct mt76_connac_wow_gpio_param_tlv {
923 __le32 gpio_interval;
927 struct mt76_connac_arpns_tlv {
936 struct mt76_connac_suspend_tlv {
939 u8 enable; /* 0: suspend mode disabled
940 * 1: suspend mode enabled
942 u8 mdtim; /* LP parameter */
943 u8 wow_suspend; /* 0: update by origin policy
944 * 1: update by wow dtim
949 enum mt76_sta_info_state {
950 MT76_STA_INFO_STATE_NONE,
951 MT76_STA_INFO_STATE_AUTH,
952 MT76_STA_INFO_STATE_ASSOC
955 struct mt76_sta_cmd_info {
956 struct ieee80211_sta *sta;
957 struct mt76_wcid *wcid;
959 struct ieee80211_vif *vif;
969 #define MT_SKU_POWER_LIMIT 161
971 struct mt76_connac_sku_tlv {
973 s8 pwr_limit[MT_SKU_POWER_LIMIT];
976 struct mt76_connac_tx_power_limit_tlv {
977 /* DW0 - common info*/
982 u8 n_chan; /* # channel */
983 u8 band; /* 2.4GHz - 5GHz - 6GHz */
987 u8 alpha2[4]; /* regulatory_request.alpha2 */
991 struct mt76_connac_config {
1000 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
1001 #define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id)
1004 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid,
1005 u8 *wlan_idx_lo, u8 *wlan_idx_hi)
1009 if (is_mt7921(dev)) {
1010 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0;
1011 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0;
1013 *wlan_idx_lo = wcid ? wcid->idx : 0;
1018 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1019 struct mt76_wcid *wcid);
1020 struct wtbl_req_hdr *
1021 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid,
1022 int cmd, void *sta_wtbl, struct sk_buff **skb);
1023 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag,
1024 int len, void *sta_ntlv,
1026 static inline struct tlv *
1027 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
1029 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
1032 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy);
1033 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif);
1034 void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb,
1035 struct ieee80211_vif *vif,
1036 struct ieee80211_sta *sta, bool enable,
1038 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1039 struct ieee80211_vif *vif,
1040 struct ieee80211_sta *sta, void *sta_wtbl,
1042 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb,
1043 struct ieee80211_vif *vif,
1044 struct mt76_wcid *wcid,
1045 void *sta_wtbl, void *wtbl_tlv);
1046 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev,
1047 struct ieee80211_vif *vif,
1048 struct mt76_wcid *wcid, int cmd);
1049 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb,
1050 struct ieee80211_sta *sta,
1051 struct ieee80211_vif *vif,
1053 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1054 struct ieee80211_sta *sta, void *sta_wtbl,
1056 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1057 struct ieee80211_ampdu_params *params,
1058 bool enable, bool tx, void *sta_wtbl,
1060 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb,
1061 struct ieee80211_ampdu_params *params,
1062 bool enable, bool tx);
1063 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy,
1064 struct ieee80211_vif *vif,
1065 struct mt76_wcid *wcid,
1067 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
1068 struct ieee80211_ampdu_params *params,
1069 bool enable, bool tx);
1070 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy,
1071 struct ieee80211_vif *vif,
1072 struct mt76_wcid *wcid,
1074 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy,
1075 struct mt76_sta_cmd_info *info);
1076 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac,
1077 struct ieee80211_vif *vif);
1078 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band);
1079 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable,
1081 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len,
1083 int mt76_connac_mcu_start_patch(struct mt76_dev *dev);
1084 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
1085 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option);
1086 int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy);
1088 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
1089 struct ieee80211_scan_request *scan_req);
1090 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy,
1091 struct ieee80211_vif *vif);
1092 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy,
1093 struct ieee80211_vif *vif,
1094 struct cfg80211_sched_scan_request *sreq);
1095 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy,
1096 struct ieee80211_vif *vif,
1098 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev,
1099 struct mt76_vif *vif,
1100 struct ieee80211_bss_conf *info);
1101 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
1102 struct ieee80211_vif *vif,
1103 struct cfg80211_gtk_rekey_data *key);
1104 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend);
1105 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac,
1106 struct ieee80211_vif *vif);
1107 int mt76_connac_sta_state_dp(struct mt76_dev *dev,
1108 enum ieee80211_sta_state old_state,
1109 enum ieee80211_sta_state new_state);
1110 int mt76_connac_mcu_chip_config(struct mt76_dev *dev);
1111 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable);
1112 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb,
1113 struct mt76_connac_coredump *coredump);
1114 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy);
1115 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw,
1116 struct ieee80211_vif *vif);
1117 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset);
1118 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val);
1119 #endif /* __MT76_CONNAC_MCU_H */