1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2019 MediaTek Inc. */
4 #ifndef __MT7615_REGS_H
5 #define __MT7615_REGS_H
7 #define MT_HW_REV 0x1000
8 #define MT_HW_CHIPID 0x1008
9 #define MT_TOP_STRAP_STA 0x1010
10 #define MT_TOP_3NSS BIT(24)
12 #define MT_TOP_OFF_RSV 0x1128
13 #define MT_TOP_OFF_RSV_FW_STATE GENMASK(18, 16)
15 #define MT_TOP_MISC2 0x1134
16 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
18 #define MT_MCU_BASE 0x2000
19 #define MT_MCU(ofs) (MT_MCU_BASE + (ofs))
21 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
22 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
23 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
24 #define MT_PCIE_REMAP_BASE_1 0x40000
26 #define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504)
27 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
28 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
29 #define MT_PCIE_REMAP_BASE_2 0x80000
31 #define MT_HIF_BASE 0x4000
32 #define MT_HIF(ofs) (MT_HIF_BASE + (ofs))
34 #define MT_CFG_LPCR_HOST MT_HIF(0x1f0)
35 #define MT_CFG_LPCR_HOST_FW_OWN BIT(0)
36 #define MT_CFG_LPCR_HOST_DRV_OWN BIT(1)
38 #define MT_INT_SOURCE_CSR MT_HIF(0x200)
39 #define MT_INT_MASK_CSR MT_HIF(0x204)
40 #define MT_DELAY_INT_CFG MT_HIF(0x210)
42 #define MT_INT_RX_DONE(_n) BIT(_n)
43 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
44 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
45 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
47 #define MT_WPDMA_GLO_CFG MT_HIF(0x208)
48 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
49 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
50 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
51 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
52 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
53 #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6)
54 #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
55 #define MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0 BIT(9)
56 #define MT_WPDMA_GLO_CFG_BYPASS_TX_SCH BIT(9) /* MT7622 */
57 #define MT_WPDMA_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10)
58 #define MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
59 #define MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21 GENMASK(23, 22)
60 #define MT_WPDMA_GLO_CFG_SW_RESET BIT(24)
61 #define MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)
62 #define MT_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28)
64 #define MT_WPDMA_RST_IDX MT_HIF(0x20c)
66 #define MT_TX_RING_BASE MT_HIF(0x300)
67 #define MT_RX_RING_BASE MT_HIF(0x400)
69 #define MT_WPDMA_GLO_CFG1 MT_HIF(0x500)
70 #define MT_WPDMA_TX_PRE_CFG MT_HIF(0x510)
71 #define MT_WPDMA_RX_PRE_CFG MT_HIF(0x520)
72 #define MT_WPDMA_ABT_CFG MT_HIF(0x530)
73 #define MT_WPDMA_ABT_CFG1 MT_HIF(0x534)
75 #define MT_PLE_BASE 0x8000
76 #define MT_PLE(ofs) (MT_PLE_BASE + (ofs))
78 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0)
79 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4)
80 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8)
81 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc)
83 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \
86 #define MT_WF_PHY_BASE 0x10000
87 #define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs))
89 #define MT_WF_PHY_WF2_RFCTRL0(n) MT_WF_PHY(0x1900 + (n) * 0x400)
90 #define MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN BIT(9)
92 #define MT_WF_PHY_R0_PHYMUX_5(_phy) MT_WF_PHY(0x0614 + ((_phy) << 9))
94 #define MT_WF_PHY_R0_PHYCTRL_STS0(_phy) MT_WF_PHY(0x020c + ((_phy) << 9))
95 #define MT_WF_PHYCTRL_STAT_PD_OFDM GENMASK(31, 16)
96 #define MT_WF_PHYCTRL_STAT_PD_CCK GENMASK(15, 0)
98 #define MT_WF_PHY_R0_PHYCTRL_STS5(_phy) MT_WF_PHY(0x0220 + ((_phy) << 9))
99 #define MT_WF_PHYCTRL_STAT_MDRDY_OFDM GENMASK(31, 16)
100 #define MT_WF_PHYCTRL_STAT_MDRDY_CCK GENMASK(15, 0)
102 #define MT_WF_PHY_MIN_PRI_PWR(_phy) MT_WF_PHY((_phy) ? 0x084 : 0x229c)
103 #define MT_WF_PHY_PD_OFDM_MASK(_phy) ((_phy) ? GENMASK(24, 16) : \
105 #define MT_WF_PHY_PD_OFDM(_phy, v) ((v) << ((_phy) ? 16 : 20))
106 #define MT_WF_PHY_PD_BLK(_phy) ((_phy) ? BIT(25) : BIT(19))
108 #define MT_WF_PHY_RXTD_BASE MT_WF_PHY(0x2200)
109 #define MT_WF_PHY_RXTD(_n) (MT_WF_PHY_RXTD_BASE + ((_n) << 2))
111 #define MT_WF_PHY_RXTD_CCK_PD(_phy) MT_WF_PHY((_phy) ? 0x2314 : 0x2310)
112 #define MT_WF_PHY_PD_CCK_MASK(_phy) (_phy) ? GENMASK(31, 24) : \
114 #define MT_WF_PHY_PD_CCK(_phy, v) ((v) << ((_phy) ? 24 : 1))
116 #define MT_WF_PHY_RXTD2_BASE MT_WF_PHY(0x2a00)
117 #define MT_WF_PHY_RXTD2(_n) (MT_WF_PHY_RXTD2_BASE + ((_n) << 2))
119 #define MT_WF_CFG_BASE 0x20200
120 #define MT_WF_CFG(ofs) (MT_WF_CFG_BASE + (ofs))
122 #define MT_CFG_CCR MT_WF_CFG(0x000)
123 #define MT_CFG_CCR_MAC_D1_1X_GC_EN BIT(24)
124 #define MT_CFG_CCR_MAC_D0_1X_GC_EN BIT(25)
125 #define MT_CFG_CCR_MAC_D1_2X_GC_EN BIT(30)
126 #define MT_CFG_CCR_MAC_D0_2X_GC_EN BIT(31)
128 #define MT_WF_AGG_BASE 0x20a00
129 #define MT_WF_AGG(ofs) (MT_WF_AGG_BASE + (ofs))
131 #define MT_AGG_ARCR MT_WF_AGG(0x010)
132 #define MT_AGG_ARCR_INIT_RATE1 BIT(0)
133 #define MT_AGG_ARCR_RTS_RATE_THR GENMASK(12, 8)
134 #define MT_AGG_ARCR_RATE_DOWN_RATIO GENMASK(17, 16)
135 #define MT_AGG_ARCR_RATE_DOWN_RATIO_EN BIT(19)
136 #define MT_AGG_ARCR_RATE_UP_EXTRA_TH GENMASK(22, 20)
138 #define MT_AGG_ARUCR(_band) MT_WF_AGG(0x018 + (_band) * 0x100)
139 #define MT_AGG_ARDCR(_band) MT_WF_AGG(0x01c + (_band) * 0x100)
140 #define MT_AGG_ARxCR_LIMIT_SHIFT(_n) (4 * (_n))
141 #define MT_AGG_ARxCR_LIMIT(_n) GENMASK(2 + \
142 MT_AGG_ARxCR_LIMIT_SHIFT(_n), \
143 MT_AGG_ARxCR_LIMIT_SHIFT(_n))
145 #define MT_AGG_ASRCR0 MT_WF_AGG(0x060)
146 #define MT_AGG_ASRCR1 MT_WF_AGG(0x064)
147 #define MT_AGG_ASRCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(5, 0))
149 #define MT_AGG_ACR(_band) MT_WF_AGG(0x070 + (_band) * 0x100)
150 #define MT_AGG_ACR_NO_BA_RULE BIT(0)
151 #define MT_AGG_ACR_NO_BA_AR_RULE BIT(1)
152 #define MT_AGG_ACR_PKT_TIME_EN BIT(2)
153 #define MT_AGG_ACR_CFEND_RATE GENMASK(15, 4)
154 #define MT_AGG_ACR_BAR_RATE GENMASK(31, 20)
156 #define MT_AGG_SCR MT_WF_AGG(0x0fc)
157 #define MT_AGG_SCR_NLNAV_MID_PTEC_DIS BIT(3)
159 #define MT_WF_ARB_BASE 0x20c00
160 #define MT_WF_ARB(ofs) (MT_WF_ARB_BASE + (ofs))
162 #define MT_ARB_SCR MT_WF_ARB(0x080)
163 #define MT_ARB_SCR_TX0_DISABLE BIT(8)
164 #define MT_ARB_SCR_RX0_DISABLE BIT(9)
165 #define MT_ARB_SCR_TX1_DISABLE BIT(10)
166 #define MT_ARB_SCR_RX1_DISABLE BIT(11)
168 #define MT_WF_TMAC_BASE 0x21000
169 #define MT_WF_TMAC(ofs) (MT_WF_TMAC_BASE + (ofs))
171 #define MT_TMAC_CDTR MT_WF_TMAC(0x090)
172 #define MT_TMAC_ODTR MT_WF_TMAC(0x094)
173 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
174 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
176 #define MT_TMAC_TRCR(_band) MT_WF_TMAC((_band) ? 0x070 : 0x09c)
177 #define MT_TMAC_TRCR_CCA_SEL GENMASK(31, 30)
178 #define MT_TMAC_TRCR_SEC_CCA_SEL GENMASK(29, 28)
180 #define MT_TMAC_ICR(_band) MT_WF_TMAC((_band) ? 0x074 : 0x0a4)
181 #define MT_IFS_EIFS GENMASK(8, 0)
182 #define MT_IFS_RIFS GENMASK(14, 10)
183 #define MT_IFS_SIFS GENMASK(22, 16)
184 #define MT_IFS_SLOT GENMASK(30, 24)
186 #define MT_TMAC_CTCR0 MT_WF_TMAC(0x0f4)
187 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
188 #define MT_TMAC_CTCR0_INS_DDLMT_DENSITY GENMASK(15, 12)
189 #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
190 #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18)
192 #define MT_WF_RMAC_BASE 0x21200
193 #define MT_WF_RMAC(ofs) (MT_WF_RMAC_BASE + (ofs))
195 #define MT_WF_RFCR(_band) MT_WF_RMAC((_band) ? 0x100 : 0x000)
196 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
197 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1)
198 #define MT_WF_RFCR_DROP_VERSION BIT(3)
199 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
200 #define MT_WF_RFCR_DROP_MCAST BIT(5)
201 #define MT_WF_RFCR_DROP_BCAST BIT(6)
202 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)
203 #define MT_WF_RFCR_DROP_A3_MAC BIT(8)
204 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9)
205 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10)
206 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)
207 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)
208 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13)
209 #define MT_WF_RFCR_DROP_CTS BIT(14)
210 #define MT_WF_RFCR_DROP_RTS BIT(15)
211 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16)
212 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)
213 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18)
214 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)
215 #define MT_WF_RFCR_DROP_NDPA BIT(20)
216 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
218 #define MT_WF_RFCR1(_band) MT_WF_RMAC((_band) ? 0x104 : 0x004)
219 #define MT_WF_RFCR1_DROP_ACK BIT(4)
220 #define MT_WF_RFCR1_DROP_BF_POLL BIT(5)
221 #define MT_WF_RFCR1_DROP_BA BIT(6)
222 #define MT_WF_RFCR1_DROP_CFEND BIT(7)
223 #define MT_WF_RFCR1_DROP_CFACK BIT(8)
225 #define MT_CHFREQ(_band) MT_WF_RMAC((_band) ? 0x130 : 0x030)
227 #define MT_WF_RMAC_MIB_TIME0 MT_WF_RMAC(0x03c4)
228 #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31)
229 #define MT_WF_RMAC_MIB_RXTIME_EN BIT(30)
231 #define MT_WF_RMAC_MIB_AIRTIME0 MT_WF_RMAC(0x0380)
233 #define MT_WF_RMAC_MIB_TIME5 MT_WF_RMAC(0x03d8)
234 #define MT_WF_RMAC_MIB_TIME6 MT_WF_RMAC(0x03dc)
235 #define MT_MIB_OBSSTIME_MASK GENMASK(23, 0)
237 #define MT_WF_DMA_BASE 0x21800
238 #define MT_WF_DMA(ofs) (MT_WF_DMA_BASE + (ofs))
240 #define MT_DMA_DCR0 MT_WF_DMA(0x000)
241 #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 2)
242 #define MT_DMA_DCR0_RX_VEC_DROP BIT(17)
244 #define MT_DMA_RCFR0(_band) MT_WF_DMA(0x070 + (_band) * 0x40)
245 #define MT_DMA_RCFR0_MCU_RX_MGMT BIT(2)
246 #define MT_DMA_RCFR0_MCU_RX_CTL_NON_BAR BIT(3)
247 #define MT_DMA_RCFR0_MCU_RX_CTL_BAR BIT(4)
248 #define MT_DMA_RCFR0_MCU_RX_BYPASS BIT(21)
249 #define MT_DMA_RCFR0_RX_DROPPED_UCAST GENMASK(25, 24)
250 #define MT_DMA_RCFR0_RX_DROPPED_MCAST GENMASK(27, 26)
252 #define MT_WTBL_BASE 0x30000
253 #define MT_WTBL_ENTRY_SIZE 256
255 #define MT_WTBL_OFF_BASE 0x23400
256 #define MT_WTBL_OFF(n) (MT_WTBL_OFF_BASE + (n))
258 #define MT_WTBL_W0_KEY_IDX GENMASK(24, 23)
259 #define MT_WTBL_W0_RX_KEY_VALID BIT(26)
260 #define MT_WTBL_W0_RX_IK_VALID BIT(27)
262 #define MT_WTBL_W2_KEY_TYPE GENMASK(7, 4)
264 #define MT_WTBL_UPDATE MT_WTBL_OFF(0x030)
265 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(7, 0)
266 #define MT_WTBL_UPDATE_RXINFO_UPDATE BIT(11)
267 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
268 #define MT_WTBL_UPDATE_RATE_UPDATE BIT(13)
269 #define MT_WTBL_UPDATE_TX_COUNT_CLEAR BIT(14)
270 #define MT_WTBL_UPDATE_BUSY BIT(31)
272 #define MT_WTBL_ON_BASE 0x23000
273 #define MT_WTBL_ON(_n) (MT_WTBL_ON_BASE + (_n))
275 #define MT_WTBL_RICR0 MT_WTBL_ON(0x010)
276 #define MT_WTBL_RICR1 MT_WTBL_ON(0x014)
278 #define MT_WTBL_RIUCR0 MT_WTBL_ON(0x020)
280 #define MT_WTBL_RIUCR1 MT_WTBL_ON(0x024)
281 #define MT_WTBL_RIUCR1_RATE0 GENMASK(11, 0)
282 #define MT_WTBL_RIUCR1_RATE1 GENMASK(23, 12)
283 #define MT_WTBL_RIUCR1_RATE2_LO GENMASK(31, 24)
285 #define MT_WTBL_RIUCR2 MT_WTBL_ON(0x028)
286 #define MT_WTBL_RIUCR2_RATE2_HI GENMASK(3, 0)
287 #define MT_WTBL_RIUCR2_RATE3 GENMASK(15, 4)
288 #define MT_WTBL_RIUCR2_RATE4 GENMASK(27, 16)
289 #define MT_WTBL_RIUCR2_RATE5_LO GENMASK(31, 28)
291 #define MT_WTBL_RIUCR3 MT_WTBL_ON(0x02c)
292 #define MT_WTBL_RIUCR3_RATE5_HI GENMASK(7, 0)
293 #define MT_WTBL_RIUCR3_RATE6 GENMASK(19, 8)
294 #define MT_WTBL_RIUCR3_RATE7 GENMASK(31, 20)
296 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)
297 #define MT_WTBL_W5_SHORT_GI_20 BIT(8)
298 #define MT_WTBL_W5_SHORT_GI_40 BIT(9)
299 #define MT_WTBL_W5_SHORT_GI_80 BIT(10)
300 #define MT_WTBL_W5_SHORT_GI_160 BIT(11)
301 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12)
302 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)
303 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)
304 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)
306 #define MT_WTBL_W27_CC_BW_SEL GENMASK(6, 5)
308 #define MT_LPON_BASE 0x24200
309 #define MT_LPON(_n) (MT_LPON_BASE + (_n))
311 #define MT_LPON_T0CR MT_LPON(0x010)
312 #define MT_LPON_T0CR_MODE GENMASK(1, 0)
314 #define MT_LPON_UTTR0 MT_LPON(0x018)
315 #define MT_LPON_UTTR1 MT_LPON(0x01c)
317 #define MT_WF_MIB_BASE 0x24800
318 #define MT_WF_MIB(ofs) (MT_WF_MIB_BASE + (ofs))
320 #define MT_MIB_M0_MISC_CR MT_WF_MIB(0x00c)
322 #define MT_MIB_SDR3(n) MT_WF_MIB(0x014 + ((n) << 9))
323 #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)
325 #define MT_MIB_SDR9(n) MT_WF_MIB(0x02c + ((n) << 9))
326 #define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0)
328 #define MT_MIB_SDR16(n) MT_WF_MIB(0x048 + ((n) << 9))
329 #define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0)
331 #define MT_MIB_SDR36(n) MT_WF_MIB(0x098 + ((n) << 9))
332 #define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0)
333 #define MT_MIB_SDR37(n) MT_WF_MIB(0x09c + ((n) << 9))
334 #define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0)
336 #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(0x100 + ((_band) << 9) + \
338 #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
339 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
341 #define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(0x104 + ((_band) << 9) + \
343 #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)
345 #define MT_TX_AGG_CNT(n) MT_WF_MIB(0xa8 + ((n) << 2))
347 #define MT_DMASHDL_BASE 0x5000a000
348 #define MT_DMASHDL_OPTIONAL 0x008
349 #define MT_DMASHDL_PAGE 0x00c
351 #define MT_DMASHDL_REFILL 0x010
353 #define MT_DMASHDL_PKT_MAX_SIZE 0x01c
354 #define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0)
355 #define MT_DMASHDL_PKT_MAX_SIZE_PSE GENMASK(27, 16)
357 #define MT_DMASHDL_GROUP_QUOTA(_n) (0x020 + ((_n) << 2))
358 #define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0)
359 #define MT_DMASHDL_GROUP_QUOTA_MAX GENMASK(27, 16)
361 #define MT_DMASHDL_SCHED_SET0 0x0b0
362 #define MT_DMASHDL_SCHED_SET1 0x0b4
364 #define MT_DMASHDL_Q_MAP(_n) (0x0d0 + ((_n) << 2))
365 #define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0)
366 #define MT_DMASHDL_Q_MAP_SHIFT(_n) (4 * ((_n) % 8))
368 #define MT_LED_BASE_PHYS 0x80024000
369 #define MT_LED_PHYS(_n) (MT_LED_BASE_PHYS + (_n))
371 #define MT_LED_CTRL MT_LED_PHYS(0x00)
373 #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n)))
374 #define MT_LED_CTRL_POLARITY(_n) BIT(1 + (8 * (_n)))
375 #define MT_LED_CTRL_TX_BLINK_MODE(_n) BIT(2 + (8 * (_n)))
376 #define MT_LED_CTRL_TX_MANUAL_BLINK(_n) BIT(3 + (8 * (_n)))
377 #define MT_LED_CTRL_TX_OVER_BLINK(_n) BIT(5 + (8 * (_n)))
378 #define MT_LED_CTRL_KICK(_n) BIT(7 + (8 * (_n)))
380 #define MT_LED_STATUS_0(_n) MT_LED_PHYS(0x10 + ((_n) * 8))
381 #define MT_LED_STATUS_1(_n) MT_LED_PHYS(0x14 + ((_n) * 8))
382 #define MT_LED_STATUS_OFF GENMASK(31, 24)
383 #define MT_LED_STATUS_ON GENMASK(23, 16)
384 #define MT_LED_STATUS_DURATION GENMASK(15, 0)
386 #define MT_EFUSE_BASE 0x81070000
387 #define MT_EFUSE_BASE_CTRL 0x000
388 #define MT_EFUSE_BASE_CTRL_EMPTY BIT(30)
390 #define MT_EFUSE_CTRL 0x008
391 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
392 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
393 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
394 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
395 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
396 #define MT_EFUSE_CTRL_VALID BIT(29)
397 #define MT_EFUSE_CTRL_KICK BIT(30)
398 #define MT_EFUSE_CTRL_SEL BIT(31)
400 #define MT_EFUSE_WDATA(_i) (0x010 + ((_i) * 4))
401 #define MT_EFUSE_RDATA(_i) (0x030 + ((_i) * 4))
403 /* INFRACFG host register range on MT7622 */
404 #define MT_INFRACFG_MISC 0x700
405 #define MT_INFRACFG_MISC_AP2CONN_WAKE BIT(1)