1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2019 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Felix Fietkau <nbd@nbd.name>
7 * Lorenzo Bianconi <lorenzo@kernel.org>
10 #include <linux/etherdevice.h>
11 #include <linux/timekeeping.h>
15 #include "mt7615_trace.h"
18 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
20 static const struct mt7615_dfs_radar_spec etsi_radar_specs = {
21 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
23 [5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 },
24 [6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 },
25 [7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 },
26 [8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 },
27 [9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 },
28 [10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 },
29 [11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 },
30 [12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 },
34 static const struct mt7615_dfs_radar_spec fcc_radar_specs = {
35 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
37 [0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 },
38 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
39 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
40 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
41 [4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 },
45 static const struct mt7615_dfs_radar_spec jp_radar_specs = {
46 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
48 [0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 },
49 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
50 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
51 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
52 [4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 },
53 [13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 },
54 [14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 },
58 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
61 struct mt7615_sta *sta;
62 struct mt76_wcid *wcid;
64 if (idx >= ARRAY_SIZE(dev->mt76.wcid))
67 wcid = rcu_dereference(dev->mt76.wcid[idx]);
74 sta = container_of(wcid, struct mt7615_sta, wcid);
78 return &sta->vif->sta.wcid;
81 void mt7615_mac_reset_counters(struct mt7615_dev *dev)
85 for (i = 0; i < 4; i++) {
86 mt76_rr(dev, MT_TX_AGG_CNT(0, i));
87 mt76_rr(dev, MT_TX_AGG_CNT(1, i));
90 memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats));
91 dev->mt76.phy.survey_time = ktime_get_boottime();
93 dev->mt76.phy2->survey_time = ktime_get_boottime();
95 /* reset airtime counters */
96 mt76_rr(dev, MT_MIB_SDR9(0));
97 mt76_rr(dev, MT_MIB_SDR9(1));
99 mt76_rr(dev, MT_MIB_SDR36(0));
100 mt76_rr(dev, MT_MIB_SDR36(1));
102 mt76_rr(dev, MT_MIB_SDR37(0));
103 mt76_rr(dev, MT_MIB_SDR37(1));
105 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
106 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
109 void mt7615_mac_set_timing(struct mt7615_phy *phy)
111 s16 coverage_class = phy->coverage_class;
112 struct mt7615_dev *dev = phy->dev;
113 bool ext_phy = phy != &dev->phy;
115 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
116 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
117 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
118 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
120 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
122 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
131 coverage_class = max_t(s16, dev->phy.coverage_class,
133 mt76_set(dev, MT_ARB_SCR,
134 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
136 struct mt7615_phy *phy_ext = mt7615_ext_phy(dev);
139 coverage_class = max_t(s16, phy_ext->coverage_class,
141 mt76_set(dev, MT_ARB_SCR,
142 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
146 offset = 3 * coverage_class;
147 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
148 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
149 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset);
150 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset);
152 mt76_wr(dev, MT_TMAC_ICR(ext_phy),
153 FIELD_PREP(MT_IFS_EIFS, 360) |
154 FIELD_PREP(MT_IFS_RIFS, 2) |
155 FIELD_PREP(MT_IFS_SIFS, sifs) |
156 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
158 if (phy->slottime < 20 || is_5ghz)
159 val = MT7615_CFEND_RATE_DEFAULT;
161 val = MT7615_CFEND_RATE_11B;
163 mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
165 mt76_clear(dev, MT_ARB_SCR,
166 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
168 mt76_clear(dev, MT_ARB_SCR,
169 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
174 mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy,
175 struct mt76_rx_status *status, u8 chfreq)
177 if (!test_bit(MT76_HW_SCANNING, &mphy->state) &&
178 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state)) {
179 status->freq = mphy->chandef.chan->center_freq;
180 status->band = mphy->chandef.chan->band;
184 status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
185 status->freq = ieee80211_channel_to_frequency(chfreq, status->band);
188 static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
190 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
191 struct mt76_phy *mphy = &dev->mt76.phy;
192 struct mt7615_phy *phy = &dev->phy;
193 struct mt7615_phy *phy2 = dev->mt76.phy2 ? dev->mt76.phy2->priv : NULL;
194 struct ieee80211_supported_band *sband;
195 struct ieee80211_hdr *hdr;
196 __le32 *rxd = (__le32 *)skb->data;
197 u32 rxd0 = le32_to_cpu(rxd[0]);
198 u32 rxd1 = le32_to_cpu(rxd[1]);
199 u32 rxd2 = le32_to_cpu(rxd[2]);
200 __le32 rxd12 = rxd[12];
201 bool unicast, remove_pad, insert_ccmp_hdr = false;
206 memset(status, 0, sizeof(*status));
208 chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1);
211 else if (phy2->chfreq == phy->chfreq)
213 else if (phy->chfreq == chfreq)
215 else if (phy2->chfreq == chfreq)
220 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M;
221 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
222 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast);
225 struct mt7615_sta *msta;
227 msta = container_of(status->wcid, struct mt7615_sta, wcid);
228 spin_lock_bh(&dev->sta_poll_lock);
229 if (list_empty(&msta->poll_list))
230 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
231 spin_unlock_bh(&dev->sta_poll_lock);
234 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
235 status->flag |= RX_FLAG_FAILED_FCS_CRC;
237 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
238 status->flag |= RX_FLAG_MMIC_ERROR;
240 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
241 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
242 status->flag |= RX_FLAG_DECRYPTED;
243 status->flag |= RX_FLAG_IV_STRIPPED;
244 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
247 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
249 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
253 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
255 if ((u8 *)rxd - skb->data >= skb->len)
259 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
260 u8 *data = (u8 *)rxd;
262 if (status->flag & RX_FLAG_DECRYPTED) {
263 status->iv[0] = data[5];
264 status->iv[1] = data[4];
265 status->iv[2] = data[3];
266 status->iv[3] = data[2];
267 status->iv[4] = data[1];
268 status->iv[5] = data[0];
270 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
273 if ((u8 *)rxd - skb->data >= skb->len)
277 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
279 if ((u8 *)rxd - skb->data >= skb->len)
283 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
284 u32 rxdg5 = le32_to_cpu(rxd[5]);
287 * If both PHYs are on the same channel and we don't have a WCID,
288 * we need to figure out which PHY this packet was received on.
289 * On the primary PHY, the noise value for the chains belonging to the
290 * second PHY will be set to the noise value of the last packet from
294 int first_chain = ffs(phy2->chainmask) - 1;
296 phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0;
300 if (phy_idx == 1 && phy2) {
301 mphy = dev->mt76.phy2;
303 status->ext_phy = true;
306 if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq)
309 mt7615_get_status_freq_info(dev, mphy, status, chfreq);
310 if (status->band == NL80211_BAND_5GHZ)
311 sband = &mphy->sband_5g.sband;
313 sband = &mphy->sband_2g.sband;
315 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
318 if (!sband->channels)
321 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB |
322 MT_RXD2_NORMAL_NON_AMPDU))) {
323 status->flag |= RX_FLAG_AMPDU_DETAILS;
325 /* all subframes of an A-MPDU have the same timestamp */
326 if (phy->rx_ampdu_ts != rxd12) {
327 if (!++phy->ampdu_ref)
330 phy->rx_ampdu_ts = rxd12;
332 status->ampdu_ref = phy->ampdu_ref;
335 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
336 u32 rxdg0 = le32_to_cpu(rxd[0]);
337 u32 rxdg1 = le32_to_cpu(rxd[1]);
338 u32 rxdg3 = le32_to_cpu(rxd[3]);
339 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
342 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
343 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
344 case MT_PHY_TYPE_CCK:
347 case MT_PHY_TYPE_OFDM:
348 i = mt76_get_rate(&dev->mt76, sband, i, cck);
350 case MT_PHY_TYPE_HT_GF:
352 status->encoding = RX_ENC_HT;
356 case MT_PHY_TYPE_VHT:
357 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1;
358 status->encoding = RX_ENC_VHT;
363 status->rate_idx = i;
365 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) {
369 status->bw = RATE_INFO_BW_40;
372 status->bw = RATE_INFO_BW_80;
375 status->bw = RATE_INFO_BW_160;
381 if (rxdg0 & MT_RXV1_HT_SHORT_GI)
382 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
383 if (rxdg0 & MT_RXV1_HT_AD_CODE)
384 status->enc_flags |= RX_ENC_FLAG_LDPC;
386 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
388 status->chains = mphy->antenna_mask;
389 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3);
390 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3);
391 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3);
392 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3);
393 status->signal = status->chain_signal[0];
395 for (i = 1; i < hweight8(mphy->antenna_mask); i++) {
396 if (!(status->chains & BIT(i)))
399 status->signal = max(status->signal,
400 status->chain_signal[i]);
404 if ((u8 *)rxd - skb->data >= skb->len)
408 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
410 if (insert_ccmp_hdr) {
411 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
413 mt76_insert_ccmp_hdr(skb, key_id);
416 hdr = (struct ieee80211_hdr *)skb->data;
417 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
420 status->aggr = unicast &&
421 !ieee80211_is_qos_nullfunc(hdr->frame_control);
422 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
423 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
428 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
431 EXPORT_SYMBOL_GPL(mt7615_sta_ps);
434 mt7615_mac_tx_rate_val(struct mt7615_dev *dev,
435 struct mt76_phy *mphy,
436 const struct ieee80211_tx_rate *rate,
439 u8 phy, nss, rate_idx;
444 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
445 rate_idx = ieee80211_rate_get_vht_mcs(rate);
446 nss = ieee80211_rate_get_vht_nss(rate);
447 phy = MT_PHY_TYPE_VHT;
448 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
450 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
452 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
454 } else if (rate->flags & IEEE80211_TX_RC_MCS) {
455 rate_idx = rate->idx;
456 nss = 1 + (rate->idx >> 3);
457 phy = MT_PHY_TYPE_HT;
458 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
459 phy = MT_PHY_TYPE_HT_GF;
460 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
463 const struct ieee80211_rate *r;
464 int band = mphy->chandef.chan->band;
468 r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx];
469 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
470 val = r->hw_value_short;
475 rate_idx = val & 0xff;
478 if (stbc && nss == 1) {
480 rateval |= MT_TX_RATE_STBC;
483 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
484 FIELD_PREP(MT_TX_RATE_MODE, phy) |
485 FIELD_PREP(MT_TX_RATE_NSS, nss - 1));
490 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
491 struct sk_buff *skb, struct mt76_wcid *wcid,
492 struct ieee80211_sta *sta, int pid,
493 struct ieee80211_key_conf *key, bool beacon)
495 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
496 struct ieee80211_tx_rate *rate = &info->control.rates[0];
497 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
498 bool multicast = is_multicast_ether_addr(hdr->addr1);
499 struct ieee80211_vif *vif = info->control.vif;
500 struct mt76_phy *mphy = &dev->mphy;
501 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY;
502 bool is_usb = mt76_is_usb(&dev->mt76);
504 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
505 __le16 fc = hdr->frame_control;
506 u32 val, sz_txd = is_usb ? MT_USB_TXD_SIZE : MT_TXD_SIZE;
510 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
512 omac_idx = mvif->omac_idx;
513 wmm_idx = mvif->wmm_idx;
517 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
519 tx_count = msta->rate_count;
522 if (ext_phy && dev->mt76.phy2)
523 mphy = dev->mt76.phy2;
525 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
526 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
528 if (ieee80211_is_data(fc) || ieee80211_is_bufferable_mmpdu(fc)) {
529 q_idx = wmm_idx * MT7615_MAX_WMM_SETS +
530 skb_get_queue_mapping(skb);
531 p_fmt = is_usb ? MT_TX_TYPE_SF : MT_TX_TYPE_CT;
534 q_idx = MT_LMAC_BCN1;
536 q_idx = MT_LMAC_BCN0;
537 p_fmt = MT_TX_TYPE_FW;
540 q_idx = MT_LMAC_ALTX1;
542 q_idx = MT_LMAC_ALTX0;
543 p_fmt = is_usb ? MT_TX_TYPE_SF : MT_TX_TYPE_CT;
546 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) |
547 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) |
548 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
549 txwi[0] = cpu_to_le32(val);
551 val = MT_TXD1_LONG_FORMAT |
552 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
553 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
554 FIELD_PREP(MT_TXD1_HDR_INFO,
555 ieee80211_get_hdrlen_from_skb(skb) / 2) |
556 FIELD_PREP(MT_TXD1_TID,
557 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
558 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) |
559 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
560 txwi[1] = cpu_to_le32(val);
562 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
563 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
564 FIELD_PREP(MT_TXD2_MULTICAST, multicast);
566 if (multicast && ieee80211_is_robust_mgmt_frame(skb) &&
567 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
571 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME);
576 txwi[2] = cpu_to_le32(val);
578 if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
579 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
584 if (rate->idx >= 0 && rate->count &&
585 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
586 bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
588 u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc,
591 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
593 val = MT_TXD6_FIXED_BW |
594 FIELD_PREP(MT_TXD6_BW, bw) |
595 FIELD_PREP(MT_TXD6_TX_RATE, rateval);
596 txwi[6] |= cpu_to_le32(val);
598 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
599 txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
601 if (info->flags & IEEE80211_TX_CTL_LDPC)
602 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC);
604 if (!(rate->flags & (IEEE80211_TX_RC_MCS |
605 IEEE80211_TX_RC_VHT_MCS)))
606 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
608 tx_count = rate->count;
611 if (!ieee80211_is_beacon(fc)) {
612 struct ieee80211_hw *hw = mt76_hw(dev);
614 val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid);
615 if (!ieee80211_hw_check(hw, SUPPORTS_PS))
616 val |= MT_TXD5_SW_POWER_MGMT;
617 txwi[5] = cpu_to_le32(val);
620 /* use maximum tx count for beacons */
624 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
625 if (ieee80211_is_data_qos(hdr->frame_control)) {
626 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
627 val |= MT_TXD3_SN_VALID;
628 } else if (ieee80211_is_back_req(hdr->frame_control)) {
629 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data;
631 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(bar->start_seq_num));
632 val |= MT_TXD3_SN_VALID;
634 val |= FIELD_PREP(MT_TXD3_SEQ, seqno);
636 txwi[3] |= cpu_to_le32(val);
638 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
639 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
641 txwi[7] = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
642 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
644 txwi[8] = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) |
645 FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype);
649 EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi);
652 mt7615_txp_skb_unmap_fw(struct mt76_dev *dev, struct mt7615_fw_txp *txp)
656 for (i = 1; i < txp->nbuf; i++)
657 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
658 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
662 mt7615_txp_skb_unmap_hw(struct mt76_dev *dev, struct mt7615_hw_txp *txp)
667 last_mask = is_mt7663(dev) ? MT_TXD_LEN_LAST : MT_TXD_LEN_MSDU_LAST;
669 for (i = 0; i < ARRAY_SIZE(txp->ptr); i++) {
670 struct mt7615_txp_ptr *ptr = &txp->ptr[i];
674 len = le16_to_cpu(ptr->len0);
675 last = len & last_mask;
676 len &= MT_TXD_LEN_MASK;
677 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf0), len,
682 len = le16_to_cpu(ptr->len1);
683 last = len & last_mask;
684 len &= MT_TXD_LEN_MASK;
685 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf1), len,
692 void mt7615_txp_skb_unmap(struct mt76_dev *dev,
693 struct mt76_txwi_cache *t)
695 struct mt7615_txp_common *txp;
697 txp = mt7615_txwi_to_txp(dev, t);
699 mt7615_txp_skb_unmap_fw(dev, &txp->fw);
701 mt7615_txp_skb_unmap_hw(dev, &txp->hw);
703 EXPORT_SYMBOL_GPL(mt7615_txp_skb_unmap);
705 bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask)
707 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
708 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
710 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
714 void mt7615_mac_sta_poll(struct mt7615_dev *dev)
716 static const u8 ac_to_tid[4] = {
717 [IEEE80211_AC_BE] = 0,
718 [IEEE80211_AC_BK] = 1,
719 [IEEE80211_AC_VI] = 4,
720 [IEEE80211_AC_VO] = 6
722 static const u8 hw_queue_map[] = {
723 [IEEE80211_AC_BK] = 0,
724 [IEEE80211_AC_BE] = 1,
725 [IEEE80211_AC_VI] = 2,
726 [IEEE80211_AC_VO] = 3,
728 struct ieee80211_sta *sta;
729 struct mt7615_sta *msta;
730 u32 addr, tx_time[4], rx_time[4];
731 struct list_head sta_poll_list;
734 INIT_LIST_HEAD(&sta_poll_list);
735 spin_lock_bh(&dev->sta_poll_lock);
736 list_splice_init(&dev->sta_poll_list, &sta_poll_list);
737 spin_unlock_bh(&dev->sta_poll_lock);
739 while (!list_empty(&sta_poll_list)) {
742 msta = list_first_entry(&sta_poll_list, struct mt7615_sta,
744 list_del_init(&msta->poll_list);
746 addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4;
748 for (i = 0; i < 4; i++, addr += 8) {
749 u32 tx_last = msta->airtime_ac[i];
750 u32 rx_last = msta->airtime_ac[i + 4];
752 msta->airtime_ac[i] = mt76_rr(dev, addr);
753 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
754 tx_time[i] = msta->airtime_ac[i] - tx_last;
755 rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
757 if ((tx_last | rx_last) & BIT(30))
762 mt7615_mac_wtbl_update(dev, msta->wcid.idx,
763 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
764 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
770 sta = container_of((void *)msta, struct ieee80211_sta,
772 for (i = 0; i < 4; i++) {
773 u32 tx_cur = tx_time[i];
774 u32 rx_cur = rx_time[hw_queue_map[i]];
775 u8 tid = ac_to_tid[i];
777 if (!tx_cur && !rx_cur)
780 ieee80211_sta_register_airtime(sta, tid, tx_cur,
785 EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll);
788 mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta,
789 struct ieee80211_tx_rate *probe_rate,
790 struct ieee80211_tx_rate *rates,
791 struct mt7615_rate_desc *rd)
793 struct mt7615_dev *dev = phy->dev;
794 struct mt76_phy *mphy = phy->mt76;
795 struct ieee80211_tx_rate *ref;
796 bool rateset, stbc = false;
797 int n_rates = sta->n_rates;
801 for (i = n_rates; i < 4; i++)
802 rates[i] = rates[n_rates - 1];
804 rateset = !(sta->rate_set_tsf & BIT(0));
805 memcpy(sta->rateset[rateset].rates, rates,
806 sizeof(sta->rateset[rateset].rates));
808 sta->rateset[rateset].probe_rate = *probe_rate;
809 ref = &sta->rateset[rateset].probe_rate;
811 sta->rateset[rateset].probe_rate.idx = -1;
812 ref = &sta->rateset[rateset].rates[0];
815 rates = sta->rateset[rateset].rates;
816 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
818 * We don't support switching between short and long GI
819 * within the rate set. For accurate tx status reporting, we
820 * need to make sure that flags match.
821 * For improved performance, avoid duplicate entries by
822 * decrementing the MCS index if necessary
824 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
825 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
827 for (j = 0; j < i; j++) {
828 if (rates[i].idx != rates[j].idx)
830 if ((rates[i].flags ^ rates[j].flags) &
831 (IEEE80211_TX_RC_40_MHZ_WIDTH |
832 IEEE80211_TX_RC_80_MHZ_WIDTH |
833 IEEE80211_TX_RC_160_MHZ_WIDTH))
843 rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw);
847 rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate,
854 rd->probe_val = rd->val[0];
857 rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw);
863 rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw);
869 rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw);
873 rd->rateset = rateset;
878 mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta,
879 struct ieee80211_tx_rate *probe_rate,
880 struct ieee80211_tx_rate *rates)
882 struct mt7615_dev *dev = phy->dev;
883 struct mt7615_wtbl_desc *wd;
885 wd = kzalloc(sizeof(*wd), GFP_ATOMIC);
889 wd->type = MT7615_WTBL_RATE_DESC;
892 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates,
894 list_add_tail(&wd->node, &dev->wd_head);
895 queue_work(dev->mt76.usb.wq, &dev->wtbl_work);
900 void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
901 struct ieee80211_tx_rate *probe_rate,
902 struct ieee80211_tx_rate *rates)
904 int wcid = sta->wcid.idx, n_rates = sta->n_rates;
905 struct mt7615_dev *dev = phy->dev;
906 struct mt7615_rate_desc rd;
909 if (mt76_is_usb(&dev->mt76)) {
910 mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates);
914 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
917 memset(&rd, 0, sizeof(struct mt7615_rate_desc));
918 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd);
920 addr = mt7615_mac_wtbl_addr(dev, wcid);
921 w27 = mt76_rr(dev, addr + 27 * 4);
922 w27 &= ~MT_WTBL_W27_CC_BW_SEL;
923 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw);
925 w5 = mt76_rr(dev, addr + 5 * 4);
926 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE |
927 MT_WTBL_W5_MPDU_OK_COUNT |
928 MT_WTBL_W5_MPDU_FAIL_COUNT |
929 MT_WTBL_W5_RATE_IDX);
930 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) |
931 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE,
932 rd.bw_idx ? rd.bw_idx - 1 : 7);
934 mt76_wr(dev, MT_WTBL_RIUCR0, w5);
936 mt76_wr(dev, MT_WTBL_RIUCR1,
937 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) |
938 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) |
939 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1]));
941 mt76_wr(dev, MT_WTBL_RIUCR2,
942 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) |
943 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) |
944 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) |
945 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2]));
947 mt76_wr(dev, MT_WTBL_RIUCR3,
948 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) |
949 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) |
950 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3]));
952 mt76_wr(dev, MT_WTBL_UPDATE,
953 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
954 MT_WTBL_UPDATE_RATE_UPDATE |
955 MT_WTBL_UPDATE_TX_COUNT_CLEAR);
957 mt76_wr(dev, addr + 27 * 4, w27);
959 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
960 sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0);
961 sta->rate_set_tsf |= rd.rateset;
963 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
964 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
966 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates;
967 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
969 EXPORT_SYMBOL_GPL(mt7615_mac_set_rates);
971 int mt7615_mac_wtbl_update_key(struct mt7615_dev *dev,
972 struct mt76_wcid *wcid,
974 enum mt7615_cipher_type cipher,
975 enum set_key_cmd cmd)
977 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4;
980 if (keylen > sizeof(data))
983 mt76_rr_copy(dev, addr, data, sizeof(data));
984 if (cmd == SET_KEY) {
985 if (cipher == MT_CIPHER_TKIP) {
986 /* Rx/Tx MIC keys are swapped */
987 memcpy(data + 16, key + 24, 8);
988 memcpy(data + 24, key + 16, 8);
990 if (cipher != MT_CIPHER_BIP_CMAC_128 && wcid->cipher)
991 memmove(data + 16, data, 16);
992 if (cipher != MT_CIPHER_BIP_CMAC_128 || !wcid->cipher)
993 memcpy(data, key, keylen);
994 else if (cipher == MT_CIPHER_BIP_CMAC_128)
995 memcpy(data + 16, key, 16);
997 if (wcid->cipher & ~BIT(cipher)) {
998 if (cipher != MT_CIPHER_BIP_CMAC_128)
999 memmove(data, data + 16, 16);
1000 memset(data + 16, 0, 16);
1002 memset(data, 0, sizeof(data));
1005 mt76_wr_copy(dev, addr, data, sizeof(data));
1009 EXPORT_SYMBOL_GPL(mt7615_mac_wtbl_update_key);
1011 int mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev,
1012 struct mt76_wcid *wcid,
1013 enum mt7615_cipher_type cipher,
1014 int keyidx, enum set_key_cmd cmd)
1016 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1;
1018 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
1021 w0 = mt76_rr(dev, addr);
1022 w1 = mt76_rr(dev, addr + 4);
1023 if (cmd == SET_KEY) {
1024 w0 |= MT_WTBL_W0_RX_KEY_VALID |
1025 FIELD_PREP(MT_WTBL_W0_RX_IK_VALID,
1026 cipher == MT_CIPHER_BIP_CMAC_128);
1027 if (cipher != MT_CIPHER_BIP_CMAC_128 ||
1029 w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx);
1031 if (!(wcid->cipher & ~BIT(cipher)))
1032 w0 &= ~(MT_WTBL_W0_RX_KEY_VALID |
1033 MT_WTBL_W0_KEY_IDX);
1034 if (cipher == MT_CIPHER_BIP_CMAC_128)
1035 w0 &= ~MT_WTBL_W0_RX_IK_VALID;
1037 mt76_wr(dev, MT_WTBL_RICR0, w0);
1038 mt76_wr(dev, MT_WTBL_RICR1, w1);
1040 if (!mt7615_mac_wtbl_update(dev, wcid->idx,
1041 MT_WTBL_UPDATE_RXINFO_UPDATE))
1046 EXPORT_SYMBOL_GPL(mt7615_mac_wtbl_update_pk);
1048 void mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev,
1049 struct mt76_wcid *wcid,
1050 enum mt7615_cipher_type cipher,
1051 enum set_key_cmd cmd)
1053 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx);
1055 if (cmd == SET_KEY) {
1056 if (cipher != MT_CIPHER_BIP_CMAC_128 || !wcid->cipher)
1057 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
1058 FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher));
1060 if (cipher != MT_CIPHER_BIP_CMAC_128 &&
1061 wcid->cipher & BIT(MT_CIPHER_BIP_CMAC_128))
1062 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
1063 FIELD_PREP(MT_WTBL_W2_KEY_TYPE,
1064 MT_CIPHER_BIP_CMAC_128));
1065 else if (!(wcid->cipher & ~BIT(cipher)))
1066 mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE);
1069 EXPORT_SYMBOL_GPL(mt7615_mac_wtbl_update_cipher);
1071 int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev,
1072 struct mt76_wcid *wcid,
1073 struct ieee80211_key_conf *key,
1074 enum set_key_cmd cmd)
1076 enum mt7615_cipher_type cipher;
1079 cipher = mt7615_mac_get_cipher(key->cipher);
1080 if (cipher == MT_CIPHER_NONE)
1083 spin_lock_bh(&dev->mt76.lock);
1085 mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cmd);
1086 err = mt7615_mac_wtbl_update_key(dev, wcid, key->key, key->keylen,
1091 err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, key->keyidx,
1097 wcid->cipher |= BIT(cipher);
1099 wcid->cipher &= ~BIT(cipher);
1102 spin_unlock_bh(&dev->mt76.lock);
1107 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta,
1108 struct ieee80211_tx_info *info, __le32 *txs_data)
1110 struct ieee80211_supported_band *sband;
1111 struct mt7615_rate_set *rs;
1112 struct mt76_phy *mphy;
1113 int first_idx = 0, last_idx;
1115 bool fixed_rate, ack_timeout;
1116 bool probe, ampdu, cck = false;
1119 u32 final_rate, final_rate_flags, final_nss, txs;
1121 fixed_rate = info->status.rates[0].count;
1122 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1124 txs = le32_to_cpu(txs_data[1]);
1125 ampdu = !fixed_rate && (txs & MT_TXS1_AMPDU);
1127 txs = le32_to_cpu(txs_data[3]);
1128 count = FIELD_GET(MT_TXS3_TX_COUNT, txs);
1129 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs);
1131 txs = le32_to_cpu(txs_data[0]);
1132 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
1133 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
1135 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
1138 if (txs & MT_TXS0_QUEUE_TIMEOUT)
1142 info->flags |= IEEE80211_TX_STAT_ACK;
1144 info->status.ampdu_len = 1;
1145 info->status.ampdu_ack_len = !!(info->flags &
1146 IEEE80211_TX_STAT_ACK);
1148 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
1149 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
1151 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY);
1153 if (fixed_rate && !probe) {
1154 info->status.rates[0].count = count;
1159 rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
1160 rs_idx = !((u32)(FIELD_GET(MT_TXS4_F0_TIMESTAMP, le32_to_cpu(txs_data[4])) -
1161 rate_set_tsf) < 1000000);
1162 rs_idx ^= rate_set_tsf & BIT(0);
1163 rs = &sta->rateset[rs_idx];
1165 if (!first_idx && rs->probe_rate.idx >= 0) {
1166 info->status.rates[0] = rs->probe_rate;
1168 spin_lock_bh(&dev->mt76.lock);
1169 if (sta->rate_probe) {
1170 struct mt7615_phy *phy = &dev->phy;
1172 if (sta->wcid.ext_phy && dev->mt76.phy2)
1173 phy = dev->mt76.phy2->priv;
1175 mt7615_mac_set_rates(phy, sta, NULL, sta->rates);
1176 sta->rate_probe = false;
1178 spin_unlock_bh(&dev->mt76.lock);
1180 info->status.rates[0] = rs->rates[first_idx / 2];
1182 info->status.rates[0].count = 0;
1184 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
1185 struct ieee80211_tx_rate *cur_rate;
1188 cur_rate = &rs->rates[idx / 2];
1189 cur_count = min_t(int, MT7615_RATE_RETRY, count);
1192 if (idx && (cur_rate->idx != info->status.rates[i].idx ||
1193 cur_rate->flags != info->status.rates[i].flags)) {
1195 if (i == ARRAY_SIZE(info->status.rates)) {
1200 info->status.rates[i] = *cur_rate;
1201 info->status.rates[i].count = 0;
1204 info->status.rates[i].count += cur_count;
1208 final_rate_flags = info->status.rates[i].flags;
1210 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
1211 case MT_PHY_TYPE_CCK:
1214 case MT_PHY_TYPE_OFDM:
1216 if (sta->wcid.ext_phy && dev->mt76.phy2)
1217 mphy = dev->mt76.phy2;
1219 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
1220 sband = &mphy->sband_5g.sband;
1222 sband = &mphy->sband_2g.sband;
1223 final_rate &= MT_TX_RATE_IDX;
1224 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
1226 final_rate_flags = 0;
1228 case MT_PHY_TYPE_HT_GF:
1229 case MT_PHY_TYPE_HT:
1230 final_rate_flags |= IEEE80211_TX_RC_MCS;
1231 final_rate &= MT_TX_RATE_IDX;
1232 if (final_rate > 31)
1235 case MT_PHY_TYPE_VHT:
1236 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate);
1238 if ((final_rate & MT_TX_RATE_STBC) && final_nss)
1241 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS;
1242 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4);
1248 info->status.rates[i].idx = final_rate;
1249 info->status.rates[i].flags = final_rate_flags;
1254 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev,
1255 struct mt7615_sta *sta, int pid,
1258 struct mt76_dev *mdev = &dev->mt76;
1259 struct sk_buff_head list;
1260 struct sk_buff *skb;
1262 if (pid < MT_PACKET_ID_FIRST)
1265 trace_mac_txdone(mdev, sta->wcid.idx, pid);
1267 mt76_tx_status_lock(mdev, &list);
1268 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
1270 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1272 if (!mt7615_fill_txs(dev, sta, info, txs_data)) {
1273 ieee80211_tx_info_clear_status(info);
1274 info->status.rates[0].idx = -1;
1277 mt76_tx_status_skb_done(mdev, skb, &list);
1279 mt76_tx_status_unlock(mdev, &list);
1284 static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data)
1286 struct ieee80211_tx_info info = {};
1287 struct ieee80211_sta *sta = NULL;
1288 struct mt7615_sta *msta = NULL;
1289 struct mt76_wcid *wcid;
1290 struct mt76_phy *mphy = &dev->mt76.phy;
1291 __le32 *txs_data = data;
1296 txs = le32_to_cpu(txs_data[0]);
1297 pid = FIELD_GET(MT_TXS0_PID, txs);
1298 txs = le32_to_cpu(txs_data[2]);
1299 wcidx = FIELD_GET(MT_TXS2_WCID, txs);
1301 if (pid == MT_PACKET_ID_NO_ACK)
1304 if (wcidx >= ARRAY_SIZE(dev->mt76.wcid))
1309 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1313 msta = container_of(wcid, struct mt7615_sta, wcid);
1314 sta = wcid_to_sta(wcid);
1316 spin_lock_bh(&dev->sta_poll_lock);
1317 if (list_empty(&msta->poll_list))
1318 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1319 spin_unlock_bh(&dev->sta_poll_lock);
1321 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data))
1324 if (wcidx >= MT7615_WTBL_STA || !sta)
1327 if (wcid->ext_phy && dev->mt76.phy2)
1328 mphy = dev->mt76.phy2;
1330 if (mt7615_fill_txs(dev, msta, &info, txs_data))
1331 ieee80211_tx_status_noskb(mphy->hw, sta, &info);
1338 mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token)
1340 struct mt76_dev *mdev = &dev->mt76;
1341 struct mt76_txwi_cache *txwi;
1343 trace_mac_tx_free(dev, token);
1345 spin_lock_bh(&dev->token_lock);
1346 txwi = idr_remove(&dev->token, token);
1347 spin_unlock_bh(&dev->token_lock);
1352 mt7615_txp_skb_unmap(mdev, txwi);
1354 mt76_tx_complete_skb(mdev, txwi->skb);
1358 mt76_put_txwi(mdev, txwi);
1361 static void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
1363 struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
1366 count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
1367 if (is_mt7615(&dev->mt76)) {
1368 __le16 *token = &free->token[0];
1370 for (i = 0; i < count; i++)
1371 mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i]));
1373 __le32 *token = (__le32 *)&free->token[0];
1375 for (i = 0; i < count; i++)
1376 mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i]));
1382 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1383 struct sk_buff *skb)
1385 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1386 __le32 *rxd = (__le32 *)skb->data;
1387 __le32 *end = (__le32 *)&skb->data[skb->len];
1388 enum rx_pkt_type type;
1391 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
1392 flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0]));
1393 if (type == PKT_TYPE_RX_EVENT && flag == 0x1)
1394 type = PKT_TYPE_NORMAL_MCU;
1398 for (rxd++; rxd + 7 <= end; rxd += 7)
1399 mt7615_mac_add_txs(dev, rxd);
1402 case PKT_TYPE_TXRX_NOTIFY:
1403 mt7615_mac_tx_free(dev, skb);
1405 case PKT_TYPE_RX_EVENT:
1406 mt7615_mcu_rx_event(dev, skb);
1408 case PKT_TYPE_NORMAL_MCU:
1409 case PKT_TYPE_NORMAL:
1410 if (!mt7615_mac_fill_rx(dev, skb)) {
1411 mt76_rx(&dev->mt76, q, skb);
1420 EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb);
1423 mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm)
1425 struct mt7615_dev *dev = phy->dev;
1426 bool ext_phy = phy != &dev->phy;
1428 if (is_mt7663(&dev->mt76)) {
1430 mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy),
1431 MT_WF_PHY_PD_OFDM_MASK(0),
1432 MT_WF_PHY_PD_OFDM(0, val));
1434 mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy),
1435 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1436 MT_WF_PHY_PD_CCK(ext_phy, val));
1441 mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy),
1442 MT_WF_PHY_PD_OFDM_MASK(ext_phy),
1443 MT_WF_PHY_PD_OFDM(ext_phy, val));
1445 mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy),
1446 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1447 MT_WF_PHY_PD_CCK(ext_phy, val));
1451 mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy)
1454 mt7615_mac_set_sensitivity(phy, 0x13c, true);
1456 mt7615_mac_set_sensitivity(phy, 0x92, false);
1458 phy->ofdm_sensitivity = -98;
1459 phy->cck_sensitivity = -110;
1460 phy->last_cca_adj = jiffies;
1463 void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable)
1465 struct mt7615_dev *dev = phy->dev;
1466 bool ext_phy = phy != &dev->phy;
1469 mutex_lock(&dev->mt76.mutex);
1471 if (phy->scs_en == enable)
1474 if (is_mt7663(&dev->mt76)) {
1475 reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy);
1476 mask = MT_WF_PHY_PD_BLK(0);
1478 reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy);
1479 mask = MT_WF_PHY_PD_BLK(ext_phy);
1483 mt76_set(dev, reg, mask);
1484 if (is_mt7622(&dev->mt76)) {
1485 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8);
1486 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7);
1489 mt76_clear(dev, reg, mask);
1492 mt7615_mac_set_default_sensitivity(phy);
1493 phy->scs_en = enable;
1496 mutex_unlock(&dev->mt76.mutex);
1499 void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy)
1503 if (is_mt7663(&dev->mt76))
1504 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1506 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1509 rxtd = MT_WF_PHY_RXTD2(10);
1511 rxtd = MT_WF_PHY_RXTD(12);
1513 mt76_set(dev, rxtd, BIT(18) | BIT(29));
1514 mt76_set(dev, reg, 0x5 << 12);
1517 void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy)
1519 struct mt7615_dev *dev = phy->dev;
1520 bool ext_phy = phy != &dev->phy;
1523 if (is_mt7663(&dev->mt76))
1524 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1526 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1528 /* reset PD and MDRDY counters */
1529 mt76_clear(dev, reg, GENMASK(22, 20));
1530 mt76_set(dev, reg, BIT(22) | BIT(20));
1534 mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy,
1535 u32 rts_err_rate, bool ofdm)
1537 struct mt7615_dev *dev = phy->dev;
1538 int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck;
1539 bool ext_phy = phy != &dev->phy;
1540 u16 def_th = ofdm ? -98 : -110;
1541 bool update = false;
1545 sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity;
1546 signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy);
1548 mt7615_mac_set_default_sensitivity(phy);
1552 signal = min(signal, -72);
1553 if (false_cca > 500) {
1554 if (rts_err_rate > MT_FRAC(40, 100))
1557 /* decrease coverage */
1558 if (*sensitivity == def_th && signal > -90) {
1561 } else if (*sensitivity + 2 < signal) {
1565 } else if ((false_cca > 0 && false_cca < 50) ||
1566 rts_err_rate > MT_FRAC(60, 100)) {
1567 /* increase coverage */
1568 if (*sensitivity - 2 >= def_th) {
1574 if (*sensitivity > signal) {
1575 *sensitivity = signal;
1580 u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256;
1582 mt7615_mac_set_sensitivity(phy, val, ofdm);
1583 phy->last_cca_adj = jiffies;
1588 mt7615_mac_scs_check(struct mt7615_phy *phy)
1590 struct mt7615_dev *dev = phy->dev;
1591 struct mib_stats *mib = &phy->mib;
1592 u32 val, rts_err_rate = 0;
1593 u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm;
1594 bool ext_phy = phy != &dev->phy;
1599 if (is_mt7663(&dev->mt76))
1600 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1602 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1603 pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val);
1604 pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val);
1606 if (is_mt7663(&dev->mt76))
1607 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1609 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1610 mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val);
1611 mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val);
1613 phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1614 phy->false_cca_cck = pd_cck - mdrdy_cck;
1615 mt7615_mac_cca_stats_reset(phy);
1617 if (mib->rts_cnt + mib->rts_retries_cnt)
1618 rts_err_rate = MT_FRAC(mib->rts_retries_cnt,
1619 mib->rts_cnt + mib->rts_retries_cnt);
1622 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false);
1624 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true);
1626 if (time_after(jiffies, phy->last_cca_adj + 10 * HZ))
1627 mt7615_mac_set_default_sensitivity(phy);
1631 mt7615_phy_get_nf(struct mt7615_dev *dev, int idx)
1633 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
1634 u32 reg, val, sum = 0, n = 0;
1637 if (is_mt7663(&dev->mt76))
1638 reg = MT7663_WF_PHY_RXTD(20);
1640 reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20);
1642 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
1643 val = mt76_rr(dev, reg);
1644 sum += val * nf_power[i];
1655 mt7615_phy_update_channel(struct mt76_phy *mphy, int idx)
1657 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76);
1658 struct mt7615_phy *phy = mphy->priv;
1659 struct mt76_channel_state *state;
1660 u64 busy_time, tx_time, rx_time, obss_time;
1661 u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5;
1664 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
1665 MT_MIB_SDR9_BUSY_MASK);
1666 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
1667 MT_MIB_SDR36_TXTIME_MASK);
1668 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
1669 MT_MIB_SDR37_RXTIME_MASK);
1670 obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK);
1672 nf = mt7615_phy_get_nf(dev, idx);
1674 phy->noise = nf << 4;
1676 phy->noise += nf - (phy->noise >> 4);
1678 state = mphy->chan_state;
1679 state->cc_busy += busy_time;
1680 state->cc_tx += tx_time;
1681 state->cc_rx += rx_time + obss_time;
1682 state->cc_bss_rx += rx_time;
1683 state->noise = -(phy->noise >> 4);
1686 void mt7615_update_channel(struct mt76_dev *mdev)
1688 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1690 mt7615_phy_update_channel(&mdev->phy, 0);
1692 mt7615_phy_update_channel(mdev->phy2, 1);
1694 /* reset obss airtime */
1695 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
1697 EXPORT_SYMBOL_GPL(mt7615_update_channel);
1700 mt7615_mac_update_mib_stats(struct mt7615_phy *phy)
1702 struct mt7615_dev *dev = phy->dev;
1703 struct mib_stats *mib = &phy->mib;
1704 bool ext_phy = phy != &dev->phy;
1708 memset(mib, 0, sizeof(*mib));
1710 mib->fcs_err_cnt = mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
1711 MT_MIB_SDR3_FCS_ERR_MASK);
1713 val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy),
1714 MT_MIB_AMPDU_MPDU_COUNT);
1716 val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy),
1717 MT_MIB_AMPDU_ACK_COUNT);
1718 mib->aggr_per = 1000 * (val - val2) / val;
1721 aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
1722 for (i = 0; i < 4; i++) {
1723 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i));
1725 val2 = FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val);
1726 if (val2 > mib->ack_fail_cnt)
1727 mib->ack_fail_cnt = val2;
1729 val2 = FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
1730 if (val2 > mib->ba_miss_cnt)
1731 mib->ba_miss_cnt = val2;
1733 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
1734 val2 = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
1735 if (val2 > mib->rts_retries_cnt) {
1736 mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
1737 mib->rts_retries_cnt = val2;
1740 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
1742 dev->mt76.aggr_stats[aggr++] += val & 0xffff;
1743 dev->mt76.aggr_stats[aggr++] += val >> 16;
1747 void mt7615_mac_work(struct work_struct *work)
1749 struct mt7615_phy *phy;
1750 struct mt76_dev *mdev;
1752 phy = (struct mt7615_phy *)container_of(work, struct mt7615_phy,
1754 mdev = &phy->dev->mt76;
1756 mutex_lock(&mdev->mutex);
1758 mt76_update_survey(mdev);
1759 if (++phy->mac_work_count == 5) {
1760 phy->mac_work_count = 0;
1762 mt7615_mac_update_mib_stats(phy);
1763 mt7615_mac_scs_check(phy);
1766 mutex_unlock(&mdev->mutex);
1768 mt76_tx_status_check(mdev, NULL, false);
1769 ieee80211_queue_delayed_work(phy->mt76->hw, &phy->mac_work,
1770 MT7615_WATCHDOG_TIME);
1774 mt7615_wait_reset_state(struct mt7615_dev *dev, u32 state)
1778 ret = wait_event_timeout(dev->reset_wait,
1779 (READ_ONCE(dev->reset_state) & state),
1780 MT7615_RESET_TIMEOUT);
1781 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
1786 mt7615_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
1788 struct ieee80211_hw *hw = priv;
1789 struct mt7615_dev *dev = mt7615_hw_dev(hw);
1791 mt7615_mcu_add_beacon(dev, hw, vif, vif->bss_conf.enable_beacon);
1795 mt7615_update_beacons(struct mt7615_dev *dev)
1797 ieee80211_iterate_active_interfaces(dev->mt76.hw,
1798 IEEE80211_IFACE_ITER_RESUME_ALL,
1799 mt7615_update_vif_beacon, dev->mt76.hw);
1801 if (!dev->mt76.phy2)
1804 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw,
1805 IEEE80211_IFACE_ITER_RESUME_ALL,
1806 mt7615_update_vif_beacon, dev->mt76.phy2->hw);
1810 mt7615_dma_reset(struct mt7615_dev *dev)
1814 mt76_clear(dev, MT_WPDMA_GLO_CFG,
1815 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
1816 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
1817 usleep_range(1000, 2000);
1819 for (i = 0; i < __MT_TXQ_MAX; i++)
1820 mt76_queue_tx_cleanup(dev, i, true);
1822 for (i = 0; i < ARRAY_SIZE(dev->mt76.q_rx); i++)
1823 mt76_queue_rx_reset(dev, i);
1825 mt76_set(dev, MT_WPDMA_GLO_CFG,
1826 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
1827 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
1830 void mt7615_mac_reset_work(struct work_struct *work)
1832 struct mt7615_phy *phy2;
1833 struct mt76_phy *ext_phy;
1834 struct mt7615_dev *dev;
1836 dev = container_of(work, struct mt7615_dev, reset_work);
1837 ext_phy = dev->mt76.phy2;
1838 phy2 = ext_phy ? ext_phy->priv : NULL;
1840 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_PDMA))
1843 ieee80211_stop_queues(mt76_hw(dev));
1845 ieee80211_stop_queues(ext_phy->hw);
1847 set_bit(MT76_RESET, &dev->mphy.state);
1848 set_bit(MT76_MCU_RESET, &dev->mphy.state);
1849 wake_up(&dev->mt76.mcu.wait);
1850 cancel_delayed_work_sync(&dev->phy.mac_work);
1852 cancel_delayed_work_sync(&phy2->mac_work);
1854 /* lock/unlock all queues to ensure that no tx is pending */
1855 mt76_txq_schedule_all(&dev->mphy);
1857 mt76_txq_schedule_all(ext_phy);
1859 tasklet_disable(&dev->mt76.tx_tasklet);
1860 napi_disable(&dev->mt76.napi[0]);
1861 napi_disable(&dev->mt76.napi[1]);
1862 napi_disable(&dev->mt76.tx_napi);
1864 mutex_lock(&dev->mt76.mutex);
1866 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_PDMA_STOPPED);
1868 if (mt7615_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
1869 mt7615_dma_reset(dev);
1871 mt76_wr(dev, MT_WPDMA_MEM_RNG_ERR, 0);
1873 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_PDMA_INIT);
1874 mt7615_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
1877 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
1878 clear_bit(MT76_RESET, &dev->mphy.state);
1880 tasklet_enable(&dev->mt76.tx_tasklet);
1881 napi_enable(&dev->mt76.tx_napi);
1882 napi_schedule(&dev->mt76.tx_napi);
1884 napi_enable(&dev->mt76.napi[0]);
1885 napi_schedule(&dev->mt76.napi[0]);
1887 napi_enable(&dev->mt76.napi[1]);
1888 napi_schedule(&dev->mt76.napi[1]);
1890 ieee80211_wake_queues(mt76_hw(dev));
1892 ieee80211_wake_queues(ext_phy->hw);
1894 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
1895 mt7615_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
1897 mutex_unlock(&dev->mt76.mutex);
1899 mt7615_update_beacons(dev);
1901 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->phy.mac_work,
1902 MT7615_WATCHDOG_TIME);
1904 ieee80211_queue_delayed_work(ext_phy->hw, &phy2->mac_work,
1905 MT7615_WATCHDOG_TIME);
1909 static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy)
1911 struct mt7615_dev *dev = phy->dev;
1913 if (phy->rdd_state & BIT(0))
1914 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0);
1915 if (phy->rdd_state & BIT(1))
1916 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0);
1919 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain)
1923 err = mt7615_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
1927 return mt7615_mcu_rdd_cmd(dev, RDD_DET_MODE, chain,
1931 static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy)
1933 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1934 struct mt7615_dev *dev = phy->dev;
1935 bool ext_phy = phy != &dev->phy;
1939 err = mt7615_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0);
1943 err = mt7615_dfs_start_rdd(dev, ext_phy);
1947 phy->rdd_state |= BIT(ext_phy);
1949 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
1950 chandef->width == NL80211_CHAN_WIDTH_80P80) {
1951 err = mt7615_dfs_start_rdd(dev, 1);
1955 phy->rdd_state |= BIT(1);
1962 mt7615_dfs_init_radar_specs(struct mt7615_phy *phy)
1964 const struct mt7615_dfs_radar_spec *radar_specs;
1965 struct mt7615_dev *dev = phy->dev;
1968 switch (dev->mt76.region) {
1969 case NL80211_DFS_FCC:
1970 radar_specs = &fcc_radar_specs;
1971 err = mt7615_mcu_set_fcc5_lpn(dev, 8);
1975 case NL80211_DFS_ETSI:
1976 radar_specs = &etsi_radar_specs;
1978 case NL80211_DFS_JP:
1979 radar_specs = &jp_radar_specs;
1985 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
1986 err = mt7615_mcu_set_radar_th(dev, i,
1987 &radar_specs->radar_pattern[i]);
1992 return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
1995 int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy)
1997 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1998 struct mt7615_dev *dev = phy->dev;
1999 bool ext_phy = phy != &dev->phy;
2002 if (is_mt7663(&dev->mt76))
2005 if (dev->mt76.region == NL80211_DFS_UNSET) {
2006 phy->dfs_state = -1;
2013 if (test_bit(MT76_SCANNING, &phy->mt76->state))
2016 if (phy->dfs_state == chandef->chan->dfs_state)
2019 err = mt7615_dfs_init_radar_specs(phy);
2021 phy->dfs_state = -1;
2025 phy->dfs_state = chandef->chan->dfs_state;
2027 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
2028 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
2029 return mt7615_dfs_start_radar_detector(phy);
2031 return mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy,
2036 err = mt7615_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy, MT_RX_SEL0, 0);
2040 mt7615_dfs_stop_radar_detector(phy);