drivers/net/wireless/mediatek/mt76/dma.c

   1 // SPDX-License-Identifier: ISC
   2 /*
   3  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
   4  */
   5
   6 #include <linux/dma-mapping.h>
   7 #include "mt76.h"
   8 #include "dma.h"
   9
  10 #if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED)
  11
  12 #define Q_READ(_dev, _q, _field) ({                                     \
  13         u32 _offset = offsetof(struct mt76_queue_regs, _field);         \
  14         u32 _val;                                                       \
  15         if ((_q)->flags & MT_QFLAG_WED)                                 \
  16                 _val = mtk_wed_device_reg_read(&(_dev)->mmio.wed,       \
  17                                                ((_q)->wed_regs +        \
  18                                                 _offset));              \
  19         else                                                            \
  20                 _val = readl(&(_q)->regs->_field);                      \
  21         _val;                                                           \
  22 })
  23
  24 #define Q_WRITE(_dev, _q, _field, _val) do {                            \
  25         u32 _offset = offsetof(struct mt76_queue_regs, _field);         \
  26         if ((_q)->flags & MT_QFLAG_WED)                                 \
  27                 mtk_wed_device_reg_write(&(_dev)->mmio.wed,             \
  28                                          ((_q)->wed_regs + _offset),    \
  29                                          _val);                         \
  30         else                                                            \
  31                 writel(_val, &(_q)->regs->_field);                      \
  32 } while (0)
  33
  34 #else
  35
  36 #define Q_READ(_dev, _q, _field)        readl(&(_q)->regs->_field)
  37 #define Q_WRITE(_dev, _q, _field, _val) writel(_val, &(_q)->regs->_field)
  38
  39 #endif
  40
  41 static struct mt76_txwi_cache *
  42 mt76_alloc_txwi(struct mt76_dev *dev)
  43 {
  44         struct mt76_txwi_cache *t;
  45         dma_addr_t addr;
  46         u8 *txwi;
  47         int size;
  48
  49         size = L1_CACHE_ALIGN(dev->drv->txwi_size + sizeof(*t));
  50         txwi = kzalloc(size, GFP_ATOMIC);
  51         if (!txwi)
  52                 return NULL;
  53
  54         addr = dma_map_single(dev->dma_dev, txwi, dev->drv->txwi_size,
  55                               DMA_TO_DEVICE);
  56         t = (struct mt76_txwi_cache *)(txwi + dev->drv->txwi_size);
  57         t->dma_addr = addr;
  58
  59         return t;
  60 }
  61
  62 static struct mt76_txwi_cache *
  63 mt76_alloc_rxwi(struct mt76_dev *dev)
  64 {
  65         struct mt76_txwi_cache *t;
  66
  67         t = kzalloc(L1_CACHE_ALIGN(sizeof(*t)), GFP_ATOMIC);
  68         if (!t)
  69                 return NULL;
  70
  71         t->ptr = NULL;
  72         return t;
  73 }
  74
  75 static struct mt76_txwi_cache *
  76 __mt76_get_txwi(struct mt76_dev *dev)
  77 {
  78         struct mt76_txwi_cache *t = NULL;
  79
  80         spin_lock(&dev->lock);
  81         if (!list_empty(&dev->txwi_cache)) {
  82                 t = list_first_entry(&dev->txwi_cache, struct mt76_txwi_cache,
  83                                      list);
  84                 list_del(&t->list);
  85         }
  86         spin_unlock(&dev->lock);
  87
  88         return t;
  89 }
  90
  91 static struct mt76_txwi_cache *
  92 __mt76_get_rxwi(struct mt76_dev *dev)
  93 {
  94         struct mt76_txwi_cache *t = NULL;
  95
  96         spin_lock(&dev->wed_lock);
  97         if (!list_empty(&dev->rxwi_cache)) {
  98                 t = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache,
  99                                      list);
 100                 list_del(&t->list);
 101         }
 102         spin_unlock(&dev->wed_lock);
 103
 104         return t;
 105 }
 106
 107 static struct mt76_txwi_cache *
 108 mt76_get_txwi(struct mt76_dev *dev)
 109 {
 110         struct mt76_txwi_cache *t = __mt76_get_txwi(dev);
 111
 112         if (t)
 113                 return t;
 114
 115         return mt76_alloc_txwi(dev);
 116 }
 117
 118 struct mt76_txwi_cache *
 119 mt76_get_rxwi(struct mt76_dev *dev)
 120 {
 121         struct mt76_txwi_cache *t = __mt76_get_rxwi(dev);
 122
 123         if (t)
 124                 return t;
 125
 126         return mt76_alloc_rxwi(dev);
 127 }
 128 EXPORT_SYMBOL_GPL(mt76_get_rxwi);
 129
 130 void
 131 mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
 132 {
 133         if (!t)
 134                 return;
 135
 136         spin_lock(&dev->lock);
 137         list_add(&t->list, &dev->txwi_cache);
 138         spin_unlock(&dev->lock);
 139 }
 140 EXPORT_SYMBOL_GPL(mt76_put_txwi);
 141
 142 void
 143 mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
 144 {
 145         if (!t)
 146                 return;
 147
 148         spin_lock(&dev->wed_lock);
 149         list_add(&t->list, &dev->rxwi_cache);
 150         spin_unlock(&dev->wed_lock);
 151 }
 152 EXPORT_SYMBOL_GPL(mt76_put_rxwi);
 153
 154 static void
 155 mt76_free_pending_txwi(struct mt76_dev *dev)
 156 {
 157         struct mt76_txwi_cache *t;
 158
 159         local_bh_disable();
 160         while ((t = __mt76_get_txwi(dev)) != NULL) {
 161                 dma_unmap_single(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
 162                                  DMA_TO_DEVICE);
 163                 kfree(mt76_get_txwi_ptr(dev, t));
 164         }
 165         local_bh_enable();
 166 }
 167
 168 static void
 169 mt76_free_pending_rxwi(struct mt76_dev *dev)
 170 {
 171         struct mt76_txwi_cache *t;
 172
 173         local_bh_disable();
 174         while ((t = __mt76_get_rxwi(dev)) != NULL) {
 175                 if (t->ptr)
 176                         skb_free_frag(t->ptr);
 177                 kfree(t);
 178         }
 179         local_bh_enable();
 180 }
 181
 182 static void
 183 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
 184 {
 185         Q_WRITE(dev, q, desc_base, q->desc_dma);
 186         Q_WRITE(dev, q, ring_size, q->ndesc);
 187         q->head = Q_READ(dev, q, dma_idx);
 188         q->tail = q->head;
 189 }
 190
 191 static void
 192 mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
 193 {
 194         int i;
 195
 196         if (!q || !q->ndesc)
 197                 return;
 198
 199         /* clear descriptors */
 200         for (i = 0; i < q->ndesc; i++)
 201                 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
 202
 203         Q_WRITE(dev, q, cpu_idx, 0);
 204         Q_WRITE(dev, q, dma_idx, 0);
 205         mt76_dma_sync_idx(dev, q);
 206 }
 207
 208 static int
 209 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
 210                  struct mt76_queue_buf *buf, int nbufs, u32 info,
 211                  struct sk_buff *skb, void *txwi)
 212 {
 213         struct mt76_queue_entry *entry;
 214         struct mt76_desc *desc;
 215         int i, idx = -1;
 216         u32 ctrl, next;
 217
 218         for (i = 0; i < nbufs; i += 2, buf += 2) {
 219                 u32 buf0 = buf[0].addr, buf1 = 0;
 220
 221                 idx = q->head;
 222                 next = (q->head + 1) % q->ndesc;
 223
 224                 desc = &q->desc[idx];
 225                 entry = &q->entry[idx];
 226
 227                 if ((q->flags & MT_QFLAG_WED) &&
 228                     FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX) {
 229                         struct mt76_txwi_cache *t = txwi;
 230                         int rx_token;
 231
 232                         if (!t)
 233                                 return -ENOMEM;
 234
 235                         rx_token = mt76_rx_token_consume(dev, (void *)skb, t,
 236                                                          buf[0].addr);
 237                         buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token);
 238                         ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len) |
 239                                MT_DMA_CTL_TO_HOST;
 240                 } else {
 241                         if (txwi) {
 242                                 q->entry[next].txwi = DMA_DUMMY_DATA;
 243                                 q->entry[next].skip_buf0 = true;
 244                         }
 245
 246                         if (buf[0].skip_unmap)
 247                                 entry->skip_buf0 = true;
 248                         entry->skip_buf1 = i == nbufs - 1;
 249
 250                         entry->dma_addr[0] = buf[0].addr;
 251                         entry->dma_len[0] = buf[0].len;
 252
 253                         ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
 254                         if (i < nbufs - 1) {
 255                                 entry->dma_addr[1] = buf[1].addr;
 256                                 entry->dma_len[1] = buf[1].len;
 257                                 buf1 = buf[1].addr;
 258                                 ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
 259                                 if (buf[1].skip_unmap)
 260                                         entry->skip_buf1 = true;
 261                         }
 262
 263                         if (i == nbufs - 1)
 264                                 ctrl |= MT_DMA_CTL_LAST_SEC0;
 265                         else if (i == nbufs - 2)
 266                                 ctrl |= MT_DMA_CTL_LAST_SEC1;
 267                 }
 268
 269                 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
 270                 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
 271                 WRITE_ONCE(desc->info, cpu_to_le32(info));
 272                 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl));
 273
 274                 q->head = next;
 275                 q->queued++;
 276         }
 277
 278         q->entry[idx].txwi = txwi;
 279         q->entry[idx].skb = skb;
 280         q->entry[idx].wcid = 0xffff;
 281
 282         return idx;
 283 }
 284
 285 static void
 286 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,
 287                         struct mt76_queue_entry *prev_e)
 288 {
 289         struct mt76_queue_entry *e = &q->entry[idx];
 290
 291         if (!e->skip_buf0)
 292                 dma_unmap_single(dev->dma_dev, e->dma_addr[0], e->dma_len[0],
 293                                  DMA_TO_DEVICE);
 294
 295         if (!e->skip_buf1)
 296                 dma_unmap_single(dev->dma_dev, e->dma_addr[1], e->dma_len[1],
 297                                  DMA_TO_DEVICE);
 298
 299         if (e->txwi == DMA_DUMMY_DATA)
 300                 e->txwi = NULL;
 301
 302         if (e->skb == DMA_DUMMY_DATA)
 303                 e->skb = NULL;
 304
 305         *prev_e = *e;
 306         memset(e, 0, sizeof(*e));
 307 }
 308
 309 static void
 310 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q)
 311 {
 312         wmb();
 313         Q_WRITE(dev, q, cpu_idx, q->head);
 314 }
 315
 316 static void
 317 mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
 318 {
 319         struct mt76_queue_entry entry;
 320         int last;
 321
 322         if (!q || !q->ndesc)
 323                 return;
 324
 325         spin_lock_bh(&q->cleanup_lock);
 326         if (flush)
 327                 last = -1;
 328         else
 329                 last = Q_READ(dev, q, dma_idx);
 330
 331         while (q->queued > 0 && q->tail != last) {
 332                 mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry);
 333                 mt76_queue_tx_complete(dev, q, &entry);
 334
 335                 if (entry.txwi) {
 336                         if (!(dev->drv->drv_flags & MT_DRV_TXWI_NO_FREE))
 337                                 mt76_put_txwi(dev, entry.txwi);
 338                 }
 339
 340                 if (!flush && q->tail == last)
 341                         last = Q_READ(dev, q, dma_idx);
 342         }
 343         spin_unlock_bh(&q->cleanup_lock);
 344
 345         if (flush) {
 346                 spin_lock_bh(&q->lock);
 347                 mt76_dma_sync_idx(dev, q);
 348                 mt76_dma_kick_queue(dev, q);
 349                 spin_unlock_bh(&q->lock);
 350         }
 351
 352         if (!q->queued)
 353                 wake_up(&dev->tx_wait);
 354 }
 355
 356 static void *
 357 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
 358                  int *len, u32 *info, bool *more, bool *drop)
 359 {
 360         struct mt76_queue_entry *e = &q->entry[idx];
 361         struct mt76_desc *desc = &q->desc[idx];
 362         void *buf;
 363
 364         if (len) {
 365                 u32 ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
 366                 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl);
 367                 *more = !(ctrl & MT_DMA_CTL_LAST_SEC0);
 368         }
 369
 370         if (info)
 371                 *info = le32_to_cpu(desc->info);
 372
 373         if ((q->flags & MT_QFLAG_WED) &&
 374             FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX) {
 375                 u32 token = FIELD_GET(MT_DMA_CTL_TOKEN,
 376                                       le32_to_cpu(desc->buf1));
 377                 struct mt76_txwi_cache *t = mt76_rx_token_release(dev, token);
 378
 379                 if (!t)
 380                         return NULL;
 381
 382                 dma_unmap_single(dev->dma_dev, t->dma_addr,
 383                                  SKB_WITH_OVERHEAD(q->buf_size),
 384                                  DMA_FROM_DEVICE);
 385
 386                 buf = t->ptr;
 387                 t->dma_addr = 0;
 388                 t->ptr = NULL;
 389
 390                 mt76_put_rxwi(dev, t);
 391
 392                 if (drop) {
 393                         u32 ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
 394
 395                         *drop = !!(ctrl & (MT_DMA_CTL_TO_HOST_A |
 396                                            MT_DMA_CTL_DROP));
 397                 }
 398         } else {
 399                 buf = e->buf;
 400                 e->buf = NULL;
 401                 dma_unmap_single(dev->dma_dev, e->dma_addr[0],
 402                                  SKB_WITH_OVERHEAD(q->buf_size),
 403                                  DMA_FROM_DEVICE);
 404         }
 405
 406         return buf;
 407 }
 408
 409 static void *
 410 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
 411                  int *len, u32 *info, bool *more, bool *drop)
 412 {
 413         int idx = q->tail;
 414
 415         *more = false;
 416         if (!q->queued)
 417                 return NULL;
 418
 419         if (flush)
 420                 q->desc[idx].ctrl |= cpu_to_le32(MT_DMA_CTL_DMA_DONE);
 421         else if (!(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE)))
 422                 return NULL;
 423
 424         q->tail = (q->tail + 1) % q->ndesc;
 425         q->queued--;
 426
 427         return mt76_dma_get_buf(dev, q, idx, len, info, more, drop);
 428 }
 429
 430 static int
 431 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
 432                           struct sk_buff *skb, u32 tx_info)
 433 {
 434         struct mt76_queue_buf buf = {};
 435         dma_addr_t addr;
 436
 437         if (q->queued + 1 >= q->ndesc - 1)
 438                 goto error;
 439
 440         addr = dma_map_single(dev->dma_dev, skb->data, skb->len,
 441                               DMA_TO_DEVICE);
 442         if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
 443                 goto error;
 444
 445         buf.addr = addr;
 446         buf.len = skb->len;
 447
 448         spin_lock_bh(&q->lock);
 449         mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
 450         mt76_dma_kick_queue(dev, q);
 451         spin_unlock_bh(&q->lock);
 452
 453         return 0;
 454
 455 error:
 456         dev_kfree_skb(skb);
 457         return -ENOMEM;
 458 }
 459
 460 static int
 461 mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
 462                       enum mt76_txq_id qid, struct sk_buff *skb,
 463                       struct mt76_wcid *wcid, struct ieee80211_sta *sta)
 464 {
 465         struct ieee80211_tx_status status = {
 466                 .sta = sta,
 467         };
 468         struct mt76_tx_info tx_info = {
 469                 .skb = skb,
 470         };
 471         struct ieee80211_hw *hw;
 472         int len, n = 0, ret = -ENOMEM;
 473         struct mt76_txwi_cache *t;
 474         struct sk_buff *iter;
 475         dma_addr_t addr;
 476         u8 *txwi;
 477
 478         t = mt76_get_txwi(dev);
 479         if (!t)
 480                 goto free_skb;
 481
 482         txwi = mt76_get_txwi_ptr(dev, t);
 483
 484         skb->prev = skb->next = NULL;
 485         if (dev->drv->drv_flags & MT_DRV_TX_ALIGNED4_SKBS)
 486                 mt76_insert_hdr_pad(skb);
 487
 488         len = skb_headlen(skb);
 489         addr = dma_map_single(dev->dma_dev, skb->data, len, DMA_TO_DEVICE);
 490         if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
 491                 goto free;
 492
 493         tx_info.buf[n].addr = t->dma_addr;
 494         tx_info.buf[n++].len = dev->drv->txwi_size;
 495         tx_info.buf[n].addr = addr;
 496         tx_info.buf[n++].len = len;
 497
 498         skb_walk_frags(skb, iter) {
 499                 if (n == ARRAY_SIZE(tx_info.buf))
 500                         goto unmap;
 501
 502                 addr = dma_map_single(dev->dma_dev, iter->data, iter->len,
 503                                       DMA_TO_DEVICE);
 504                 if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
 505                         goto unmap;
 506
 507                 tx_info.buf[n].addr = addr;
 508                 tx_info.buf[n++].len = iter->len;
 509         }
 510         tx_info.nbuf = n;
 511
 512         if (q->queued + (tx_info.nbuf + 1) / 2 >= q->ndesc - 1) {
 513                 ret = -ENOMEM;
 514                 goto unmap;
 515         }
 516
 517         dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
 518                                 DMA_TO_DEVICE);
 519         ret = dev->drv->tx_prepare_skb(dev, txwi, qid, wcid, sta, &tx_info);
 520         dma_sync_single_for_device(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
 521                                    DMA_TO_DEVICE);
 522         if (ret < 0)
 523                 goto unmap;
 524
 525         return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
 526                                 tx_info.info, tx_info.skb, t);
 527
 528 unmap:
 529         for (n--; n > 0; n--)
 530                 dma_unmap_single(dev->dma_dev, tx_info.buf[n].addr,
 531                                  tx_info.buf[n].len, DMA_TO_DEVICE);
 532
 533 free:
 534 #ifdef CONFIG_NL80211_TESTMODE
 535         /* fix tx_done accounting on queue overflow */
 536         if (mt76_is_testmode_skb(dev, skb, &hw)) {
 537                 struct mt76_phy *phy = hw->priv;
 538
 539                 if (tx_info.skb == phy->test.tx_skb)
 540                         phy->test.tx_done--;
 541         }
 542 #endif
 543
 544         mt76_put_txwi(dev, t);
 545
 546 free_skb:
 547         status.skb = tx_info.skb;
 548         hw = mt76_tx_status_get_hw(dev, tx_info.skb);
 549         ieee80211_tx_status_ext(hw, &status);
 550
 551         return ret;
 552 }
 553
 554 static struct page_frag_cache *
 555 mt76_dma_rx_get_frag_cache(struct mt76_dev *dev, struct mt76_queue *q)
 556 {
 557         struct page_frag_cache *rx_page = &q->rx_page;
 558
 559 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
 560         if ((q->flags & MT_QFLAG_WED) &&
 561             FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX)
 562                 rx_page = &dev->mmio.wed.rx_buf_ring.rx_page;
 563 #endif
 564         return rx_page;
 565 }
 566
 567 static int
 568 mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
 569 {
 570         struct page_frag_cache *rx_page = mt76_dma_rx_get_frag_cache(dev, q);
 571         int len = SKB_WITH_OVERHEAD(q->buf_size);
 572         int frames = 0, offset = q->buf_offset;
 573         dma_addr_t addr;
 574
 575         if (!q->ndesc)
 576                 return 0;
 577
 578         spin_lock_bh(&q->lock);
 579
 580         while (q->queued < q->ndesc - 1) {
 581                 struct mt76_txwi_cache *t = NULL;
 582                 struct mt76_queue_buf qbuf;
 583                 void *buf = NULL;
 584
 585                 if ((q->flags & MT_QFLAG_WED) &&
 586                     FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX) {
 587                         t = mt76_get_rxwi(dev);
 588                         if (!t)
 589                                 break;
 590                 }
 591
 592                 buf = page_frag_alloc(rx_page, q->buf_size, GFP_ATOMIC);
 593                 if (!buf)
 594                         break;
 595
 596                 addr = dma_map_single(dev->dma_dev, buf, len, DMA_FROM_DEVICE);
 597                 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) {
 598                         skb_free_frag(buf);
 599                         break;
 600                 }
 601
 602                 qbuf.addr = addr + offset;
 603                 qbuf.len = len - offset;
 604                 qbuf.skip_unmap = false;
 605                 mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, t);
 606                 frames++;
 607         }
 608
 609         if (frames)
 610                 mt76_dma_kick_queue(dev, q);
 611
 612         spin_unlock_bh(&q->lock);
 613
 614         return frames;
 615 }
 616
 617 static int
 618 mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
 619 {
 620 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
 621         struct mtk_wed_device *wed = &dev->mmio.wed;
 622         int ret, type, ring;
 623         u8 flags = q->flags;
 624
 625         if (!mtk_wed_device_active(wed))
 626                 q->flags &= ~MT_QFLAG_WED;
 627
 628         if (!(q->flags & MT_QFLAG_WED))
 629                 return 0;
 630
 631         type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
 632         ring = FIELD_GET(MT_QFLAG_WED_RING, q->flags);
 633
 634         switch (type) {
 635         case MT76_WED_Q_TX:
 636                 ret = mtk_wed_device_tx_ring_setup(wed, ring, q->regs, false);
 637                 if (!ret)
 638                         q->wed_regs = wed->tx_ring[ring].reg_base;
 639                 break;
 640         case MT76_WED_Q_TXFREE:
 641                 /* WED txfree queue needs ring to be initialized before setup */
 642                 q->flags = 0;
 643                 mt76_dma_queue_reset(dev, q);
 644                 mt76_dma_rx_fill(dev, q);
 645                 q->flags = flags;
 646
 647                 ret = mtk_wed_device_txfree_ring_setup(wed, q->regs);
 648                 if (!ret)
 649                         q->wed_regs = wed->txfree_ring.reg_base;
 650                 break;
 651         case MT76_WED_Q_RX:
 652                 ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs);
 653                 if (!ret)
 654                         q->wed_regs = wed->rx_ring[ring].reg_base;
 655                 break;
 656         default:
 657                 ret = -EINVAL;
 658         }
 659
 660         return ret;
 661 #else
 662         return 0;
 663 #endif
 664 }
 665
 666 static int
 667 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
 668                      int idx, int n_desc, int bufsize,
 669                      u32 ring_base)
 670 {
 671         int ret, size;
 672
 673         spin_lock_init(&q->lock);
 674         spin_lock_init(&q->cleanup_lock);
 675
 676         q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE;
 677         q->ndesc = n_desc;
 678         q->buf_size = bufsize;
 679         q->hw_idx = idx;
 680
 681         size = q->ndesc * sizeof(struct mt76_desc);
 682         q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
 683         if (!q->desc)
 684                 return -ENOMEM;
 685
 686         size = q->ndesc * sizeof(*q->entry);
 687         q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL);
 688         if (!q->entry)
 689                 return -ENOMEM;
 690
 691         ret = mt76_dma_wed_setup(dev, q);
 692         if (ret)
 693                 return ret;
 694
 695         if (q->flags != MT_WED_Q_TXFREE)
 696                 mt76_dma_queue_reset(dev, q);
 697
 698         return 0;
 699 }
 700
 701 static void
 702 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
 703 {
 704         struct page *page;
 705         void *buf;
 706         bool more;
 707
 708         if (!q->ndesc)
 709                 return;
 710
 711         spin_lock_bh(&q->lock);
 712         do {
 713                 buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL);
 714                 if (!buf)
 715                         break;
 716
 717                 skb_free_frag(buf);
 718         } while (1);
 719         spin_unlock_bh(&q->lock);
 720
 721         if (!q->rx_page.va)
 722                 return;
 723
 724         page = virt_to_page(q->rx_page.va);
 725         __page_frag_cache_drain(page, q->rx_page.pagecnt_bias);
 726         memset(&q->rx_page, 0, sizeof(q->rx_page));
 727 }
 728
 729 static void
 730 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
 731 {
 732         struct mt76_queue *q = &dev->q_rx[qid];
 733         int i;
 734
 735         if (!q->ndesc)
 736                 return;
 737
 738         for (i = 0; i < q->ndesc; i++)
 739                 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
 740
 741         mt76_dma_rx_cleanup(dev, q);
 742         mt76_dma_sync_idx(dev, q);
 743         mt76_dma_rx_fill(dev, q);
 744
 745         if (!q->rx_head)
 746                 return;
 747
 748         dev_kfree_skb(q->rx_head);
 749         q->rx_head = NULL;
 750 }
 751
 752 static void
 753 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
 754                   int len, bool more, u32 info)
 755 {
 756         struct sk_buff *skb = q->rx_head;
 757         struct skb_shared_info *shinfo = skb_shinfo(skb);
 758         int nr_frags = shinfo->nr_frags;
 759
 760         if (nr_frags < ARRAY_SIZE(shinfo->frags)) {
 761                 struct page *page = virt_to_head_page(data);
 762                 int offset = data - page_address(page) + q->buf_offset;
 763
 764                 skb_add_rx_frag(skb, nr_frags, page, offset, len, q->buf_size);
 765         } else {
 766                 skb_free_frag(data);
 767         }
 768
 769         if (more)
 770                 return;
 771
 772         q->rx_head = NULL;
 773         if (nr_frags < ARRAY_SIZE(shinfo->frags))
 774                 dev->drv->rx_skb(dev, q - dev->q_rx, skb, &info);
 775         else
 776                 dev_kfree_skb(skb);
 777 }
 778
 779 static int
 780 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
 781 {
 782         int len, data_len, done = 0, dma_idx;
 783         struct sk_buff *skb;
 784         unsigned char *data;
 785         bool check_ddone = false;
 786         bool more;
 787
 788         if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) &&
 789             q->flags == MT_WED_Q_TXFREE) {
 790                 dma_idx = Q_READ(dev, q, dma_idx);
 791                 check_ddone = true;
 792         }
 793
 794         while (done < budget) {
 795                 bool drop = false;
 796                 u32 info;
 797
 798                 if (check_ddone) {
 799                         if (q->tail == dma_idx)
 800                                 dma_idx = Q_READ(dev, q, dma_idx);
 801
 802                         if (q->tail == dma_idx)
 803                                 break;
 804                 }
 805
 806                 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more,
 807                                         &drop);
 808                 if (!data)
 809                         break;
 810
 811                 if (drop)
 812                         goto free_frag;
 813
 814                 if (q->rx_head)
 815                         data_len = q->buf_size;
 816                 else
 817                         data_len = SKB_WITH_OVERHEAD(q->buf_size);
 818
 819                 if (data_len < len + q->buf_offset) {
 820                         dev_kfree_skb(q->rx_head);
 821                         q->rx_head = NULL;
 822                         goto free_frag;
 823                 }
 824
 825                 if (q->rx_head) {
 826                         mt76_add_fragment(dev, q, data, len, more, info);
 827                         continue;
 828                 }
 829
 830                 if (!more && dev->drv->rx_check &&
 831                     !(dev->drv->rx_check(dev, data, len)))
 832                         goto free_frag;
 833
 834                 skb = build_skb(data, q->buf_size);
 835                 if (!skb)
 836                         goto free_frag;
 837
 838                 skb_reserve(skb, q->buf_offset);
 839
 840                 *(u32 *)skb->cb = info;
 841
 842                 __skb_put(skb, len);
 843                 done++;
 844
 845                 if (more) {
 846                         q->rx_head = skb;
 847                         continue;
 848                 }
 849
 850                 dev->drv->rx_skb(dev, q - dev->q_rx, skb, &info);
 851                 continue;
 852
 853 free_frag:
 854                 skb_free_frag(data);
 855         }
 856
 857         mt76_dma_rx_fill(dev, q);
 858         return done;
 859 }
 860
 861 int mt76_dma_rx_poll(struct napi_struct *napi, int budget)
 862 {
 863         struct mt76_dev *dev;
 864         int qid, done = 0, cur;
 865
 866         dev = container_of(napi->dev, struct mt76_dev, napi_dev);
 867         qid = napi - dev->napi;
 868
 869         rcu_read_lock();
 870
 871         do {
 872                 cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done);
 873                 mt76_rx_poll_complete(dev, qid, napi);
 874                 done += cur;
 875         } while (cur && done < budget);
 876
 877         rcu_read_unlock();
 878
 879         if (done < budget && napi_complete(napi))
 880                 dev->drv->rx_poll_complete(dev, qid);
 881
 882         return done;
 883 }
 884 EXPORT_SYMBOL_GPL(mt76_dma_rx_poll);
 885
 886 static int
 887 mt76_dma_init(struct mt76_dev *dev,
 888               int (*poll)(struct napi_struct *napi, int budget))
 889 {
 890         int i;
 891
 892         init_dummy_netdev(&dev->napi_dev);
 893         init_dummy_netdev(&dev->tx_napi_dev);
 894         snprintf(dev->napi_dev.name, sizeof(dev->napi_dev.name), "%s",
 895                  wiphy_name(dev->hw->wiphy));
 896         dev->napi_dev.threaded = 1;
 897
 898         mt76_for_each_q_rx(dev, i) {
 899                 netif_napi_add(&dev->napi_dev, &dev->napi[i], poll);
 900                 mt76_dma_rx_fill(dev, &dev->q_rx[i]);
 901                 napi_enable(&dev->napi[i]);
 902         }
 903
 904         return 0;
 905 }
 906
 907 static const struct mt76_queue_ops mt76_dma_ops = {
 908         .init = mt76_dma_init,
 909         .alloc = mt76_dma_alloc_queue,
 910         .reset_q = mt76_dma_queue_reset,
 911         .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw,
 912         .tx_queue_skb = mt76_dma_tx_queue_skb,
 913         .tx_cleanup = mt76_dma_tx_cleanup,
 914         .rx_cleanup = mt76_dma_rx_cleanup,
 915         .rx_reset = mt76_dma_rx_reset,
 916         .kick = mt76_dma_kick_queue,
 917 };
 918
 919 void mt76_dma_attach(struct mt76_dev *dev)
 920 {
 921         dev->queue_ops = &mt76_dma_ops;
 922 }
 923 EXPORT_SYMBOL_GPL(mt76_dma_attach);
 924
 925 void mt76_dma_cleanup(struct mt76_dev *dev)
 926 {
 927         int i;
 928
 929         mt76_worker_disable(&dev->tx_worker);
 930         netif_napi_del(&dev->tx_napi);
 931
 932         for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {
 933                 struct mt76_phy *phy = dev->phys[i];
 934                 int j;
 935
 936                 if (!phy)
 937                         continue;
 938
 939                 for (j = 0; j < ARRAY_SIZE(phy->q_tx); j++)
 940                         mt76_dma_tx_cleanup(dev, phy->q_tx[j], true);
 941         }
 942
 943         for (i = 0; i < ARRAY_SIZE(dev->q_mcu); i++)
 944                 mt76_dma_tx_cleanup(dev, dev->q_mcu[i], true);
 945
 946         mt76_for_each_q_rx(dev, i) {
 947                 struct mt76_queue *q = &dev->q_rx[i];
 948
 949                 netif_napi_del(&dev->napi[i]);
 950                 if (FIELD_GET(MT_QFLAG_WED_TYPE, q->flags))
 951                         mt76_dma_rx_cleanup(dev, q);
 952         }
 953
 954         mt76_free_pending_txwi(dev);
 955         mt76_free_pending_rxwi(dev);
 956
 957         if (mtk_wed_device_active(&dev->mmio.wed))
 958                 mtk_wed_device_detach(&dev->mmio.wed);
 959 }
 960 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);