1 // SPDX-License-Identifier: ISC
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
6 #include <linux/dma-mapping.h>
10 #if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED)
12 #define Q_READ(_dev, _q, _field) ({ \
13 u32 _offset = offsetof(struct mt76_queue_regs, _field); \
15 if ((_q)->flags & MT_QFLAG_WED) \
16 _val = mtk_wed_device_reg_read(&(_dev)->mmio.wed, \
20 _val = readl(&(_q)->regs->_field); \
24 #define Q_WRITE(_dev, _q, _field, _val) do { \
25 u32 _offset = offsetof(struct mt76_queue_regs, _field); \
26 if ((_q)->flags & MT_QFLAG_WED) \
27 mtk_wed_device_reg_write(&(_dev)->mmio.wed, \
28 ((_q)->wed_regs + _offset), \
31 writel(_val, &(_q)->regs->_field); \
36 #define Q_READ(_dev, _q, _field) readl(&(_q)->regs->_field)
37 #define Q_WRITE(_dev, _q, _field, _val) writel(_val, &(_q)->regs->_field)
41 static struct mt76_txwi_cache *
42 mt76_alloc_txwi(struct mt76_dev *dev)
44 struct mt76_txwi_cache *t;
49 size = L1_CACHE_ALIGN(dev->drv->txwi_size + sizeof(*t));
50 txwi = kzalloc(size, GFP_ATOMIC);
54 addr = dma_map_single(dev->dma_dev, txwi, dev->drv->txwi_size,
56 t = (struct mt76_txwi_cache *)(txwi + dev->drv->txwi_size);
62 static struct mt76_txwi_cache *
63 __mt76_get_txwi(struct mt76_dev *dev)
65 struct mt76_txwi_cache *t = NULL;
67 spin_lock(&dev->lock);
68 if (!list_empty(&dev->txwi_cache)) {
69 t = list_first_entry(&dev->txwi_cache, struct mt76_txwi_cache,
73 spin_unlock(&dev->lock);
78 static struct mt76_txwi_cache *
79 mt76_get_txwi(struct mt76_dev *dev)
81 struct mt76_txwi_cache *t = __mt76_get_txwi(dev);
86 return mt76_alloc_txwi(dev);
90 mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
95 spin_lock(&dev->lock);
96 list_add(&t->list, &dev->txwi_cache);
97 spin_unlock(&dev->lock);
99 EXPORT_SYMBOL_GPL(mt76_put_txwi);
102 mt76_free_pending_txwi(struct mt76_dev *dev)
104 struct mt76_txwi_cache *t;
107 while ((t = __mt76_get_txwi(dev)) != NULL) {
108 dma_unmap_single(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
110 kfree(mt76_get_txwi_ptr(dev, t));
116 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
118 Q_WRITE(dev, q, desc_base, q->desc_dma);
119 Q_WRITE(dev, q, ring_size, q->ndesc);
120 q->head = Q_READ(dev, q, dma_idx);
125 mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
132 /* clear descriptors */
133 for (i = 0; i < q->ndesc; i++)
134 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
136 Q_WRITE(dev, q, cpu_idx, 0);
137 Q_WRITE(dev, q, dma_idx, 0);
138 mt76_dma_sync_idx(dev, q);
142 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
143 struct mt76_queue_buf *buf, int nbufs, u32 info,
144 struct sk_buff *skb, void *txwi)
146 struct mt76_queue_entry *entry;
147 struct mt76_desc *desc;
152 q->entry[q->head].txwi = DMA_DUMMY_DATA;
153 q->entry[q->head].skip_buf0 = true;
156 for (i = 0; i < nbufs; i += 2, buf += 2) {
157 u32 buf0 = buf[0].addr, buf1 = 0;
160 q->head = (q->head + 1) % q->ndesc;
162 desc = &q->desc[idx];
163 entry = &q->entry[idx];
165 if (buf[0].skip_unmap)
166 entry->skip_buf0 = true;
167 entry->skip_buf1 = i == nbufs - 1;
169 entry->dma_addr[0] = buf[0].addr;
170 entry->dma_len[0] = buf[0].len;
172 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
174 entry->dma_addr[1] = buf[1].addr;
175 entry->dma_len[1] = buf[1].len;
177 ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
178 if (buf[1].skip_unmap)
179 entry->skip_buf1 = true;
183 ctrl |= MT_DMA_CTL_LAST_SEC0;
184 else if (i == nbufs - 2)
185 ctrl |= MT_DMA_CTL_LAST_SEC1;
187 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
188 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
189 WRITE_ONCE(desc->info, cpu_to_le32(info));
190 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl));
195 q->entry[idx].txwi = txwi;
196 q->entry[idx].skb = skb;
197 q->entry[idx].wcid = 0xffff;
203 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,
204 struct mt76_queue_entry *prev_e)
206 struct mt76_queue_entry *e = &q->entry[idx];
209 dma_unmap_single(dev->dma_dev, e->dma_addr[0], e->dma_len[0],
213 dma_unmap_single(dev->dma_dev, e->dma_addr[1], e->dma_len[1],
216 if (e->txwi == DMA_DUMMY_DATA)
219 if (e->skb == DMA_DUMMY_DATA)
223 memset(e, 0, sizeof(*e));
227 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q)
230 Q_WRITE(dev, q, cpu_idx, q->head);
234 mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
236 struct mt76_queue_entry entry;
242 spin_lock_bh(&q->cleanup_lock);
246 last = Q_READ(dev, q, dma_idx);
248 while (q->queued > 0 && q->tail != last) {
249 mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry);
250 mt76_queue_tx_complete(dev, q, &entry);
253 if (!(dev->drv->drv_flags & MT_DRV_TXWI_NO_FREE))
254 mt76_put_txwi(dev, entry.txwi);
257 if (!flush && q->tail == last)
258 last = Q_READ(dev, q, dma_idx);
260 spin_unlock_bh(&q->cleanup_lock);
263 spin_lock_bh(&q->lock);
264 mt76_dma_sync_idx(dev, q);
265 mt76_dma_kick_queue(dev, q);
266 spin_unlock_bh(&q->lock);
270 wake_up(&dev->tx_wait);
274 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
275 int *len, u32 *info, bool *more)
277 struct mt76_queue_entry *e = &q->entry[idx];
278 struct mt76_desc *desc = &q->desc[idx];
281 int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
283 buf_addr = e->dma_addr[0];
285 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl));
286 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
287 *more = !(ctl & MT_DMA_CTL_LAST_SEC0);
291 *info = le32_to_cpu(desc->info);
293 dma_unmap_single(dev->dma_dev, buf_addr, buf_len, DMA_FROM_DEVICE);
300 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
301 int *len, u32 *info, bool *more)
310 q->desc[idx].ctrl |= cpu_to_le32(MT_DMA_CTL_DMA_DONE);
311 else if (!(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE)))
314 q->tail = (q->tail + 1) % q->ndesc;
317 return mt76_dma_get_buf(dev, q, idx, len, info, more);
321 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
322 struct sk_buff *skb, u32 tx_info)
324 struct mt76_queue_buf buf = {};
327 if (q->queued + 1 >= q->ndesc - 1)
330 addr = dma_map_single(dev->dma_dev, skb->data, skb->len,
332 if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
338 spin_lock_bh(&q->lock);
339 mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
340 mt76_dma_kick_queue(dev, q);
341 spin_unlock_bh(&q->lock);
351 mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
352 enum mt76_txq_id qid, struct sk_buff *skb,
353 struct mt76_wcid *wcid, struct ieee80211_sta *sta)
355 struct ieee80211_tx_status status = {
358 struct mt76_tx_info tx_info = {
361 struct ieee80211_hw *hw;
362 int len, n = 0, ret = -ENOMEM;
363 struct mt76_txwi_cache *t;
364 struct sk_buff *iter;
368 t = mt76_get_txwi(dev);
372 txwi = mt76_get_txwi_ptr(dev, t);
374 skb->prev = skb->next = NULL;
375 if (dev->drv->drv_flags & MT_DRV_TX_ALIGNED4_SKBS)
376 mt76_insert_hdr_pad(skb);
378 len = skb_headlen(skb);
379 addr = dma_map_single(dev->dma_dev, skb->data, len, DMA_TO_DEVICE);
380 if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
383 tx_info.buf[n].addr = t->dma_addr;
384 tx_info.buf[n++].len = dev->drv->txwi_size;
385 tx_info.buf[n].addr = addr;
386 tx_info.buf[n++].len = len;
388 skb_walk_frags(skb, iter) {
389 if (n == ARRAY_SIZE(tx_info.buf))
392 addr = dma_map_single(dev->dma_dev, iter->data, iter->len,
394 if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
397 tx_info.buf[n].addr = addr;
398 tx_info.buf[n++].len = iter->len;
402 if (q->queued + (tx_info.nbuf + 1) / 2 >= q->ndesc - 1) {
407 dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
409 ret = dev->drv->tx_prepare_skb(dev, txwi, qid, wcid, sta, &tx_info);
410 dma_sync_single_for_device(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
415 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
416 tx_info.info, tx_info.skb, t);
419 for (n--; n > 0; n--)
420 dma_unmap_single(dev->dma_dev, tx_info.buf[n].addr,
421 tx_info.buf[n].len, DMA_TO_DEVICE);
424 #ifdef CONFIG_NL80211_TESTMODE
425 /* fix tx_done accounting on queue overflow */
426 if (mt76_is_testmode_skb(dev, skb, &hw)) {
427 struct mt76_phy *phy = hw->priv;
429 if (tx_info.skb == phy->test.tx_skb)
434 mt76_put_txwi(dev, t);
437 status.skb = tx_info.skb;
438 hw = mt76_tx_status_get_hw(dev, tx_info.skb);
439 ieee80211_tx_status_ext(hw, &status);
445 mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
450 int len = SKB_WITH_OVERHEAD(q->buf_size);
451 int offset = q->buf_offset;
456 spin_lock_bh(&q->lock);
458 while (q->queued < q->ndesc - 1) {
459 struct mt76_queue_buf qbuf;
461 buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
465 addr = dma_map_single(dev->dma_dev, buf, len, DMA_FROM_DEVICE);
466 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) {
471 qbuf.addr = addr + offset;
472 qbuf.len = len - offset;
473 qbuf.skip_unmap = false;
474 mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL);
479 mt76_dma_kick_queue(dev, q);
481 spin_unlock_bh(&q->lock);
487 mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
489 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
490 struct mtk_wed_device *wed = &dev->mmio.wed;
494 if (!mtk_wed_device_active(wed))
495 q->flags &= ~MT_QFLAG_WED;
497 if (!(q->flags & MT_QFLAG_WED))
500 type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
501 ring = FIELD_GET(MT_QFLAG_WED_RING, q->flags);
505 ret = mtk_wed_device_tx_ring_setup(wed, ring, q->regs);
507 q->wed_regs = wed->tx_ring[ring].reg_base;
509 case MT76_WED_Q_TXFREE:
510 /* WED txfree queue needs ring to be initialized before setup */
512 mt76_dma_queue_reset(dev, q);
513 mt76_dma_rx_fill(dev, q);
516 ret = mtk_wed_device_txfree_ring_setup(wed, q->regs);
518 q->wed_regs = wed->txfree_ring.reg_base;
531 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
532 int idx, int n_desc, int bufsize,
537 spin_lock_init(&q->lock);
538 spin_lock_init(&q->cleanup_lock);
540 q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE;
542 q->buf_size = bufsize;
545 size = q->ndesc * sizeof(struct mt76_desc);
546 q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
550 size = q->ndesc * sizeof(*q->entry);
551 q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL);
555 ret = mt76_dma_wed_setup(dev, q);
559 if (q->flags != MT_WED_Q_TXFREE)
560 mt76_dma_queue_reset(dev, q);
566 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
575 spin_lock_bh(&q->lock);
577 buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
583 spin_unlock_bh(&q->lock);
588 page = virt_to_page(q->rx_page.va);
589 __page_frag_cache_drain(page, q->rx_page.pagecnt_bias);
590 memset(&q->rx_page, 0, sizeof(q->rx_page));
594 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
596 struct mt76_queue *q = &dev->q_rx[qid];
602 for (i = 0; i < q->ndesc; i++)
603 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
605 mt76_dma_rx_cleanup(dev, q);
606 mt76_dma_sync_idx(dev, q);
607 mt76_dma_rx_fill(dev, q);
612 dev_kfree_skb(q->rx_head);
617 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
620 struct sk_buff *skb = q->rx_head;
621 struct skb_shared_info *shinfo = skb_shinfo(skb);
622 int nr_frags = shinfo->nr_frags;
624 if (nr_frags < ARRAY_SIZE(shinfo->frags)) {
625 struct page *page = virt_to_head_page(data);
626 int offset = data - page_address(page) + q->buf_offset;
628 skb_add_rx_frag(skb, nr_frags, page, offset, len, q->buf_size);
637 if (nr_frags < ARRAY_SIZE(shinfo->frags))
638 dev->drv->rx_skb(dev, q - dev->q_rx, skb);
644 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
646 int len, data_len, done = 0, dma_idx;
649 bool check_ddone = false;
652 if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) &&
653 q->flags == MT_WED_Q_TXFREE) {
654 dma_idx = Q_READ(dev, q, dma_idx);
658 while (done < budget) {
662 if (q->tail == dma_idx)
663 dma_idx = Q_READ(dev, q, dma_idx);
665 if (q->tail == dma_idx)
669 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
674 data_len = q->buf_size;
676 data_len = SKB_WITH_OVERHEAD(q->buf_size);
678 if (data_len < len + q->buf_offset) {
679 dev_kfree_skb(q->rx_head);
685 mt76_add_fragment(dev, q, data, len, more);
689 if (!more && dev->drv->rx_check &&
690 !(dev->drv->rx_check(dev, data, len)))
693 skb = build_skb(data, q->buf_size);
697 skb_reserve(skb, q->buf_offset);
699 *(u32 *)skb->cb = info;
709 dev->drv->rx_skb(dev, q - dev->q_rx, skb);
716 mt76_dma_rx_fill(dev, q);
720 int mt76_dma_rx_poll(struct napi_struct *napi, int budget)
722 struct mt76_dev *dev;
723 int qid, done = 0, cur;
725 dev = container_of(napi->dev, struct mt76_dev, napi_dev);
726 qid = napi - dev->napi;
731 cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done);
732 mt76_rx_poll_complete(dev, qid, napi);
734 } while (cur && done < budget);
738 if (done < budget && napi_complete(napi))
739 dev->drv->rx_poll_complete(dev, qid);
743 EXPORT_SYMBOL_GPL(mt76_dma_rx_poll);
746 mt76_dma_init(struct mt76_dev *dev,
747 int (*poll)(struct napi_struct *napi, int budget))
751 init_dummy_netdev(&dev->napi_dev);
752 init_dummy_netdev(&dev->tx_napi_dev);
753 snprintf(dev->napi_dev.name, sizeof(dev->napi_dev.name), "%s",
754 wiphy_name(dev->hw->wiphy));
755 dev->napi_dev.threaded = 1;
757 mt76_for_each_q_rx(dev, i) {
758 netif_napi_add(&dev->napi_dev, &dev->napi[i], poll);
759 mt76_dma_rx_fill(dev, &dev->q_rx[i]);
760 napi_enable(&dev->napi[i]);
766 static const struct mt76_queue_ops mt76_dma_ops = {
767 .init = mt76_dma_init,
768 .alloc = mt76_dma_alloc_queue,
769 .reset_q = mt76_dma_queue_reset,
770 .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw,
771 .tx_queue_skb = mt76_dma_tx_queue_skb,
772 .tx_cleanup = mt76_dma_tx_cleanup,
773 .rx_cleanup = mt76_dma_rx_cleanup,
774 .rx_reset = mt76_dma_rx_reset,
775 .kick = mt76_dma_kick_queue,
778 void mt76_dma_attach(struct mt76_dev *dev)
780 dev->queue_ops = &mt76_dma_ops;
782 EXPORT_SYMBOL_GPL(mt76_dma_attach);
784 void mt76_dma_cleanup(struct mt76_dev *dev)
788 mt76_worker_disable(&dev->tx_worker);
789 netif_napi_del(&dev->tx_napi);
791 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {
792 struct mt76_phy *phy = dev->phys[i];
798 for (j = 0; j < ARRAY_SIZE(phy->q_tx); j++)
799 mt76_dma_tx_cleanup(dev, phy->q_tx[j], true);
802 for (i = 0; i < ARRAY_SIZE(dev->q_mcu); i++)
803 mt76_dma_tx_cleanup(dev, dev->q_mcu[i], true);
805 mt76_for_each_q_rx(dev, i) {
806 netif_napi_del(&dev->napi[i]);
807 mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
810 mt76_free_pending_txwi(dev);
812 if (mtk_wed_device_active(&dev->mmio.wed))
813 mtk_wed_device_detach(&dev->mmio.wed);
815 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);