drivers/net/wireless/mediatek/mt76/dma.c

   1 // SPDX-License-Identifier: ISC
   2 /*
   3  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
   4  */
   5
   6 #include <linux/dma-mapping.h>
   7 #include "mt76.h"
   8 #include "dma.h"
   9
  10 static int
  11 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
  12                      int idx, int n_desc, int bufsize,
  13                      u32 ring_base)
  14 {
  15         int size;
  16         int i;
  17
  18         spin_lock_init(&q->lock);
  19
  20         q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE;
  21         q->ndesc = n_desc;
  22         q->buf_size = bufsize;
  23         q->hw_idx = idx;
  24
  25         size = q->ndesc * sizeof(struct mt76_desc);
  26         q->desc = dmam_alloc_coherent(dev->dev, size, &q->desc_dma, GFP_KERNEL);
  27         if (!q->desc)
  28                 return -ENOMEM;
  29
  30         size = q->ndesc * sizeof(*q->entry);
  31         q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL);
  32         if (!q->entry)
  33                 return -ENOMEM;
  34
  35         /* clear descriptors */
  36         for (i = 0; i < q->ndesc; i++)
  37                 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
  38
  39         writel(q->desc_dma, &q->regs->desc_base);
  40         writel(0, &q->regs->cpu_idx);
  41         writel(0, &q->regs->dma_idx);
  42         writel(q->ndesc, &q->regs->ring_size);
  43
  44         return 0;
  45 }
  46
  47 static int
  48 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
  49                  struct mt76_queue_buf *buf, int nbufs, u32 info,
  50                  struct sk_buff *skb, void *txwi)
  51 {
  52         struct mt76_desc *desc;
  53         u32 ctrl;
  54         int i, idx = -1;
  55
  56         if (txwi) {
  57                 q->entry[q->head].txwi = DMA_DUMMY_DATA;
  58                 q->entry[q->head].skip_buf0 = true;
  59         }
  60
  61         for (i = 0; i < nbufs; i += 2, buf += 2) {
  62                 u32 buf0 = buf[0].addr, buf1 = 0;
  63
  64                 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
  65                 if (i < nbufs - 1) {
  66                         buf1 = buf[1].addr;
  67                         ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
  68                 }
  69
  70                 if (i == nbufs - 1)
  71                         ctrl |= MT_DMA_CTL_LAST_SEC0;
  72                 else if (i == nbufs - 2)
  73                         ctrl |= MT_DMA_CTL_LAST_SEC1;
  74
  75                 idx = q->head;
  76                 q->head = (q->head + 1) % q->ndesc;
  77
  78                 desc = &q->desc[idx];
  79
  80                 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
  81                 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
  82                 WRITE_ONCE(desc->info, cpu_to_le32(info));
  83                 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl));
  84
  85                 q->queued++;
  86         }
  87
  88         q->entry[idx].txwi = txwi;
  89         q->entry[idx].skb = skb;
  90
  91         return idx;
  92 }
  93
  94 static void
  95 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,
  96                         struct mt76_queue_entry *prev_e)
  97 {
  98         struct mt76_queue_entry *e = &q->entry[idx];
  99         __le32 __ctrl = READ_ONCE(q->desc[idx].ctrl);
 100         u32 ctrl = le32_to_cpu(__ctrl);
 101
 102         if (!e->skip_buf0) {
 103                 __le32 addr = READ_ONCE(q->desc[idx].buf0);
 104                 u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl);
 105
 106                 dma_unmap_single(dev->dev, le32_to_cpu(addr), len,
 107                                  DMA_TO_DEVICE);
 108         }
 109
 110         if (!(ctrl & MT_DMA_CTL_LAST_SEC0)) {
 111                 __le32 addr = READ_ONCE(q->desc[idx].buf1);
 112                 u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN1, ctrl);
 113
 114                 dma_unmap_single(dev->dev, le32_to_cpu(addr), len,
 115                                  DMA_TO_DEVICE);
 116         }
 117
 118         if (e->txwi == DMA_DUMMY_DATA)
 119                 e->txwi = NULL;
 120
 121         if (e->skb == DMA_DUMMY_DATA)
 122                 e->skb = NULL;
 123
 124         *prev_e = *e;
 125         memset(e, 0, sizeof(*e));
 126 }
 127
 128 static void
 129 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
 130 {
 131         writel(q->desc_dma, &q->regs->desc_base);
 132         writel(q->ndesc, &q->regs->ring_size);
 133         q->head = readl(&q->regs->dma_idx);
 134         q->tail = q->head;
 135         writel(q->head, &q->regs->cpu_idx);
 136 }
 137
 138 static void
 139 mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush)
 140 {
 141         struct mt76_sw_queue *sq = &dev->q_tx[qid];
 142         struct mt76_queue *q = sq->q;
 143         struct mt76_queue_entry entry;
 144         unsigned int n_swq_queued[8] = {};
 145         unsigned int n_queued = 0;
 146         bool wake = false;
 147         int i, last;
 148
 149         if (!q)
 150                 return;
 151
 152         if (flush)
 153                 last = -1;
 154         else
 155                 last = readl(&q->regs->dma_idx);
 156
 157         while ((q->queued > n_queued) && q->tail != last) {
 158                 mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry);
 159                 if (entry.schedule)
 160                         n_swq_queued[entry.qid]++;
 161
 162                 q->tail = (q->tail + 1) % q->ndesc;
 163                 n_queued++;
 164
 165                 if (entry.skb)
 166                         dev->drv->tx_complete_skb(dev, qid, &entry);
 167
 168                 if (entry.txwi) {
 169                         if (!(dev->drv->drv_flags & MT_DRV_TXWI_NO_FREE))
 170                                 mt76_put_txwi(dev, entry.txwi);
 171                         wake = !flush;
 172                 }
 173
 174                 if (!flush && q->tail == last)
 175                         last = readl(&q->regs->dma_idx);
 176         }
 177
 178         spin_lock_bh(&q->lock);
 179
 180         q->queued -= n_queued;
 181         for (i = 0; i < 4; i++) {
 182                 if (!n_swq_queued[i])
 183                         continue;
 184
 185                 dev->q_tx[i].swq_queued -= n_swq_queued[i];
 186         }
 187
 188         /* ext PHY */
 189         for (i = 0; i < 4; i++) {
 190                 if (!n_swq_queued[i])
 191                         continue;
 192
 193                 dev->q_tx[__MT_TXQ_MAX + i].swq_queued -= n_swq_queued[4 + i];
 194         }
 195
 196         if (flush)
 197                 mt76_dma_sync_idx(dev, q);
 198
 199         wake = wake && q->stopped &&
 200                qid < IEEE80211_NUM_ACS && q->queued < q->ndesc - 8;
 201         if (wake)
 202                 q->stopped = false;
 203
 204         if (!q->queued)
 205                 wake_up(&dev->tx_wait);
 206
 207         spin_unlock_bh(&q->lock);
 208
 209         if (wake)
 210                 ieee80211_wake_queue(dev->hw, qid);
 211 }
 212
 213 static void *
 214 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
 215                  int *len, u32 *info, bool *more)
 216 {
 217         struct mt76_queue_entry *e = &q->entry[idx];
 218         struct mt76_desc *desc = &q->desc[idx];
 219         dma_addr_t buf_addr;
 220         void *buf = e->buf;
 221         int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
 222
 223         buf_addr = le32_to_cpu(READ_ONCE(desc->buf0));
 224         if (len) {
 225                 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl));
 226                 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
 227                 *more = !(ctl & MT_DMA_CTL_LAST_SEC0);
 228         }
 229
 230         if (info)
 231                 *info = le32_to_cpu(desc->info);
 232
 233         dma_unmap_single(dev->dev, buf_addr, buf_len, DMA_FROM_DEVICE);
 234         e->buf = NULL;
 235
 236         return buf;
 237 }
 238
 239 static void *
 240 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
 241                  int *len, u32 *info, bool *more)
 242 {
 243         int idx = q->tail;
 244
 245         *more = false;
 246         if (!q->queued)
 247                 return NULL;
 248
 249         if (!flush && !(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE)))
 250                 return NULL;
 251
 252         q->tail = (q->tail + 1) % q->ndesc;
 253         q->queued--;
 254
 255         return mt76_dma_get_buf(dev, q, idx, len, info, more);
 256 }
 257
 258 static void
 259 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q)
 260 {
 261         writel(q->head, &q->regs->cpu_idx);
 262 }
 263
 264 static int
 265 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, enum mt76_txq_id qid,
 266                           struct sk_buff *skb, u32 tx_info)
 267 {
 268         struct mt76_queue *q = dev->q_tx[qid].q;
 269         struct mt76_queue_buf buf;
 270         dma_addr_t addr;
 271
 272         addr = dma_map_single(dev->dev, skb->data, skb->len,
 273                               DMA_TO_DEVICE);
 274         if (unlikely(dma_mapping_error(dev->dev, addr)))
 275                 return -ENOMEM;
 276
 277         buf.addr = addr;
 278         buf.len = skb->len;
 279
 280         spin_lock_bh(&q->lock);
 281         mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
 282         mt76_dma_kick_queue(dev, q);
 283         spin_unlock_bh(&q->lock);
 284
 285         return 0;
 286 }
 287
 288 static int
 289 mt76_dma_tx_queue_skb(struct mt76_dev *dev, enum mt76_txq_id qid,
 290                       struct sk_buff *skb, struct mt76_wcid *wcid,
 291                       struct ieee80211_sta *sta)
 292 {
 293         struct mt76_queue *q = dev->q_tx[qid].q;
 294         struct mt76_tx_info tx_info = {
 295                 .skb = skb,
 296         };
 297         struct ieee80211_hw *hw;
 298         int len, n = 0, ret = -ENOMEM;
 299         struct mt76_queue_entry e;
 300         struct mt76_txwi_cache *t;
 301         struct sk_buff *iter;
 302         dma_addr_t addr;
 303         u8 *txwi;
 304
 305         t = mt76_get_txwi(dev);
 306         if (!t) {
 307                 hw = mt76_tx_status_get_hw(dev, skb);
 308                 ieee80211_free_txskb(hw, skb);
 309                 return -ENOMEM;
 310         }
 311         txwi = mt76_get_txwi_ptr(dev, t);
 312
 313         skb->prev = skb->next = NULL;
 314         if (dev->drv->drv_flags & MT_DRV_TX_ALIGNED4_SKBS)
 315                 mt76_insert_hdr_pad(skb);
 316
 317         len = skb_headlen(skb);
 318         addr = dma_map_single(dev->dev, skb->data, len, DMA_TO_DEVICE);
 319         if (unlikely(dma_mapping_error(dev->dev, addr)))
 320                 goto free;
 321
 322         tx_info.buf[n].addr = t->dma_addr;
 323         tx_info.buf[n++].len = dev->drv->txwi_size;
 324         tx_info.buf[n].addr = addr;
 325         tx_info.buf[n++].len = len;
 326
 327         skb_walk_frags(skb, iter) {
 328                 if (n == ARRAY_SIZE(tx_info.buf))
 329                         goto unmap;
 330
 331                 addr = dma_map_single(dev->dev, iter->data, iter->len,
 332                                       DMA_TO_DEVICE);
 333                 if (unlikely(dma_mapping_error(dev->dev, addr)))
 334                         goto unmap;
 335
 336                 tx_info.buf[n].addr = addr;
 337                 tx_info.buf[n++].len = iter->len;
 338         }
 339         tx_info.nbuf = n;
 340
 341         dma_sync_single_for_cpu(dev->dev, t->dma_addr, dev->drv->txwi_size,
 342                                 DMA_TO_DEVICE);
 343         ret = dev->drv->tx_prepare_skb(dev, txwi, qid, wcid, sta, &tx_info);
 344         dma_sync_single_for_device(dev->dev, t->dma_addr, dev->drv->txwi_size,
 345                                    DMA_TO_DEVICE);
 346         if (ret < 0)
 347                 goto unmap;
 348
 349         if (q->queued + (tx_info.nbuf + 1) / 2 >= q->ndesc - 1) {
 350                 ret = -ENOMEM;
 351                 goto unmap;
 352         }
 353
 354         return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
 355                                 tx_info.info, tx_info.skb, t);
 356
 357 unmap:
 358         for (n--; n > 0; n--)
 359                 dma_unmap_single(dev->dev, tx_info.buf[n].addr,
 360                                  tx_info.buf[n].len, DMA_TO_DEVICE);
 361
 362 free:
 363         e.skb = tx_info.skb;
 364         e.txwi = t;
 365         dev->drv->tx_complete_skb(dev, qid, &e);
 366         mt76_put_txwi(dev, t);
 367         return ret;
 368 }
 369
 370 static int
 371 mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
 372 {
 373         dma_addr_t addr;
 374         void *buf;
 375         int frames = 0;
 376         int len = SKB_WITH_OVERHEAD(q->buf_size);
 377         int offset = q->buf_offset;
 378
 379         spin_lock_bh(&q->lock);
 380
 381         while (q->queued < q->ndesc - 1) {
 382                 struct mt76_queue_buf qbuf;
 383
 384                 buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
 385                 if (!buf)
 386                         break;
 387
 388                 addr = dma_map_single(dev->dev, buf, len, DMA_FROM_DEVICE);
 389                 if (unlikely(dma_mapping_error(dev->dev, addr))) {
 390                         skb_free_frag(buf);
 391                         break;
 392                 }
 393
 394                 qbuf.addr = addr + offset;
 395                 qbuf.len = len - offset;
 396                 mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL);
 397                 frames++;
 398         }
 399
 400         if (frames)
 401                 mt76_dma_kick_queue(dev, q);
 402
 403         spin_unlock_bh(&q->lock);
 404
 405         return frames;
 406 }
 407
 408 static void
 409 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
 410 {
 411         struct page *page;
 412         void *buf;
 413         bool more;
 414
 415         spin_lock_bh(&q->lock);
 416         do {
 417                 buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
 418                 if (!buf)
 419                         break;
 420
 421                 skb_free_frag(buf);
 422         } while (1);
 423         spin_unlock_bh(&q->lock);
 424
 425         if (!q->rx_page.va)
 426                 return;
 427
 428         page = virt_to_page(q->rx_page.va);
 429         __page_frag_cache_drain(page, q->rx_page.pagecnt_bias);
 430         memset(&q->rx_page, 0, sizeof(q->rx_page));
 431 }
 432
 433 static void
 434 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
 435 {
 436         struct mt76_queue *q = &dev->q_rx[qid];
 437         int i;
 438
 439         for (i = 0; i < q->ndesc; i++)
 440                 q->desc[i].ctrl &= ~cpu_to_le32(MT_DMA_CTL_DMA_DONE);
 441
 442         mt76_dma_rx_cleanup(dev, q);
 443         mt76_dma_sync_idx(dev, q);
 444         mt76_dma_rx_fill(dev, q);
 445
 446         if (!q->rx_head)
 447                 return;
 448
 449         dev_kfree_skb(q->rx_head);
 450         q->rx_head = NULL;
 451 }
 452
 453 static void
 454 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
 455                   int len, bool more)
 456 {
 457         struct page *page = virt_to_head_page(data);
 458         int offset = data - page_address(page);
 459         struct sk_buff *skb = q->rx_head;
 460
 461         offset += q->buf_offset;
 462         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, offset, len,
 463                         q->buf_size);
 464
 465         if (more)
 466                 return;
 467
 468         q->rx_head = NULL;
 469         dev->drv->rx_skb(dev, q - dev->q_rx, skb);
 470 }
 471
 472 static int
 473 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
 474 {
 475         int len, data_len, done = 0;
 476         struct sk_buff *skb;
 477         unsigned char *data;
 478         bool more;
 479
 480         while (done < budget) {
 481                 u32 info;
 482
 483                 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
 484                 if (!data)
 485                         break;
 486
 487                 if (q->rx_head)
 488                         data_len = q->buf_size;
 489                 else
 490                         data_len = SKB_WITH_OVERHEAD(q->buf_size);
 491
 492                 if (data_len < len + q->buf_offset) {
 493                         dev_kfree_skb(q->rx_head);
 494                         q->rx_head = NULL;
 495
 496                         skb_free_frag(data);
 497                         continue;
 498                 }
 499
 500                 if (q->rx_head) {
 501                         mt76_add_fragment(dev, q, data, len, more);
 502                         continue;
 503                 }
 504
 505                 skb = build_skb(data, q->buf_size);
 506                 if (!skb) {
 507                         skb_free_frag(data);
 508                         continue;
 509                 }
 510                 skb_reserve(skb, q->buf_offset);
 511
 512                 if (q == &dev->q_rx[MT_RXQ_MCU]) {
 513                         u32 *rxfce = (u32 *)skb->cb;
 514                         *rxfce = info;
 515                 }
 516
 517                 __skb_put(skb, len);
 518                 done++;
 519
 520                 if (more) {
 521                         q->rx_head = skb;
 522                         continue;
 523                 }
 524
 525                 dev->drv->rx_skb(dev, q - dev->q_rx, skb);
 526         }
 527
 528         mt76_dma_rx_fill(dev, q);
 529         return done;
 530 }
 531
 532 static int
 533 mt76_dma_rx_poll(struct napi_struct *napi, int budget)
 534 {
 535         struct mt76_dev *dev;
 536         int qid, done = 0, cur;
 537
 538         dev = container_of(napi->dev, struct mt76_dev, napi_dev);
 539         qid = napi - dev->napi;
 540
 541         rcu_read_lock();
 542
 543         do {
 544                 cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done);
 545                 mt76_rx_poll_complete(dev, qid, napi);
 546                 done += cur;
 547         } while (cur && done < budget);
 548
 549         rcu_read_unlock();
 550
 551         if (done < budget && napi_complete(napi))
 552                 dev->drv->rx_poll_complete(dev, qid);
 553
 554         return done;
 555 }
 556
 557 static int
 558 mt76_dma_init(struct mt76_dev *dev)
 559 {
 560         int i;
 561
 562         init_dummy_netdev(&dev->napi_dev);
 563
 564         for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) {
 565                 netif_napi_add(&dev->napi_dev, &dev->napi[i], mt76_dma_rx_poll,
 566                                64);
 567                 mt76_dma_rx_fill(dev, &dev->q_rx[i]);
 568                 napi_enable(&dev->napi[i]);
 569         }
 570
 571         return 0;
 572 }
 573
 574 static const struct mt76_queue_ops mt76_dma_ops = {
 575         .init = mt76_dma_init,
 576         .alloc = mt76_dma_alloc_queue,
 577         .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw,
 578         .tx_queue_skb = mt76_dma_tx_queue_skb,
 579         .tx_cleanup = mt76_dma_tx_cleanup,
 580         .rx_reset = mt76_dma_rx_reset,
 581         .kick = mt76_dma_kick_queue,
 582 };
 583
 584 void mt76_dma_attach(struct mt76_dev *dev)
 585 {
 586         dev->queue_ops = &mt76_dma_ops;
 587 }
 588 EXPORT_SYMBOL_GPL(mt76_dma_attach);
 589
 590 void mt76_dma_cleanup(struct mt76_dev *dev)
 591 {
 592         int i;
 593
 594         netif_napi_del(&dev->tx_napi);
 595         for (i = 0; i < ARRAY_SIZE(dev->q_tx); i++)
 596                 mt76_dma_tx_cleanup(dev, i, true);
 597
 598         for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) {
 599                 netif_napi_del(&dev->napi[i]);
 600                 mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
 601         }
 602 }
 603 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);